aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/usb/phy
diff options
context:
space:
mode:
authorGreg Kroah-Hartman <gregkh@linuxfoundation.org>2013-04-05 18:18:00 -0400
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2013-04-05 18:18:00 -0400
commit64dc9e2e7320f079b97c46b106133b58b8e18d40 (patch)
treeab010dc1337d44e29c2b32b7f11788620a91fe4f /drivers/usb/phy
parent01a60e76b6392547ad3dca3ac05b9c886fa5da45 (diff)
parent9b192de60b5a584ee4ed967fb6758773c75e4643 (diff)
Merge tag 'usb-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/balbi/usb into usb-next
Felipe writes: usb: patches for v3.10 merge window Here is the big Gadget & PHY pull request. Many of us have been really busy lately getting multiple drivers to a better position. Since this pull request is so large, I will divide it in sections so it's easier to grasp what's included. - cleanups: . UDC drivers no longer touch gadget->dev, that's now udc-core responsibility . Many more UDC drivers converted to usb_gadget_map/unmap_request() . UDC drivers no longer initialize DMA-related fields from gadget's device structure . UDC drivers don't touch gadget.dev.driver directly . UDC drivers don't assign gadget.dev.release directly . Removal of some unused DMA_ADDR_INVALID . Introduction of CONFIG_USB_PHY . All phy drivers have been moved to drivers/usb/phy and renamed to a common naming scheme . Fix PHY layer so it never returns a NULL pointer, also fix all callers to avoid using IS_ERR_OR_NULL() . Sparse fixes all over the place . drivers/usb/otg/ has been deleted . Marvel drivers (mv_udc, ehci-mv, mv_otg and mv_u3d) improved clock usage - new features: . UDC core now provides a generic way for tracking and reporting UDC's state (not attached, resuming, suspended, addressed, default, etc) . twl4030-usb learned that it shouldn't be enabled during init . Full DT support for DWC3 has been implemented . ab8500-usb learned about pinctrl framework . nop PHY learned about DeviceTree and regulators . DWC3 learned about suspend/resume . DWC3 can now be compiled in host-only and gadget-only (as well as DRD) configurations . UVC now enables streaming endpoint based on negotiated speed . isp1301 now implements the PHY API properly . configfs-based interface for gadget drivers which will lead to the removal of all code which just combines functions together to build functional gadget drivers. . f_serial and f_obex were converted to new configfs interface while maintaining old interface around. - non-critical fixes: . UVC gadget driver got fixes for Endpoint usage and stream calculation . ab8500-usb fixed unbalanced clock and regulator API usage . twl4030-usb got a fix for when OMAP3 is booted with cable connected . fusb300_udc got a fix for DMA usage . UVC got fixes for two assertions of the USB Video Class Compliance specification revision 1.1 . build warning issues caused by recent addition of __must_check to regulator API These are all changes which deserve a mention, all other changes are related to these one or minor spelling fixes and other similar tasks. Signed-of-by: Felipe Balbi <balbi@ti.com>
Diffstat (limited to 'drivers/usb/phy')
-rw-r--r--drivers/usb/phy/Kconfig180
-rw-r--r--drivers/usb/phy/Makefile35
-rw-r--r--drivers/usb/phy/isp1301.c71
-rw-r--r--drivers/usb/phy/phy-ab8500-usb.c924
-rw-r--r--drivers/usb/phy/phy-fsl-usb.c1173
-rw-r--r--drivers/usb/phy/phy-fsl-usb.h406
-rw-r--r--drivers/usb/phy/phy-fsm-usb.c348
-rw-r--r--drivers/usb/phy/phy-fsm-usb.h154
-rw-r--r--drivers/usb/phy/phy-gpio-vbus-usb.c421
-rw-r--r--drivers/usb/phy/phy-isp1301-omap.c1656
-rw-r--r--drivers/usb/phy/phy-isp1301.c162
-rw-r--r--drivers/usb/phy/phy-msm-usb.c1762
-rw-r--r--drivers/usb/phy/phy-mv-u3d-usb.c (renamed from drivers/usb/phy/mv_u3d_phy.c)2
-rw-r--r--drivers/usb/phy/phy-mv-u3d-usb.h (renamed from drivers/usb/phy/mv_u3d_phy.h)0
-rw-r--r--drivers/usb/phy/phy-mv-usb.c909
-rw-r--r--drivers/usb/phy/phy-mv-usb.h164
-rw-r--r--drivers/usb/phy/phy-mxs-usb.c220
-rw-r--r--drivers/usb/phy/phy-nop.c294
-rw-r--r--drivers/usb/phy/phy-omap-control.c (renamed from drivers/usb/phy/omap-control-usb.c)0
-rw-r--r--drivers/usb/phy/phy-omap-usb2.c (renamed from drivers/usb/phy/omap-usb2.c)0
-rw-r--r--drivers/usb/phy/phy-omap-usb3.c (renamed from drivers/usb/phy/omap-usb3.c)0
-rw-r--r--drivers/usb/phy/phy-rcar-usb.c (renamed from drivers/usb/phy/rcar-phy.c)0
-rw-r--r--drivers/usb/phy/phy-samsung-usb.c236
-rw-r--r--drivers/usb/phy/phy-samsung-usb.h327
-rw-r--r--drivers/usb/phy/phy-samsung-usb2.c509
-rw-r--r--drivers/usb/phy/phy-samsung-usb3.c347
-rw-r--r--drivers/usb/phy/phy-tegra-usb.c (renamed from drivers/usb/phy/tegra_usb_phy.c)0
-rw-r--r--drivers/usb/phy/phy-twl4030-usb.c794
-rw-r--r--drivers/usb/phy/phy-twl6030-usb.c453
-rw-r--r--drivers/usb/phy/phy-ulpi-viewport.c80
-rw-r--r--drivers/usb/phy/phy-ulpi.c283
-rw-r--r--drivers/usb/phy/phy.c438
-rw-r--r--drivers/usb/phy/samsung-usbphy.c928
33 files changed, 12244 insertions, 1032 deletions
diff --git a/drivers/usb/phy/Kconfig b/drivers/usb/phy/Kconfig
index 90549382eba5..3a7fec957ca7 100644
--- a/drivers/usb/phy/Kconfig
+++ b/drivers/usb/phy/Kconfig
@@ -1,13 +1,74 @@
1# 1#
2# Physical Layer USB driver configuration 2# Physical Layer USB driver configuration
3# 3#
4comment "USB Physical Layer drivers" 4menuconfig USB_PHY
5 depends on USB || USB_GADGET 5 tristate "USB Physical Layer drivers"
6 help
7 USB controllers (those which are host, device or DRD) need a
8 device to handle the physical layer signalling, commonly called
9 a PHY.
10
11 The following drivers add support for such PHY devices.
12
13if USB_PHY
14
15#
16# USB Transceiver Drivers
17#
18config AB8500_USB
19 tristate "AB8500 USB Transceiver Driver"
20 depends on AB8500_CORE
21 help
22 Enable this to support the USB OTG transceiver in AB8500 chip.
23 This transceiver supports high and full speed devices plus,
24 in host mode, low speed.
25
26config FSL_USB2_OTG
27 bool "Freescale USB OTG Transceiver Driver"
28 depends on USB_EHCI_FSL && USB_FSL_USB2 && USB_SUSPEND
29 select USB_OTG
30 help
31 Enable this to support Freescale USB OTG transceiver.
32
33config ISP1301_OMAP
34 tristate "Philips ISP1301 with OMAP OTG"
35 depends on I2C && ARCH_OMAP_OTG
36 help
37 If you say yes here you get support for the Philips ISP1301
38 USB-On-The-Go transceiver working with the OMAP OTG controller.
39 The ISP1301 is a full speed USB transceiver which is used in
40 products including H2, H3, and H4 development boards for Texas
41 Instruments OMAP processors.
42
43 This driver can also be built as a module. If so, the module
44 will be called isp1301_omap.
45
46config MV_U3D_PHY
47 bool "Marvell USB 3.0 PHY controller Driver"
48 depends on CPU_MMP3
49 help
50 Enable this to support Marvell USB 3.0 phy controller for Marvell
51 SoC.
52
53config NOP_USB_XCEIV
54 tristate "NOP USB Transceiver Driver"
55 help
56 This driver is to be used by all the usb transceiver which are either
57 built-in with usb ip or which are autonomous and doesn't require any
58 phy programming such as ISP1x04 etc.
59
60config OMAP_CONTROL_USB
61 tristate "OMAP CONTROL USB Driver"
62 help
63 Enable this to add support for the USB part present in the control
64 module. This driver has API to power on the USB2 PHY and to write to
65 the mailbox. The mailbox is present only in omap4 and the register to
66 power on the USB2 PHY is present in OMAP4 and OMAP5. OMAP5 has an
67 additional register to power on USB3 PHY.
6 68
7config OMAP_USB2 69config OMAP_USB2
8 tristate "OMAP USB2 PHY Driver" 70 tristate "OMAP USB2 PHY Driver"
9 depends on ARCH_OMAP2PLUS 71 depends on ARCH_OMAP2PLUS
10 select USB_OTG_UTILS
11 select OMAP_CONTROL_USB 72 select OMAP_CONTROL_USB
12 help 73 help
13 Enable this to support the transceiver that is part of SOC. This 74 Enable this to support the transceiver that is part of SOC. This
@@ -17,7 +78,6 @@ config OMAP_USB2
17 78
18config OMAP_USB3 79config OMAP_USB3
19 tristate "OMAP USB3 PHY Driver" 80 tristate "OMAP USB3 PHY Driver"
20 select USB_OTG_UTILS
21 select OMAP_CONTROL_USB 81 select OMAP_CONTROL_USB
22 help 82 help
23 Enable this to support the USB3 PHY that is part of SOC. This 83 Enable this to support the USB3 PHY that is part of SOC. This
@@ -25,14 +85,55 @@ config OMAP_USB3
25 This driver interacts with the "OMAP Control USB Driver" to power 85 This driver interacts with the "OMAP Control USB Driver" to power
26 on/off the PHY. 86 on/off the PHY.
27 87
28config OMAP_CONTROL_USB 88config SAMSUNG_USBPHY
29 tristate "OMAP CONTROL USB Driver" 89 tristate "Samsung USB PHY Driver"
30 help 90 help
31 Enable this to add support for the USB part present in the control 91 Enable this to support Samsung USB phy helper driver for Samsung SoCs.
32 module. This driver has API to power on the USB2 PHY and to write to 92 This driver provides common interface to interact, for Samsung USB 2.0 PHY
33 the mailbox. The mailbox is present only in omap4 and the register to 93 driver and later for Samsung USB 3.0 PHY driver.
34 power on the USB2 PHY is present in OMAP4 and OMAP5. OMAP5 has an 94
35 additional register to power on USB3 PHY. 95config SAMSUNG_USB2PHY
96 tristate "Samsung USB 2.0 PHY controller Driver"
97 select SAMSUNG_USBPHY
98 help
99 Enable this to support Samsung USB 2.0 (High Speed) PHY controller
100 driver for Samsung SoCs.
101
102config SAMSUNG_USB3PHY
103 tristate "Samsung USB 3.0 PHY controller Driver"
104 select SAMSUNG_USBPHY
105 help
106 Enable this to support Samsung USB 3.0 (Super Speed) phy controller
107 for samsung SoCs.
108
109config TWL4030_USB
110 tristate "TWL4030 USB Transceiver Driver"
111 depends on TWL4030_CORE && REGULATOR_TWL4030 && USB_MUSB_OMAP2PLUS
112 help
113 Enable this to support the USB OTG transceiver on TWL4030
114 family chips (including the TWL5030 and TPS659x0 devices).
115 This transceiver supports high and full speed devices plus,
116 in host mode, low speed.
117
118config TWL6030_USB
119 tristate "TWL6030 USB Transceiver Driver"
120 depends on TWL4030_CORE && OMAP_USB2 && USB_MUSB_OMAP2PLUS
121 help
122 Enable this to support the USB OTG transceiver on TWL6030
123 family chips. This TWL6030 transceiver has the VBUS and ID GND
124 and OTG SRP events capabilities. For all other transceiver functionality
125 UTMI PHY is embedded in OMAP4430. The internal PHY configurations APIs
126 are hooked to this driver through platform_data structure.
127 The definition of internal PHY APIs are in the mach-omap2 layer.
128
129config USB_GPIO_VBUS
130 tristate "GPIO based peripheral-only VBUS sensing 'transceiver'"
131 depends on GENERIC_GPIO
132 help
133 Provides simple GPIO VBUS sensing for controllers with an
134 internal transceiver via the usb_phy interface, and
135 optionally control of a D+ pullup GPIO as well as a VBUS
136 current limit regulator.
36 137
37config USB_ISP1301 138config USB_ISP1301
38 tristate "NXP ISP1301 USB transceiver support" 139 tristate "NXP ISP1301 USB transceiver support"
@@ -47,18 +148,41 @@ config USB_ISP1301
47 To compile this driver as a module, choose M here: the 148 To compile this driver as a module, choose M here: the
48 module will be called isp1301. 149 module will be called isp1301.
49 150
50config MV_U3D_PHY 151config USB_MSM_OTG
51 bool "Marvell USB 3.0 PHY controller Driver" 152 tristate "OTG support for Qualcomm on-chip USB controller"
52 depends on USB_MV_U3D 153 depends on (USB || USB_GADGET) && ARCH_MSM
53 select USB_OTG_UTILS
54 help 154 help
55 Enable this to support Marvell USB 3.0 phy controller for Marvell 155 Enable this to support the USB OTG transceiver on MSM chips. It
56 SoC. 156 handles PHY initialization, clock management, and workarounds
157 required after resetting the hardware and power management.
158 This driver is required even for peripheral only or host only
159 mode configurations.
160 This driver is not supported on boards like trout which
161 has an external PHY.
162
163config USB_MV_OTG
164 tristate "Marvell USB OTG support"
165 depends on USB_EHCI_MV && USB_MV_UDC && USB_SUSPEND
166 select USB_OTG
167 help
168 Say Y here if you want to build Marvell USB OTG transciever
169 driver in kernel (including PXA and MMP series). This driver
170 implements role switch between EHCI host driver and gadget driver.
171
172 To compile this driver as a module, choose M here.
173
174config USB_MXS_PHY
175 tristate "Freescale MXS USB PHY support"
176 depends on ARCH_MXC || ARCH_MXS
177 select STMP_DEVICE
178 help
179 Enable this to support the Freescale MXS USB PHY.
180
181 MXS Phy is used by some of the i.MX SoCs, for example imx23/28/6x.
57 182
58config USB_RCAR_PHY 183config USB_RCAR_PHY
59 tristate "Renesas R-Car USB phy support" 184 tristate "Renesas R-Car USB phy support"
60 depends on USB || USB_GADGET 185 depends on USB || USB_GADGET
61 select USB_OTG_UTILS
62 help 186 help
63 Say Y here to add support for the Renesas R-Car USB phy driver. 187 Say Y here to add support for the Renesas R-Car USB phy driver.
64 This chip is typically used as USB phy for USB host, gadget. 188 This chip is typically used as USB phy for USB host, gadget.
@@ -67,10 +191,18 @@ config USB_RCAR_PHY
67 To compile this driver as a module, choose M here: the 191 To compile this driver as a module, choose M here: the
68 module will be called rcar-phy. 192 module will be called rcar-phy.
69 193
70config SAMSUNG_USBPHY 194config USB_ULPI
71 bool "Samsung USB PHY controller Driver" 195 bool "Generic ULPI Transceiver Driver"
72 depends on USB_S3C_HSOTG || USB_EHCI_S5P || USB_OHCI_EXYNOS 196 depends on ARM
73 select USB_OTG_UTILS 197 help
198 Enable this to support ULPI connected USB OTG transceivers which
199 are likely found on embedded boards.
200
201config USB_ULPI_VIEWPORT
202 bool
203 depends on USB_ULPI
74 help 204 help
75 Enable this to support Samsung USB phy controller for samsung 205 Provides read/write operations to the ULPI phy register set for
76 SoCs. 206 controllers with a viewport register (e.g. Chipidea/ARC controllers).
207
208endif # USB_PHY
diff --git a/drivers/usb/phy/Makefile b/drivers/usb/phy/Makefile
index b13faa193e0c..33863c09f3dc 100644
--- a/drivers/usb/phy/Makefile
+++ b/drivers/usb/phy/Makefile
@@ -4,11 +4,30 @@
4 4
5ccflags-$(CONFIG_USB_DEBUG) := -DDEBUG 5ccflags-$(CONFIG_USB_DEBUG) := -DDEBUG
6 6
7obj-$(CONFIG_OMAP_USB2) += omap-usb2.o 7obj-$(CONFIG_USB_PHY) += phy.o
8obj-$(CONFIG_OMAP_USB3) += omap-usb3.o 8
9obj-$(CONFIG_OMAP_CONTROL_USB) += omap-control-usb.o 9# transceiver drivers, keep the list sorted
10obj-$(CONFIG_USB_ISP1301) += isp1301.o 10
11obj-$(CONFIG_MV_U3D_PHY) += mv_u3d_phy.o 11obj-$(CONFIG_AB8500_USB) += phy-ab8500-usb.o
12obj-$(CONFIG_USB_EHCI_TEGRA) += tegra_usb_phy.o 12phy-fsl-usb2-objs := phy-fsl-usb.o phy-fsm-usb.o
13obj-$(CONFIG_USB_RCAR_PHY) += rcar-phy.o 13obj-$(CONFIG_FSL_USB2_OTG) += phy-fsl-usb2.o
14obj-$(CONFIG_SAMSUNG_USBPHY) += samsung-usbphy.o 14obj-$(CONFIG_ISP1301_OMAP) += phy-isp1301.omap.o
15obj-$(CONFIG_MV_U3D_PHY) += phy-mv-u3d-usb.o
16obj-$(CONFIG_NOP_USB_XCEIV) += phy-nop.o
17obj-$(CONFIG_OMAP_CONTROL_USB) += phy-omap-control.o
18obj-$(CONFIG_OMAP_USB2) += phy-omap-usb2.o
19obj-$(CONFIG_OMAP_USB3) += phy-omap-usb3.o
20obj-$(CONFIG_SAMSUNG_USBPHY) += phy-samsung-usb.o
21obj-$(CONFIG_SAMSUNG_USB2PHY) += phy-samsung-usb2.o
22obj-$(CONFIG_SAMSUNG_USB3PHY) += phy-samsung-usb3.o
23obj-$(CONFIG_TWL4030_USB) += phy-twl4030-usb.o
24obj-$(CONFIG_TWL6030_USB) += phy-twl6030-usb.o
25obj-$(CONFIG_USB_EHCI_TEGRA) += phy-tegra-usb.o
26obj-$(CONFIG_USB_GPIO_VBUS) += phy-gpio-vbus-usb.o
27obj-$(CONFIG_USB_ISP1301) += phy-isp1301.o
28obj-$(CONFIG_USB_MSM_OTG) += phy-msm-usb.o
29obj-$(CONFIG_USB_MV_OTG) += phy-mv-usb.o
30obj-$(CONFIG_USB_MXS_PHY) += phy-mxs-usb.o
31obj-$(CONFIG_USB_RCAR_PHY) += phy-rcar-usb.o
32obj-$(CONFIG_USB_ULPI) += phy-ulpi.o
33obj-$(CONFIG_USB_ULPI_VIEWPORT) += phy-ulpi-viewport.o
diff --git a/drivers/usb/phy/isp1301.c b/drivers/usb/phy/isp1301.c
deleted file mode 100644
index 18dbf7e37607..000000000000
--- a/drivers/usb/phy/isp1301.c
+++ /dev/null
@@ -1,71 +0,0 @@
1/*
2 * NXP ISP1301 USB transceiver driver
3 *
4 * Copyright (C) 2012 Roland Stigge
5 *
6 * Author: Roland Stigge <stigge@antcom.de>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/module.h>
14#include <linux/i2c.h>
15
16#define DRV_NAME "isp1301"
17
18static const struct i2c_device_id isp1301_id[] = {
19 { "isp1301", 0 },
20 { }
21};
22
23static struct i2c_client *isp1301_i2c_client;
24
25static int isp1301_probe(struct i2c_client *client,
26 const struct i2c_device_id *i2c_id)
27{
28 isp1301_i2c_client = client;
29 return 0;
30}
31
32static int isp1301_remove(struct i2c_client *client)
33{
34 return 0;
35}
36
37static struct i2c_driver isp1301_driver = {
38 .driver = {
39 .name = DRV_NAME,
40 },
41 .probe = isp1301_probe,
42 .remove = isp1301_remove,
43 .id_table = isp1301_id,
44};
45
46module_i2c_driver(isp1301_driver);
47
48static int match(struct device *dev, void *data)
49{
50 struct device_node *node = (struct device_node *)data;
51 return (dev->of_node == node) &&
52 (dev->driver == &isp1301_driver.driver);
53}
54
55struct i2c_client *isp1301_get_client(struct device_node *node)
56{
57 if (node) { /* reference of ISP1301 I2C node via DT */
58 struct device *dev = bus_find_device(&i2c_bus_type, NULL,
59 node, match);
60 if (!dev)
61 return NULL;
62 return to_i2c_client(dev);
63 } else { /* non-DT: only one ISP1301 chip supported */
64 return isp1301_i2c_client;
65 }
66}
67EXPORT_SYMBOL_GPL(isp1301_get_client);
68
69MODULE_AUTHOR("Roland Stigge <stigge@antcom.de>");
70MODULE_DESCRIPTION("NXP ISP1301 USB transceiver driver");
71MODULE_LICENSE("GPL");
diff --git a/drivers/usb/phy/phy-ab8500-usb.c b/drivers/usb/phy/phy-ab8500-usb.c
new file mode 100644
index 000000000000..4acef26a2ef5
--- /dev/null
+++ b/drivers/usb/phy/phy-ab8500-usb.c
@@ -0,0 +1,924 @@
1/*
2 * drivers/usb/otg/ab8500_usb.c
3 *
4 * USB transceiver driver for AB8500 chip
5 *
6 * Copyright (C) 2010 ST-Ericsson AB
7 * Mian Yousaf Kaukab <mian.yousaf.kaukab@stericsson.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 *
23 */
24
25#include <linux/module.h>
26#include <linux/platform_device.h>
27#include <linux/usb/otg.h>
28#include <linux/slab.h>
29#include <linux/notifier.h>
30#include <linux/interrupt.h>
31#include <linux/delay.h>
32#include <linux/mfd/abx500.h>
33#include <linux/mfd/abx500/ab8500.h>
34#include <linux/usb/musb-ux500.h>
35#include <linux/regulator/consumer.h>
36#include <linux/pinctrl/consumer.h>
37
38/* Bank AB8500_SYS_CTRL2_BLOCK */
39#define AB8500_MAIN_WD_CTRL_REG 0x01
40
41/* Bank AB8500_USB */
42#define AB8500_USB_LINE_STAT_REG 0x80
43#define AB8505_USB_LINE_STAT_REG 0x94
44#define AB8500_USB_PHY_CTRL_REG 0x8A
45
46/* Bank AB8500_DEVELOPMENT */
47#define AB8500_BANK12_ACCESS 0x00
48
49/* Bank AB8500_DEBUG */
50#define AB8500_USB_PHY_TUNE1 0x05
51#define AB8500_USB_PHY_TUNE2 0x06
52#define AB8500_USB_PHY_TUNE3 0x07
53
54#define AB8500_BIT_OTG_STAT_ID (1 << 0)
55#define AB8500_BIT_PHY_CTRL_HOST_EN (1 << 0)
56#define AB8500_BIT_PHY_CTRL_DEVICE_EN (1 << 1)
57#define AB8500_BIT_WD_CTRL_ENABLE (1 << 0)
58#define AB8500_BIT_WD_CTRL_KICK (1 << 1)
59
60#define AB8500_WD_KICK_DELAY_US 100 /* usec */
61#define AB8500_WD_V11_DISABLE_DELAY_US 100 /* usec */
62#define AB8500_V20_31952_DISABLE_DELAY_US 100 /* usec */
63
64/* Usb line status register */
65enum ab8500_usb_link_status {
66 USB_LINK_NOT_CONFIGURED_8500 = 0,
67 USB_LINK_STD_HOST_NC_8500,
68 USB_LINK_STD_HOST_C_NS_8500,
69 USB_LINK_STD_HOST_C_S_8500,
70 USB_LINK_HOST_CHG_NM_8500,
71 USB_LINK_HOST_CHG_HS_8500,
72 USB_LINK_HOST_CHG_HS_CHIRP_8500,
73 USB_LINK_DEDICATED_CHG_8500,
74 USB_LINK_ACA_RID_A_8500,
75 USB_LINK_ACA_RID_B_8500,
76 USB_LINK_ACA_RID_C_NM_8500,
77 USB_LINK_ACA_RID_C_HS_8500,
78 USB_LINK_ACA_RID_C_HS_CHIRP_8500,
79 USB_LINK_HM_IDGND_8500,
80 USB_LINK_RESERVED_8500,
81 USB_LINK_NOT_VALID_LINK_8500,
82};
83
84enum ab8505_usb_link_status {
85 USB_LINK_NOT_CONFIGURED_8505 = 0,
86 USB_LINK_STD_HOST_NC_8505,
87 USB_LINK_STD_HOST_C_NS_8505,
88 USB_LINK_STD_HOST_C_S_8505,
89 USB_LINK_CDP_8505,
90 USB_LINK_RESERVED0_8505,
91 USB_LINK_RESERVED1_8505,
92 USB_LINK_DEDICATED_CHG_8505,
93 USB_LINK_ACA_RID_A_8505,
94 USB_LINK_ACA_RID_B_8505,
95 USB_LINK_ACA_RID_C_NM_8505,
96 USB_LINK_RESERVED2_8505,
97 USB_LINK_RESERVED3_8505,
98 USB_LINK_HM_IDGND_8505,
99 USB_LINK_CHARGERPORT_NOT_OK_8505,
100 USB_LINK_CHARGER_DM_HIGH_8505,
101 USB_LINK_PHYEN_NO_VBUS_NO_IDGND_8505,
102 USB_LINK_STD_UPSTREAM_NO_IDGNG_NO_VBUS_8505,
103 USB_LINK_STD_UPSTREAM_8505,
104 USB_LINK_CHARGER_SE1_8505,
105 USB_LINK_CARKIT_CHGR_1_8505,
106 USB_LINK_CARKIT_CHGR_2_8505,
107 USB_LINK_ACA_DOCK_CHGR_8505,
108 USB_LINK_SAMSUNG_BOOT_CBL_PHY_EN_8505,
109 USB_LINK_SAMSUNG_BOOT_CBL_PHY_DISB_8505,
110 USB_LINK_SAMSUNG_UART_CBL_PHY_EN_8505,
111 USB_LINK_SAMSUNG_UART_CBL_PHY_DISB_8505,
112 USB_LINK_MOTOROLA_FACTORY_CBL_PHY_EN_8505,
113};
114
115enum ab8500_usb_mode {
116 USB_IDLE = 0,
117 USB_PERIPHERAL,
118 USB_HOST,
119 USB_DEDICATED_CHG
120};
121
122struct ab8500_usb {
123 struct usb_phy phy;
124 struct device *dev;
125 struct ab8500 *ab8500;
126 unsigned vbus_draw;
127 struct work_struct phy_dis_work;
128 enum ab8500_usb_mode mode;
129 struct regulator *v_ape;
130 struct regulator *v_musb;
131 struct regulator *v_ulpi;
132 int saved_v_ulpi;
133 int previous_link_status_state;
134 struct pinctrl *pinctrl;
135 struct pinctrl_state *pins_sleep;
136};
137
138static inline struct ab8500_usb *phy_to_ab(struct usb_phy *x)
139{
140 return container_of(x, struct ab8500_usb, phy);
141}
142
143static void ab8500_usb_wd_workaround(struct ab8500_usb *ab)
144{
145 abx500_set_register_interruptible(ab->dev,
146 AB8500_SYS_CTRL2_BLOCK,
147 AB8500_MAIN_WD_CTRL_REG,
148 AB8500_BIT_WD_CTRL_ENABLE);
149
150 udelay(AB8500_WD_KICK_DELAY_US);
151
152 abx500_set_register_interruptible(ab->dev,
153 AB8500_SYS_CTRL2_BLOCK,
154 AB8500_MAIN_WD_CTRL_REG,
155 (AB8500_BIT_WD_CTRL_ENABLE
156 | AB8500_BIT_WD_CTRL_KICK));
157
158 udelay(AB8500_WD_V11_DISABLE_DELAY_US);
159
160 abx500_set_register_interruptible(ab->dev,
161 AB8500_SYS_CTRL2_BLOCK,
162 AB8500_MAIN_WD_CTRL_REG,
163 0);
164}
165
166static void ab8500_usb_regulator_enable(struct ab8500_usb *ab)
167{
168 int ret, volt;
169
170 ret = regulator_enable(ab->v_ape);
171 if (ret)
172 dev_err(ab->dev, "Failed to enable v-ape\n");
173
174 if (!is_ab8500_2p0_or_earlier(ab->ab8500)) {
175 ab->saved_v_ulpi = regulator_get_voltage(ab->v_ulpi);
176 if (ab->saved_v_ulpi < 0)
177 dev_err(ab->dev, "Failed to get v_ulpi voltage\n");
178
179 ret = regulator_set_voltage(ab->v_ulpi, 1300000, 1350000);
180 if (ret < 0)
181 dev_err(ab->dev, "Failed to set the Vintcore to 1.3V, ret=%d\n",
182 ret);
183
184 ret = regulator_set_optimum_mode(ab->v_ulpi, 28000);
185 if (ret < 0)
186 dev_err(ab->dev, "Failed to set optimum mode (ret=%d)\n",
187 ret);
188 }
189
190 ret = regulator_enable(ab->v_ulpi);
191 if (ret)
192 dev_err(ab->dev, "Failed to enable vddulpivio18\n");
193
194 if (!is_ab8500_2p0_or_earlier(ab->ab8500)) {
195 volt = regulator_get_voltage(ab->v_ulpi);
196 if ((volt != 1300000) && (volt != 1350000))
197 dev_err(ab->dev, "Vintcore is not set to 1.3V volt=%d\n",
198 volt);
199 }
200
201 ret = regulator_enable(ab->v_musb);
202 if (ret)
203 dev_err(ab->dev, "Failed to enable musb_1v8\n");
204}
205
206static void ab8500_usb_regulator_disable(struct ab8500_usb *ab)
207{
208 int ret;
209
210 regulator_disable(ab->v_musb);
211
212 regulator_disable(ab->v_ulpi);
213
214 /* USB is not the only consumer of Vintcore, restore old settings */
215 if (!is_ab8500_2p0_or_earlier(ab->ab8500)) {
216 if (ab->saved_v_ulpi > 0) {
217 ret = regulator_set_voltage(ab->v_ulpi,
218 ab->saved_v_ulpi, ab->saved_v_ulpi);
219 if (ret < 0)
220 dev_err(ab->dev, "Failed to set the Vintcore to %duV, ret=%d\n",
221 ab->saved_v_ulpi, ret);
222 }
223
224 ret = regulator_set_optimum_mode(ab->v_ulpi, 0);
225 if (ret < 0)
226 dev_err(ab->dev, "Failed to set optimum mode (ret=%d)\n",
227 ret);
228 }
229
230 regulator_disable(ab->v_ape);
231}
232
233static void ab8500_usb_wd_linkstatus(struct ab8500_usb *ab, u8 bit)
234{
235 /* Workaround for v2.0 bug # 31952 */
236 if (is_ab8500_2p0(ab->ab8500)) {
237 abx500_mask_and_set_register_interruptible(ab->dev,
238 AB8500_USB, AB8500_USB_PHY_CTRL_REG,
239 bit, bit);
240 udelay(AB8500_V20_31952_DISABLE_DELAY_US);
241 }
242}
243
244static void ab8500_usb_phy_enable(struct ab8500_usb *ab, bool sel_host)
245{
246 u8 bit;
247 bit = sel_host ? AB8500_BIT_PHY_CTRL_HOST_EN :
248 AB8500_BIT_PHY_CTRL_DEVICE_EN;
249
250 /* mux and configure USB pins to DEFAULT state */
251 ab->pinctrl = pinctrl_get_select(ab->dev, PINCTRL_STATE_DEFAULT);
252 if (IS_ERR(ab->pinctrl))
253 dev_err(ab->dev, "could not get/set default pinstate\n");
254
255 ab8500_usb_regulator_enable(ab);
256
257 abx500_mask_and_set_register_interruptible(ab->dev,
258 AB8500_USB, AB8500_USB_PHY_CTRL_REG,
259 bit, bit);
260}
261
262static void ab8500_usb_phy_disable(struct ab8500_usb *ab, bool sel_host)
263{
264 u8 bit;
265 bit = sel_host ? AB8500_BIT_PHY_CTRL_HOST_EN :
266 AB8500_BIT_PHY_CTRL_DEVICE_EN;
267
268 ab8500_usb_wd_linkstatus(ab, bit);
269
270 abx500_mask_and_set_register_interruptible(ab->dev,
271 AB8500_USB, AB8500_USB_PHY_CTRL_REG,
272 bit, 0);
273
274 /* Needed to disable the phy.*/
275 ab8500_usb_wd_workaround(ab);
276
277 ab8500_usb_regulator_disable(ab);
278
279 if (!IS_ERR(ab->pinctrl)) {
280 /* configure USB pins to SLEEP state */
281 ab->pins_sleep = pinctrl_lookup_state(ab->pinctrl,
282 PINCTRL_STATE_SLEEP);
283
284 if (IS_ERR(ab->pins_sleep))
285 dev_dbg(ab->dev, "could not get sleep pinstate\n");
286 else if (pinctrl_select_state(ab->pinctrl, ab->pins_sleep))
287 dev_err(ab->dev, "could not set pins to sleep state\n");
288
289 /* as USB pins are shared with idddet, release them to allow
290 * iddet to request them
291 */
292 pinctrl_put(ab->pinctrl);
293 }
294}
295
296#define ab8500_usb_host_phy_en(ab) ab8500_usb_phy_enable(ab, true)
297#define ab8500_usb_host_phy_dis(ab) ab8500_usb_phy_disable(ab, true)
298#define ab8500_usb_peri_phy_en(ab) ab8500_usb_phy_enable(ab, false)
299#define ab8500_usb_peri_phy_dis(ab) ab8500_usb_phy_disable(ab, false)
300
301static int ab8505_usb_link_status_update(struct ab8500_usb *ab,
302 enum ab8505_usb_link_status lsts)
303{
304 enum ux500_musb_vbus_id_status event = 0;
305
306 dev_dbg(ab->dev, "ab8505_usb_link_status_update %d\n", lsts);
307
308 /*
309 * Spurious link_status interrupts are seen at the time of
310 * disconnection of a device in RIDA state
311 */
312 if (ab->previous_link_status_state == USB_LINK_ACA_RID_A_8505 &&
313 (lsts == USB_LINK_STD_HOST_NC_8505))
314 return 0;
315
316 ab->previous_link_status_state = lsts;
317
318 switch (lsts) {
319 case USB_LINK_ACA_RID_B_8505:
320 event = UX500_MUSB_RIDB;
321 case USB_LINK_NOT_CONFIGURED_8505:
322 case USB_LINK_RESERVED0_8505:
323 case USB_LINK_RESERVED1_8505:
324 case USB_LINK_RESERVED2_8505:
325 case USB_LINK_RESERVED3_8505:
326 ab->mode = USB_IDLE;
327 ab->phy.otg->default_a = false;
328 ab->vbus_draw = 0;
329 if (event != UX500_MUSB_RIDB)
330 event = UX500_MUSB_NONE;
331 /*
332 * Fallback to default B_IDLE as nothing
333 * is connected
334 */
335 ab->phy.state = OTG_STATE_B_IDLE;
336 break;
337
338 case USB_LINK_ACA_RID_C_NM_8505:
339 event = UX500_MUSB_RIDC;
340 case USB_LINK_STD_HOST_NC_8505:
341 case USB_LINK_STD_HOST_C_NS_8505:
342 case USB_LINK_STD_HOST_C_S_8505:
343 case USB_LINK_CDP_8505:
344 if (ab->mode == USB_IDLE) {
345 ab->mode = USB_PERIPHERAL;
346 ab8500_usb_peri_phy_en(ab);
347 atomic_notifier_call_chain(&ab->phy.notifier,
348 UX500_MUSB_PREPARE, &ab->vbus_draw);
349 }
350 if (event != UX500_MUSB_RIDC)
351 event = UX500_MUSB_VBUS;
352 break;
353
354 case USB_LINK_ACA_RID_A_8505:
355 case USB_LINK_ACA_DOCK_CHGR_8505:
356 event = UX500_MUSB_RIDA;
357 case USB_LINK_HM_IDGND_8505:
358 if (ab->mode == USB_IDLE) {
359 ab->mode = USB_HOST;
360 ab8500_usb_host_phy_en(ab);
361 atomic_notifier_call_chain(&ab->phy.notifier,
362 UX500_MUSB_PREPARE, &ab->vbus_draw);
363 }
364 ab->phy.otg->default_a = true;
365 if (event != UX500_MUSB_RIDA)
366 event = UX500_MUSB_ID;
367 atomic_notifier_call_chain(&ab->phy.notifier,
368 event, &ab->vbus_draw);
369 break;
370
371 case USB_LINK_DEDICATED_CHG_8505:
372 ab->mode = USB_DEDICATED_CHG;
373 event = UX500_MUSB_CHARGER;
374 atomic_notifier_call_chain(&ab->phy.notifier,
375 event, &ab->vbus_draw);
376 break;
377
378 default:
379 break;
380 }
381
382 return 0;
383}
384
385static int ab8500_usb_link_status_update(struct ab8500_usb *ab,
386 enum ab8500_usb_link_status lsts)
387{
388 enum ux500_musb_vbus_id_status event = 0;
389
390 dev_dbg(ab->dev, "ab8500_usb_link_status_update %d\n", lsts);
391
392 /*
393 * Spurious link_status interrupts are seen in case of a
394 * disconnection of a device in IDGND and RIDA stage
395 */
396 if (ab->previous_link_status_state == USB_LINK_HM_IDGND_8500 &&
397 (lsts == USB_LINK_STD_HOST_C_NS_8500 ||
398 lsts == USB_LINK_STD_HOST_NC_8500))
399 return 0;
400
401 if (ab->previous_link_status_state == USB_LINK_ACA_RID_A_8500 &&
402 lsts == USB_LINK_STD_HOST_NC_8500)
403 return 0;
404
405 ab->previous_link_status_state = lsts;
406
407 switch (lsts) {
408 case USB_LINK_ACA_RID_B_8500:
409 event = UX500_MUSB_RIDB;
410 case USB_LINK_NOT_CONFIGURED_8500:
411 case USB_LINK_NOT_VALID_LINK_8500:
412 ab->mode = USB_IDLE;
413 ab->phy.otg->default_a = false;
414 ab->vbus_draw = 0;
415 if (event != UX500_MUSB_RIDB)
416 event = UX500_MUSB_NONE;
417 /* Fallback to default B_IDLE as nothing is connected */
418 ab->phy.state = OTG_STATE_B_IDLE;
419 break;
420
421 case USB_LINK_ACA_RID_C_NM_8500:
422 case USB_LINK_ACA_RID_C_HS_8500:
423 case USB_LINK_ACA_RID_C_HS_CHIRP_8500:
424 event = UX500_MUSB_RIDC;
425 case USB_LINK_STD_HOST_NC_8500:
426 case USB_LINK_STD_HOST_C_NS_8500:
427 case USB_LINK_STD_HOST_C_S_8500:
428 case USB_LINK_HOST_CHG_NM_8500:
429 case USB_LINK_HOST_CHG_HS_8500:
430 case USB_LINK_HOST_CHG_HS_CHIRP_8500:
431 if (ab->mode == USB_IDLE) {
432 ab->mode = USB_PERIPHERAL;
433 ab8500_usb_peri_phy_en(ab);
434 atomic_notifier_call_chain(&ab->phy.notifier,
435 UX500_MUSB_PREPARE, &ab->vbus_draw);
436 }
437 if (event != UX500_MUSB_RIDC)
438 event = UX500_MUSB_VBUS;
439 break;
440
441 case USB_LINK_ACA_RID_A_8500:
442 event = UX500_MUSB_RIDA;
443 case USB_LINK_HM_IDGND_8500:
444 if (ab->mode == USB_IDLE) {
445 ab->mode = USB_HOST;
446 ab8500_usb_host_phy_en(ab);
447 atomic_notifier_call_chain(&ab->phy.notifier,
448 UX500_MUSB_PREPARE, &ab->vbus_draw);
449 }
450 ab->phy.otg->default_a = true;
451 if (event != UX500_MUSB_RIDA)
452 event = UX500_MUSB_ID;
453 atomic_notifier_call_chain(&ab->phy.notifier,
454 event, &ab->vbus_draw);
455 break;
456
457 case USB_LINK_DEDICATED_CHG_8500:
458 ab->mode = USB_DEDICATED_CHG;
459 event = UX500_MUSB_CHARGER;
460 atomic_notifier_call_chain(&ab->phy.notifier,
461 event, &ab->vbus_draw);
462 break;
463
464 case USB_LINK_RESERVED_8500:
465 break;
466 }
467
468 return 0;
469}
470
471/*
472 * Connection Sequence:
473 * 1. Link Status Interrupt
474 * 2. Enable AB clock
475 * 3. Enable AB regulators
476 * 4. Enable USB phy
477 * 5. Reset the musb controller
478 * 6. Switch the ULPI GPIO pins to fucntion mode
479 * 7. Enable the musb Peripheral5 clock
480 * 8. Restore MUSB context
481 */
482static int abx500_usb_link_status_update(struct ab8500_usb *ab)
483{
484 u8 reg;
485 int ret = 0;
486
487 if (is_ab8500(ab->ab8500)) {
488 enum ab8500_usb_link_status lsts;
489
490 abx500_get_register_interruptible(ab->dev,
491 AB8500_USB, AB8500_USB_LINE_STAT_REG, &reg);
492 lsts = (reg >> 3) & 0x0F;
493 ret = ab8500_usb_link_status_update(ab, lsts);
494 } else if (is_ab8505(ab->ab8500)) {
495 enum ab8505_usb_link_status lsts;
496
497 abx500_get_register_interruptible(ab->dev,
498 AB8500_USB, AB8505_USB_LINE_STAT_REG, &reg);
499 lsts = (reg >> 3) & 0x1F;
500 ret = ab8505_usb_link_status_update(ab, lsts);
501 }
502
503 return ret;
504}
505
506/*
507 * Disconnection Sequence:
508 * 1. Disconect Interrupt
509 * 2. Disable regulators
510 * 3. Disable AB clock
511 * 4. Disable the Phy
512 * 5. Link Status Interrupt
513 * 6. Disable Musb Clock
514 */
515static irqreturn_t ab8500_usb_disconnect_irq(int irq, void *data)
516{
517 struct ab8500_usb *ab = (struct ab8500_usb *) data;
518 enum usb_phy_events event = UX500_MUSB_NONE;
519
520 /* Link status will not be updated till phy is disabled. */
521 if (ab->mode == USB_HOST) {
522 ab->phy.otg->default_a = false;
523 ab->vbus_draw = 0;
524 atomic_notifier_call_chain(&ab->phy.notifier,
525 event, &ab->vbus_draw);
526 ab8500_usb_host_phy_dis(ab);
527 ab->mode = USB_IDLE;
528 }
529
530 if (ab->mode == USB_PERIPHERAL) {
531 atomic_notifier_call_chain(&ab->phy.notifier,
532 event, &ab->vbus_draw);
533 ab8500_usb_peri_phy_dis(ab);
534 atomic_notifier_call_chain(&ab->phy.notifier,
535 UX500_MUSB_CLEAN, &ab->vbus_draw);
536 ab->mode = USB_IDLE;
537 ab->phy.otg->default_a = false;
538 ab->vbus_draw = 0;
539 }
540
541 if (is_ab8500_2p0(ab->ab8500)) {
542 if (ab->mode == USB_DEDICATED_CHG) {
543 ab8500_usb_wd_linkstatus(ab,
544 AB8500_BIT_PHY_CTRL_DEVICE_EN);
545 abx500_mask_and_set_register_interruptible(ab->dev,
546 AB8500_USB, AB8500_USB_PHY_CTRL_REG,
547 AB8500_BIT_PHY_CTRL_DEVICE_EN, 0);
548 }
549 }
550
551 return IRQ_HANDLED;
552}
553
554static irqreturn_t ab8500_usb_link_status_irq(int irq, void *data)
555{
556 struct ab8500_usb *ab = (struct ab8500_usb *) data;
557
558 abx500_usb_link_status_update(ab);
559
560 return IRQ_HANDLED;
561}
562
563static void ab8500_usb_phy_disable_work(struct work_struct *work)
564{
565 struct ab8500_usb *ab = container_of(work, struct ab8500_usb,
566 phy_dis_work);
567
568 if (!ab->phy.otg->host)
569 ab8500_usb_host_phy_dis(ab);
570
571 if (!ab->phy.otg->gadget)
572 ab8500_usb_peri_phy_dis(ab);
573}
574
575static unsigned ab8500_eyediagram_workaroud(struct ab8500_usb *ab, unsigned mA)
576{
577 /*
578 * AB8500 V2 has eye diagram issues when drawing more than 100mA from
579 * VBUS. Set charging current to 100mA in case of standard host
580 */
581 if (is_ab8500_2p0_or_earlier(ab->ab8500))
582 if (mA > 100)
583 mA = 100;
584
585 return mA;
586}
587
588static int ab8500_usb_set_power(struct usb_phy *phy, unsigned mA)
589{
590 struct ab8500_usb *ab;
591
592 if (!phy)
593 return -ENODEV;
594
595 ab = phy_to_ab(phy);
596
597 mA = ab8500_eyediagram_workaroud(ab, mA);
598
599 ab->vbus_draw = mA;
600
601 atomic_notifier_call_chain(&ab->phy.notifier,
602 UX500_MUSB_VBUS, &ab->vbus_draw);
603
604 return 0;
605}
606
607static int ab8500_usb_set_suspend(struct usb_phy *x, int suspend)
608{
609 /* TODO */
610 return 0;
611}
612
613static int ab8500_usb_set_peripheral(struct usb_otg *otg,
614 struct usb_gadget *gadget)
615{
616 struct ab8500_usb *ab;
617
618 if (!otg)
619 return -ENODEV;
620
621 ab = phy_to_ab(otg->phy);
622
623 ab->phy.otg->gadget = gadget;
624
625 /* Some drivers call this function in atomic context.
626 * Do not update ab8500 registers directly till this
627 * is fixed.
628 */
629
630 if ((ab->mode != USB_IDLE) && (!gadget)) {
631 ab->mode = USB_IDLE;
632 schedule_work(&ab->phy_dis_work);
633 }
634
635 return 0;
636}
637
638static int ab8500_usb_set_host(struct usb_otg *otg, struct usb_bus *host)
639{
640 struct ab8500_usb *ab;
641
642 if (!otg)
643 return -ENODEV;
644
645 ab = phy_to_ab(otg->phy);
646
647 ab->phy.otg->host = host;
648
649 /* Some drivers call this function in atomic context.
650 * Do not update ab8500 registers directly till this
651 * is fixed.
652 */
653
654 if ((ab->mode != USB_IDLE) && (!host)) {
655 ab->mode = USB_IDLE;
656 schedule_work(&ab->phy_dis_work);
657 }
658
659 return 0;
660}
661
662static int ab8500_usb_regulator_get(struct ab8500_usb *ab)
663{
664 int err;
665
666 ab->v_ape = devm_regulator_get(ab->dev, "v-ape");
667 if (IS_ERR(ab->v_ape)) {
668 dev_err(ab->dev, "Could not get v-ape supply\n");
669 err = PTR_ERR(ab->v_ape);
670 return err;
671 }
672
673 ab->v_ulpi = devm_regulator_get(ab->dev, "vddulpivio18");
674 if (IS_ERR(ab->v_ulpi)) {
675 dev_err(ab->dev, "Could not get vddulpivio18 supply\n");
676 err = PTR_ERR(ab->v_ulpi);
677 return err;
678 }
679
680 ab->v_musb = devm_regulator_get(ab->dev, "musb_1v8");
681 if (IS_ERR(ab->v_musb)) {
682 dev_err(ab->dev, "Could not get musb_1v8 supply\n");
683 err = PTR_ERR(ab->v_musb);
684 return err;
685 }
686
687 return 0;
688}
689
690static int ab8500_usb_irq_setup(struct platform_device *pdev,
691 struct ab8500_usb *ab)
692{
693 int err;
694 int irq;
695
696 irq = platform_get_irq_byname(pdev, "USB_LINK_STATUS");
697 if (irq < 0) {
698 dev_err(&pdev->dev, "Link status irq not found\n");
699 return irq;
700 }
701 err = devm_request_threaded_irq(&pdev->dev, irq, NULL,
702 ab8500_usb_link_status_irq,
703 IRQF_NO_SUSPEND | IRQF_SHARED, "usb-link-status", ab);
704 if (err < 0) {
705 dev_err(ab->dev, "request_irq failed for link status irq\n");
706 return err;
707 }
708
709 irq = platform_get_irq_byname(pdev, "ID_WAKEUP_F");
710 if (irq < 0) {
711 dev_err(&pdev->dev, "ID fall irq not found\n");
712 return irq;
713 }
714 err = devm_request_threaded_irq(&pdev->dev, irq, NULL,
715 ab8500_usb_disconnect_irq,
716 IRQF_NO_SUSPEND | IRQF_SHARED, "usb-id-fall", ab);
717 if (err < 0) {
718 dev_err(ab->dev, "request_irq failed for ID fall irq\n");
719 return err;
720 }
721
722 irq = platform_get_irq_byname(pdev, "VBUS_DET_F");
723 if (irq < 0) {
724 dev_err(&pdev->dev, "VBUS fall irq not found\n");
725 return irq;
726 }
727 err = devm_request_threaded_irq(&pdev->dev, irq, NULL,
728 ab8500_usb_disconnect_irq,
729 IRQF_NO_SUSPEND | IRQF_SHARED, "usb-vbus-fall", ab);
730 if (err < 0) {
731 dev_err(ab->dev, "request_irq failed for Vbus fall irq\n");
732 return err;
733 }
734
735 return 0;
736}
737
738static int ab8500_usb_probe(struct platform_device *pdev)
739{
740 struct ab8500_usb *ab;
741 struct ab8500 *ab8500;
742 struct usb_otg *otg;
743 int err;
744 int rev;
745
746 ab8500 = dev_get_drvdata(pdev->dev.parent);
747 rev = abx500_get_chip_id(&pdev->dev);
748
749 if (is_ab8500_1p1_or_earlier(ab8500)) {
750 dev_err(&pdev->dev, "Unsupported AB8500 chip rev=%d\n", rev);
751 return -ENODEV;
752 }
753
754 ab = devm_kzalloc(&pdev->dev, sizeof(*ab), GFP_KERNEL);
755 if (!ab)
756 return -ENOMEM;
757
758 otg = devm_kzalloc(&pdev->dev, sizeof(*otg), GFP_KERNEL);
759 if (!otg)
760 return -ENOMEM;
761
762 ab->dev = &pdev->dev;
763 ab->ab8500 = ab8500;
764 ab->phy.dev = ab->dev;
765 ab->phy.otg = otg;
766 ab->phy.label = "ab8500";
767 ab->phy.set_suspend = ab8500_usb_set_suspend;
768 ab->phy.set_power = ab8500_usb_set_power;
769 ab->phy.state = OTG_STATE_UNDEFINED;
770
771 otg->phy = &ab->phy;
772 otg->set_host = ab8500_usb_set_host;
773 otg->set_peripheral = ab8500_usb_set_peripheral;
774
775 platform_set_drvdata(pdev, ab);
776
777 ATOMIC_INIT_NOTIFIER_HEAD(&ab->phy.notifier);
778
779 /* all: Disable phy when called from set_host and set_peripheral */
780 INIT_WORK(&ab->phy_dis_work, ab8500_usb_phy_disable_work);
781
782 err = ab8500_usb_regulator_get(ab);
783 if (err)
784 return err;
785
786 err = ab8500_usb_irq_setup(pdev, ab);
787 if (err < 0)
788 return err;
789
790 err = usb_add_phy(&ab->phy, USB_PHY_TYPE_USB2);
791 if (err) {
792 dev_err(&pdev->dev, "Can't register transceiver\n");
793 return err;
794 }
795
796 /* Phy tuning values for AB8500 */
797 if (!is_ab8500_2p0_or_earlier(ab->ab8500)) {
798 /* Enable the PBT/Bank 0x12 access */
799 err = abx500_set_register_interruptible(ab->dev,
800 AB8500_DEVELOPMENT, AB8500_BANK12_ACCESS, 0x01);
801 if (err < 0)
802 dev_err(ab->dev, "Failed to enable bank12 access err=%d\n",
803 err);
804
805 err = abx500_set_register_interruptible(ab->dev,
806 AB8500_DEBUG, AB8500_USB_PHY_TUNE1, 0xC8);
807 if (err < 0)
808 dev_err(ab->dev, "Failed to set PHY_TUNE1 register err=%d\n",
809 err);
810
811 err = abx500_set_register_interruptible(ab->dev,
812 AB8500_DEBUG, AB8500_USB_PHY_TUNE2, 0x00);
813 if (err < 0)
814 dev_err(ab->dev, "Failed to set PHY_TUNE2 register err=%d\n",
815 err);
816
817 err = abx500_set_register_interruptible(ab->dev,
818 AB8500_DEBUG, AB8500_USB_PHY_TUNE3, 0x78);
819 if (err < 0)
820 dev_err(ab->dev, "Failed to set PHY_TUNE3 regester err=%d\n",
821 err);
822
823 /* Switch to normal mode/disable Bank 0x12 access */
824 err = abx500_set_register_interruptible(ab->dev,
825 AB8500_DEVELOPMENT, AB8500_BANK12_ACCESS, 0x00);
826 if (err < 0)
827 dev_err(ab->dev, "Failed to switch bank12 access err=%d\n",
828 err);
829 }
830
831 /* Phy tuning values for AB8505 */
832 if (is_ab8505(ab->ab8500)) {
833 /* Enable the PBT/Bank 0x12 access */
834 err = abx500_mask_and_set_register_interruptible(ab->dev,
835 AB8500_DEVELOPMENT, AB8500_BANK12_ACCESS,
836 0x01, 0x01);
837 if (err < 0)
838 dev_err(ab->dev, "Failed to enable bank12 access err=%d\n",
839 err);
840
841 err = abx500_mask_and_set_register_interruptible(ab->dev,
842 AB8500_DEBUG, AB8500_USB_PHY_TUNE1,
843 0xC8, 0xC8);
844 if (err < 0)
845 dev_err(ab->dev, "Failed to set PHY_TUNE1 register err=%d\n",
846 err);
847
848 err = abx500_mask_and_set_register_interruptible(ab->dev,
849 AB8500_DEBUG, AB8500_USB_PHY_TUNE2,
850 0x60, 0x60);
851 if (err < 0)
852 dev_err(ab->dev, "Failed to set PHY_TUNE2 register err=%d\n",
853 err);
854
855 err = abx500_mask_and_set_register_interruptible(ab->dev,
856 AB8500_DEBUG, AB8500_USB_PHY_TUNE3,
857 0xFC, 0x80);
858
859 if (err < 0)
860 dev_err(ab->dev, "Failed to set PHY_TUNE3 regester err=%d\n",
861 err);
862
863 /* Switch to normal mode/disable Bank 0x12 access */
864 err = abx500_mask_and_set_register_interruptible(ab->dev,
865 AB8500_DEVELOPMENT, AB8500_BANK12_ACCESS,
866 0x00, 0x00);
867 if (err < 0)
868 dev_err(ab->dev, "Failed to switch bank12 access err=%d\n",
869 err);
870 }
871
872 /* Needed to enable ID detection. */
873 ab8500_usb_wd_workaround(ab);
874
875 abx500_usb_link_status_update(ab);
876
877 dev_info(&pdev->dev, "revision 0x%2x driver initialized\n", rev);
878
879 return 0;
880}
881
882static int ab8500_usb_remove(struct platform_device *pdev)
883{
884 struct ab8500_usb *ab = platform_get_drvdata(pdev);
885
886 cancel_work_sync(&ab->phy_dis_work);
887
888 usb_remove_phy(&ab->phy);
889
890 if (ab->mode == USB_HOST)
891 ab8500_usb_host_phy_dis(ab);
892 else if (ab->mode == USB_PERIPHERAL)
893 ab8500_usb_peri_phy_dis(ab);
894
895 platform_set_drvdata(pdev, NULL);
896
897 return 0;
898}
899
900static struct platform_driver ab8500_usb_driver = {
901 .probe = ab8500_usb_probe,
902 .remove = ab8500_usb_remove,
903 .driver = {
904 .name = "ab8500-usb",
905 .owner = THIS_MODULE,
906 },
907};
908
909static int __init ab8500_usb_init(void)
910{
911 return platform_driver_register(&ab8500_usb_driver);
912}
913subsys_initcall(ab8500_usb_init);
914
915static void __exit ab8500_usb_exit(void)
916{
917 platform_driver_unregister(&ab8500_usb_driver);
918}
919module_exit(ab8500_usb_exit);
920
921MODULE_ALIAS("platform:ab8500_usb");
922MODULE_AUTHOR("ST-Ericsson AB");
923MODULE_DESCRIPTION("AB8500 usb transceiver driver");
924MODULE_LICENSE("GPL");
diff --git a/drivers/usb/phy/phy-fsl-usb.c b/drivers/usb/phy/phy-fsl-usb.c
new file mode 100644
index 000000000000..97b9308507c3
--- /dev/null
+++ b/drivers/usb/phy/phy-fsl-usb.c
@@ -0,0 +1,1173 @@
1/*
2 * Copyright (C) 2007,2008 Freescale semiconductor, Inc.
3 *
4 * Author: Li Yang <LeoLi@freescale.com>
5 * Jerry Huang <Chang-Ming.Huang@freescale.com>
6 *
7 * Initialization based on code from Shlomi Gridish.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, write to the Free Software Foundation, Inc.,
21 * 675 Mass Ave, Cambridge, MA 02139, USA.
22 */
23
24#include <linux/module.h>
25#include <linux/kernel.h>
26#include <linux/delay.h>
27#include <linux/slab.h>
28#include <linux/proc_fs.h>
29#include <linux/errno.h>
30#include <linux/init.h>
31#include <linux/interrupt.h>
32#include <linux/io.h>
33#include <linux/timer.h>
34#include <linux/usb.h>
35#include <linux/device.h>
36#include <linux/usb/ch9.h>
37#include <linux/usb/gadget.h>
38#include <linux/workqueue.h>
39#include <linux/time.h>
40#include <linux/fsl_devices.h>
41#include <linux/platform_device.h>
42#include <linux/uaccess.h>
43
44#include <asm/unaligned.h>
45
46#include "phy-fsl-usb.h"
47
48#define DRIVER_VERSION "Rev. 1.55"
49#define DRIVER_AUTHOR "Jerry Huang/Li Yang"
50#define DRIVER_DESC "Freescale USB OTG Transceiver Driver"
51#define DRIVER_INFO DRIVER_DESC " " DRIVER_VERSION
52
53static const char driver_name[] = "fsl-usb2-otg";
54
55const pm_message_t otg_suspend_state = {
56 .event = 1,
57};
58
59#define HA_DATA_PULSE
60
61static struct usb_dr_mmap *usb_dr_regs;
62static struct fsl_otg *fsl_otg_dev;
63static int srp_wait_done;
64
65/* FSM timers */
66struct fsl_otg_timer *a_wait_vrise_tmr, *a_wait_bcon_tmr, *a_aidl_bdis_tmr,
67 *b_ase0_brst_tmr, *b_se0_srp_tmr;
68
69/* Driver specific timers */
70struct fsl_otg_timer *b_data_pulse_tmr, *b_vbus_pulse_tmr, *b_srp_fail_tmr,
71 *b_srp_wait_tmr, *a_wait_enum_tmr;
72
73static struct list_head active_timers;
74
75static struct fsl_otg_config fsl_otg_initdata = {
76 .otg_port = 1,
77};
78
79#ifdef CONFIG_PPC32
80static u32 _fsl_readl_be(const unsigned __iomem *p)
81{
82 return in_be32(p);
83}
84
85static u32 _fsl_readl_le(const unsigned __iomem *p)
86{
87 return in_le32(p);
88}
89
90static void _fsl_writel_be(u32 v, unsigned __iomem *p)
91{
92 out_be32(p, v);
93}
94
95static void _fsl_writel_le(u32 v, unsigned __iomem *p)
96{
97 out_le32(p, v);
98}
99
100static u32 (*_fsl_readl)(const unsigned __iomem *p);
101static void (*_fsl_writel)(u32 v, unsigned __iomem *p);
102
103#define fsl_readl(p) (*_fsl_readl)((p))
104#define fsl_writel(v, p) (*_fsl_writel)((v), (p))
105
106#else
107#define fsl_readl(addr) readl(addr)
108#define fsl_writel(val, addr) writel(val, addr)
109#endif /* CONFIG_PPC32 */
110
111/* Routines to access transceiver ULPI registers */
112u8 view_ulpi(u8 addr)
113{
114 u32 temp;
115
116 temp = 0x40000000 | (addr << 16);
117 fsl_writel(temp, &usb_dr_regs->ulpiview);
118 udelay(1000);
119 while (temp & 0x40)
120 temp = fsl_readl(&usb_dr_regs->ulpiview);
121 return (le32_to_cpu(temp) & 0x0000ff00) >> 8;
122}
123
124int write_ulpi(u8 addr, u8 data)
125{
126 u32 temp;
127
128 temp = 0x60000000 | (addr << 16) | data;
129 fsl_writel(temp, &usb_dr_regs->ulpiview);
130 return 0;
131}
132
133/* -------------------------------------------------------------*/
134/* Operations that will be called from OTG Finite State Machine */
135
136/* Charge vbus for vbus pulsing in SRP */
137void fsl_otg_chrg_vbus(int on)
138{
139 u32 tmp;
140
141 tmp = fsl_readl(&usb_dr_regs->otgsc) & ~OTGSC_INTSTS_MASK;
142
143 if (on)
144 /* stop discharging, start charging */
145 tmp = (tmp & ~OTGSC_CTRL_VBUS_DISCHARGE) |
146 OTGSC_CTRL_VBUS_CHARGE;
147 else
148 /* stop charging */
149 tmp &= ~OTGSC_CTRL_VBUS_CHARGE;
150
151 fsl_writel(tmp, &usb_dr_regs->otgsc);
152}
153
154/* Discharge vbus through a resistor to ground */
155void fsl_otg_dischrg_vbus(int on)
156{
157 u32 tmp;
158
159 tmp = fsl_readl(&usb_dr_regs->otgsc) & ~OTGSC_INTSTS_MASK;
160
161 if (on)
162 /* stop charging, start discharging */
163 tmp = (tmp & ~OTGSC_CTRL_VBUS_CHARGE) |
164 OTGSC_CTRL_VBUS_DISCHARGE;
165 else
166 /* stop discharging */
167 tmp &= ~OTGSC_CTRL_VBUS_DISCHARGE;
168
169 fsl_writel(tmp, &usb_dr_regs->otgsc);
170}
171
172/* A-device driver vbus, controlled through PP bit in PORTSC */
173void fsl_otg_drv_vbus(int on)
174{
175 u32 tmp;
176
177 if (on) {
178 tmp = fsl_readl(&usb_dr_regs->portsc) & ~PORTSC_W1C_BITS;
179 fsl_writel(tmp | PORTSC_PORT_POWER, &usb_dr_regs->portsc);
180 } else {
181 tmp = fsl_readl(&usb_dr_regs->portsc) &
182 ~PORTSC_W1C_BITS & ~PORTSC_PORT_POWER;
183 fsl_writel(tmp, &usb_dr_regs->portsc);
184 }
185}
186
187/*
188 * Pull-up D+, signalling connect by periperal. Also used in
189 * data-line pulsing in SRP
190 */
191void fsl_otg_loc_conn(int on)
192{
193 u32 tmp;
194
195 tmp = fsl_readl(&usb_dr_regs->otgsc) & ~OTGSC_INTSTS_MASK;
196
197 if (on)
198 tmp |= OTGSC_CTRL_DATA_PULSING;
199 else
200 tmp &= ~OTGSC_CTRL_DATA_PULSING;
201
202 fsl_writel(tmp, &usb_dr_regs->otgsc);
203}
204
205/*
206 * Generate SOF by host. This is controlled through suspend/resume the
207 * port. In host mode, controller will automatically send SOF.
208 * Suspend will block the data on the port.
209 */
210void fsl_otg_loc_sof(int on)
211{
212 u32 tmp;
213
214 tmp = fsl_readl(&fsl_otg_dev->dr_mem_map->portsc) & ~PORTSC_W1C_BITS;
215 if (on)
216 tmp |= PORTSC_PORT_FORCE_RESUME;
217 else
218 tmp |= PORTSC_PORT_SUSPEND;
219
220 fsl_writel(tmp, &fsl_otg_dev->dr_mem_map->portsc);
221
222}
223
224/* Start SRP pulsing by data-line pulsing, followed with v-bus pulsing. */
225void fsl_otg_start_pulse(void)
226{
227 u32 tmp;
228
229 srp_wait_done = 0;
230#ifdef HA_DATA_PULSE
231 tmp = fsl_readl(&usb_dr_regs->otgsc) & ~OTGSC_INTSTS_MASK;
232 tmp |= OTGSC_HA_DATA_PULSE;
233 fsl_writel(tmp, &usb_dr_regs->otgsc);
234#else
235 fsl_otg_loc_conn(1);
236#endif
237
238 fsl_otg_add_timer(b_data_pulse_tmr);
239}
240
241void b_data_pulse_end(unsigned long foo)
242{
243#ifdef HA_DATA_PULSE
244#else
245 fsl_otg_loc_conn(0);
246#endif
247
248 /* Do VBUS pulse after data pulse */
249 fsl_otg_pulse_vbus();
250}
251
252void fsl_otg_pulse_vbus(void)
253{
254 srp_wait_done = 0;
255 fsl_otg_chrg_vbus(1);
256 /* start the timer to end vbus charge */
257 fsl_otg_add_timer(b_vbus_pulse_tmr);
258}
259
260void b_vbus_pulse_end(unsigned long foo)
261{
262 fsl_otg_chrg_vbus(0);
263
264 /*
265 * As USB3300 using the same a_sess_vld and b_sess_vld voltage
266 * we need to discharge the bus for a while to distinguish
267 * residual voltage of vbus pulsing and A device pull up
268 */
269 fsl_otg_dischrg_vbus(1);
270 fsl_otg_add_timer(b_srp_wait_tmr);
271}
272
273void b_srp_end(unsigned long foo)
274{
275 fsl_otg_dischrg_vbus(0);
276 srp_wait_done = 1;
277
278 if ((fsl_otg_dev->phy.state == OTG_STATE_B_SRP_INIT) &&
279 fsl_otg_dev->fsm.b_sess_vld)
280 fsl_otg_dev->fsm.b_srp_done = 1;
281}
282
283/*
284 * Workaround for a_host suspending too fast. When a_bus_req=0,
285 * a_host will start by SRP. It needs to set b_hnp_enable before
286 * actually suspending to start HNP
287 */
288void a_wait_enum(unsigned long foo)
289{
290 VDBG("a_wait_enum timeout\n");
291 if (!fsl_otg_dev->phy.otg->host->b_hnp_enable)
292 fsl_otg_add_timer(a_wait_enum_tmr);
293 else
294 otg_statemachine(&fsl_otg_dev->fsm);
295}
296
297/* The timeout callback function to set time out bit */
298void set_tmout(unsigned long indicator)
299{
300 *(int *)indicator = 1;
301}
302
303/* Initialize timers */
304int fsl_otg_init_timers(struct otg_fsm *fsm)
305{
306 /* FSM used timers */
307 a_wait_vrise_tmr = otg_timer_initializer(&set_tmout, TA_WAIT_VRISE,
308 (unsigned long)&fsm->a_wait_vrise_tmout);
309 if (!a_wait_vrise_tmr)
310 return -ENOMEM;
311
312 a_wait_bcon_tmr = otg_timer_initializer(&set_tmout, TA_WAIT_BCON,
313 (unsigned long)&fsm->a_wait_bcon_tmout);
314 if (!a_wait_bcon_tmr)
315 return -ENOMEM;
316
317 a_aidl_bdis_tmr = otg_timer_initializer(&set_tmout, TA_AIDL_BDIS,
318 (unsigned long)&fsm->a_aidl_bdis_tmout);
319 if (!a_aidl_bdis_tmr)
320 return -ENOMEM;
321
322 b_ase0_brst_tmr = otg_timer_initializer(&set_tmout, TB_ASE0_BRST,
323 (unsigned long)&fsm->b_ase0_brst_tmout);
324 if (!b_ase0_brst_tmr)
325 return -ENOMEM;
326
327 b_se0_srp_tmr = otg_timer_initializer(&set_tmout, TB_SE0_SRP,
328 (unsigned long)&fsm->b_se0_srp);
329 if (!b_se0_srp_tmr)
330 return -ENOMEM;
331
332 b_srp_fail_tmr = otg_timer_initializer(&set_tmout, TB_SRP_FAIL,
333 (unsigned long)&fsm->b_srp_done);
334 if (!b_srp_fail_tmr)
335 return -ENOMEM;
336
337 a_wait_enum_tmr = otg_timer_initializer(&a_wait_enum, 10,
338 (unsigned long)&fsm);
339 if (!a_wait_enum_tmr)
340 return -ENOMEM;
341
342 /* device driver used timers */
343 b_srp_wait_tmr = otg_timer_initializer(&b_srp_end, TB_SRP_WAIT, 0);
344 if (!b_srp_wait_tmr)
345 return -ENOMEM;
346
347 b_data_pulse_tmr = otg_timer_initializer(&b_data_pulse_end,
348 TB_DATA_PLS, 0);
349 if (!b_data_pulse_tmr)
350 return -ENOMEM;
351
352 b_vbus_pulse_tmr = otg_timer_initializer(&b_vbus_pulse_end,
353 TB_VBUS_PLS, 0);
354 if (!b_vbus_pulse_tmr)
355 return -ENOMEM;
356
357 return 0;
358}
359
360/* Uninitialize timers */
361void fsl_otg_uninit_timers(void)
362{
363 /* FSM used timers */
364 kfree(a_wait_vrise_tmr);
365 kfree(a_wait_bcon_tmr);
366 kfree(a_aidl_bdis_tmr);
367 kfree(b_ase0_brst_tmr);
368 kfree(b_se0_srp_tmr);
369 kfree(b_srp_fail_tmr);
370 kfree(a_wait_enum_tmr);
371
372 /* device driver used timers */
373 kfree(b_srp_wait_tmr);
374 kfree(b_data_pulse_tmr);
375 kfree(b_vbus_pulse_tmr);
376}
377
378/* Add timer to timer list */
379void fsl_otg_add_timer(void *gtimer)
380{
381 struct fsl_otg_timer *timer = gtimer;
382 struct fsl_otg_timer *tmp_timer;
383
384 /*
385 * Check if the timer is already in the active list,
386 * if so update timer count
387 */
388 list_for_each_entry(tmp_timer, &active_timers, list)
389 if (tmp_timer == timer) {
390 timer->count = timer->expires;
391 return;
392 }
393 timer->count = timer->expires;
394 list_add_tail(&timer->list, &active_timers);
395}
396
397/* Remove timer from the timer list; clear timeout status */
398void fsl_otg_del_timer(void *gtimer)
399{
400 struct fsl_otg_timer *timer = gtimer;
401 struct fsl_otg_timer *tmp_timer, *del_tmp;
402
403 list_for_each_entry_safe(tmp_timer, del_tmp, &active_timers, list)
404 if (tmp_timer == timer)
405 list_del(&timer->list);
406}
407
408/*
409 * Reduce timer count by 1, and find timeout conditions.
410 * Called by fsl_otg 1ms timer interrupt
411 */
412int fsl_otg_tick_timer(void)
413{
414 struct fsl_otg_timer *tmp_timer, *del_tmp;
415 int expired = 0;
416
417 list_for_each_entry_safe(tmp_timer, del_tmp, &active_timers, list) {
418 tmp_timer->count--;
419 /* check if timer expires */
420 if (!tmp_timer->count) {
421 list_del(&tmp_timer->list);
422 tmp_timer->function(tmp_timer->data);
423 expired = 1;
424 }
425 }
426
427 return expired;
428}
429
430/* Reset controller, not reset the bus */
431void otg_reset_controller(void)
432{
433 u32 command;
434
435 command = fsl_readl(&usb_dr_regs->usbcmd);
436 command |= (1 << 1);
437 fsl_writel(command, &usb_dr_regs->usbcmd);
438 while (fsl_readl(&usb_dr_regs->usbcmd) & (1 << 1))
439 ;
440}
441
442/* Call suspend/resume routines in host driver */
443int fsl_otg_start_host(struct otg_fsm *fsm, int on)
444{
445 struct usb_otg *otg = fsm->otg;
446 struct device *dev;
447 struct fsl_otg *otg_dev = container_of(otg->phy, struct fsl_otg, phy);
448 u32 retval = 0;
449
450 if (!otg->host)
451 return -ENODEV;
452 dev = otg->host->controller;
453
454 /*
455 * Update a_vbus_vld state as a_vbus_vld int is disabled
456 * in device mode
457 */
458 fsm->a_vbus_vld =
459 !!(fsl_readl(&usb_dr_regs->otgsc) & OTGSC_STS_A_VBUS_VALID);
460 if (on) {
461 /* start fsl usb host controller */
462 if (otg_dev->host_working)
463 goto end;
464 else {
465 otg_reset_controller();
466 VDBG("host on......\n");
467 if (dev->driver->pm && dev->driver->pm->resume) {
468 retval = dev->driver->pm->resume(dev);
469 if (fsm->id) {
470 /* default-b */
471 fsl_otg_drv_vbus(1);
472 /*
473 * Workaround: b_host can't driver
474 * vbus, but PP in PORTSC needs to
475 * be 1 for host to work.
476 * So we set drv_vbus bit in
477 * transceiver to 0 thru ULPI.
478 */
479 write_ulpi(0x0c, 0x20);
480 }
481 }
482
483 otg_dev->host_working = 1;
484 }
485 } else {
486 /* stop fsl usb host controller */
487 if (!otg_dev->host_working)
488 goto end;
489 else {
490 VDBG("host off......\n");
491 if (dev && dev->driver) {
492 if (dev->driver->pm && dev->driver->pm->suspend)
493 retval = dev->driver->pm->suspend(dev);
494 if (fsm->id)
495 /* default-b */
496 fsl_otg_drv_vbus(0);
497 }
498 otg_dev->host_working = 0;
499 }
500 }
501end:
502 return retval;
503}
504
505/*
506 * Call suspend and resume function in udc driver
507 * to stop and start udc driver.
508 */
509int fsl_otg_start_gadget(struct otg_fsm *fsm, int on)
510{
511 struct usb_otg *otg = fsm->otg;
512 struct device *dev;
513
514 if (!otg->gadget || !otg->gadget->dev.parent)
515 return -ENODEV;
516
517 VDBG("gadget %s\n", on ? "on" : "off");
518 dev = otg->gadget->dev.parent;
519
520 if (on) {
521 if (dev->driver->resume)
522 dev->driver->resume(dev);
523 } else {
524 if (dev->driver->suspend)
525 dev->driver->suspend(dev, otg_suspend_state);
526 }
527
528 return 0;
529}
530
531/*
532 * Called by initialization code of host driver. Register host controller
533 * to the OTG. Suspend host for OTG role detection.
534 */
535static int fsl_otg_set_host(struct usb_otg *otg, struct usb_bus *host)
536{
537 struct fsl_otg *otg_dev;
538
539 if (!otg)
540 return -ENODEV;
541
542 otg_dev = container_of(otg->phy, struct fsl_otg, phy);
543 if (otg_dev != fsl_otg_dev)
544 return -ENODEV;
545
546 otg->host = host;
547
548 otg_dev->fsm.a_bus_drop = 0;
549 otg_dev->fsm.a_bus_req = 1;
550
551 if (host) {
552 VDBG("host off......\n");
553
554 otg->host->otg_port = fsl_otg_initdata.otg_port;
555 otg->host->is_b_host = otg_dev->fsm.id;
556 /*
557 * must leave time for khubd to finish its thing
558 * before yanking the host driver out from under it,
559 * so suspend the host after a short delay.
560 */
561 otg_dev->host_working = 1;
562 schedule_delayed_work(&otg_dev->otg_event, 100);
563 return 0;
564 } else {
565 /* host driver going away */
566 if (!(fsl_readl(&otg_dev->dr_mem_map->otgsc) &
567 OTGSC_STS_USB_ID)) {
568 /* Mini-A cable connected */
569 struct otg_fsm *fsm = &otg_dev->fsm;
570
571 otg->phy->state = OTG_STATE_UNDEFINED;
572 fsm->protocol = PROTO_UNDEF;
573 }
574 }
575
576 otg_dev->host_working = 0;
577
578 otg_statemachine(&otg_dev->fsm);
579
580 return 0;
581}
582
583/* Called by initialization code of udc. Register udc to OTG. */
584static int fsl_otg_set_peripheral(struct usb_otg *otg,
585 struct usb_gadget *gadget)
586{
587 struct fsl_otg *otg_dev;
588
589 if (!otg)
590 return -ENODEV;
591
592 otg_dev = container_of(otg->phy, struct fsl_otg, phy);
593 VDBG("otg_dev 0x%x\n", (int)otg_dev);
594 VDBG("fsl_otg_dev 0x%x\n", (int)fsl_otg_dev);
595 if (otg_dev != fsl_otg_dev)
596 return -ENODEV;
597
598 if (!gadget) {
599 if (!otg->default_a)
600 otg->gadget->ops->vbus_draw(otg->gadget, 0);
601 usb_gadget_vbus_disconnect(otg->gadget);
602 otg->gadget = 0;
603 otg_dev->fsm.b_bus_req = 0;
604 otg_statemachine(&otg_dev->fsm);
605 return 0;
606 }
607
608 otg->gadget = gadget;
609 otg->gadget->is_a_peripheral = !otg_dev->fsm.id;
610
611 otg_dev->fsm.b_bus_req = 1;
612
613 /* start the gadget right away if the ID pin says Mini-B */
614 DBG("ID pin=%d\n", otg_dev->fsm.id);
615 if (otg_dev->fsm.id == 1) {
616 fsl_otg_start_host(&otg_dev->fsm, 0);
617 otg_drv_vbus(&otg_dev->fsm, 0);
618 fsl_otg_start_gadget(&otg_dev->fsm, 1);
619 }
620
621 return 0;
622}
623
624/* Set OTG port power, only for B-device */
625static int fsl_otg_set_power(struct usb_phy *phy, unsigned mA)
626{
627 if (!fsl_otg_dev)
628 return -ENODEV;
629 if (phy->state == OTG_STATE_B_PERIPHERAL)
630 pr_info("FSL OTG: Draw %d mA\n", mA);
631
632 return 0;
633}
634
635/*
636 * Delayed pin detect interrupt processing.
637 *
638 * When the Mini-A cable is disconnected from the board,
639 * the pin-detect interrupt happens before the disconnect
640 * interrupts for the connected device(s). In order to
641 * process the disconnect interrupt(s) prior to switching
642 * roles, the pin-detect interrupts are delayed, and handled
643 * by this routine.
644 */
645static void fsl_otg_event(struct work_struct *work)
646{
647 struct fsl_otg *og = container_of(work, struct fsl_otg, otg_event.work);
648 struct otg_fsm *fsm = &og->fsm;
649
650 if (fsm->id) { /* switch to gadget */
651 fsl_otg_start_host(fsm, 0);
652 otg_drv_vbus(fsm, 0);
653 fsl_otg_start_gadget(fsm, 1);
654 }
655}
656
657/* B-device start SRP */
658static int fsl_otg_start_srp(struct usb_otg *otg)
659{
660 struct fsl_otg *otg_dev;
661
662 if (!otg || otg->phy->state != OTG_STATE_B_IDLE)
663 return -ENODEV;
664
665 otg_dev = container_of(otg->phy, struct fsl_otg, phy);
666 if (otg_dev != fsl_otg_dev)
667 return -ENODEV;
668
669 otg_dev->fsm.b_bus_req = 1;
670 otg_statemachine(&otg_dev->fsm);
671
672 return 0;
673}
674
675/* A_host suspend will call this function to start hnp */
676static int fsl_otg_start_hnp(struct usb_otg *otg)
677{
678 struct fsl_otg *otg_dev;
679
680 if (!otg)
681 return -ENODEV;
682
683 otg_dev = container_of(otg->phy, struct fsl_otg, phy);
684 if (otg_dev != fsl_otg_dev)
685 return -ENODEV;
686
687 DBG("start_hnp...n");
688
689 /* clear a_bus_req to enter a_suspend state */
690 otg_dev->fsm.a_bus_req = 0;
691 otg_statemachine(&otg_dev->fsm);
692
693 return 0;
694}
695
696/*
697 * Interrupt handler. OTG/host/peripheral share the same int line.
698 * OTG driver clears OTGSC interrupts and leaves USB interrupts
699 * intact. It needs to have knowledge of some USB interrupts
700 * such as port change.
701 */
702irqreturn_t fsl_otg_isr(int irq, void *dev_id)
703{
704 struct otg_fsm *fsm = &((struct fsl_otg *)dev_id)->fsm;
705 struct usb_otg *otg = ((struct fsl_otg *)dev_id)->phy.otg;
706 u32 otg_int_src, otg_sc;
707
708 otg_sc = fsl_readl(&usb_dr_regs->otgsc);
709 otg_int_src = otg_sc & OTGSC_INTSTS_MASK & (otg_sc >> 8);
710
711 /* Only clear otg interrupts */
712 fsl_writel(otg_sc, &usb_dr_regs->otgsc);
713
714 /*FIXME: ID change not generate when init to 0 */
715 fsm->id = (otg_sc & OTGSC_STS_USB_ID) ? 1 : 0;
716 otg->default_a = (fsm->id == 0);
717
718 /* process OTG interrupts */
719 if (otg_int_src) {
720 if (otg_int_src & OTGSC_INTSTS_USB_ID) {
721 fsm->id = (otg_sc & OTGSC_STS_USB_ID) ? 1 : 0;
722 otg->default_a = (fsm->id == 0);
723 /* clear conn information */
724 if (fsm->id)
725 fsm->b_conn = 0;
726 else
727 fsm->a_conn = 0;
728
729 if (otg->host)
730 otg->host->is_b_host = fsm->id;
731 if (otg->gadget)
732 otg->gadget->is_a_peripheral = !fsm->id;
733 VDBG("ID int (ID is %d)\n", fsm->id);
734
735 if (fsm->id) { /* switch to gadget */
736 schedule_delayed_work(
737 &((struct fsl_otg *)dev_id)->otg_event,
738 100);
739 } else { /* switch to host */
740 cancel_delayed_work(&
741 ((struct fsl_otg *)dev_id)->
742 otg_event);
743 fsl_otg_start_gadget(fsm, 0);
744 otg_drv_vbus(fsm, 1);
745 fsl_otg_start_host(fsm, 1);
746 }
747 return IRQ_HANDLED;
748 }
749 }
750 return IRQ_NONE;
751}
752
753static struct otg_fsm_ops fsl_otg_ops = {
754 .chrg_vbus = fsl_otg_chrg_vbus,
755 .drv_vbus = fsl_otg_drv_vbus,
756 .loc_conn = fsl_otg_loc_conn,
757 .loc_sof = fsl_otg_loc_sof,
758 .start_pulse = fsl_otg_start_pulse,
759
760 .add_timer = fsl_otg_add_timer,
761 .del_timer = fsl_otg_del_timer,
762
763 .start_host = fsl_otg_start_host,
764 .start_gadget = fsl_otg_start_gadget,
765};
766
767/* Initialize the global variable fsl_otg_dev and request IRQ for OTG */
768static int fsl_otg_conf(struct platform_device *pdev)
769{
770 struct fsl_otg *fsl_otg_tc;
771 int status;
772
773 if (fsl_otg_dev)
774 return 0;
775
776 /* allocate space to fsl otg device */
777 fsl_otg_tc = kzalloc(sizeof(struct fsl_otg), GFP_KERNEL);
778 if (!fsl_otg_tc)
779 return -ENOMEM;
780
781 fsl_otg_tc->phy.otg = kzalloc(sizeof(struct usb_otg), GFP_KERNEL);
782 if (!fsl_otg_tc->phy.otg) {
783 kfree(fsl_otg_tc);
784 return -ENOMEM;
785 }
786
787 INIT_DELAYED_WORK(&fsl_otg_tc->otg_event, fsl_otg_event);
788
789 INIT_LIST_HEAD(&active_timers);
790 status = fsl_otg_init_timers(&fsl_otg_tc->fsm);
791 if (status) {
792 pr_info("Couldn't init OTG timers\n");
793 goto err;
794 }
795 spin_lock_init(&fsl_otg_tc->fsm.lock);
796
797 /* Set OTG state machine operations */
798 fsl_otg_tc->fsm.ops = &fsl_otg_ops;
799
800 /* initialize the otg structure */
801 fsl_otg_tc->phy.label = DRIVER_DESC;
802 fsl_otg_tc->phy.set_power = fsl_otg_set_power;
803
804 fsl_otg_tc->phy.otg->phy = &fsl_otg_tc->phy;
805 fsl_otg_tc->phy.otg->set_host = fsl_otg_set_host;
806 fsl_otg_tc->phy.otg->set_peripheral = fsl_otg_set_peripheral;
807 fsl_otg_tc->phy.otg->start_hnp = fsl_otg_start_hnp;
808 fsl_otg_tc->phy.otg->start_srp = fsl_otg_start_srp;
809
810 fsl_otg_dev = fsl_otg_tc;
811
812 /* Store the otg transceiver */
813 status = usb_add_phy(&fsl_otg_tc->phy, USB_PHY_TYPE_USB2);
814 if (status) {
815 pr_warn(FSL_OTG_NAME ": unable to register OTG transceiver.\n");
816 goto err;
817 }
818
819 return 0;
820err:
821 fsl_otg_uninit_timers();
822 kfree(fsl_otg_tc->phy.otg);
823 kfree(fsl_otg_tc);
824 return status;
825}
826
827/* OTG Initialization */
828int usb_otg_start(struct platform_device *pdev)
829{
830 struct fsl_otg *p_otg;
831 struct usb_phy *otg_trans = usb_get_phy(USB_PHY_TYPE_USB2);
832 struct otg_fsm *fsm;
833 int status;
834 struct resource *res;
835 u32 temp;
836 struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data;
837
838 p_otg = container_of(otg_trans, struct fsl_otg, phy);
839 fsm = &p_otg->fsm;
840
841 /* Initialize the state machine structure with default values */
842 SET_OTG_STATE(otg_trans, OTG_STATE_UNDEFINED);
843 fsm->otg = p_otg->phy.otg;
844
845 /* We don't require predefined MEM/IRQ resource index */
846 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
847 if (!res)
848 return -ENXIO;
849
850 /* We don't request_mem_region here to enable resource sharing
851 * with host/device */
852
853 usb_dr_regs = ioremap(res->start, sizeof(struct usb_dr_mmap));
854 p_otg->dr_mem_map = (struct usb_dr_mmap *)usb_dr_regs;
855 pdata->regs = (void *)usb_dr_regs;
856
857 if (pdata->init && pdata->init(pdev) != 0)
858 return -EINVAL;
859
860 if (pdata->big_endian_mmio) {
861 _fsl_readl = _fsl_readl_be;
862 _fsl_writel = _fsl_writel_be;
863 } else {
864 _fsl_readl = _fsl_readl_le;
865 _fsl_writel = _fsl_writel_le;
866 }
867
868 /* request irq */
869 p_otg->irq = platform_get_irq(pdev, 0);
870 status = request_irq(p_otg->irq, fsl_otg_isr,
871 IRQF_SHARED, driver_name, p_otg);
872 if (status) {
873 dev_dbg(p_otg->phy.dev, "can't get IRQ %d, error %d\n",
874 p_otg->irq, status);
875 iounmap(p_otg->dr_mem_map);
876 kfree(p_otg->phy.otg);
877 kfree(p_otg);
878 return status;
879 }
880
881 /* stop the controller */
882 temp = fsl_readl(&p_otg->dr_mem_map->usbcmd);
883 temp &= ~USB_CMD_RUN_STOP;
884 fsl_writel(temp, &p_otg->dr_mem_map->usbcmd);
885
886 /* reset the controller */
887 temp = fsl_readl(&p_otg->dr_mem_map->usbcmd);
888 temp |= USB_CMD_CTRL_RESET;
889 fsl_writel(temp, &p_otg->dr_mem_map->usbcmd);
890
891 /* wait reset completed */
892 while (fsl_readl(&p_otg->dr_mem_map->usbcmd) & USB_CMD_CTRL_RESET)
893 ;
894
895 /* configure the VBUSHS as IDLE(both host and device) */
896 temp = USB_MODE_STREAM_DISABLE | (pdata->es ? USB_MODE_ES : 0);
897 fsl_writel(temp, &p_otg->dr_mem_map->usbmode);
898
899 /* configure PHY interface */
900 temp = fsl_readl(&p_otg->dr_mem_map->portsc);
901 temp &= ~(PORTSC_PHY_TYPE_SEL | PORTSC_PTW);
902 switch (pdata->phy_mode) {
903 case FSL_USB2_PHY_ULPI:
904 temp |= PORTSC_PTS_ULPI;
905 break;
906 case FSL_USB2_PHY_UTMI_WIDE:
907 temp |= PORTSC_PTW_16BIT;
908 /* fall through */
909 case FSL_USB2_PHY_UTMI:
910 temp |= PORTSC_PTS_UTMI;
911 /* fall through */
912 default:
913 break;
914 }
915 fsl_writel(temp, &p_otg->dr_mem_map->portsc);
916
917 if (pdata->have_sysif_regs) {
918 /* configure control enable IO output, big endian register */
919 temp = __raw_readl(&p_otg->dr_mem_map->control);
920 temp |= USB_CTRL_IOENB;
921 __raw_writel(temp, &p_otg->dr_mem_map->control);
922 }
923
924 /* disable all interrupt and clear all OTGSC status */
925 temp = fsl_readl(&p_otg->dr_mem_map->otgsc);
926 temp &= ~OTGSC_INTERRUPT_ENABLE_BITS_MASK;
927 temp |= OTGSC_INTERRUPT_STATUS_BITS_MASK | OTGSC_CTRL_VBUS_DISCHARGE;
928 fsl_writel(temp, &p_otg->dr_mem_map->otgsc);
929
930 /*
931 * The identification (id) input is FALSE when a Mini-A plug is inserted
932 * in the devices Mini-AB receptacle. Otherwise, this input is TRUE.
933 * Also: record initial state of ID pin
934 */
935 if (fsl_readl(&p_otg->dr_mem_map->otgsc) & OTGSC_STS_USB_ID) {
936 p_otg->phy.state = OTG_STATE_UNDEFINED;
937 p_otg->fsm.id = 1;
938 } else {
939 p_otg->phy.state = OTG_STATE_A_IDLE;
940 p_otg->fsm.id = 0;
941 }
942
943 DBG("initial ID pin=%d\n", p_otg->fsm.id);
944
945 /* enable OTG ID pin interrupt */
946 temp = fsl_readl(&p_otg->dr_mem_map->otgsc);
947 temp |= OTGSC_INTR_USB_ID_EN;
948 temp &= ~(OTGSC_CTRL_VBUS_DISCHARGE | OTGSC_INTR_1MS_TIMER_EN);
949 fsl_writel(temp, &p_otg->dr_mem_map->otgsc);
950
951 return 0;
952}
953
954/*
955 * state file in sysfs
956 */
957static int show_fsl_usb2_otg_state(struct device *dev,
958 struct device_attribute *attr, char *buf)
959{
960 struct otg_fsm *fsm = &fsl_otg_dev->fsm;
961 char *next = buf;
962 unsigned size = PAGE_SIZE;
963 unsigned long flags;
964 int t;
965
966 spin_lock_irqsave(&fsm->lock, flags);
967
968 /* basic driver infomation */
969 t = scnprintf(next, size,
970 DRIVER_DESC "\n" "fsl_usb2_otg version: %s\n\n",
971 DRIVER_VERSION);
972 size -= t;
973 next += t;
974
975 /* Registers */
976 t = scnprintf(next, size,
977 "OTGSC: 0x%08x\n"
978 "PORTSC: 0x%08x\n"
979 "USBMODE: 0x%08x\n"
980 "USBCMD: 0x%08x\n"
981 "USBSTS: 0x%08x\n"
982 "USBINTR: 0x%08x\n",
983 fsl_readl(&usb_dr_regs->otgsc),
984 fsl_readl(&usb_dr_regs->portsc),
985 fsl_readl(&usb_dr_regs->usbmode),
986 fsl_readl(&usb_dr_regs->usbcmd),
987 fsl_readl(&usb_dr_regs->usbsts),
988 fsl_readl(&usb_dr_regs->usbintr));
989 size -= t;
990 next += t;
991
992 /* State */
993 t = scnprintf(next, size,
994 "OTG state: %s\n\n",
995 usb_otg_state_string(fsl_otg_dev->phy.state));
996 size -= t;
997 next += t;
998
999 /* State Machine Variables */
1000 t = scnprintf(next, size,
1001 "a_bus_req: %d\n"
1002 "b_bus_req: %d\n"
1003 "a_bus_resume: %d\n"
1004 "a_bus_suspend: %d\n"
1005 "a_conn: %d\n"
1006 "a_sess_vld: %d\n"
1007 "a_srp_det: %d\n"
1008 "a_vbus_vld: %d\n"
1009 "b_bus_resume: %d\n"
1010 "b_bus_suspend: %d\n"
1011 "b_conn: %d\n"
1012 "b_se0_srp: %d\n"
1013 "b_sess_end: %d\n"
1014 "b_sess_vld: %d\n"
1015 "id: %d\n",
1016 fsm->a_bus_req,
1017 fsm->b_bus_req,
1018 fsm->a_bus_resume,
1019 fsm->a_bus_suspend,
1020 fsm->a_conn,
1021 fsm->a_sess_vld,
1022 fsm->a_srp_det,
1023 fsm->a_vbus_vld,
1024 fsm->b_bus_resume,
1025 fsm->b_bus_suspend,
1026 fsm->b_conn,
1027 fsm->b_se0_srp,
1028 fsm->b_sess_end,
1029 fsm->b_sess_vld,
1030 fsm->id);
1031 size -= t;
1032 next += t;
1033
1034 spin_unlock_irqrestore(&fsm->lock, flags);
1035
1036 return PAGE_SIZE - size;
1037}
1038
1039static DEVICE_ATTR(fsl_usb2_otg_state, S_IRUGO, show_fsl_usb2_otg_state, NULL);
1040
1041
1042/* Char driver interface to control some OTG input */
1043
1044/*
1045 * Handle some ioctl command, such as get otg
1046 * status and set host suspend
1047 */
1048static long fsl_otg_ioctl(struct file *file, unsigned int cmd,
1049 unsigned long arg)
1050{
1051 u32 retval = 0;
1052
1053 switch (cmd) {
1054 case GET_OTG_STATUS:
1055 retval = fsl_otg_dev->host_working;
1056 break;
1057
1058 case SET_A_SUSPEND_REQ:
1059 fsl_otg_dev->fsm.a_suspend_req = arg;
1060 break;
1061
1062 case SET_A_BUS_DROP:
1063 fsl_otg_dev->fsm.a_bus_drop = arg;
1064 break;
1065
1066 case SET_A_BUS_REQ:
1067 fsl_otg_dev->fsm.a_bus_req = arg;
1068 break;
1069
1070 case SET_B_BUS_REQ:
1071 fsl_otg_dev->fsm.b_bus_req = arg;
1072 break;
1073
1074 default:
1075 break;
1076 }
1077
1078 otg_statemachine(&fsl_otg_dev->fsm);
1079
1080 return retval;
1081}
1082
1083static int fsl_otg_open(struct inode *inode, struct file *file)
1084{
1085 return 0;
1086}
1087
1088static int fsl_otg_release(struct inode *inode, struct file *file)
1089{
1090 return 0;
1091}
1092
1093static const struct file_operations otg_fops = {
1094 .owner = THIS_MODULE,
1095 .llseek = NULL,
1096 .read = NULL,
1097 .write = NULL,
1098 .unlocked_ioctl = fsl_otg_ioctl,
1099 .open = fsl_otg_open,
1100 .release = fsl_otg_release,
1101};
1102
1103static int fsl_otg_probe(struct platform_device *pdev)
1104{
1105 int ret;
1106
1107 if (!pdev->dev.platform_data)
1108 return -ENODEV;
1109
1110 /* configure the OTG */
1111 ret = fsl_otg_conf(pdev);
1112 if (ret) {
1113 dev_err(&pdev->dev, "Couldn't configure OTG module\n");
1114 return ret;
1115 }
1116
1117 /* start OTG */
1118 ret = usb_otg_start(pdev);
1119 if (ret) {
1120 dev_err(&pdev->dev, "Can't init FSL OTG device\n");
1121 return ret;
1122 }
1123
1124 ret = register_chrdev(FSL_OTG_MAJOR, FSL_OTG_NAME, &otg_fops);
1125 if (ret) {
1126 dev_err(&pdev->dev, "unable to register FSL OTG device\n");
1127 return ret;
1128 }
1129
1130 ret = device_create_file(&pdev->dev, &dev_attr_fsl_usb2_otg_state);
1131 if (ret)
1132 dev_warn(&pdev->dev, "Can't register sysfs attribute\n");
1133
1134 return ret;
1135}
1136
1137static int fsl_otg_remove(struct platform_device *pdev)
1138{
1139 struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data;
1140
1141 usb_remove_phy(&fsl_otg_dev->phy);
1142 free_irq(fsl_otg_dev->irq, fsl_otg_dev);
1143
1144 iounmap((void *)usb_dr_regs);
1145
1146 fsl_otg_uninit_timers();
1147 kfree(fsl_otg_dev->phy.otg);
1148 kfree(fsl_otg_dev);
1149
1150 device_remove_file(&pdev->dev, &dev_attr_fsl_usb2_otg_state);
1151
1152 unregister_chrdev(FSL_OTG_MAJOR, FSL_OTG_NAME);
1153
1154 if (pdata->exit)
1155 pdata->exit(pdev);
1156
1157 return 0;
1158}
1159
1160struct platform_driver fsl_otg_driver = {
1161 .probe = fsl_otg_probe,
1162 .remove = fsl_otg_remove,
1163 .driver = {
1164 .name = driver_name,
1165 .owner = THIS_MODULE,
1166 },
1167};
1168
1169module_platform_driver(fsl_otg_driver);
1170
1171MODULE_DESCRIPTION(DRIVER_INFO);
1172MODULE_AUTHOR(DRIVER_AUTHOR);
1173MODULE_LICENSE("GPL");
diff --git a/drivers/usb/phy/phy-fsl-usb.h b/drivers/usb/phy/phy-fsl-usb.h
new file mode 100644
index 000000000000..ca266280895d
--- /dev/null
+++ b/drivers/usb/phy/phy-fsl-usb.h
@@ -0,0 +1,406 @@
1/* Copyright (C) 2007,2008 Freescale Semiconductor, Inc.
2 *
3 * This program is free software; you can redistribute it and/or modify it
4 * under the terms of the GNU General Public License as published by the
5 * Free Software Foundation; either version 2 of the License, or (at your
6 * option) any later version.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License along
14 * with this program; if not, write to the Free Software Foundation, Inc.,
15 * 675 Mass Ave, Cambridge, MA 02139, USA.
16 */
17
18#include "otg_fsm.h"
19#include <linux/usb/otg.h>
20#include <linux/ioctl.h>
21
22/* USB Command Register Bit Masks */
23#define USB_CMD_RUN_STOP (0x1<<0)
24#define USB_CMD_CTRL_RESET (0x1<<1)
25#define USB_CMD_PERIODIC_SCHEDULE_EN (0x1<<4)
26#define USB_CMD_ASYNC_SCHEDULE_EN (0x1<<5)
27#define USB_CMD_INT_AA_DOORBELL (0x1<<6)
28#define USB_CMD_ASP (0x3<<8)
29#define USB_CMD_ASYNC_SCH_PARK_EN (0x1<<11)
30#define USB_CMD_SUTW (0x1<<13)
31#define USB_CMD_ATDTW (0x1<<14)
32#define USB_CMD_ITC (0xFF<<16)
33
34/* bit 15,3,2 are frame list size */
35#define USB_CMD_FRAME_SIZE_1024 (0x0<<15 | 0x0<<2)
36#define USB_CMD_FRAME_SIZE_512 (0x0<<15 | 0x1<<2)
37#define USB_CMD_FRAME_SIZE_256 (0x0<<15 | 0x2<<2)
38#define USB_CMD_FRAME_SIZE_128 (0x0<<15 | 0x3<<2)
39#define USB_CMD_FRAME_SIZE_64 (0x1<<15 | 0x0<<2)
40#define USB_CMD_FRAME_SIZE_32 (0x1<<15 | 0x1<<2)
41#define USB_CMD_FRAME_SIZE_16 (0x1<<15 | 0x2<<2)
42#define USB_CMD_FRAME_SIZE_8 (0x1<<15 | 0x3<<2)
43
44/* bit 9-8 are async schedule park mode count */
45#define USB_CMD_ASP_00 (0x0<<8)
46#define USB_CMD_ASP_01 (0x1<<8)
47#define USB_CMD_ASP_10 (0x2<<8)
48#define USB_CMD_ASP_11 (0x3<<8)
49#define USB_CMD_ASP_BIT_POS (8)
50
51/* bit 23-16 are interrupt threshold control */
52#define USB_CMD_ITC_NO_THRESHOLD (0x00<<16)
53#define USB_CMD_ITC_1_MICRO_FRM (0x01<<16)
54#define USB_CMD_ITC_2_MICRO_FRM (0x02<<16)
55#define USB_CMD_ITC_4_MICRO_FRM (0x04<<16)
56#define USB_CMD_ITC_8_MICRO_FRM (0x08<<16)
57#define USB_CMD_ITC_16_MICRO_FRM (0x10<<16)
58#define USB_CMD_ITC_32_MICRO_FRM (0x20<<16)
59#define USB_CMD_ITC_64_MICRO_FRM (0x40<<16)
60#define USB_CMD_ITC_BIT_POS (16)
61
62/* USB Status Register Bit Masks */
63#define USB_STS_INT (0x1<<0)
64#define USB_STS_ERR (0x1<<1)
65#define USB_STS_PORT_CHANGE (0x1<<2)
66#define USB_STS_FRM_LST_ROLL (0x1<<3)
67#define USB_STS_SYS_ERR (0x1<<4)
68#define USB_STS_IAA (0x1<<5)
69#define USB_STS_RESET_RECEIVED (0x1<<6)
70#define USB_STS_SOF (0x1<<7)
71#define USB_STS_DCSUSPEND (0x1<<8)
72#define USB_STS_HC_HALTED (0x1<<12)
73#define USB_STS_RCL (0x1<<13)
74#define USB_STS_PERIODIC_SCHEDULE (0x1<<14)
75#define USB_STS_ASYNC_SCHEDULE (0x1<<15)
76
77/* USB Interrupt Enable Register Bit Masks */
78#define USB_INTR_INT_EN (0x1<<0)
79#define USB_INTR_ERR_INT_EN (0x1<<1)
80#define USB_INTR_PC_DETECT_EN (0x1<<2)
81#define USB_INTR_FRM_LST_ROLL_EN (0x1<<3)
82#define USB_INTR_SYS_ERR_EN (0x1<<4)
83#define USB_INTR_ASYN_ADV_EN (0x1<<5)
84#define USB_INTR_RESET_EN (0x1<<6)
85#define USB_INTR_SOF_EN (0x1<<7)
86#define USB_INTR_DEVICE_SUSPEND (0x1<<8)
87
88/* Device Address bit masks */
89#define USB_DEVICE_ADDRESS_MASK (0x7F<<25)
90#define USB_DEVICE_ADDRESS_BIT_POS (25)
91/* PORTSC Register Bit Masks,Only one PORT in OTG mode*/
92#define PORTSC_CURRENT_CONNECT_STATUS (0x1<<0)
93#define PORTSC_CONNECT_STATUS_CHANGE (0x1<<1)
94#define PORTSC_PORT_ENABLE (0x1<<2)
95#define PORTSC_PORT_EN_DIS_CHANGE (0x1<<3)
96#define PORTSC_OVER_CURRENT_ACT (0x1<<4)
97#define PORTSC_OVER_CUURENT_CHG (0x1<<5)
98#define PORTSC_PORT_FORCE_RESUME (0x1<<6)
99#define PORTSC_PORT_SUSPEND (0x1<<7)
100#define PORTSC_PORT_RESET (0x1<<8)
101#define PORTSC_LINE_STATUS_BITS (0x3<<10)
102#define PORTSC_PORT_POWER (0x1<<12)
103#define PORTSC_PORT_INDICTOR_CTRL (0x3<<14)
104#define PORTSC_PORT_TEST_CTRL (0xF<<16)
105#define PORTSC_WAKE_ON_CONNECT_EN (0x1<<20)
106#define PORTSC_WAKE_ON_CONNECT_DIS (0x1<<21)
107#define PORTSC_WAKE_ON_OVER_CURRENT (0x1<<22)
108#define PORTSC_PHY_LOW_POWER_SPD (0x1<<23)
109#define PORTSC_PORT_FORCE_FULL_SPEED (0x1<<24)
110#define PORTSC_PORT_SPEED_MASK (0x3<<26)
111#define PORTSC_TRANSCEIVER_WIDTH (0x1<<28)
112#define PORTSC_PHY_TYPE_SEL (0x3<<30)
113/* bit 11-10 are line status */
114#define PORTSC_LINE_STATUS_SE0 (0x0<<10)
115#define PORTSC_LINE_STATUS_JSTATE (0x1<<10)
116#define PORTSC_LINE_STATUS_KSTATE (0x2<<10)
117#define PORTSC_LINE_STATUS_UNDEF (0x3<<10)
118#define PORTSC_LINE_STATUS_BIT_POS (10)
119
120/* bit 15-14 are port indicator control */
121#define PORTSC_PIC_OFF (0x0<<14)
122#define PORTSC_PIC_AMBER (0x1<<14)
123#define PORTSC_PIC_GREEN (0x2<<14)
124#define PORTSC_PIC_UNDEF (0x3<<14)
125#define PORTSC_PIC_BIT_POS (14)
126
127/* bit 19-16 are port test control */
128#define PORTSC_PTC_DISABLE (0x0<<16)
129#define PORTSC_PTC_JSTATE (0x1<<16)
130#define PORTSC_PTC_KSTATE (0x2<<16)
131#define PORTSC_PTC_SEQNAK (0x3<<16)
132#define PORTSC_PTC_PACKET (0x4<<16)
133#define PORTSC_PTC_FORCE_EN (0x5<<16)
134#define PORTSC_PTC_BIT_POS (16)
135
136/* bit 27-26 are port speed */
137#define PORTSC_PORT_SPEED_FULL (0x0<<26)
138#define PORTSC_PORT_SPEED_LOW (0x1<<26)
139#define PORTSC_PORT_SPEED_HIGH (0x2<<26)
140#define PORTSC_PORT_SPEED_UNDEF (0x3<<26)
141#define PORTSC_SPEED_BIT_POS (26)
142
143/* bit 28 is parallel transceiver width for UTMI interface */
144#define PORTSC_PTW (0x1<<28)
145#define PORTSC_PTW_8BIT (0x0<<28)
146#define PORTSC_PTW_16BIT (0x1<<28)
147
148/* bit 31-30 are port transceiver select */
149#define PORTSC_PTS_UTMI (0x0<<30)
150#define PORTSC_PTS_ULPI (0x2<<30)
151#define PORTSC_PTS_FSLS_SERIAL (0x3<<30)
152#define PORTSC_PTS_BIT_POS (30)
153
154#define PORTSC_W1C_BITS \
155 (PORTSC_CONNECT_STATUS_CHANGE | \
156 PORTSC_PORT_EN_DIS_CHANGE | \
157 PORTSC_OVER_CUURENT_CHG)
158
159/* OTG Status Control Register Bit Masks */
160#define OTGSC_CTRL_VBUS_DISCHARGE (0x1<<0)
161#define OTGSC_CTRL_VBUS_CHARGE (0x1<<1)
162#define OTGSC_CTRL_OTG_TERMINATION (0x1<<3)
163#define OTGSC_CTRL_DATA_PULSING (0x1<<4)
164#define OTGSC_CTRL_ID_PULL_EN (0x1<<5)
165#define OTGSC_HA_DATA_PULSE (0x1<<6)
166#define OTGSC_HA_BA (0x1<<7)
167#define OTGSC_STS_USB_ID (0x1<<8)
168#define OTGSC_STS_A_VBUS_VALID (0x1<<9)
169#define OTGSC_STS_A_SESSION_VALID (0x1<<10)
170#define OTGSC_STS_B_SESSION_VALID (0x1<<11)
171#define OTGSC_STS_B_SESSION_END (0x1<<12)
172#define OTGSC_STS_1MS_TOGGLE (0x1<<13)
173#define OTGSC_STS_DATA_PULSING (0x1<<14)
174#define OTGSC_INTSTS_USB_ID (0x1<<16)
175#define OTGSC_INTSTS_A_VBUS_VALID (0x1<<17)
176#define OTGSC_INTSTS_A_SESSION_VALID (0x1<<18)
177#define OTGSC_INTSTS_B_SESSION_VALID (0x1<<19)
178#define OTGSC_INTSTS_B_SESSION_END (0x1<<20)
179#define OTGSC_INTSTS_1MS (0x1<<21)
180#define OTGSC_INTSTS_DATA_PULSING (0x1<<22)
181#define OTGSC_INTR_USB_ID_EN (0x1<<24)
182#define OTGSC_INTR_A_VBUS_VALID_EN (0x1<<25)
183#define OTGSC_INTR_A_SESSION_VALID_EN (0x1<<26)
184#define OTGSC_INTR_B_SESSION_VALID_EN (0x1<<27)
185#define OTGSC_INTR_B_SESSION_END_EN (0x1<<28)
186#define OTGSC_INTR_1MS_TIMER_EN (0x1<<29)
187#define OTGSC_INTR_DATA_PULSING_EN (0x1<<30)
188#define OTGSC_INTSTS_MASK (0x00ff0000)
189
190/* USB MODE Register Bit Masks */
191#define USB_MODE_CTRL_MODE_IDLE (0x0<<0)
192#define USB_MODE_CTRL_MODE_DEVICE (0x2<<0)
193#define USB_MODE_CTRL_MODE_HOST (0x3<<0)
194#define USB_MODE_CTRL_MODE_RSV (0x1<<0)
195#define USB_MODE_SETUP_LOCK_OFF (0x1<<3)
196#define USB_MODE_STREAM_DISABLE (0x1<<4)
197#define USB_MODE_ES (0x1<<2) /* Endian Select */
198
199/* control Register Bit Masks */
200#define USB_CTRL_IOENB (0x1<<2)
201#define USB_CTRL_ULPI_INT0EN (0x1<<0)
202
203/* BCSR5 */
204#define BCSR5_INT_USB (0x02)
205
206/* USB module clk cfg */
207#define SCCR_OFFS (0xA08)
208#define SCCR_USB_CLK_DISABLE (0x00000000) /* USB clk disable */
209#define SCCR_USB_MPHCM_11 (0x00c00000)
210#define SCCR_USB_MPHCM_01 (0x00400000)
211#define SCCR_USB_MPHCM_10 (0x00800000)
212#define SCCR_USB_DRCM_11 (0x00300000)
213#define SCCR_USB_DRCM_01 (0x00100000)
214#define SCCR_USB_DRCM_10 (0x00200000)
215
216#define SICRL_OFFS (0x114)
217#define SICRL_USB0 (0x40000000)
218#define SICRL_USB1 (0x20000000)
219
220#define SICRH_OFFS (0x118)
221#define SICRH_USB_UTMI (0x00020000)
222
223/* OTG interrupt enable bit masks */
224#define OTGSC_INTERRUPT_ENABLE_BITS_MASK \
225 (OTGSC_INTR_USB_ID_EN | \
226 OTGSC_INTR_1MS_TIMER_EN | \
227 OTGSC_INTR_A_VBUS_VALID_EN | \
228 OTGSC_INTR_A_SESSION_VALID_EN | \
229 OTGSC_INTR_B_SESSION_VALID_EN | \
230 OTGSC_INTR_B_SESSION_END_EN | \
231 OTGSC_INTR_DATA_PULSING_EN)
232
233/* OTG interrupt status bit masks */
234#define OTGSC_INTERRUPT_STATUS_BITS_MASK \
235 (OTGSC_INTSTS_USB_ID | \
236 OTGSC_INTR_1MS_TIMER_EN | \
237 OTGSC_INTSTS_A_VBUS_VALID | \
238 OTGSC_INTSTS_A_SESSION_VALID | \
239 OTGSC_INTSTS_B_SESSION_VALID | \
240 OTGSC_INTSTS_B_SESSION_END | \
241 OTGSC_INTSTS_DATA_PULSING)
242
243/*
244 * A-DEVICE timing constants
245 */
246
247/* Wait for VBUS Rise */
248#define TA_WAIT_VRISE (100) /* a_wait_vrise 100 ms, section: 6.6.5.1 */
249
250/* Wait for B-Connect */
251#define TA_WAIT_BCON (10000) /* a_wait_bcon > 1 sec, section: 6.6.5.2
252 * This is only used to get out of
253 * OTG_STATE_A_WAIT_BCON state if there was
254 * no connection for these many milliseconds
255 */
256
257/* A-Idle to B-Disconnect */
258/* It is necessary for this timer to be more than 750 ms because of a bug in OPT
259 * test 5.4 in which B OPT disconnects after 750 ms instead of 75ms as stated
260 * in the test description
261 */
262#define TA_AIDL_BDIS (5000) /* a_suspend minimum 200 ms, section: 6.6.5.3 */
263
264/* B-Idle to A-Disconnect */
265#define TA_BIDL_ADIS (12) /* 3 to 200 ms */
266
267/* B-device timing constants */
268
269
270/* Data-Line Pulse Time*/
271#define TB_DATA_PLS (10) /* b_srp_init,continue 5~10ms, section:5.3.3 */
272#define TB_DATA_PLS_MIN (5) /* minimum 5 ms */
273#define TB_DATA_PLS_MAX (10) /* maximum 10 ms */
274
275/* SRP Initiate Time */
276#define TB_SRP_INIT (100) /* b_srp_init,maximum 100 ms, section:5.3.8 */
277
278/* SRP Fail Time */
279#define TB_SRP_FAIL (7000) /* b_srp_init,Fail time 5~30s, section:6.8.2.2*/
280
281/* SRP result wait time */
282#define TB_SRP_WAIT (60)
283
284/* VBus time */
285#define TB_VBUS_PLS (30) /* time to keep vbus pulsing asserted */
286
287/* Discharge time */
288/* This time should be less than 10ms. It varies from system to system. */
289#define TB_VBUS_DSCHRG (8)
290
291/* A-SE0 to B-Reset */
292#define TB_ASE0_BRST (20) /* b_wait_acon, mini 3.125 ms,section:6.8.2.4 */
293
294/* A bus suspend timer before we can switch to b_wait_aconn */
295#define TB_A_SUSPEND (7)
296#define TB_BUS_RESUME (12)
297
298/* SE0 Time Before SRP */
299#define TB_SE0_SRP (2) /* b_idle,minimum 2 ms, section:5.3.2 */
300
301#define SET_OTG_STATE(otg_ptr, newstate) ((otg_ptr)->state = newstate)
302
303struct usb_dr_mmap {
304 /* Capability register */
305 u8 res1[256];
306 u16 caplength; /* Capability Register Length */
307 u16 hciversion; /* Host Controller Interface Version */
308 u32 hcsparams; /* Host Controller Structual Parameters */
309 u32 hccparams; /* Host Controller Capability Parameters */
310 u8 res2[20];
311 u32 dciversion; /* Device Controller Interface Version */
312 u32 dccparams; /* Device Controller Capability Parameters */
313 u8 res3[24];
314 /* Operation register */
315 u32 usbcmd; /* USB Command Register */
316 u32 usbsts; /* USB Status Register */
317 u32 usbintr; /* USB Interrupt Enable Register */
318 u32 frindex; /* Frame Index Register */
319 u8 res4[4];
320 u32 deviceaddr; /* Device Address */
321 u32 endpointlistaddr; /* Endpoint List Address Register */
322 u8 res5[4];
323 u32 burstsize; /* Master Interface Data Burst Size Register */
324 u32 txttfilltuning; /* Transmit FIFO Tuning Controls Register */
325 u8 res6[8];
326 u32 ulpiview; /* ULPI register access */
327 u8 res7[12];
328 u32 configflag; /* Configure Flag Register */
329 u32 portsc; /* Port 1 Status and Control Register */
330 u8 res8[28];
331 u32 otgsc; /* On-The-Go Status and Control */
332 u32 usbmode; /* USB Mode Register */
333 u32 endptsetupstat; /* Endpoint Setup Status Register */
334 u32 endpointprime; /* Endpoint Initialization Register */
335 u32 endptflush; /* Endpoint Flush Register */
336 u32 endptstatus; /* Endpoint Status Register */
337 u32 endptcomplete; /* Endpoint Complete Register */
338 u32 endptctrl[6]; /* Endpoint Control Registers */
339 u8 res9[552];
340 u32 snoop1;
341 u32 snoop2;
342 u32 age_cnt_thresh; /* Age Count Threshold Register */
343 u32 pri_ctrl; /* Priority Control Register */
344 u32 si_ctrl; /* System Interface Control Register */
345 u8 res10[236];
346 u32 control; /* General Purpose Control Register */
347};
348
349struct fsl_otg_timer {
350 unsigned long expires; /* Number of count increase to timeout */
351 unsigned long count; /* Tick counter */
352 void (*function)(unsigned long); /* Timeout function */
353 unsigned long data; /* Data passed to function */
354 struct list_head list;
355};
356
357inline struct fsl_otg_timer *otg_timer_initializer
358(void (*function)(unsigned long), unsigned long expires, unsigned long data)
359{
360 struct fsl_otg_timer *timer;
361
362 timer = kmalloc(sizeof(struct fsl_otg_timer), GFP_KERNEL);
363 if (!timer)
364 return NULL;
365 timer->function = function;
366 timer->expires = expires;
367 timer->data = data;
368 return timer;
369}
370
371struct fsl_otg {
372 struct usb_phy phy;
373 struct otg_fsm fsm;
374 struct usb_dr_mmap *dr_mem_map;
375 struct delayed_work otg_event;
376
377 /* used for usb host */
378 struct work_struct work_wq;
379 u8 host_working;
380
381 int irq;
382};
383
384struct fsl_otg_config {
385 u8 otg_port;
386};
387
388/* For SRP and HNP handle */
389#define FSL_OTG_MAJOR 240
390#define FSL_OTG_NAME "fsl-usb2-otg"
391/* Command to OTG driver ioctl */
392#define OTG_IOCTL_MAGIC FSL_OTG_MAJOR
393/* if otg work as host, it should return 1, otherwise return 0 */
394#define GET_OTG_STATUS _IOR(OTG_IOCTL_MAGIC, 1, int)
395#define SET_A_SUSPEND_REQ _IOW(OTG_IOCTL_MAGIC, 2, int)
396#define SET_A_BUS_DROP _IOW(OTG_IOCTL_MAGIC, 3, int)
397#define SET_A_BUS_REQ _IOW(OTG_IOCTL_MAGIC, 4, int)
398#define SET_B_BUS_REQ _IOW(OTG_IOCTL_MAGIC, 5, int)
399#define GET_A_SUSPEND_REQ _IOR(OTG_IOCTL_MAGIC, 6, int)
400#define GET_A_BUS_DROP _IOR(OTG_IOCTL_MAGIC, 7, int)
401#define GET_A_BUS_REQ _IOR(OTG_IOCTL_MAGIC, 8, int)
402#define GET_B_BUS_REQ _IOR(OTG_IOCTL_MAGIC, 9, int)
403
404void fsl_otg_add_timer(void *timer);
405void fsl_otg_del_timer(void *timer);
406void fsl_otg_pulse_vbus(void);
diff --git a/drivers/usb/phy/phy-fsm-usb.c b/drivers/usb/phy/phy-fsm-usb.c
new file mode 100644
index 000000000000..c520b3548e7c
--- /dev/null
+++ b/drivers/usb/phy/phy-fsm-usb.c
@@ -0,0 +1,348 @@
1/*
2 * OTG Finite State Machine from OTG spec
3 *
4 * Copyright (C) 2007,2008 Freescale Semiconductor, Inc.
5 *
6 * Author: Li Yang <LeoLi@freescale.com>
7 * Jerry Huang <Chang-Ming.Huang@freescale.com>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, write to the Free Software Foundation, Inc.,
21 * 675 Mass Ave, Cambridge, MA 02139, USA.
22 */
23
24#include <linux/kernel.h>
25#include <linux/types.h>
26#include <linux/spinlock.h>
27#include <linux/delay.h>
28#include <linux/usb.h>
29#include <linux/usb/gadget.h>
30#include <linux/usb/otg.h>
31
32#include "phy-otg-fsm.h"
33
34/* Change USB protocol when there is a protocol change */
35static int otg_set_protocol(struct otg_fsm *fsm, int protocol)
36{
37 int ret = 0;
38
39 if (fsm->protocol != protocol) {
40 VDBG("Changing role fsm->protocol= %d; new protocol= %d\n",
41 fsm->protocol, protocol);
42 /* stop old protocol */
43 if (fsm->protocol == PROTO_HOST)
44 ret = fsm->ops->start_host(fsm, 0);
45 else if (fsm->protocol == PROTO_GADGET)
46 ret = fsm->ops->start_gadget(fsm, 0);
47 if (ret)
48 return ret;
49
50 /* start new protocol */
51 if (protocol == PROTO_HOST)
52 ret = fsm->ops->start_host(fsm, 1);
53 else if (protocol == PROTO_GADGET)
54 ret = fsm->ops->start_gadget(fsm, 1);
55 if (ret)
56 return ret;
57
58 fsm->protocol = protocol;
59 return 0;
60 }
61
62 return 0;
63}
64
65static int state_changed;
66
67/* Called when leaving a state. Do state clean up jobs here */
68void otg_leave_state(struct otg_fsm *fsm, enum usb_otg_state old_state)
69{
70 switch (old_state) {
71 case OTG_STATE_B_IDLE:
72 otg_del_timer(fsm, b_se0_srp_tmr);
73 fsm->b_se0_srp = 0;
74 break;
75 case OTG_STATE_B_SRP_INIT:
76 fsm->b_srp_done = 0;
77 break;
78 case OTG_STATE_B_PERIPHERAL:
79 break;
80 case OTG_STATE_B_WAIT_ACON:
81 otg_del_timer(fsm, b_ase0_brst_tmr);
82 fsm->b_ase0_brst_tmout = 0;
83 break;
84 case OTG_STATE_B_HOST:
85 break;
86 case OTG_STATE_A_IDLE:
87 break;
88 case OTG_STATE_A_WAIT_VRISE:
89 otg_del_timer(fsm, a_wait_vrise_tmr);
90 fsm->a_wait_vrise_tmout = 0;
91 break;
92 case OTG_STATE_A_WAIT_BCON:
93 otg_del_timer(fsm, a_wait_bcon_tmr);
94 fsm->a_wait_bcon_tmout = 0;
95 break;
96 case OTG_STATE_A_HOST:
97 otg_del_timer(fsm, a_wait_enum_tmr);
98 break;
99 case OTG_STATE_A_SUSPEND:
100 otg_del_timer(fsm, a_aidl_bdis_tmr);
101 fsm->a_aidl_bdis_tmout = 0;
102 fsm->a_suspend_req = 0;
103 break;
104 case OTG_STATE_A_PERIPHERAL:
105 break;
106 case OTG_STATE_A_WAIT_VFALL:
107 otg_del_timer(fsm, a_wait_vrise_tmr);
108 break;
109 case OTG_STATE_A_VBUS_ERR:
110 break;
111 default:
112 break;
113 }
114}
115
116/* Called when entering a state */
117int otg_set_state(struct otg_fsm *fsm, enum usb_otg_state new_state)
118{
119 state_changed = 1;
120 if (fsm->otg->phy->state == new_state)
121 return 0;
122 VDBG("Set state: %s\n", usb_otg_state_string(new_state));
123 otg_leave_state(fsm, fsm->otg->phy->state);
124 switch (new_state) {
125 case OTG_STATE_B_IDLE:
126 otg_drv_vbus(fsm, 0);
127 otg_chrg_vbus(fsm, 0);
128 otg_loc_conn(fsm, 0);
129 otg_loc_sof(fsm, 0);
130 otg_set_protocol(fsm, PROTO_UNDEF);
131 otg_add_timer(fsm, b_se0_srp_tmr);
132 break;
133 case OTG_STATE_B_SRP_INIT:
134 otg_start_pulse(fsm);
135 otg_loc_sof(fsm, 0);
136 otg_set_protocol(fsm, PROTO_UNDEF);
137 otg_add_timer(fsm, b_srp_fail_tmr);
138 break;
139 case OTG_STATE_B_PERIPHERAL:
140 otg_chrg_vbus(fsm, 0);
141 otg_loc_conn(fsm, 1);
142 otg_loc_sof(fsm, 0);
143 otg_set_protocol(fsm, PROTO_GADGET);
144 break;
145 case OTG_STATE_B_WAIT_ACON:
146 otg_chrg_vbus(fsm, 0);
147 otg_loc_conn(fsm, 0);
148 otg_loc_sof(fsm, 0);
149 otg_set_protocol(fsm, PROTO_HOST);
150 otg_add_timer(fsm, b_ase0_brst_tmr);
151 fsm->a_bus_suspend = 0;
152 break;
153 case OTG_STATE_B_HOST:
154 otg_chrg_vbus(fsm, 0);
155 otg_loc_conn(fsm, 0);
156 otg_loc_sof(fsm, 1);
157 otg_set_protocol(fsm, PROTO_HOST);
158 usb_bus_start_enum(fsm->otg->host,
159 fsm->otg->host->otg_port);
160 break;
161 case OTG_STATE_A_IDLE:
162 otg_drv_vbus(fsm, 0);
163 otg_chrg_vbus(fsm, 0);
164 otg_loc_conn(fsm, 0);
165 otg_loc_sof(fsm, 0);
166 otg_set_protocol(fsm, PROTO_HOST);
167 break;
168 case OTG_STATE_A_WAIT_VRISE:
169 otg_drv_vbus(fsm, 1);
170 otg_loc_conn(fsm, 0);
171 otg_loc_sof(fsm, 0);
172 otg_set_protocol(fsm, PROTO_HOST);
173 otg_add_timer(fsm, a_wait_vrise_tmr);
174 break;
175 case OTG_STATE_A_WAIT_BCON:
176 otg_drv_vbus(fsm, 1);
177 otg_loc_conn(fsm, 0);
178 otg_loc_sof(fsm, 0);
179 otg_set_protocol(fsm, PROTO_HOST);
180 otg_add_timer(fsm, a_wait_bcon_tmr);
181 break;
182 case OTG_STATE_A_HOST:
183 otg_drv_vbus(fsm, 1);
184 otg_loc_conn(fsm, 0);
185 otg_loc_sof(fsm, 1);
186 otg_set_protocol(fsm, PROTO_HOST);
187 /*
188 * When HNP is triggered while a_bus_req = 0, a_host will
189 * suspend too fast to complete a_set_b_hnp_en
190 */
191 if (!fsm->a_bus_req || fsm->a_suspend_req)
192 otg_add_timer(fsm, a_wait_enum_tmr);
193 break;
194 case OTG_STATE_A_SUSPEND:
195 otg_drv_vbus(fsm, 1);
196 otg_loc_conn(fsm, 0);
197 otg_loc_sof(fsm, 0);
198 otg_set_protocol(fsm, PROTO_HOST);
199 otg_add_timer(fsm, a_aidl_bdis_tmr);
200
201 break;
202 case OTG_STATE_A_PERIPHERAL:
203 otg_loc_conn(fsm, 1);
204 otg_loc_sof(fsm, 0);
205 otg_set_protocol(fsm, PROTO_GADGET);
206 otg_drv_vbus(fsm, 1);
207 break;
208 case OTG_STATE_A_WAIT_VFALL:
209 otg_drv_vbus(fsm, 0);
210 otg_loc_conn(fsm, 0);
211 otg_loc_sof(fsm, 0);
212 otg_set_protocol(fsm, PROTO_HOST);
213 break;
214 case OTG_STATE_A_VBUS_ERR:
215 otg_drv_vbus(fsm, 0);
216 otg_loc_conn(fsm, 0);
217 otg_loc_sof(fsm, 0);
218 otg_set_protocol(fsm, PROTO_UNDEF);
219 break;
220 default:
221 break;
222 }
223
224 fsm->otg->phy->state = new_state;
225 return 0;
226}
227
228/* State change judgement */
229int otg_statemachine(struct otg_fsm *fsm)
230{
231 enum usb_otg_state state;
232 unsigned long flags;
233
234 spin_lock_irqsave(&fsm->lock, flags);
235
236 state = fsm->otg->phy->state;
237 state_changed = 0;
238 /* State machine state change judgement */
239
240 switch (state) {
241 case OTG_STATE_UNDEFINED:
242 VDBG("fsm->id = %d\n", fsm->id);
243 if (fsm->id)
244 otg_set_state(fsm, OTG_STATE_B_IDLE);
245 else
246 otg_set_state(fsm, OTG_STATE_A_IDLE);
247 break;
248 case OTG_STATE_B_IDLE:
249 if (!fsm->id)
250 otg_set_state(fsm, OTG_STATE_A_IDLE);
251 else if (fsm->b_sess_vld && fsm->otg->gadget)
252 otg_set_state(fsm, OTG_STATE_B_PERIPHERAL);
253 else if (fsm->b_bus_req && fsm->b_sess_end && fsm->b_se0_srp)
254 otg_set_state(fsm, OTG_STATE_B_SRP_INIT);
255 break;
256 case OTG_STATE_B_SRP_INIT:
257 if (!fsm->id || fsm->b_srp_done)
258 otg_set_state(fsm, OTG_STATE_B_IDLE);
259 break;
260 case OTG_STATE_B_PERIPHERAL:
261 if (!fsm->id || !fsm->b_sess_vld)
262 otg_set_state(fsm, OTG_STATE_B_IDLE);
263 else if (fsm->b_bus_req && fsm->otg->
264 gadget->b_hnp_enable && fsm->a_bus_suspend)
265 otg_set_state(fsm, OTG_STATE_B_WAIT_ACON);
266 break;
267 case OTG_STATE_B_WAIT_ACON:
268 if (fsm->a_conn)
269 otg_set_state(fsm, OTG_STATE_B_HOST);
270 else if (!fsm->id || !fsm->b_sess_vld)
271 otg_set_state(fsm, OTG_STATE_B_IDLE);
272 else if (fsm->a_bus_resume || fsm->b_ase0_brst_tmout) {
273 fsm->b_ase0_brst_tmout = 0;
274 otg_set_state(fsm, OTG_STATE_B_PERIPHERAL);
275 }
276 break;
277 case OTG_STATE_B_HOST:
278 if (!fsm->id || !fsm->b_sess_vld)
279 otg_set_state(fsm, OTG_STATE_B_IDLE);
280 else if (!fsm->b_bus_req || !fsm->a_conn)
281 otg_set_state(fsm, OTG_STATE_B_PERIPHERAL);
282 break;
283 case OTG_STATE_A_IDLE:
284 if (fsm->id)
285 otg_set_state(fsm, OTG_STATE_B_IDLE);
286 else if (!fsm->a_bus_drop && (fsm->a_bus_req || fsm->a_srp_det))
287 otg_set_state(fsm, OTG_STATE_A_WAIT_VRISE);
288 break;
289 case OTG_STATE_A_WAIT_VRISE:
290 if (fsm->id || fsm->a_bus_drop || fsm->a_vbus_vld ||
291 fsm->a_wait_vrise_tmout) {
292 otg_set_state(fsm, OTG_STATE_A_WAIT_BCON);
293 }
294 break;
295 case OTG_STATE_A_WAIT_BCON:
296 if (!fsm->a_vbus_vld)
297 otg_set_state(fsm, OTG_STATE_A_VBUS_ERR);
298 else if (fsm->b_conn)
299 otg_set_state(fsm, OTG_STATE_A_HOST);
300 else if (fsm->id | fsm->a_bus_drop | fsm->a_wait_bcon_tmout)
301 otg_set_state(fsm, OTG_STATE_A_WAIT_VFALL);
302 break;
303 case OTG_STATE_A_HOST:
304 if ((!fsm->a_bus_req || fsm->a_suspend_req) &&
305 fsm->otg->host->b_hnp_enable)
306 otg_set_state(fsm, OTG_STATE_A_SUSPEND);
307 else if (fsm->id || !fsm->b_conn || fsm->a_bus_drop)
308 otg_set_state(fsm, OTG_STATE_A_WAIT_BCON);
309 else if (!fsm->a_vbus_vld)
310 otg_set_state(fsm, OTG_STATE_A_VBUS_ERR);
311 break;
312 case OTG_STATE_A_SUSPEND:
313 if (!fsm->b_conn && fsm->otg->host->b_hnp_enable)
314 otg_set_state(fsm, OTG_STATE_A_PERIPHERAL);
315 else if (!fsm->b_conn && !fsm->otg->host->b_hnp_enable)
316 otg_set_state(fsm, OTG_STATE_A_WAIT_BCON);
317 else if (fsm->a_bus_req || fsm->b_bus_resume)
318 otg_set_state(fsm, OTG_STATE_A_HOST);
319 else if (fsm->id || fsm->a_bus_drop || fsm->a_aidl_bdis_tmout)
320 otg_set_state(fsm, OTG_STATE_A_WAIT_VFALL);
321 else if (!fsm->a_vbus_vld)
322 otg_set_state(fsm, OTG_STATE_A_VBUS_ERR);
323 break;
324 case OTG_STATE_A_PERIPHERAL:
325 if (fsm->id || fsm->a_bus_drop)
326 otg_set_state(fsm, OTG_STATE_A_WAIT_VFALL);
327 else if (fsm->b_bus_suspend)
328 otg_set_state(fsm, OTG_STATE_A_WAIT_BCON);
329 else if (!fsm->a_vbus_vld)
330 otg_set_state(fsm, OTG_STATE_A_VBUS_ERR);
331 break;
332 case OTG_STATE_A_WAIT_VFALL:
333 if (fsm->id || fsm->a_bus_req || (!fsm->a_sess_vld &&
334 !fsm->b_conn))
335 otg_set_state(fsm, OTG_STATE_A_IDLE);
336 break;
337 case OTG_STATE_A_VBUS_ERR:
338 if (fsm->id || fsm->a_bus_drop || fsm->a_clr_err)
339 otg_set_state(fsm, OTG_STATE_A_WAIT_VFALL);
340 break;
341 default:
342 break;
343 }
344 spin_unlock_irqrestore(&fsm->lock, flags);
345
346 VDBG("quit statemachine, changed = %d\n", state_changed);
347 return state_changed;
348}
diff --git a/drivers/usb/phy/phy-fsm-usb.h b/drivers/usb/phy/phy-fsm-usb.h
new file mode 100644
index 000000000000..c30a2e1d9e46
--- /dev/null
+++ b/drivers/usb/phy/phy-fsm-usb.h
@@ -0,0 +1,154 @@
1/* Copyright (C) 2007,2008 Freescale Semiconductor, Inc.
2 *
3 * This program is free software; you can redistribute it and/or modify it
4 * under the terms of the GNU General Public License as published by the
5 * Free Software Foundation; either version 2 of the License, or (at your
6 * option) any later version.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License along
14 * with this program; if not, write to the Free Software Foundation, Inc.,
15 * 675 Mass Ave, Cambridge, MA 02139, USA.
16 */
17
18#undef DEBUG
19#undef VERBOSE
20
21#ifdef DEBUG
22#define DBG(fmt, args...) printk(KERN_DEBUG "[%s] " fmt , \
23 __func__, ## args)
24#else
25#define DBG(fmt, args...) do {} while (0)
26#endif
27
28#ifdef VERBOSE
29#define VDBG DBG
30#else
31#define VDBG(stuff...) do {} while (0)
32#endif
33
34#ifdef VERBOSE
35#define MPC_LOC printk("Current Location [%s]:[%d]\n", __FILE__, __LINE__)
36#else
37#define MPC_LOC do {} while (0)
38#endif
39
40#define PROTO_UNDEF (0)
41#define PROTO_HOST (1)
42#define PROTO_GADGET (2)
43
44/* OTG state machine according to the OTG spec */
45struct otg_fsm {
46 /* Input */
47 int a_bus_resume;
48 int a_bus_suspend;
49 int a_conn;
50 int a_sess_vld;
51 int a_srp_det;
52 int a_vbus_vld;
53 int b_bus_resume;
54 int b_bus_suspend;
55 int b_conn;
56 int b_se0_srp;
57 int b_sess_end;
58 int b_sess_vld;
59 int id;
60
61 /* Internal variables */
62 int a_set_b_hnp_en;
63 int b_srp_done;
64 int b_hnp_enable;
65
66 /* Timeout indicator for timers */
67 int a_wait_vrise_tmout;
68 int a_wait_bcon_tmout;
69 int a_aidl_bdis_tmout;
70 int b_ase0_brst_tmout;
71
72 /* Informative variables */
73 int a_bus_drop;
74 int a_bus_req;
75 int a_clr_err;
76 int a_suspend_req;
77 int b_bus_req;
78
79 /* Output */
80 int drv_vbus;
81 int loc_conn;
82 int loc_sof;
83
84 struct otg_fsm_ops *ops;
85 struct usb_otg *otg;
86
87 /* Current usb protocol used: 0:undefine; 1:host; 2:client */
88 int protocol;
89 spinlock_t lock;
90};
91
92struct otg_fsm_ops {
93 void (*chrg_vbus)(int on);
94 void (*drv_vbus)(int on);
95 void (*loc_conn)(int on);
96 void (*loc_sof)(int on);
97 void (*start_pulse)(void);
98 void (*add_timer)(void *timer);
99 void (*del_timer)(void *timer);
100 int (*start_host)(struct otg_fsm *fsm, int on);
101 int (*start_gadget)(struct otg_fsm *fsm, int on);
102};
103
104
105static inline void otg_chrg_vbus(struct otg_fsm *fsm, int on)
106{
107 fsm->ops->chrg_vbus(on);
108}
109
110static inline void otg_drv_vbus(struct otg_fsm *fsm, int on)
111{
112 if (fsm->drv_vbus != on) {
113 fsm->drv_vbus = on;
114 fsm->ops->drv_vbus(on);
115 }
116}
117
118static inline void otg_loc_conn(struct otg_fsm *fsm, int on)
119{
120 if (fsm->loc_conn != on) {
121 fsm->loc_conn = on;
122 fsm->ops->loc_conn(on);
123 }
124}
125
126static inline void otg_loc_sof(struct otg_fsm *fsm, int on)
127{
128 if (fsm->loc_sof != on) {
129 fsm->loc_sof = on;
130 fsm->ops->loc_sof(on);
131 }
132}
133
134static inline void otg_start_pulse(struct otg_fsm *fsm)
135{
136 fsm->ops->start_pulse();
137}
138
139static inline void otg_add_timer(struct otg_fsm *fsm, void *timer)
140{
141 fsm->ops->add_timer(timer);
142}
143
144static inline void otg_del_timer(struct otg_fsm *fsm, void *timer)
145{
146 fsm->ops->del_timer(timer);
147}
148
149int otg_statemachine(struct otg_fsm *fsm);
150
151/* Defined by device specific driver, for different timer implementation */
152extern struct fsl_otg_timer *a_wait_vrise_tmr, *a_wait_bcon_tmr,
153 *a_aidl_bdis_tmr, *b_ase0_brst_tmr, *b_se0_srp_tmr, *b_srp_fail_tmr,
154 *a_wait_enum_tmr;
diff --git a/drivers/usb/phy/phy-gpio-vbus-usb.c b/drivers/usb/phy/phy-gpio-vbus-usb.c
new file mode 100644
index 000000000000..4c76074e518d
--- /dev/null
+++ b/drivers/usb/phy/phy-gpio-vbus-usb.c
@@ -0,0 +1,421 @@
1/*
2 * gpio-vbus.c - simple GPIO VBUS sensing driver for B peripheral devices
3 *
4 * Copyright (c) 2008 Philipp Zabel <philipp.zabel@gmail.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/kernel.h>
12#include <linux/platform_device.h>
13#include <linux/gpio.h>
14#include <linux/module.h>
15#include <linux/slab.h>
16#include <linux/interrupt.h>
17#include <linux/usb.h>
18#include <linux/workqueue.h>
19
20#include <linux/regulator/consumer.h>
21
22#include <linux/usb/gadget.h>
23#include <linux/usb/gpio_vbus.h>
24#include <linux/usb/otg.h>
25
26
27/*
28 * A simple GPIO VBUS sensing driver for B peripheral only devices
29 * with internal transceivers. It can control a D+ pullup GPIO and
30 * a regulator to limit the current drawn from VBUS.
31 *
32 * Needs to be loaded before the UDC driver that will use it.
33 */
34struct gpio_vbus_data {
35 struct usb_phy phy;
36 struct device *dev;
37 struct regulator *vbus_draw;
38 int vbus_draw_enabled;
39 unsigned mA;
40 struct delayed_work work;
41 int vbus;
42 int irq;
43};
44
45
46/*
47 * This driver relies on "both edges" triggering. VBUS has 100 msec to
48 * stabilize, so the peripheral controller driver may need to cope with
49 * some bouncing due to current surges (e.g. charging local capacitance)
50 * and contact chatter.
51 *
52 * REVISIT in desperate straits, toggling between rising and falling
53 * edges might be workable.
54 */
55#define VBUS_IRQ_FLAGS \
56 (IRQF_SHARED | IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)
57
58
59/* interface to regulator framework */
60static void set_vbus_draw(struct gpio_vbus_data *gpio_vbus, unsigned mA)
61{
62 struct regulator *vbus_draw = gpio_vbus->vbus_draw;
63 int enabled;
64 int ret;
65
66 if (!vbus_draw)
67 return;
68
69 enabled = gpio_vbus->vbus_draw_enabled;
70 if (mA) {
71 regulator_set_current_limit(vbus_draw, 0, 1000 * mA);
72 if (!enabled) {
73 ret = regulator_enable(vbus_draw);
74 if (ret < 0)
75 return;
76 gpio_vbus->vbus_draw_enabled = 1;
77 }
78 } else {
79 if (enabled) {
80 ret = regulator_disable(vbus_draw);
81 if (ret < 0)
82 return;
83 gpio_vbus->vbus_draw_enabled = 0;
84 }
85 }
86 gpio_vbus->mA = mA;
87}
88
89static int is_vbus_powered(struct gpio_vbus_mach_info *pdata)
90{
91 int vbus;
92
93 vbus = gpio_get_value(pdata->gpio_vbus);
94 if (pdata->gpio_vbus_inverted)
95 vbus = !vbus;
96
97 return vbus;
98}
99
100static void gpio_vbus_work(struct work_struct *work)
101{
102 struct gpio_vbus_data *gpio_vbus =
103 container_of(work, struct gpio_vbus_data, work.work);
104 struct gpio_vbus_mach_info *pdata = gpio_vbus->dev->platform_data;
105 int gpio, status, vbus;
106
107 if (!gpio_vbus->phy.otg->gadget)
108 return;
109
110 vbus = is_vbus_powered(pdata);
111 if ((vbus ^ gpio_vbus->vbus) == 0)
112 return;
113 gpio_vbus->vbus = vbus;
114
115 /* Peripheral controllers which manage the pullup themselves won't have
116 * gpio_pullup configured here. If it's configured here, we'll do what
117 * isp1301_omap::b_peripheral() does and enable the pullup here... although
118 * that may complicate usb_gadget_{,dis}connect() support.
119 */
120 gpio = pdata->gpio_pullup;
121
122 if (vbus) {
123 status = USB_EVENT_VBUS;
124 gpio_vbus->phy.state = OTG_STATE_B_PERIPHERAL;
125 gpio_vbus->phy.last_event = status;
126 usb_gadget_vbus_connect(gpio_vbus->phy.otg->gadget);
127
128 /* drawing a "unit load" is *always* OK, except for OTG */
129 set_vbus_draw(gpio_vbus, 100);
130
131 /* optionally enable D+ pullup */
132 if (gpio_is_valid(gpio))
133 gpio_set_value(gpio, !pdata->gpio_pullup_inverted);
134
135 atomic_notifier_call_chain(&gpio_vbus->phy.notifier,
136 status, gpio_vbus->phy.otg->gadget);
137 } else {
138 /* optionally disable D+ pullup */
139 if (gpio_is_valid(gpio))
140 gpio_set_value(gpio, pdata->gpio_pullup_inverted);
141
142 set_vbus_draw(gpio_vbus, 0);
143
144 usb_gadget_vbus_disconnect(gpio_vbus->phy.otg->gadget);
145 status = USB_EVENT_NONE;
146 gpio_vbus->phy.state = OTG_STATE_B_IDLE;
147 gpio_vbus->phy.last_event = status;
148
149 atomic_notifier_call_chain(&gpio_vbus->phy.notifier,
150 status, gpio_vbus->phy.otg->gadget);
151 }
152}
153
154/* VBUS change IRQ handler */
155static irqreturn_t gpio_vbus_irq(int irq, void *data)
156{
157 struct platform_device *pdev = data;
158 struct gpio_vbus_mach_info *pdata = pdev->dev.platform_data;
159 struct gpio_vbus_data *gpio_vbus = platform_get_drvdata(pdev);
160 struct usb_otg *otg = gpio_vbus->phy.otg;
161
162 dev_dbg(&pdev->dev, "VBUS %s (gadget: %s)\n",
163 is_vbus_powered(pdata) ? "supplied" : "inactive",
164 otg->gadget ? otg->gadget->name : "none");
165
166 if (otg->gadget)
167 schedule_delayed_work(&gpio_vbus->work, msecs_to_jiffies(100));
168
169 return IRQ_HANDLED;
170}
171
172/* OTG transceiver interface */
173
174/* bind/unbind the peripheral controller */
175static int gpio_vbus_set_peripheral(struct usb_otg *otg,
176 struct usb_gadget *gadget)
177{
178 struct gpio_vbus_data *gpio_vbus;
179 struct gpio_vbus_mach_info *pdata;
180 struct platform_device *pdev;
181 int gpio;
182
183 gpio_vbus = container_of(otg->phy, struct gpio_vbus_data, phy);
184 pdev = to_platform_device(gpio_vbus->dev);
185 pdata = gpio_vbus->dev->platform_data;
186 gpio = pdata->gpio_pullup;
187
188 if (!gadget) {
189 dev_dbg(&pdev->dev, "unregistering gadget '%s'\n",
190 otg->gadget->name);
191
192 /* optionally disable D+ pullup */
193 if (gpio_is_valid(gpio))
194 gpio_set_value(gpio, pdata->gpio_pullup_inverted);
195
196 set_vbus_draw(gpio_vbus, 0);
197
198 usb_gadget_vbus_disconnect(otg->gadget);
199 otg->phy->state = OTG_STATE_UNDEFINED;
200
201 otg->gadget = NULL;
202 return 0;
203 }
204
205 otg->gadget = gadget;
206 dev_dbg(&pdev->dev, "registered gadget '%s'\n", gadget->name);
207
208 /* initialize connection state */
209 gpio_vbus->vbus = 0; /* start with disconnected */
210 gpio_vbus_irq(gpio_vbus->irq, pdev);
211 return 0;
212}
213
214/* effective for B devices, ignored for A-peripheral */
215static int gpio_vbus_set_power(struct usb_phy *phy, unsigned mA)
216{
217 struct gpio_vbus_data *gpio_vbus;
218
219 gpio_vbus = container_of(phy, struct gpio_vbus_data, phy);
220
221 if (phy->state == OTG_STATE_B_PERIPHERAL)
222 set_vbus_draw(gpio_vbus, mA);
223 return 0;
224}
225
226/* for non-OTG B devices: set/clear transceiver suspend mode */
227static int gpio_vbus_set_suspend(struct usb_phy *phy, int suspend)
228{
229 struct gpio_vbus_data *gpio_vbus;
230
231 gpio_vbus = container_of(phy, struct gpio_vbus_data, phy);
232
233 /* draw max 0 mA from vbus in suspend mode; or the previously
234 * recorded amount of current if not suspended
235 *
236 * NOTE: high powered configs (mA > 100) may draw up to 2.5 mA
237 * if they're wake-enabled ... we don't handle that yet.
238 */
239 return gpio_vbus_set_power(phy, suspend ? 0 : gpio_vbus->mA);
240}
241
242/* platform driver interface */
243
244static int __init gpio_vbus_probe(struct platform_device *pdev)
245{
246 struct gpio_vbus_mach_info *pdata = pdev->dev.platform_data;
247 struct gpio_vbus_data *gpio_vbus;
248 struct resource *res;
249 int err, gpio, irq;
250 unsigned long irqflags;
251
252 if (!pdata || !gpio_is_valid(pdata->gpio_vbus))
253 return -EINVAL;
254 gpio = pdata->gpio_vbus;
255
256 gpio_vbus = kzalloc(sizeof(struct gpio_vbus_data), GFP_KERNEL);
257 if (!gpio_vbus)
258 return -ENOMEM;
259
260 gpio_vbus->phy.otg = kzalloc(sizeof(struct usb_otg), GFP_KERNEL);
261 if (!gpio_vbus->phy.otg) {
262 kfree(gpio_vbus);
263 return -ENOMEM;
264 }
265
266 platform_set_drvdata(pdev, gpio_vbus);
267 gpio_vbus->dev = &pdev->dev;
268 gpio_vbus->phy.label = "gpio-vbus";
269 gpio_vbus->phy.set_power = gpio_vbus_set_power;
270 gpio_vbus->phy.set_suspend = gpio_vbus_set_suspend;
271 gpio_vbus->phy.state = OTG_STATE_UNDEFINED;
272
273 gpio_vbus->phy.otg->phy = &gpio_vbus->phy;
274 gpio_vbus->phy.otg->set_peripheral = gpio_vbus_set_peripheral;
275
276 err = gpio_request(gpio, "vbus_detect");
277 if (err) {
278 dev_err(&pdev->dev, "can't request vbus gpio %d, err: %d\n",
279 gpio, err);
280 goto err_gpio;
281 }
282 gpio_direction_input(gpio);
283
284 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
285 if (res) {
286 irq = res->start;
287 irqflags = (res->flags & IRQF_TRIGGER_MASK) | IRQF_SHARED;
288 } else {
289 irq = gpio_to_irq(gpio);
290 irqflags = VBUS_IRQ_FLAGS;
291 }
292
293 gpio_vbus->irq = irq;
294
295 /* if data line pullup is in use, initialize it to "not pulling up" */
296 gpio = pdata->gpio_pullup;
297 if (gpio_is_valid(gpio)) {
298 err = gpio_request(gpio, "udc_pullup");
299 if (err) {
300 dev_err(&pdev->dev,
301 "can't request pullup gpio %d, err: %d\n",
302 gpio, err);
303 gpio_free(pdata->gpio_vbus);
304 goto err_gpio;
305 }
306 gpio_direction_output(gpio, pdata->gpio_pullup_inverted);
307 }
308
309 err = request_irq(irq, gpio_vbus_irq, irqflags, "vbus_detect", pdev);
310 if (err) {
311 dev_err(&pdev->dev, "can't request irq %i, err: %d\n",
312 irq, err);
313 goto err_irq;
314 }
315
316 ATOMIC_INIT_NOTIFIER_HEAD(&gpio_vbus->phy.notifier);
317
318 INIT_DELAYED_WORK(&gpio_vbus->work, gpio_vbus_work);
319
320 gpio_vbus->vbus_draw = regulator_get(&pdev->dev, "vbus_draw");
321 if (IS_ERR(gpio_vbus->vbus_draw)) {
322 dev_dbg(&pdev->dev, "can't get vbus_draw regulator, err: %ld\n",
323 PTR_ERR(gpio_vbus->vbus_draw));
324 gpio_vbus->vbus_draw = NULL;
325 }
326
327 /* only active when a gadget is registered */
328 err = usb_add_phy(&gpio_vbus->phy, USB_PHY_TYPE_USB2);
329 if (err) {
330 dev_err(&pdev->dev, "can't register transceiver, err: %d\n",
331 err);
332 goto err_otg;
333 }
334
335 device_init_wakeup(&pdev->dev, pdata->wakeup);
336
337 return 0;
338err_otg:
339 regulator_put(gpio_vbus->vbus_draw);
340 free_irq(irq, pdev);
341err_irq:
342 if (gpio_is_valid(pdata->gpio_pullup))
343 gpio_free(pdata->gpio_pullup);
344 gpio_free(pdata->gpio_vbus);
345err_gpio:
346 platform_set_drvdata(pdev, NULL);
347 kfree(gpio_vbus->phy.otg);
348 kfree(gpio_vbus);
349 return err;
350}
351
352static int __exit gpio_vbus_remove(struct platform_device *pdev)
353{
354 struct gpio_vbus_data *gpio_vbus = platform_get_drvdata(pdev);
355 struct gpio_vbus_mach_info *pdata = pdev->dev.platform_data;
356 int gpio = pdata->gpio_vbus;
357
358 device_init_wakeup(&pdev->dev, 0);
359 cancel_delayed_work_sync(&gpio_vbus->work);
360 regulator_put(gpio_vbus->vbus_draw);
361
362 usb_remove_phy(&gpio_vbus->phy);
363
364 free_irq(gpio_vbus->irq, pdev);
365 if (gpio_is_valid(pdata->gpio_pullup))
366 gpio_free(pdata->gpio_pullup);
367 gpio_free(gpio);
368 platform_set_drvdata(pdev, NULL);
369 kfree(gpio_vbus->phy.otg);
370 kfree(gpio_vbus);
371
372 return 0;
373}
374
375#ifdef CONFIG_PM
376static int gpio_vbus_pm_suspend(struct device *dev)
377{
378 struct gpio_vbus_data *gpio_vbus = dev_get_drvdata(dev);
379
380 if (device_may_wakeup(dev))
381 enable_irq_wake(gpio_vbus->irq);
382
383 return 0;
384}
385
386static int gpio_vbus_pm_resume(struct device *dev)
387{
388 struct gpio_vbus_data *gpio_vbus = dev_get_drvdata(dev);
389
390 if (device_may_wakeup(dev))
391 disable_irq_wake(gpio_vbus->irq);
392
393 return 0;
394}
395
396static const struct dev_pm_ops gpio_vbus_dev_pm_ops = {
397 .suspend = gpio_vbus_pm_suspend,
398 .resume = gpio_vbus_pm_resume,
399};
400#endif
401
402/* NOTE: the gpio-vbus device may *NOT* be hotplugged */
403
404MODULE_ALIAS("platform:gpio-vbus");
405
406static struct platform_driver gpio_vbus_driver = {
407 .driver = {
408 .name = "gpio-vbus",
409 .owner = THIS_MODULE,
410#ifdef CONFIG_PM
411 .pm = &gpio_vbus_dev_pm_ops,
412#endif
413 },
414 .remove = __exit_p(gpio_vbus_remove),
415};
416
417module_platform_driver_probe(gpio_vbus_driver, gpio_vbus_probe);
418
419MODULE_DESCRIPTION("simple GPIO controlled OTG transceiver driver");
420MODULE_AUTHOR("Philipp Zabel");
421MODULE_LICENSE("GPL");
diff --git a/drivers/usb/phy/phy-isp1301-omap.c b/drivers/usb/phy/phy-isp1301-omap.c
new file mode 100644
index 000000000000..ae481afcb3ec
--- /dev/null
+++ b/drivers/usb/phy/phy-isp1301-omap.c
@@ -0,0 +1,1656 @@
1/*
2 * isp1301_omap - ISP 1301 USB transceiver, talking to OMAP OTG controller
3 *
4 * Copyright (C) 2004 Texas Instruments
5 * Copyright (C) 2004 David Brownell
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 */
21
22#include <linux/kernel.h>
23#include <linux/module.h>
24#include <linux/init.h>
25#include <linux/slab.h>
26#include <linux/interrupt.h>
27#include <linux/platform_device.h>
28#include <linux/gpio.h>
29#include <linux/usb/ch9.h>
30#include <linux/usb/gadget.h>
31#include <linux/usb.h>
32#include <linux/usb/otg.h>
33#include <linux/i2c.h>
34#include <linux/workqueue.h>
35
36#include <asm/irq.h>
37#include <asm/mach-types.h>
38
39#include <mach/mux.h>
40
41#include <mach/usb.h>
42
43#ifndef DEBUG
44#undef VERBOSE
45#endif
46
47
48#define DRIVER_VERSION "24 August 2004"
49#define DRIVER_NAME (isp1301_driver.driver.name)
50
51MODULE_DESCRIPTION("ISP1301 USB OTG Transceiver Driver");
52MODULE_LICENSE("GPL");
53
54struct isp1301 {
55 struct usb_phy phy;
56 struct i2c_client *client;
57 void (*i2c_release)(struct device *dev);
58
59 int irq_type;
60
61 u32 last_otg_ctrl;
62 unsigned working:1;
63
64 struct timer_list timer;
65
66 /* use keventd context to change the state for us */
67 struct work_struct work;
68
69 unsigned long todo;
70# define WORK_UPDATE_ISP 0 /* update ISP from OTG */
71# define WORK_UPDATE_OTG 1 /* update OTG from ISP */
72# define WORK_HOST_RESUME 4 /* resume host */
73# define WORK_TIMER 6 /* timer fired */
74# define WORK_STOP 7 /* don't resubmit */
75};
76
77
78/* bits in OTG_CTRL */
79
80#define OTG_XCEIV_OUTPUTS \
81 (OTG_ASESSVLD|OTG_BSESSEND|OTG_BSESSVLD|OTG_VBUSVLD|OTG_ID)
82#define OTG_XCEIV_INPUTS \
83 (OTG_PULLDOWN|OTG_PULLUP|OTG_DRV_VBUS|OTG_PD_VBUS|OTG_PU_VBUS|OTG_PU_ID)
84#define OTG_CTRL_BITS \
85 (OTG_A_BUSREQ|OTG_A_SETB_HNPEN|OTG_B_BUSREQ|OTG_B_HNPEN|OTG_BUSDROP)
86 /* and OTG_PULLUP is sometimes written */
87
88#define OTG_CTRL_MASK (OTG_DRIVER_SEL| \
89 OTG_XCEIV_OUTPUTS|OTG_XCEIV_INPUTS| \
90 OTG_CTRL_BITS)
91
92
93/*-------------------------------------------------------------------------*/
94
95/* board-specific PM hooks */
96
97#if defined(CONFIG_MACH_OMAP_H2) || defined(CONFIG_MACH_OMAP_H3)
98
99#if defined(CONFIG_TPS65010) || defined(CONFIG_TPS65010_MODULE)
100
101#include <linux/i2c/tps65010.h>
102
103#else
104
105static inline int tps65010_set_vbus_draw(unsigned mA)
106{
107 pr_debug("tps65010: draw %d mA (STUB)\n", mA);
108 return 0;
109}
110
111#endif
112
113static void enable_vbus_draw(struct isp1301 *isp, unsigned mA)
114{
115 int status = tps65010_set_vbus_draw(mA);
116 if (status < 0)
117 pr_debug(" VBUS %d mA error %d\n", mA, status);
118}
119
120#else
121
122static void enable_vbus_draw(struct isp1301 *isp, unsigned mA)
123{
124 /* H4 controls this by DIP switch S2.4; no soft control.
125 * ON means the charger is always enabled. Leave it OFF
126 * unless the OTG port is used only in B-peripheral mode.
127 */
128}
129
130#endif
131
132static void enable_vbus_source(struct isp1301 *isp)
133{
134 /* this board won't supply more than 8mA vbus power.
135 * some boards can switch a 100ma "unit load" (or more).
136 */
137}
138
139
140/* products will deliver OTG messages with LEDs, GUI, etc */
141static inline void notresponding(struct isp1301 *isp)
142{
143 printk(KERN_NOTICE "OTG device not responding.\n");
144}
145
146
147/*-------------------------------------------------------------------------*/
148
149static struct i2c_driver isp1301_driver;
150
151/* smbus apis are used for portability */
152
153static inline u8
154isp1301_get_u8(struct isp1301 *isp, u8 reg)
155{
156 return i2c_smbus_read_byte_data(isp->client, reg + 0);
157}
158
159static inline int
160isp1301_get_u16(struct isp1301 *isp, u8 reg)
161{
162 return i2c_smbus_read_word_data(isp->client, reg);
163}
164
165static inline int
166isp1301_set_bits(struct isp1301 *isp, u8 reg, u8 bits)
167{
168 return i2c_smbus_write_byte_data(isp->client, reg + 0, bits);
169}
170
171static inline int
172isp1301_clear_bits(struct isp1301 *isp, u8 reg, u8 bits)
173{
174 return i2c_smbus_write_byte_data(isp->client, reg + 1, bits);
175}
176
177/*-------------------------------------------------------------------------*/
178
179/* identification */
180#define ISP1301_VENDOR_ID 0x00 /* u16 read */
181#define ISP1301_PRODUCT_ID 0x02 /* u16 read */
182#define ISP1301_BCD_DEVICE 0x14 /* u16 read */
183
184#define I2C_VENDOR_ID_PHILIPS 0x04cc
185#define I2C_PRODUCT_ID_PHILIPS_1301 0x1301
186
187/* operational registers */
188#define ISP1301_MODE_CONTROL_1 0x04 /* u8 read, set, +1 clear */
189# define MC1_SPEED (1 << 0)
190# define MC1_SUSPEND (1 << 1)
191# define MC1_DAT_SE0 (1 << 2)
192# define MC1_TRANSPARENT (1 << 3)
193# define MC1_BDIS_ACON_EN (1 << 4)
194# define MC1_OE_INT_EN (1 << 5)
195# define MC1_UART_EN (1 << 6)
196# define MC1_MASK 0x7f
197#define ISP1301_MODE_CONTROL_2 0x12 /* u8 read, set, +1 clear */
198# define MC2_GLOBAL_PWR_DN (1 << 0)
199# define MC2_SPD_SUSP_CTRL (1 << 1)
200# define MC2_BI_DI (1 << 2)
201# define MC2_TRANSP_BDIR0 (1 << 3)
202# define MC2_TRANSP_BDIR1 (1 << 4)
203# define MC2_AUDIO_EN (1 << 5)
204# define MC2_PSW_EN (1 << 6)
205# define MC2_EN2V7 (1 << 7)
206#define ISP1301_OTG_CONTROL_1 0x06 /* u8 read, set, +1 clear */
207# define OTG1_DP_PULLUP (1 << 0)
208# define OTG1_DM_PULLUP (1 << 1)
209# define OTG1_DP_PULLDOWN (1 << 2)
210# define OTG1_DM_PULLDOWN (1 << 3)
211# define OTG1_ID_PULLDOWN (1 << 4)
212# define OTG1_VBUS_DRV (1 << 5)
213# define OTG1_VBUS_DISCHRG (1 << 6)
214# define OTG1_VBUS_CHRG (1 << 7)
215#define ISP1301_OTG_STATUS 0x10 /* u8 readonly */
216# define OTG_B_SESS_END (1 << 6)
217# define OTG_B_SESS_VLD (1 << 7)
218
219#define ISP1301_INTERRUPT_SOURCE 0x08 /* u8 read */
220#define ISP1301_INTERRUPT_LATCH 0x0A /* u8 read, set, +1 clear */
221
222#define ISP1301_INTERRUPT_FALLING 0x0C /* u8 read, set, +1 clear */
223#define ISP1301_INTERRUPT_RISING 0x0E /* u8 read, set, +1 clear */
224
225/* same bitfields in all interrupt registers */
226# define INTR_VBUS_VLD (1 << 0)
227# define INTR_SESS_VLD (1 << 1)
228# define INTR_DP_HI (1 << 2)
229# define INTR_ID_GND (1 << 3)
230# define INTR_DM_HI (1 << 4)
231# define INTR_ID_FLOAT (1 << 5)
232# define INTR_BDIS_ACON (1 << 6)
233# define INTR_CR_INT (1 << 7)
234
235/*-------------------------------------------------------------------------*/
236
237static inline const char *state_name(struct isp1301 *isp)
238{
239 return usb_otg_state_string(isp->phy.state);
240}
241
242/*-------------------------------------------------------------------------*/
243
244/* NOTE: some of this ISP1301 setup is specific to H2 boards;
245 * not everything is guarded by board-specific checks, or even using
246 * omap_usb_config data to deduce MC1_DAT_SE0 and MC2_BI_DI.
247 *
248 * ALSO: this currently doesn't use ISP1301 low-power modes
249 * while OTG is running.
250 */
251
252static void power_down(struct isp1301 *isp)
253{
254 isp->phy.state = OTG_STATE_UNDEFINED;
255
256 // isp1301_set_bits(isp, ISP1301_MODE_CONTROL_2, MC2_GLOBAL_PWR_DN);
257 isp1301_set_bits(isp, ISP1301_MODE_CONTROL_1, MC1_SUSPEND);
258
259 isp1301_clear_bits(isp, ISP1301_OTG_CONTROL_1, OTG1_ID_PULLDOWN);
260 isp1301_clear_bits(isp, ISP1301_MODE_CONTROL_1, MC1_DAT_SE0);
261}
262
263static void power_up(struct isp1301 *isp)
264{
265 // isp1301_clear_bits(isp, ISP1301_MODE_CONTROL_2, MC2_GLOBAL_PWR_DN);
266 isp1301_clear_bits(isp, ISP1301_MODE_CONTROL_1, MC1_SUSPEND);
267
268 /* do this only when cpu is driving transceiver,
269 * so host won't see a low speed device...
270 */
271 isp1301_set_bits(isp, ISP1301_MODE_CONTROL_1, MC1_DAT_SE0);
272}
273
274#define NO_HOST_SUSPEND
275
276static int host_suspend(struct isp1301 *isp)
277{
278#ifdef NO_HOST_SUSPEND
279 return 0;
280#else
281 struct device *dev;
282
283 if (!isp->phy.otg->host)
284 return -ENODEV;
285
286 /* Currently ASSUMES only the OTG port matters;
287 * other ports could be active...
288 */
289 dev = isp->phy.otg->host->controller;
290 return dev->driver->suspend(dev, 3, 0);
291#endif
292}
293
294static int host_resume(struct isp1301 *isp)
295{
296#ifdef NO_HOST_SUSPEND
297 return 0;
298#else
299 struct device *dev;
300
301 if (!isp->phy.otg->host)
302 return -ENODEV;
303
304 dev = isp->phy.otg->host->controller;
305 return dev->driver->resume(dev, 0);
306#endif
307}
308
309static int gadget_suspend(struct isp1301 *isp)
310{
311 isp->phy.otg->gadget->b_hnp_enable = 0;
312 isp->phy.otg->gadget->a_hnp_support = 0;
313 isp->phy.otg->gadget->a_alt_hnp_support = 0;
314 return usb_gadget_vbus_disconnect(isp->phy.otg->gadget);
315}
316
317/*-------------------------------------------------------------------------*/
318
319#define TIMER_MINUTES 10
320#define TIMER_JIFFIES (TIMER_MINUTES * 60 * HZ)
321
322/* Almost all our I2C messaging comes from a work queue's task context.
323 * NOTE: guaranteeing certain response times might mean we shouldn't
324 * share keventd's work queue; a realtime task might be safest.
325 */
326static void isp1301_defer_work(struct isp1301 *isp, int work)
327{
328 int status;
329
330 if (isp && !test_and_set_bit(work, &isp->todo)) {
331 (void) get_device(&isp->client->dev);
332 status = schedule_work(&isp->work);
333 if (!status && !isp->working)
334 dev_vdbg(&isp->client->dev,
335 "work item %d may be lost\n", work);
336 }
337}
338
339/* called from irq handlers */
340static void a_idle(struct isp1301 *isp, const char *tag)
341{
342 u32 l;
343
344 if (isp->phy.state == OTG_STATE_A_IDLE)
345 return;
346
347 isp->phy.otg->default_a = 1;
348 if (isp->phy.otg->host) {
349 isp->phy.otg->host->is_b_host = 0;
350 host_suspend(isp);
351 }
352 if (isp->phy.otg->gadget) {
353 isp->phy.otg->gadget->is_a_peripheral = 1;
354 gadget_suspend(isp);
355 }
356 isp->phy.state = OTG_STATE_A_IDLE;
357 l = omap_readl(OTG_CTRL) & OTG_XCEIV_OUTPUTS;
358 omap_writel(l, OTG_CTRL);
359 isp->last_otg_ctrl = l;
360 pr_debug(" --> %s/%s\n", state_name(isp), tag);
361}
362
363/* called from irq handlers */
364static void b_idle(struct isp1301 *isp, const char *tag)
365{
366 u32 l;
367
368 if (isp->phy.state == OTG_STATE_B_IDLE)
369 return;
370
371 isp->phy.otg->default_a = 0;
372 if (isp->phy.otg->host) {
373 isp->phy.otg->host->is_b_host = 1;
374 host_suspend(isp);
375 }
376 if (isp->phy.otg->gadget) {
377 isp->phy.otg->gadget->is_a_peripheral = 0;
378 gadget_suspend(isp);
379 }
380 isp->phy.state = OTG_STATE_B_IDLE;
381 l = omap_readl(OTG_CTRL) & OTG_XCEIV_OUTPUTS;
382 omap_writel(l, OTG_CTRL);
383 isp->last_otg_ctrl = l;
384 pr_debug(" --> %s/%s\n", state_name(isp), tag);
385}
386
387static void
388dump_regs(struct isp1301 *isp, const char *label)
389{
390#ifdef DEBUG
391 u8 ctrl = isp1301_get_u8(isp, ISP1301_OTG_CONTROL_1);
392 u8 status = isp1301_get_u8(isp, ISP1301_OTG_STATUS);
393 u8 src = isp1301_get_u8(isp, ISP1301_INTERRUPT_SOURCE);
394
395 pr_debug("otg: %06x, %s %s, otg/%02x stat/%02x.%02x\n",
396 omap_readl(OTG_CTRL), label, state_name(isp),
397 ctrl, status, src);
398 /* mode control and irq enables don't change much */
399#endif
400}
401
402/*-------------------------------------------------------------------------*/
403
404#ifdef CONFIG_USB_OTG
405
406/*
407 * The OMAP OTG controller handles most of the OTG state transitions.
408 *
409 * We translate isp1301 outputs (mostly voltage comparator status) into
410 * OTG inputs; OTG outputs (mostly pullup/pulldown controls) and HNP state
411 * flags into isp1301 inputs ... and infer state transitions.
412 */
413
414#ifdef VERBOSE
415
416static void check_state(struct isp1301 *isp, const char *tag)
417{
418 enum usb_otg_state state = OTG_STATE_UNDEFINED;
419 u8 fsm = omap_readw(OTG_TEST) & 0x0ff;
420 unsigned extra = 0;
421
422 switch (fsm) {
423
424 /* default-b */
425 case 0x0:
426 state = OTG_STATE_B_IDLE;
427 break;
428 case 0x3:
429 case 0x7:
430 extra = 1;
431 case 0x1:
432 state = OTG_STATE_B_PERIPHERAL;
433 break;
434 case 0x11:
435 state = OTG_STATE_B_SRP_INIT;
436 break;
437
438 /* extra dual-role default-b states */
439 case 0x12:
440 case 0x13:
441 case 0x16:
442 extra = 1;
443 case 0x17:
444 state = OTG_STATE_B_WAIT_ACON;
445 break;
446 case 0x34:
447 state = OTG_STATE_B_HOST;
448 break;
449
450 /* default-a */
451 case 0x36:
452 state = OTG_STATE_A_IDLE;
453 break;
454 case 0x3c:
455 state = OTG_STATE_A_WAIT_VFALL;
456 break;
457 case 0x7d:
458 state = OTG_STATE_A_VBUS_ERR;
459 break;
460 case 0x9e:
461 case 0x9f:
462 extra = 1;
463 case 0x89:
464 state = OTG_STATE_A_PERIPHERAL;
465 break;
466 case 0xb7:
467 state = OTG_STATE_A_WAIT_VRISE;
468 break;
469 case 0xb8:
470 state = OTG_STATE_A_WAIT_BCON;
471 break;
472 case 0xb9:
473 state = OTG_STATE_A_HOST;
474 break;
475 case 0xba:
476 state = OTG_STATE_A_SUSPEND;
477 break;
478 default:
479 break;
480 }
481 if (isp->phy.state == state && !extra)
482 return;
483 pr_debug("otg: %s FSM %s/%02x, %s, %06x\n", tag,
484 usb_otg_state_string(state), fsm, state_name(isp),
485 omap_readl(OTG_CTRL));
486}
487
488#else
489
490static inline void check_state(struct isp1301 *isp, const char *tag) { }
491
492#endif
493
494/* outputs from ISP1301_INTERRUPT_SOURCE */
495static void update_otg1(struct isp1301 *isp, u8 int_src)
496{
497 u32 otg_ctrl;
498
499 otg_ctrl = omap_readl(OTG_CTRL) & OTG_CTRL_MASK;
500 otg_ctrl &= ~OTG_XCEIV_INPUTS;
501 otg_ctrl &= ~(OTG_ID|OTG_ASESSVLD|OTG_VBUSVLD);
502
503 if (int_src & INTR_SESS_VLD)
504 otg_ctrl |= OTG_ASESSVLD;
505 else if (isp->phy.state == OTG_STATE_A_WAIT_VFALL) {
506 a_idle(isp, "vfall");
507 otg_ctrl &= ~OTG_CTRL_BITS;
508 }
509 if (int_src & INTR_VBUS_VLD)
510 otg_ctrl |= OTG_VBUSVLD;
511 if (int_src & INTR_ID_GND) { /* default-A */
512 if (isp->phy.state == OTG_STATE_B_IDLE
513 || isp->phy.state
514 == OTG_STATE_UNDEFINED) {
515 a_idle(isp, "init");
516 return;
517 }
518 } else { /* default-B */
519 otg_ctrl |= OTG_ID;
520 if (isp->phy.state == OTG_STATE_A_IDLE
521 || isp->phy.state == OTG_STATE_UNDEFINED) {
522 b_idle(isp, "init");
523 return;
524 }
525 }
526 omap_writel(otg_ctrl, OTG_CTRL);
527}
528
529/* outputs from ISP1301_OTG_STATUS */
530static void update_otg2(struct isp1301 *isp, u8 otg_status)
531{
532 u32 otg_ctrl;
533
534 otg_ctrl = omap_readl(OTG_CTRL) & OTG_CTRL_MASK;
535 otg_ctrl &= ~OTG_XCEIV_INPUTS;
536 otg_ctrl &= ~(OTG_BSESSVLD | OTG_BSESSEND);
537 if (otg_status & OTG_B_SESS_VLD)
538 otg_ctrl |= OTG_BSESSVLD;
539 else if (otg_status & OTG_B_SESS_END)
540 otg_ctrl |= OTG_BSESSEND;
541 omap_writel(otg_ctrl, OTG_CTRL);
542}
543
544/* inputs going to ISP1301 */
545static void otg_update_isp(struct isp1301 *isp)
546{
547 u32 otg_ctrl, otg_change;
548 u8 set = OTG1_DM_PULLDOWN, clr = OTG1_DM_PULLUP;
549
550 otg_ctrl = omap_readl(OTG_CTRL);
551 otg_change = otg_ctrl ^ isp->last_otg_ctrl;
552 isp->last_otg_ctrl = otg_ctrl;
553 otg_ctrl = otg_ctrl & OTG_XCEIV_INPUTS;
554
555 switch (isp->phy.state) {
556 case OTG_STATE_B_IDLE:
557 case OTG_STATE_B_PERIPHERAL:
558 case OTG_STATE_B_SRP_INIT:
559 if (!(otg_ctrl & OTG_PULLUP)) {
560 // if (otg_ctrl & OTG_B_HNPEN) {
561 if (isp->phy.otg->gadget->b_hnp_enable) {
562 isp->phy.state = OTG_STATE_B_WAIT_ACON;
563 pr_debug(" --> b_wait_acon\n");
564 }
565 goto pulldown;
566 }
567pullup:
568 set |= OTG1_DP_PULLUP;
569 clr |= OTG1_DP_PULLDOWN;
570 break;
571 case OTG_STATE_A_SUSPEND:
572 case OTG_STATE_A_PERIPHERAL:
573 if (otg_ctrl & OTG_PULLUP)
574 goto pullup;
575 /* FALLTHROUGH */
576 // case OTG_STATE_B_WAIT_ACON:
577 default:
578pulldown:
579 set |= OTG1_DP_PULLDOWN;
580 clr |= OTG1_DP_PULLUP;
581 break;
582 }
583
584# define toggle(OTG,ISP) do { \
585 if (otg_ctrl & OTG) set |= ISP; \
586 else clr |= ISP; \
587 } while (0)
588
589 if (!(isp->phy.otg->host))
590 otg_ctrl &= ~OTG_DRV_VBUS;
591
592 switch (isp->phy.state) {
593 case OTG_STATE_A_SUSPEND:
594 if (otg_ctrl & OTG_DRV_VBUS) {
595 set |= OTG1_VBUS_DRV;
596 break;
597 }
598 /* HNP failed for some reason (A_AIDL_BDIS timeout) */
599 notresponding(isp);
600
601 /* FALLTHROUGH */
602 case OTG_STATE_A_VBUS_ERR:
603 isp->phy.state = OTG_STATE_A_WAIT_VFALL;
604 pr_debug(" --> a_wait_vfall\n");
605 /* FALLTHROUGH */
606 case OTG_STATE_A_WAIT_VFALL:
607 /* FIXME usbcore thinks port power is still on ... */
608 clr |= OTG1_VBUS_DRV;
609 break;
610 case OTG_STATE_A_IDLE:
611 if (otg_ctrl & OTG_DRV_VBUS) {
612 isp->phy.state = OTG_STATE_A_WAIT_VRISE;
613 pr_debug(" --> a_wait_vrise\n");
614 }
615 /* FALLTHROUGH */
616 default:
617 toggle(OTG_DRV_VBUS, OTG1_VBUS_DRV);
618 }
619
620 toggle(OTG_PU_VBUS, OTG1_VBUS_CHRG);
621 toggle(OTG_PD_VBUS, OTG1_VBUS_DISCHRG);
622
623# undef toggle
624
625 isp1301_set_bits(isp, ISP1301_OTG_CONTROL_1, set);
626 isp1301_clear_bits(isp, ISP1301_OTG_CONTROL_1, clr);
627
628 /* HNP switch to host or peripheral; and SRP */
629 if (otg_change & OTG_PULLUP) {
630 u32 l;
631
632 switch (isp->phy.state) {
633 case OTG_STATE_B_IDLE:
634 if (clr & OTG1_DP_PULLUP)
635 break;
636 isp->phy.state = OTG_STATE_B_PERIPHERAL;
637 pr_debug(" --> b_peripheral\n");
638 break;
639 case OTG_STATE_A_SUSPEND:
640 if (clr & OTG1_DP_PULLUP)
641 break;
642 isp->phy.state = OTG_STATE_A_PERIPHERAL;
643 pr_debug(" --> a_peripheral\n");
644 break;
645 default:
646 break;
647 }
648 l = omap_readl(OTG_CTRL);
649 l |= OTG_PULLUP;
650 omap_writel(l, OTG_CTRL);
651 }
652
653 check_state(isp, __func__);
654 dump_regs(isp, "otg->isp1301");
655}
656
657static irqreturn_t omap_otg_irq(int irq, void *_isp)
658{
659 u16 otg_irq = omap_readw(OTG_IRQ_SRC);
660 u32 otg_ctrl;
661 int ret = IRQ_NONE;
662 struct isp1301 *isp = _isp;
663 struct usb_otg *otg = isp->phy.otg;
664
665 /* update ISP1301 transceiver from OTG controller */
666 if (otg_irq & OPRT_CHG) {
667 omap_writew(OPRT_CHG, OTG_IRQ_SRC);
668 isp1301_defer_work(isp, WORK_UPDATE_ISP);
669 ret = IRQ_HANDLED;
670
671 /* SRP to become b_peripheral failed */
672 } else if (otg_irq & B_SRP_TMROUT) {
673 pr_debug("otg: B_SRP_TIMEOUT, %06x\n", omap_readl(OTG_CTRL));
674 notresponding(isp);
675
676 /* gadget drivers that care should monitor all kinds of
677 * remote wakeup (SRP, normal) using their own timer
678 * to give "check cable and A-device" messages.
679 */
680 if (isp->phy.state == OTG_STATE_B_SRP_INIT)
681 b_idle(isp, "srp_timeout");
682
683 omap_writew(B_SRP_TMROUT, OTG_IRQ_SRC);
684 ret = IRQ_HANDLED;
685
686 /* HNP to become b_host failed */
687 } else if (otg_irq & B_HNP_FAIL) {
688 pr_debug("otg: %s B_HNP_FAIL, %06x\n",
689 state_name(isp), omap_readl(OTG_CTRL));
690 notresponding(isp);
691
692 otg_ctrl = omap_readl(OTG_CTRL);
693 otg_ctrl |= OTG_BUSDROP;
694 otg_ctrl &= OTG_CTRL_MASK & ~OTG_XCEIV_INPUTS;
695 omap_writel(otg_ctrl, OTG_CTRL);
696
697 /* subset of b_peripheral()... */
698 isp->phy.state = OTG_STATE_B_PERIPHERAL;
699 pr_debug(" --> b_peripheral\n");
700
701 omap_writew(B_HNP_FAIL, OTG_IRQ_SRC);
702 ret = IRQ_HANDLED;
703
704 /* detect SRP from B-device ... */
705 } else if (otg_irq & A_SRP_DETECT) {
706 pr_debug("otg: %s SRP_DETECT, %06x\n",
707 state_name(isp), omap_readl(OTG_CTRL));
708
709 isp1301_defer_work(isp, WORK_UPDATE_OTG);
710 switch (isp->phy.state) {
711 case OTG_STATE_A_IDLE:
712 if (!otg->host)
713 break;
714 isp1301_defer_work(isp, WORK_HOST_RESUME);
715 otg_ctrl = omap_readl(OTG_CTRL);
716 otg_ctrl |= OTG_A_BUSREQ;
717 otg_ctrl &= ~(OTG_BUSDROP|OTG_B_BUSREQ)
718 & ~OTG_XCEIV_INPUTS
719 & OTG_CTRL_MASK;
720 omap_writel(otg_ctrl, OTG_CTRL);
721 break;
722 default:
723 break;
724 }
725
726 omap_writew(A_SRP_DETECT, OTG_IRQ_SRC);
727 ret = IRQ_HANDLED;
728
729 /* timer expired: T(a_wait_bcon) and maybe T(a_wait_vrise)
730 * we don't track them separately
731 */
732 } else if (otg_irq & A_REQ_TMROUT) {
733 otg_ctrl = omap_readl(OTG_CTRL);
734 pr_info("otg: BCON_TMOUT from %s, %06x\n",
735 state_name(isp), otg_ctrl);
736 notresponding(isp);
737
738 otg_ctrl |= OTG_BUSDROP;
739 otg_ctrl &= ~OTG_A_BUSREQ & OTG_CTRL_MASK & ~OTG_XCEIV_INPUTS;
740 omap_writel(otg_ctrl, OTG_CTRL);
741 isp->phy.state = OTG_STATE_A_WAIT_VFALL;
742
743 omap_writew(A_REQ_TMROUT, OTG_IRQ_SRC);
744 ret = IRQ_HANDLED;
745
746 /* A-supplied voltage fell too low; overcurrent */
747 } else if (otg_irq & A_VBUS_ERR) {
748 otg_ctrl = omap_readl(OTG_CTRL);
749 printk(KERN_ERR "otg: %s, VBUS_ERR %04x ctrl %06x\n",
750 state_name(isp), otg_irq, otg_ctrl);
751
752 otg_ctrl |= OTG_BUSDROP;
753 otg_ctrl &= ~OTG_A_BUSREQ & OTG_CTRL_MASK & ~OTG_XCEIV_INPUTS;
754 omap_writel(otg_ctrl, OTG_CTRL);
755 isp->phy.state = OTG_STATE_A_VBUS_ERR;
756
757 omap_writew(A_VBUS_ERR, OTG_IRQ_SRC);
758 ret = IRQ_HANDLED;
759
760 /* switch driver; the transceiver code activates it,
761 * ungating the udc clock or resuming OHCI.
762 */
763 } else if (otg_irq & DRIVER_SWITCH) {
764 int kick = 0;
765
766 otg_ctrl = omap_readl(OTG_CTRL);
767 printk(KERN_NOTICE "otg: %s, SWITCH to %s, ctrl %06x\n",
768 state_name(isp),
769 (otg_ctrl & OTG_DRIVER_SEL)
770 ? "gadget" : "host",
771 otg_ctrl);
772 isp1301_defer_work(isp, WORK_UPDATE_ISP);
773
774 /* role is peripheral */
775 if (otg_ctrl & OTG_DRIVER_SEL) {
776 switch (isp->phy.state) {
777 case OTG_STATE_A_IDLE:
778 b_idle(isp, __func__);
779 break;
780 default:
781 break;
782 }
783 isp1301_defer_work(isp, WORK_UPDATE_ISP);
784
785 /* role is host */
786 } else {
787 if (!(otg_ctrl & OTG_ID)) {
788 otg_ctrl &= OTG_CTRL_MASK & ~OTG_XCEIV_INPUTS;
789 omap_writel(otg_ctrl | OTG_A_BUSREQ, OTG_CTRL);
790 }
791
792 if (otg->host) {
793 switch (isp->phy.state) {
794 case OTG_STATE_B_WAIT_ACON:
795 isp->phy.state = OTG_STATE_B_HOST;
796 pr_debug(" --> b_host\n");
797 kick = 1;
798 break;
799 case OTG_STATE_A_WAIT_BCON:
800 isp->phy.state = OTG_STATE_A_HOST;
801 pr_debug(" --> a_host\n");
802 break;
803 case OTG_STATE_A_PERIPHERAL:
804 isp->phy.state = OTG_STATE_A_WAIT_BCON;
805 pr_debug(" --> a_wait_bcon\n");
806 break;
807 default:
808 break;
809 }
810 isp1301_defer_work(isp, WORK_HOST_RESUME);
811 }
812 }
813
814 omap_writew(DRIVER_SWITCH, OTG_IRQ_SRC);
815 ret = IRQ_HANDLED;
816
817 if (kick)
818 usb_bus_start_enum(otg->host, otg->host->otg_port);
819 }
820
821 check_state(isp, __func__);
822 return ret;
823}
824
825static struct platform_device *otg_dev;
826
827static int isp1301_otg_init(struct isp1301 *isp)
828{
829 u32 l;
830
831 if (!otg_dev)
832 return -ENODEV;
833
834 dump_regs(isp, __func__);
835 /* some of these values are board-specific... */
836 l = omap_readl(OTG_SYSCON_2);
837 l |= OTG_EN
838 /* for B-device: */
839 | SRP_GPDATA /* 9msec Bdev D+ pulse */
840 | SRP_GPDVBUS /* discharge after VBUS pulse */
841 // | (3 << 24) /* 2msec VBUS pulse */
842 /* for A-device: */
843 | (0 << 20) /* 200ms nominal A_WAIT_VRISE timer */
844 | SRP_DPW /* detect 167+ns SRP pulses */
845 | SRP_DATA | SRP_VBUS /* accept both kinds of SRP pulse */
846 ;
847 omap_writel(l, OTG_SYSCON_2);
848
849 update_otg1(isp, isp1301_get_u8(isp, ISP1301_INTERRUPT_SOURCE));
850 update_otg2(isp, isp1301_get_u8(isp, ISP1301_OTG_STATUS));
851
852 check_state(isp, __func__);
853 pr_debug("otg: %s, %s %06x\n",
854 state_name(isp), __func__, omap_readl(OTG_CTRL));
855
856 omap_writew(DRIVER_SWITCH | OPRT_CHG
857 | B_SRP_TMROUT | B_HNP_FAIL
858 | A_VBUS_ERR | A_SRP_DETECT | A_REQ_TMROUT, OTG_IRQ_EN);
859
860 l = omap_readl(OTG_SYSCON_2);
861 l |= OTG_EN;
862 omap_writel(l, OTG_SYSCON_2);
863
864 return 0;
865}
866
867static int otg_probe(struct platform_device *dev)
868{
869 // struct omap_usb_config *config = dev->platform_data;
870
871 otg_dev = dev;
872 return 0;
873}
874
875static int otg_remove(struct platform_device *dev)
876{
877 otg_dev = NULL;
878 return 0;
879}
880
881static struct platform_driver omap_otg_driver = {
882 .probe = otg_probe,
883 .remove = otg_remove,
884 .driver = {
885 .owner = THIS_MODULE,
886 .name = "omap_otg",
887 },
888};
889
890static int otg_bind(struct isp1301 *isp)
891{
892 int status;
893
894 if (otg_dev)
895 return -EBUSY;
896
897 status = platform_driver_register(&omap_otg_driver);
898 if (status < 0)
899 return status;
900
901 if (otg_dev)
902 status = request_irq(otg_dev->resource[1].start, omap_otg_irq,
903 0, DRIVER_NAME, isp);
904 else
905 status = -ENODEV;
906
907 if (status < 0)
908 platform_driver_unregister(&omap_otg_driver);
909 return status;
910}
911
912static void otg_unbind(struct isp1301 *isp)
913{
914 if (!otg_dev)
915 return;
916 free_irq(otg_dev->resource[1].start, isp);
917}
918
919#else
920
921/* OTG controller isn't clocked */
922
923#endif /* CONFIG_USB_OTG */
924
925/*-------------------------------------------------------------------------*/
926
927static void b_peripheral(struct isp1301 *isp)
928{
929 u32 l;
930
931 l = omap_readl(OTG_CTRL) & OTG_XCEIV_OUTPUTS;
932 omap_writel(l, OTG_CTRL);
933
934 usb_gadget_vbus_connect(isp->phy.otg->gadget);
935
936#ifdef CONFIG_USB_OTG
937 enable_vbus_draw(isp, 8);
938 otg_update_isp(isp);
939#else
940 enable_vbus_draw(isp, 100);
941 /* UDC driver just set OTG_BSESSVLD */
942 isp1301_set_bits(isp, ISP1301_OTG_CONTROL_1, OTG1_DP_PULLUP);
943 isp1301_clear_bits(isp, ISP1301_OTG_CONTROL_1, OTG1_DP_PULLDOWN);
944 isp->phy.state = OTG_STATE_B_PERIPHERAL;
945 pr_debug(" --> b_peripheral\n");
946 dump_regs(isp, "2periph");
947#endif
948}
949
950static void isp_update_otg(struct isp1301 *isp, u8 stat)
951{
952 struct usb_otg *otg = isp->phy.otg;
953 u8 isp_stat, isp_bstat;
954 enum usb_otg_state state = isp->phy.state;
955
956 if (stat & INTR_BDIS_ACON)
957 pr_debug("OTG: BDIS_ACON, %s\n", state_name(isp));
958
959 /* start certain state transitions right away */
960 isp_stat = isp1301_get_u8(isp, ISP1301_INTERRUPT_SOURCE);
961 if (isp_stat & INTR_ID_GND) {
962 if (otg->default_a) {
963 switch (state) {
964 case OTG_STATE_B_IDLE:
965 a_idle(isp, "idle");
966 /* FALLTHROUGH */
967 case OTG_STATE_A_IDLE:
968 enable_vbus_source(isp);
969 /* FALLTHROUGH */
970 case OTG_STATE_A_WAIT_VRISE:
971 /* we skip over OTG_STATE_A_WAIT_BCON, since
972 * the HC will transition to A_HOST (or
973 * A_SUSPEND!) without our noticing except
974 * when HNP is used.
975 */
976 if (isp_stat & INTR_VBUS_VLD)
977 isp->phy.state = OTG_STATE_A_HOST;
978 break;
979 case OTG_STATE_A_WAIT_VFALL:
980 if (!(isp_stat & INTR_SESS_VLD))
981 a_idle(isp, "vfell");
982 break;
983 default:
984 if (!(isp_stat & INTR_VBUS_VLD))
985 isp->phy.state = OTG_STATE_A_VBUS_ERR;
986 break;
987 }
988 isp_bstat = isp1301_get_u8(isp, ISP1301_OTG_STATUS);
989 } else {
990 switch (state) {
991 case OTG_STATE_B_PERIPHERAL:
992 case OTG_STATE_B_HOST:
993 case OTG_STATE_B_WAIT_ACON:
994 usb_gadget_vbus_disconnect(otg->gadget);
995 break;
996 default:
997 break;
998 }
999 if (state != OTG_STATE_A_IDLE)
1000 a_idle(isp, "id");
1001 if (otg->host && state == OTG_STATE_A_IDLE)
1002 isp1301_defer_work(isp, WORK_HOST_RESUME);
1003 isp_bstat = 0;
1004 }
1005 } else {
1006 u32 l;
1007
1008 /* if user unplugged mini-A end of cable,
1009 * don't bypass A_WAIT_VFALL.
1010 */
1011 if (otg->default_a) {
1012 switch (state) {
1013 default:
1014 isp->phy.state = OTG_STATE_A_WAIT_VFALL;
1015 break;
1016 case OTG_STATE_A_WAIT_VFALL:
1017 state = OTG_STATE_A_IDLE;
1018 /* khubd may take a while to notice and
1019 * handle this disconnect, so don't go
1020 * to B_IDLE quite yet.
1021 */
1022 break;
1023 case OTG_STATE_A_IDLE:
1024 host_suspend(isp);
1025 isp1301_clear_bits(isp, ISP1301_MODE_CONTROL_1,
1026 MC1_BDIS_ACON_EN);
1027 isp->phy.state = OTG_STATE_B_IDLE;
1028 l = omap_readl(OTG_CTRL) & OTG_CTRL_MASK;
1029 l &= ~OTG_CTRL_BITS;
1030 omap_writel(l, OTG_CTRL);
1031 break;
1032 case OTG_STATE_B_IDLE:
1033 break;
1034 }
1035 }
1036 isp_bstat = isp1301_get_u8(isp, ISP1301_OTG_STATUS);
1037
1038 switch (isp->phy.state) {
1039 case OTG_STATE_B_PERIPHERAL:
1040 case OTG_STATE_B_WAIT_ACON:
1041 case OTG_STATE_B_HOST:
1042 if (likely(isp_bstat & OTG_B_SESS_VLD))
1043 break;
1044 enable_vbus_draw(isp, 0);
1045#ifndef CONFIG_USB_OTG
1046 /* UDC driver will clear OTG_BSESSVLD */
1047 isp1301_set_bits(isp, ISP1301_OTG_CONTROL_1,
1048 OTG1_DP_PULLDOWN);
1049 isp1301_clear_bits(isp, ISP1301_OTG_CONTROL_1,
1050 OTG1_DP_PULLUP);
1051 dump_regs(isp, __func__);
1052#endif
1053 /* FALLTHROUGH */
1054 case OTG_STATE_B_SRP_INIT:
1055 b_idle(isp, __func__);
1056 l = omap_readl(OTG_CTRL) & OTG_XCEIV_OUTPUTS;
1057 omap_writel(l, OTG_CTRL);
1058 /* FALLTHROUGH */
1059 case OTG_STATE_B_IDLE:
1060 if (otg->gadget && (isp_bstat & OTG_B_SESS_VLD)) {
1061#ifdef CONFIG_USB_OTG
1062 update_otg1(isp, isp_stat);
1063 update_otg2(isp, isp_bstat);
1064#endif
1065 b_peripheral(isp);
1066 } else if (!(isp_stat & (INTR_VBUS_VLD|INTR_SESS_VLD)))
1067 isp_bstat |= OTG_B_SESS_END;
1068 break;
1069 case OTG_STATE_A_WAIT_VFALL:
1070 break;
1071 default:
1072 pr_debug("otg: unsupported b-device %s\n",
1073 state_name(isp));
1074 break;
1075 }
1076 }
1077
1078 if (state != isp->phy.state)
1079 pr_debug(" isp, %s -> %s\n",
1080 usb_otg_state_string(state), state_name(isp));
1081
1082#ifdef CONFIG_USB_OTG
1083 /* update the OTG controller state to match the isp1301; may
1084 * trigger OPRT_CHG irqs for changes going to the isp1301.
1085 */
1086 update_otg1(isp, isp_stat);
1087 update_otg2(isp, isp_bstat);
1088 check_state(isp, __func__);
1089#endif
1090
1091 dump_regs(isp, "isp1301->otg");
1092}
1093
1094/*-------------------------------------------------------------------------*/
1095
1096static u8 isp1301_clear_latch(struct isp1301 *isp)
1097{
1098 u8 latch = isp1301_get_u8(isp, ISP1301_INTERRUPT_LATCH);
1099 isp1301_clear_bits(isp, ISP1301_INTERRUPT_LATCH, latch);
1100 return latch;
1101}
1102
1103static void
1104isp1301_work(struct work_struct *work)
1105{
1106 struct isp1301 *isp = container_of(work, struct isp1301, work);
1107 int stop;
1108
1109 /* implicit lock: we're the only task using this device */
1110 isp->working = 1;
1111 do {
1112 stop = test_bit(WORK_STOP, &isp->todo);
1113
1114#ifdef CONFIG_USB_OTG
1115 /* transfer state from otg engine to isp1301 */
1116 if (test_and_clear_bit(WORK_UPDATE_ISP, &isp->todo)) {
1117 otg_update_isp(isp);
1118 put_device(&isp->client->dev);
1119 }
1120#endif
1121 /* transfer state from isp1301 to otg engine */
1122 if (test_and_clear_bit(WORK_UPDATE_OTG, &isp->todo)) {
1123 u8 stat = isp1301_clear_latch(isp);
1124
1125 isp_update_otg(isp, stat);
1126 put_device(&isp->client->dev);
1127 }
1128
1129 if (test_and_clear_bit(WORK_HOST_RESUME, &isp->todo)) {
1130 u32 otg_ctrl;
1131
1132 /*
1133 * skip A_WAIT_VRISE; hc transitions invisibly
1134 * skip A_WAIT_BCON; same.
1135 */
1136 switch (isp->phy.state) {
1137 case OTG_STATE_A_WAIT_BCON:
1138 case OTG_STATE_A_WAIT_VRISE:
1139 isp->phy.state = OTG_STATE_A_HOST;
1140 pr_debug(" --> a_host\n");
1141 otg_ctrl = omap_readl(OTG_CTRL);
1142 otg_ctrl |= OTG_A_BUSREQ;
1143 otg_ctrl &= ~(OTG_BUSDROP|OTG_B_BUSREQ)
1144 & OTG_CTRL_MASK;
1145 omap_writel(otg_ctrl, OTG_CTRL);
1146 break;
1147 case OTG_STATE_B_WAIT_ACON:
1148 isp->phy.state = OTG_STATE_B_HOST;
1149 pr_debug(" --> b_host (acon)\n");
1150 break;
1151 case OTG_STATE_B_HOST:
1152 case OTG_STATE_B_IDLE:
1153 case OTG_STATE_A_IDLE:
1154 break;
1155 default:
1156 pr_debug(" host resume in %s\n",
1157 state_name(isp));
1158 }
1159 host_resume(isp);
1160 // mdelay(10);
1161 put_device(&isp->client->dev);
1162 }
1163
1164 if (test_and_clear_bit(WORK_TIMER, &isp->todo)) {
1165#ifdef VERBOSE
1166 dump_regs(isp, "timer");
1167 if (!stop)
1168 mod_timer(&isp->timer, jiffies + TIMER_JIFFIES);
1169#endif
1170 put_device(&isp->client->dev);
1171 }
1172
1173 if (isp->todo)
1174 dev_vdbg(&isp->client->dev,
1175 "work done, todo = 0x%lx\n",
1176 isp->todo);
1177 if (stop) {
1178 dev_dbg(&isp->client->dev, "stop\n");
1179 break;
1180 }
1181 } while (isp->todo);
1182 isp->working = 0;
1183}
1184
1185static irqreturn_t isp1301_irq(int irq, void *isp)
1186{
1187 isp1301_defer_work(isp, WORK_UPDATE_OTG);
1188 return IRQ_HANDLED;
1189}
1190
1191static void isp1301_timer(unsigned long _isp)
1192{
1193 isp1301_defer_work((void *)_isp, WORK_TIMER);
1194}
1195
1196/*-------------------------------------------------------------------------*/
1197
1198static void isp1301_release(struct device *dev)
1199{
1200 struct isp1301 *isp;
1201
1202 isp = dev_get_drvdata(dev);
1203
1204 /* FIXME -- not with a "new style" driver, it doesn't!! */
1205
1206 /* ugly -- i2c hijacks our memory hook to wait_for_completion() */
1207 if (isp->i2c_release)
1208 isp->i2c_release(dev);
1209 kfree(isp->phy.otg);
1210 kfree (isp);
1211}
1212
1213static struct isp1301 *the_transceiver;
1214
1215static int isp1301_remove(struct i2c_client *i2c)
1216{
1217 struct isp1301 *isp;
1218
1219 isp = i2c_get_clientdata(i2c);
1220
1221 isp1301_clear_bits(isp, ISP1301_INTERRUPT_FALLING, ~0);
1222 isp1301_clear_bits(isp, ISP1301_INTERRUPT_RISING, ~0);
1223 free_irq(i2c->irq, isp);
1224#ifdef CONFIG_USB_OTG
1225 otg_unbind(isp);
1226#endif
1227 if (machine_is_omap_h2())
1228 gpio_free(2);
1229
1230 isp->timer.data = 0;
1231 set_bit(WORK_STOP, &isp->todo);
1232 del_timer_sync(&isp->timer);
1233 flush_work(&isp->work);
1234
1235 put_device(&i2c->dev);
1236 the_transceiver = NULL;
1237
1238 return 0;
1239}
1240
1241/*-------------------------------------------------------------------------*/
1242
1243/* NOTE: three modes are possible here, only one of which
1244 * will be standards-conformant on any given system:
1245 *
1246 * - OTG mode (dual-role), required if there's a Mini-AB connector
1247 * - HOST mode, for when there's one or more A (host) connectors
1248 * - DEVICE mode, for when there's a B/Mini-B (device) connector
1249 *
1250 * As a rule, you won't have an isp1301 chip unless it's there to
1251 * support the OTG mode. Other modes help testing USB controllers
1252 * in isolation from (full) OTG support, or maybe so later board
1253 * revisions can help to support those feature.
1254 */
1255
1256#ifdef CONFIG_USB_OTG
1257
1258static int isp1301_otg_enable(struct isp1301 *isp)
1259{
1260 power_up(isp);
1261 isp1301_otg_init(isp);
1262
1263 /* NOTE: since we don't change this, this provides
1264 * a few more interrupts than are strictly needed.
1265 */
1266 isp1301_set_bits(isp, ISP1301_INTERRUPT_RISING,
1267 INTR_VBUS_VLD | INTR_SESS_VLD | INTR_ID_GND);
1268 isp1301_set_bits(isp, ISP1301_INTERRUPT_FALLING,
1269 INTR_VBUS_VLD | INTR_SESS_VLD | INTR_ID_GND);
1270
1271 dev_info(&isp->client->dev, "ready for dual-role USB ...\n");
1272
1273 return 0;
1274}
1275
1276#endif
1277
1278/* add or disable the host device+driver */
1279static int
1280isp1301_set_host(struct usb_otg *otg, struct usb_bus *host)
1281{
1282 struct isp1301 *isp = container_of(otg->phy, struct isp1301, phy);
1283
1284 if (!otg || isp != the_transceiver)
1285 return -ENODEV;
1286
1287 if (!host) {
1288 omap_writew(0, OTG_IRQ_EN);
1289 power_down(isp);
1290 otg->host = NULL;
1291 return 0;
1292 }
1293
1294#ifdef CONFIG_USB_OTG
1295 otg->host = host;
1296 dev_dbg(&isp->client->dev, "registered host\n");
1297 host_suspend(isp);
1298 if (otg->gadget)
1299 return isp1301_otg_enable(isp);
1300 return 0;
1301
1302#elif !defined(CONFIG_USB_GADGET_OMAP)
1303 // FIXME update its refcount
1304 otg->host = host;
1305
1306 power_up(isp);
1307
1308 if (machine_is_omap_h2())
1309 isp1301_set_bits(isp, ISP1301_MODE_CONTROL_1, MC1_DAT_SE0);
1310
1311 dev_info(&isp->client->dev, "A-Host sessions ok\n");
1312 isp1301_set_bits(isp, ISP1301_INTERRUPT_RISING,
1313 INTR_ID_GND);
1314 isp1301_set_bits(isp, ISP1301_INTERRUPT_FALLING,
1315 INTR_ID_GND);
1316
1317 /* If this has a Mini-AB connector, this mode is highly
1318 * nonstandard ... but can be handy for testing, especially with
1319 * the Mini-A end of an OTG cable. (Or something nonstandard
1320 * like MiniB-to-StandardB, maybe built with a gender mender.)
1321 */
1322 isp1301_set_bits(isp, ISP1301_OTG_CONTROL_1, OTG1_VBUS_DRV);
1323
1324 dump_regs(isp, __func__);
1325
1326 return 0;
1327
1328#else
1329 dev_dbg(&isp->client->dev, "host sessions not allowed\n");
1330 return -EINVAL;
1331#endif
1332
1333}
1334
1335static int
1336isp1301_set_peripheral(struct usb_otg *otg, struct usb_gadget *gadget)
1337{
1338 struct isp1301 *isp = container_of(otg->phy, struct isp1301, phy);
1339
1340 if (!otg || isp != the_transceiver)
1341 return -ENODEV;
1342
1343 if (!gadget) {
1344 omap_writew(0, OTG_IRQ_EN);
1345 if (!otg->default_a)
1346 enable_vbus_draw(isp, 0);
1347 usb_gadget_vbus_disconnect(otg->gadget);
1348 otg->gadget = NULL;
1349 power_down(isp);
1350 return 0;
1351 }
1352
1353#ifdef CONFIG_USB_OTG
1354 otg->gadget = gadget;
1355 dev_dbg(&isp->client->dev, "registered gadget\n");
1356 /* gadget driver may be suspended until vbus_connect () */
1357 if (otg->host)
1358 return isp1301_otg_enable(isp);
1359 return 0;
1360
1361#elif !defined(CONFIG_USB_OHCI_HCD) && !defined(CONFIG_USB_OHCI_HCD_MODULE)
1362 otg->gadget = gadget;
1363 // FIXME update its refcount
1364
1365 {
1366 u32 l;
1367
1368 l = omap_readl(OTG_CTRL) & OTG_CTRL_MASK;
1369 l &= ~(OTG_XCEIV_OUTPUTS|OTG_CTRL_BITS);
1370 l |= OTG_ID;
1371 omap_writel(l, OTG_CTRL);
1372 }
1373
1374 power_up(isp);
1375 isp->phy.state = OTG_STATE_B_IDLE;
1376
1377 if (machine_is_omap_h2() || machine_is_omap_h3())
1378 isp1301_set_bits(isp, ISP1301_MODE_CONTROL_1, MC1_DAT_SE0);
1379
1380 isp1301_set_bits(isp, ISP1301_INTERRUPT_RISING,
1381 INTR_SESS_VLD);
1382 isp1301_set_bits(isp, ISP1301_INTERRUPT_FALLING,
1383 INTR_VBUS_VLD);
1384 dev_info(&isp->client->dev, "B-Peripheral sessions ok\n");
1385 dump_regs(isp, __func__);
1386
1387 /* If this has a Mini-AB connector, this mode is highly
1388 * nonstandard ... but can be handy for testing, so long
1389 * as you don't plug a Mini-A cable into the jack.
1390 */
1391 if (isp1301_get_u8(isp, ISP1301_INTERRUPT_SOURCE) & INTR_VBUS_VLD)
1392 b_peripheral(isp);
1393
1394 return 0;
1395
1396#else
1397 dev_dbg(&isp->client->dev, "peripheral sessions not allowed\n");
1398 return -EINVAL;
1399#endif
1400}
1401
1402
1403/*-------------------------------------------------------------------------*/
1404
1405static int
1406isp1301_set_power(struct usb_phy *dev, unsigned mA)
1407{
1408 if (!the_transceiver)
1409 return -ENODEV;
1410 if (dev->state == OTG_STATE_B_PERIPHERAL)
1411 enable_vbus_draw(the_transceiver, mA);
1412 return 0;
1413}
1414
1415static int
1416isp1301_start_srp(struct usb_otg *otg)
1417{
1418 struct isp1301 *isp = container_of(otg->phy, struct isp1301, phy);
1419 u32 otg_ctrl;
1420
1421 if (!otg || isp != the_transceiver
1422 || isp->phy.state != OTG_STATE_B_IDLE)
1423 return -ENODEV;
1424
1425 otg_ctrl = omap_readl(OTG_CTRL);
1426 if (!(otg_ctrl & OTG_BSESSEND))
1427 return -EINVAL;
1428
1429 otg_ctrl |= OTG_B_BUSREQ;
1430 otg_ctrl &= ~OTG_A_BUSREQ & OTG_CTRL_MASK;
1431 omap_writel(otg_ctrl, OTG_CTRL);
1432 isp->phy.state = OTG_STATE_B_SRP_INIT;
1433
1434 pr_debug("otg: SRP, %s ... %06x\n", state_name(isp),
1435 omap_readl(OTG_CTRL));
1436#ifdef CONFIG_USB_OTG
1437 check_state(isp, __func__);
1438#endif
1439 return 0;
1440}
1441
1442static int
1443isp1301_start_hnp(struct usb_otg *otg)
1444{
1445#ifdef CONFIG_USB_OTG
1446 struct isp1301 *isp = container_of(otg->phy, struct isp1301, phy);
1447 u32 l;
1448
1449 if (!otg || isp != the_transceiver)
1450 return -ENODEV;
1451 if (otg->default_a && (otg->host == NULL || !otg->host->b_hnp_enable))
1452 return -ENOTCONN;
1453 if (!otg->default_a && (otg->gadget == NULL
1454 || !otg->gadget->b_hnp_enable))
1455 return -ENOTCONN;
1456
1457 /* We want hardware to manage most HNP protocol timings.
1458 * So do this part as early as possible...
1459 */
1460 switch (isp->phy.state) {
1461 case OTG_STATE_B_HOST:
1462 isp->phy.state = OTG_STATE_B_PERIPHERAL;
1463 /* caller will suspend next */
1464 break;
1465 case OTG_STATE_A_HOST:
1466#if 0
1467 /* autoconnect mode avoids irq latency bugs */
1468 isp1301_set_bits(isp, ISP1301_MODE_CONTROL_1,
1469 MC1_BDIS_ACON_EN);
1470#endif
1471 /* caller must suspend then clear A_BUSREQ */
1472 usb_gadget_vbus_connect(otg->gadget);
1473 l = omap_readl(OTG_CTRL);
1474 l |= OTG_A_SETB_HNPEN;
1475 omap_writel(l, OTG_CTRL);
1476
1477 break;
1478 case OTG_STATE_A_PERIPHERAL:
1479 /* initiated by B-Host suspend */
1480 break;
1481 default:
1482 return -EILSEQ;
1483 }
1484 pr_debug("otg: HNP %s, %06x ...\n",
1485 state_name(isp), omap_readl(OTG_CTRL));
1486 check_state(isp, __func__);
1487 return 0;
1488#else
1489 /* srp-only */
1490 return -EINVAL;
1491#endif
1492}
1493
1494/*-------------------------------------------------------------------------*/
1495
1496static int
1497isp1301_probe(struct i2c_client *i2c, const struct i2c_device_id *id)
1498{
1499 int status;
1500 struct isp1301 *isp;
1501
1502 if (the_transceiver)
1503 return 0;
1504
1505 isp = kzalloc(sizeof *isp, GFP_KERNEL);
1506 if (!isp)
1507 return 0;
1508
1509 isp->phy.otg = kzalloc(sizeof *isp->phy.otg, GFP_KERNEL);
1510 if (!isp->phy.otg) {
1511 kfree(isp);
1512 return 0;
1513 }
1514
1515 INIT_WORK(&isp->work, isp1301_work);
1516 init_timer(&isp->timer);
1517 isp->timer.function = isp1301_timer;
1518 isp->timer.data = (unsigned long) isp;
1519
1520 i2c_set_clientdata(i2c, isp);
1521 isp->client = i2c;
1522
1523 /* verify the chip (shouldn't be necessary) */
1524 status = isp1301_get_u16(isp, ISP1301_VENDOR_ID);
1525 if (status != I2C_VENDOR_ID_PHILIPS) {
1526 dev_dbg(&i2c->dev, "not philips id: %d\n", status);
1527 goto fail;
1528 }
1529 status = isp1301_get_u16(isp, ISP1301_PRODUCT_ID);
1530 if (status != I2C_PRODUCT_ID_PHILIPS_1301) {
1531 dev_dbg(&i2c->dev, "not isp1301, %d\n", status);
1532 goto fail;
1533 }
1534 isp->i2c_release = i2c->dev.release;
1535 i2c->dev.release = isp1301_release;
1536
1537 /* initial development used chiprev 2.00 */
1538 status = i2c_smbus_read_word_data(i2c, ISP1301_BCD_DEVICE);
1539 dev_info(&i2c->dev, "chiprev %x.%02x, driver " DRIVER_VERSION "\n",
1540 status >> 8, status & 0xff);
1541
1542 /* make like power-on reset */
1543 isp1301_clear_bits(isp, ISP1301_MODE_CONTROL_1, MC1_MASK);
1544
1545 isp1301_set_bits(isp, ISP1301_MODE_CONTROL_2, MC2_BI_DI);
1546 isp1301_clear_bits(isp, ISP1301_MODE_CONTROL_2, ~MC2_BI_DI);
1547
1548 isp1301_set_bits(isp, ISP1301_OTG_CONTROL_1,
1549 OTG1_DM_PULLDOWN | OTG1_DP_PULLDOWN);
1550 isp1301_clear_bits(isp, ISP1301_OTG_CONTROL_1,
1551 ~(OTG1_DM_PULLDOWN | OTG1_DP_PULLDOWN));
1552
1553 isp1301_clear_bits(isp, ISP1301_INTERRUPT_LATCH, ~0);
1554 isp1301_clear_bits(isp, ISP1301_INTERRUPT_FALLING, ~0);
1555 isp1301_clear_bits(isp, ISP1301_INTERRUPT_RISING, ~0);
1556
1557#ifdef CONFIG_USB_OTG
1558 status = otg_bind(isp);
1559 if (status < 0) {
1560 dev_dbg(&i2c->dev, "can't bind OTG\n");
1561 goto fail;
1562 }
1563#endif
1564
1565 if (machine_is_omap_h2()) {
1566 /* full speed signaling by default */
1567 isp1301_set_bits(isp, ISP1301_MODE_CONTROL_1,
1568 MC1_SPEED);
1569 isp1301_set_bits(isp, ISP1301_MODE_CONTROL_2,
1570 MC2_SPD_SUSP_CTRL);
1571
1572 /* IRQ wired at M14 */
1573 omap_cfg_reg(M14_1510_GPIO2);
1574 if (gpio_request(2, "isp1301") == 0)
1575 gpio_direction_input(2);
1576 isp->irq_type = IRQF_TRIGGER_FALLING;
1577 }
1578
1579 status = request_irq(i2c->irq, isp1301_irq,
1580 isp->irq_type, DRIVER_NAME, isp);
1581 if (status < 0) {
1582 dev_dbg(&i2c->dev, "can't get IRQ %d, err %d\n",
1583 i2c->irq, status);
1584 goto fail;
1585 }
1586
1587 isp->phy.dev = &i2c->dev;
1588 isp->phy.label = DRIVER_NAME;
1589 isp->phy.set_power = isp1301_set_power,
1590
1591 isp->phy.otg->phy = &isp->phy;
1592 isp->phy.otg->set_host = isp1301_set_host,
1593 isp->phy.otg->set_peripheral = isp1301_set_peripheral,
1594 isp->phy.otg->start_srp = isp1301_start_srp,
1595 isp->phy.otg->start_hnp = isp1301_start_hnp,
1596
1597 enable_vbus_draw(isp, 0);
1598 power_down(isp);
1599 the_transceiver = isp;
1600
1601#ifdef CONFIG_USB_OTG
1602 update_otg1(isp, isp1301_get_u8(isp, ISP1301_INTERRUPT_SOURCE));
1603 update_otg2(isp, isp1301_get_u8(isp, ISP1301_OTG_STATUS));
1604#endif
1605
1606 dump_regs(isp, __func__);
1607
1608#ifdef VERBOSE
1609 mod_timer(&isp->timer, jiffies + TIMER_JIFFIES);
1610 dev_dbg(&i2c->dev, "scheduled timer, %d min\n", TIMER_MINUTES);
1611#endif
1612
1613 status = usb_add_phy(&isp->phy, USB_PHY_TYPE_USB2);
1614 if (status < 0)
1615 dev_err(&i2c->dev, "can't register transceiver, %d\n",
1616 status);
1617
1618 return 0;
1619
1620fail:
1621 kfree(isp->phy.otg);
1622 kfree(isp);
1623 return -ENODEV;
1624}
1625
1626static const struct i2c_device_id isp1301_id[] = {
1627 { "isp1301_omap", 0 },
1628 { }
1629};
1630MODULE_DEVICE_TABLE(i2c, isp1301_id);
1631
1632static struct i2c_driver isp1301_driver = {
1633 .driver = {
1634 .name = "isp1301_omap",
1635 },
1636 .probe = isp1301_probe,
1637 .remove = isp1301_remove,
1638 .id_table = isp1301_id,
1639};
1640
1641/*-------------------------------------------------------------------------*/
1642
1643static int __init isp_init(void)
1644{
1645 return i2c_add_driver(&isp1301_driver);
1646}
1647subsys_initcall(isp_init);
1648
1649static void __exit isp_exit(void)
1650{
1651 if (the_transceiver)
1652 usb_remove_phy(&the_transceiver->phy);
1653 i2c_del_driver(&isp1301_driver);
1654}
1655module_exit(isp_exit);
1656
diff --git a/drivers/usb/phy/phy-isp1301.c b/drivers/usb/phy/phy-isp1301.c
new file mode 100644
index 000000000000..225ae6c97eeb
--- /dev/null
+++ b/drivers/usb/phy/phy-isp1301.c
@@ -0,0 +1,162 @@
1/*
2 * NXP ISP1301 USB transceiver driver
3 *
4 * Copyright (C) 2012 Roland Stigge
5 *
6 * Author: Roland Stigge <stigge@antcom.de>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/module.h>
14#include <linux/mutex.h>
15#include <linux/i2c.h>
16#include <linux/usb/phy.h>
17#include <linux/usb/isp1301.h>
18
19#define DRV_NAME "isp1301"
20
21struct isp1301 {
22 struct usb_phy phy;
23 struct mutex mutex;
24
25 struct i2c_client *client;
26};
27
28#define phy_to_isp(p) (container_of((p), struct isp1301, phy))
29
30static const struct i2c_device_id isp1301_id[] = {
31 { "isp1301", 0 },
32 { }
33};
34
35static struct i2c_client *isp1301_i2c_client;
36
37static int __isp1301_write(struct isp1301 *isp, u8 reg, u8 value, u8 clear)
38{
39 return i2c_smbus_write_byte_data(isp->client, reg | clear, value);
40}
41
42static int isp1301_write(struct isp1301 *isp, u8 reg, u8 value)
43{
44 return __isp1301_write(isp, reg, value, 0);
45}
46
47static int isp1301_clear(struct isp1301 *isp, u8 reg, u8 value)
48{
49 return __isp1301_write(isp, reg, value, ISP1301_I2C_REG_CLEAR_ADDR);
50}
51
52static int isp1301_phy_init(struct usb_phy *phy)
53{
54 struct isp1301 *isp = phy_to_isp(phy);
55
56 /* Disable transparent UART mode first */
57 isp1301_clear(isp, ISP1301_I2C_MODE_CONTROL_1, MC1_UART_EN);
58 isp1301_clear(isp, ISP1301_I2C_MODE_CONTROL_1, ~MC1_SPEED_REG);
59 isp1301_write(isp, ISP1301_I2C_MODE_CONTROL_1, MC1_SPEED_REG);
60 isp1301_clear(isp, ISP1301_I2C_MODE_CONTROL_2, ~0);
61 isp1301_write(isp, ISP1301_I2C_MODE_CONTROL_2, (MC2_BI_DI | MC2_PSW_EN
62 | MC2_SPD_SUSP_CTRL));
63
64 isp1301_clear(isp, ISP1301_I2C_OTG_CONTROL_1, ~0);
65 isp1301_write(isp, ISP1301_I2C_MODE_CONTROL_1, MC1_DAT_SE0);
66 isp1301_write(isp, ISP1301_I2C_OTG_CONTROL_1, (OTG1_DM_PULLDOWN
67 | OTG1_DP_PULLDOWN));
68 isp1301_clear(isp, ISP1301_I2C_OTG_CONTROL_1, (OTG1_DM_PULLUP
69 | OTG1_DP_PULLUP));
70
71 /* mask all interrupts */
72 isp1301_clear(isp, ISP1301_I2C_INTERRUPT_LATCH, ~0);
73 isp1301_clear(isp, ISP1301_I2C_INTERRUPT_FALLING, ~0);
74 isp1301_clear(isp, ISP1301_I2C_INTERRUPT_RISING, ~0);
75
76 return 0;
77}
78
79static int isp1301_phy_set_vbus(struct usb_phy *phy, int on)
80{
81 struct isp1301 *isp = phy_to_isp(phy);
82
83 if (on)
84 isp1301_write(isp, ISP1301_I2C_OTG_CONTROL_1, OTG1_VBUS_DRV);
85 else
86 isp1301_clear(isp, ISP1301_I2C_OTG_CONTROL_1, OTG1_VBUS_DRV);
87
88 return 0;
89}
90
91static int isp1301_probe(struct i2c_client *client,
92 const struct i2c_device_id *i2c_id)
93{
94 struct isp1301 *isp;
95 struct usb_phy *phy;
96
97 isp = devm_kzalloc(&client->dev, sizeof(*isp), GFP_KERNEL);
98 if (!isp)
99 return -ENOMEM;
100
101 isp->client = client;
102 mutex_init(&isp->mutex);
103
104 phy = &isp->phy;
105 phy->label = DRV_NAME;
106 phy->init = isp1301_phy_init;
107 phy->set_vbus = isp1301_phy_set_vbus;
108 phy->type = USB_PHY_TYPE_USB2;
109
110 i2c_set_clientdata(client, isp);
111 usb_add_phy_dev(phy);
112
113 isp1301_i2c_client = client;
114
115 return 0;
116}
117
118static int isp1301_remove(struct i2c_client *client)
119{
120 struct isp1301 *isp = i2c_get_clientdata(client);
121
122 usb_remove_phy(&isp->phy);
123 isp1301_i2c_client = NULL;
124
125 return 0;
126}
127
128static struct i2c_driver isp1301_driver = {
129 .driver = {
130 .name = DRV_NAME,
131 },
132 .probe = isp1301_probe,
133 .remove = isp1301_remove,
134 .id_table = isp1301_id,
135};
136
137module_i2c_driver(isp1301_driver);
138
139static int match(struct device *dev, void *data)
140{
141 struct device_node *node = (struct device_node *)data;
142 return (dev->of_node == node) &&
143 (dev->driver == &isp1301_driver.driver);
144}
145
146struct i2c_client *isp1301_get_client(struct device_node *node)
147{
148 if (node) { /* reference of ISP1301 I2C node via DT */
149 struct device *dev = bus_find_device(&i2c_bus_type, NULL,
150 node, match);
151 if (!dev)
152 return NULL;
153 return to_i2c_client(dev);
154 } else { /* non-DT: only one ISP1301 chip supported */
155 return isp1301_i2c_client;
156 }
157}
158EXPORT_SYMBOL_GPL(isp1301_get_client);
159
160MODULE_AUTHOR("Roland Stigge <stigge@antcom.de>");
161MODULE_DESCRIPTION("NXP ISP1301 USB transceiver driver");
162MODULE_LICENSE("GPL");
diff --git a/drivers/usb/phy/phy-msm-usb.c b/drivers/usb/phy/phy-msm-usb.c
new file mode 100644
index 000000000000..749fbf41fb6f
--- /dev/null
+++ b/drivers/usb/phy/phy-msm-usb.c
@@ -0,0 +1,1762 @@
1/* Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
15 * 02110-1301, USA.
16 *
17 */
18
19#include <linux/module.h>
20#include <linux/device.h>
21#include <linux/platform_device.h>
22#include <linux/clk.h>
23#include <linux/slab.h>
24#include <linux/interrupt.h>
25#include <linux/err.h>
26#include <linux/delay.h>
27#include <linux/io.h>
28#include <linux/ioport.h>
29#include <linux/uaccess.h>
30#include <linux/debugfs.h>
31#include <linux/seq_file.h>
32#include <linux/pm_runtime.h>
33
34#include <linux/usb.h>
35#include <linux/usb/otg.h>
36#include <linux/usb/ulpi.h>
37#include <linux/usb/gadget.h>
38#include <linux/usb/hcd.h>
39#include <linux/usb/msm_hsusb.h>
40#include <linux/usb/msm_hsusb_hw.h>
41#include <linux/regulator/consumer.h>
42
43#include <mach/clk.h>
44
45#define MSM_USB_BASE (motg->regs)
46#define DRIVER_NAME "msm_otg"
47
48#define ULPI_IO_TIMEOUT_USEC (10 * 1000)
49
50#define USB_PHY_3P3_VOL_MIN 3050000 /* uV */
51#define USB_PHY_3P3_VOL_MAX 3300000 /* uV */
52#define USB_PHY_3P3_HPM_LOAD 50000 /* uA */
53#define USB_PHY_3P3_LPM_LOAD 4000 /* uA */
54
55#define USB_PHY_1P8_VOL_MIN 1800000 /* uV */
56#define USB_PHY_1P8_VOL_MAX 1800000 /* uV */
57#define USB_PHY_1P8_HPM_LOAD 50000 /* uA */
58#define USB_PHY_1P8_LPM_LOAD 4000 /* uA */
59
60#define USB_PHY_VDD_DIG_VOL_MIN 1000000 /* uV */
61#define USB_PHY_VDD_DIG_VOL_MAX 1320000 /* uV */
62
63static struct regulator *hsusb_3p3;
64static struct regulator *hsusb_1p8;
65static struct regulator *hsusb_vddcx;
66
67static int msm_hsusb_init_vddcx(struct msm_otg *motg, int init)
68{
69 int ret = 0;
70
71 if (init) {
72 hsusb_vddcx = regulator_get(motg->phy.dev, "HSUSB_VDDCX");
73 if (IS_ERR(hsusb_vddcx)) {
74 dev_err(motg->phy.dev, "unable to get hsusb vddcx\n");
75 return PTR_ERR(hsusb_vddcx);
76 }
77
78 ret = regulator_set_voltage(hsusb_vddcx,
79 USB_PHY_VDD_DIG_VOL_MIN,
80 USB_PHY_VDD_DIG_VOL_MAX);
81 if (ret) {
82 dev_err(motg->phy.dev, "unable to set the voltage "
83 "for hsusb vddcx\n");
84 regulator_put(hsusb_vddcx);
85 return ret;
86 }
87
88 ret = regulator_enable(hsusb_vddcx);
89 if (ret) {
90 dev_err(motg->phy.dev, "unable to enable hsusb vddcx\n");
91 regulator_put(hsusb_vddcx);
92 }
93 } else {
94 ret = regulator_set_voltage(hsusb_vddcx, 0,
95 USB_PHY_VDD_DIG_VOL_MAX);
96 if (ret)
97 dev_err(motg->phy.dev, "unable to set the voltage "
98 "for hsusb vddcx\n");
99 ret = regulator_disable(hsusb_vddcx);
100 if (ret)
101 dev_err(motg->phy.dev, "unable to disable hsusb vddcx\n");
102
103 regulator_put(hsusb_vddcx);
104 }
105
106 return ret;
107}
108
109static int msm_hsusb_ldo_init(struct msm_otg *motg, int init)
110{
111 int rc = 0;
112
113 if (init) {
114 hsusb_3p3 = regulator_get(motg->phy.dev, "HSUSB_3p3");
115 if (IS_ERR(hsusb_3p3)) {
116 dev_err(motg->phy.dev, "unable to get hsusb 3p3\n");
117 return PTR_ERR(hsusb_3p3);
118 }
119
120 rc = regulator_set_voltage(hsusb_3p3, USB_PHY_3P3_VOL_MIN,
121 USB_PHY_3P3_VOL_MAX);
122 if (rc) {
123 dev_err(motg->phy.dev, "unable to set voltage level "
124 "for hsusb 3p3\n");
125 goto put_3p3;
126 }
127 rc = regulator_enable(hsusb_3p3);
128 if (rc) {
129 dev_err(motg->phy.dev, "unable to enable the hsusb 3p3\n");
130 goto put_3p3;
131 }
132 hsusb_1p8 = regulator_get(motg->phy.dev, "HSUSB_1p8");
133 if (IS_ERR(hsusb_1p8)) {
134 dev_err(motg->phy.dev, "unable to get hsusb 1p8\n");
135 rc = PTR_ERR(hsusb_1p8);
136 goto disable_3p3;
137 }
138 rc = regulator_set_voltage(hsusb_1p8, USB_PHY_1P8_VOL_MIN,
139 USB_PHY_1P8_VOL_MAX);
140 if (rc) {
141 dev_err(motg->phy.dev, "unable to set voltage level "
142 "for hsusb 1p8\n");
143 goto put_1p8;
144 }
145 rc = regulator_enable(hsusb_1p8);
146 if (rc) {
147 dev_err(motg->phy.dev, "unable to enable the hsusb 1p8\n");
148 goto put_1p8;
149 }
150
151 return 0;
152 }
153
154 regulator_disable(hsusb_1p8);
155put_1p8:
156 regulator_put(hsusb_1p8);
157disable_3p3:
158 regulator_disable(hsusb_3p3);
159put_3p3:
160 regulator_put(hsusb_3p3);
161 return rc;
162}
163
164#ifdef CONFIG_PM_SLEEP
165#define USB_PHY_SUSP_DIG_VOL 500000
166static int msm_hsusb_config_vddcx(int high)
167{
168 int max_vol = USB_PHY_VDD_DIG_VOL_MAX;
169 int min_vol;
170 int ret;
171
172 if (high)
173 min_vol = USB_PHY_VDD_DIG_VOL_MIN;
174 else
175 min_vol = USB_PHY_SUSP_DIG_VOL;
176
177 ret = regulator_set_voltage(hsusb_vddcx, min_vol, max_vol);
178 if (ret) {
179 pr_err("%s: unable to set the voltage for regulator "
180 "HSUSB_VDDCX\n", __func__);
181 return ret;
182 }
183
184 pr_debug("%s: min_vol:%d max_vol:%d\n", __func__, min_vol, max_vol);
185
186 return ret;
187}
188#endif
189
190static int msm_hsusb_ldo_set_mode(int on)
191{
192 int ret = 0;
193
194 if (!hsusb_1p8 || IS_ERR(hsusb_1p8)) {
195 pr_err("%s: HSUSB_1p8 is not initialized\n", __func__);
196 return -ENODEV;
197 }
198
199 if (!hsusb_3p3 || IS_ERR(hsusb_3p3)) {
200 pr_err("%s: HSUSB_3p3 is not initialized\n", __func__);
201 return -ENODEV;
202 }
203
204 if (on) {
205 ret = regulator_set_optimum_mode(hsusb_1p8,
206 USB_PHY_1P8_HPM_LOAD);
207 if (ret < 0) {
208 pr_err("%s: Unable to set HPM of the regulator "
209 "HSUSB_1p8\n", __func__);
210 return ret;
211 }
212 ret = regulator_set_optimum_mode(hsusb_3p3,
213 USB_PHY_3P3_HPM_LOAD);
214 if (ret < 0) {
215 pr_err("%s: Unable to set HPM of the regulator "
216 "HSUSB_3p3\n", __func__);
217 regulator_set_optimum_mode(hsusb_1p8,
218 USB_PHY_1P8_LPM_LOAD);
219 return ret;
220 }
221 } else {
222 ret = regulator_set_optimum_mode(hsusb_1p8,
223 USB_PHY_1P8_LPM_LOAD);
224 if (ret < 0)
225 pr_err("%s: Unable to set LPM of the regulator "
226 "HSUSB_1p8\n", __func__);
227 ret = regulator_set_optimum_mode(hsusb_3p3,
228 USB_PHY_3P3_LPM_LOAD);
229 if (ret < 0)
230 pr_err("%s: Unable to set LPM of the regulator "
231 "HSUSB_3p3\n", __func__);
232 }
233
234 pr_debug("reg (%s)\n", on ? "HPM" : "LPM");
235 return ret < 0 ? ret : 0;
236}
237
238static int ulpi_read(struct usb_phy *phy, u32 reg)
239{
240 struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
241 int cnt = 0;
242
243 /* initiate read operation */
244 writel(ULPI_RUN | ULPI_READ | ULPI_ADDR(reg),
245 USB_ULPI_VIEWPORT);
246
247 /* wait for completion */
248 while (cnt < ULPI_IO_TIMEOUT_USEC) {
249 if (!(readl(USB_ULPI_VIEWPORT) & ULPI_RUN))
250 break;
251 udelay(1);
252 cnt++;
253 }
254
255 if (cnt >= ULPI_IO_TIMEOUT_USEC) {
256 dev_err(phy->dev, "ulpi_read: timeout %08x\n",
257 readl(USB_ULPI_VIEWPORT));
258 return -ETIMEDOUT;
259 }
260 return ULPI_DATA_READ(readl(USB_ULPI_VIEWPORT));
261}
262
263static int ulpi_write(struct usb_phy *phy, u32 val, u32 reg)
264{
265 struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
266 int cnt = 0;
267
268 /* initiate write operation */
269 writel(ULPI_RUN | ULPI_WRITE |
270 ULPI_ADDR(reg) | ULPI_DATA(val),
271 USB_ULPI_VIEWPORT);
272
273 /* wait for completion */
274 while (cnt < ULPI_IO_TIMEOUT_USEC) {
275 if (!(readl(USB_ULPI_VIEWPORT) & ULPI_RUN))
276 break;
277 udelay(1);
278 cnt++;
279 }
280
281 if (cnt >= ULPI_IO_TIMEOUT_USEC) {
282 dev_err(phy->dev, "ulpi_write: timeout\n");
283 return -ETIMEDOUT;
284 }
285 return 0;
286}
287
288static struct usb_phy_io_ops msm_otg_io_ops = {
289 .read = ulpi_read,
290 .write = ulpi_write,
291};
292
293static void ulpi_init(struct msm_otg *motg)
294{
295 struct msm_otg_platform_data *pdata = motg->pdata;
296 int *seq = pdata->phy_init_seq;
297
298 if (!seq)
299 return;
300
301 while (seq[0] >= 0) {
302 dev_vdbg(motg->phy.dev, "ulpi: write 0x%02x to 0x%02x\n",
303 seq[0], seq[1]);
304 ulpi_write(&motg->phy, seq[0], seq[1]);
305 seq += 2;
306 }
307}
308
309static int msm_otg_link_clk_reset(struct msm_otg *motg, bool assert)
310{
311 int ret;
312
313 if (assert) {
314 ret = clk_reset(motg->clk, CLK_RESET_ASSERT);
315 if (ret)
316 dev_err(motg->phy.dev, "usb hs_clk assert failed\n");
317 } else {
318 ret = clk_reset(motg->clk, CLK_RESET_DEASSERT);
319 if (ret)
320 dev_err(motg->phy.dev, "usb hs_clk deassert failed\n");
321 }
322 return ret;
323}
324
325static int msm_otg_phy_clk_reset(struct msm_otg *motg)
326{
327 int ret;
328
329 ret = clk_reset(motg->phy_reset_clk, CLK_RESET_ASSERT);
330 if (ret) {
331 dev_err(motg->phy.dev, "usb phy clk assert failed\n");
332 return ret;
333 }
334 usleep_range(10000, 12000);
335 ret = clk_reset(motg->phy_reset_clk, CLK_RESET_DEASSERT);
336 if (ret)
337 dev_err(motg->phy.dev, "usb phy clk deassert failed\n");
338 return ret;
339}
340
341static int msm_otg_phy_reset(struct msm_otg *motg)
342{
343 u32 val;
344 int ret;
345 int retries;
346
347 ret = msm_otg_link_clk_reset(motg, 1);
348 if (ret)
349 return ret;
350 ret = msm_otg_phy_clk_reset(motg);
351 if (ret)
352 return ret;
353 ret = msm_otg_link_clk_reset(motg, 0);
354 if (ret)
355 return ret;
356
357 val = readl(USB_PORTSC) & ~PORTSC_PTS_MASK;
358 writel(val | PORTSC_PTS_ULPI, USB_PORTSC);
359
360 for (retries = 3; retries > 0; retries--) {
361 ret = ulpi_write(&motg->phy, ULPI_FUNC_CTRL_SUSPENDM,
362 ULPI_CLR(ULPI_FUNC_CTRL));
363 if (!ret)
364 break;
365 ret = msm_otg_phy_clk_reset(motg);
366 if (ret)
367 return ret;
368 }
369 if (!retries)
370 return -ETIMEDOUT;
371
372 /* This reset calibrates the phy, if the above write succeeded */
373 ret = msm_otg_phy_clk_reset(motg);
374 if (ret)
375 return ret;
376
377 for (retries = 3; retries > 0; retries--) {
378 ret = ulpi_read(&motg->phy, ULPI_DEBUG);
379 if (ret != -ETIMEDOUT)
380 break;
381 ret = msm_otg_phy_clk_reset(motg);
382 if (ret)
383 return ret;
384 }
385 if (!retries)
386 return -ETIMEDOUT;
387
388 dev_info(motg->phy.dev, "phy_reset: success\n");
389 return 0;
390}
391
392#define LINK_RESET_TIMEOUT_USEC (250 * 1000)
393static int msm_otg_reset(struct usb_phy *phy)
394{
395 struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
396 struct msm_otg_platform_data *pdata = motg->pdata;
397 int cnt = 0;
398 int ret;
399 u32 val = 0;
400 u32 ulpi_val = 0;
401
402 ret = msm_otg_phy_reset(motg);
403 if (ret) {
404 dev_err(phy->dev, "phy_reset failed\n");
405 return ret;
406 }
407
408 ulpi_init(motg);
409
410 writel(USBCMD_RESET, USB_USBCMD);
411 while (cnt < LINK_RESET_TIMEOUT_USEC) {
412 if (!(readl(USB_USBCMD) & USBCMD_RESET))
413 break;
414 udelay(1);
415 cnt++;
416 }
417 if (cnt >= LINK_RESET_TIMEOUT_USEC)
418 return -ETIMEDOUT;
419
420 /* select ULPI phy */
421 writel(0x80000000, USB_PORTSC);
422
423 msleep(100);
424
425 writel(0x0, USB_AHBBURST);
426 writel(0x00, USB_AHBMODE);
427
428 if (pdata->otg_control == OTG_PHY_CONTROL) {
429 val = readl(USB_OTGSC);
430 if (pdata->mode == USB_OTG) {
431 ulpi_val = ULPI_INT_IDGRD | ULPI_INT_SESS_VALID;
432 val |= OTGSC_IDIE | OTGSC_BSVIE;
433 } else if (pdata->mode == USB_PERIPHERAL) {
434 ulpi_val = ULPI_INT_SESS_VALID;
435 val |= OTGSC_BSVIE;
436 }
437 writel(val, USB_OTGSC);
438 ulpi_write(phy, ulpi_val, ULPI_USB_INT_EN_RISE);
439 ulpi_write(phy, ulpi_val, ULPI_USB_INT_EN_FALL);
440 }
441
442 return 0;
443}
444
445#define PHY_SUSPEND_TIMEOUT_USEC (500 * 1000)
446#define PHY_RESUME_TIMEOUT_USEC (100 * 1000)
447
448#ifdef CONFIG_PM_SLEEP
449static int msm_otg_suspend(struct msm_otg *motg)
450{
451 struct usb_phy *phy = &motg->phy;
452 struct usb_bus *bus = phy->otg->host;
453 struct msm_otg_platform_data *pdata = motg->pdata;
454 int cnt = 0;
455
456 if (atomic_read(&motg->in_lpm))
457 return 0;
458
459 disable_irq(motg->irq);
460 /*
461 * Chipidea 45-nm PHY suspend sequence:
462 *
463 * Interrupt Latch Register auto-clear feature is not present
464 * in all PHY versions. Latch register is clear on read type.
465 * Clear latch register to avoid spurious wakeup from
466 * low power mode (LPM).
467 *
468 * PHY comparators are disabled when PHY enters into low power
469 * mode (LPM). Keep PHY comparators ON in LPM only when we expect
470 * VBUS/Id notifications from USB PHY. Otherwise turn off USB
471 * PHY comparators. This save significant amount of power.
472 *
473 * PLL is not turned off when PHY enters into low power mode (LPM).
474 * Disable PLL for maximum power savings.
475 */
476
477 if (motg->pdata->phy_type == CI_45NM_INTEGRATED_PHY) {
478 ulpi_read(phy, 0x14);
479 if (pdata->otg_control == OTG_PHY_CONTROL)
480 ulpi_write(phy, 0x01, 0x30);
481 ulpi_write(phy, 0x08, 0x09);
482 }
483
484 /*
485 * PHY may take some time or even fail to enter into low power
486 * mode (LPM). Hence poll for 500 msec and reset the PHY and link
487 * in failure case.
488 */
489 writel(readl(USB_PORTSC) | PORTSC_PHCD, USB_PORTSC);
490 while (cnt < PHY_SUSPEND_TIMEOUT_USEC) {
491 if (readl(USB_PORTSC) & PORTSC_PHCD)
492 break;
493 udelay(1);
494 cnt++;
495 }
496
497 if (cnt >= PHY_SUSPEND_TIMEOUT_USEC) {
498 dev_err(phy->dev, "Unable to suspend PHY\n");
499 msm_otg_reset(phy);
500 enable_irq(motg->irq);
501 return -ETIMEDOUT;
502 }
503
504 /*
505 * PHY has capability to generate interrupt asynchronously in low
506 * power mode (LPM). This interrupt is level triggered. So USB IRQ
507 * line must be disabled till async interrupt enable bit is cleared
508 * in USBCMD register. Assert STP (ULPI interface STOP signal) to
509 * block data communication from PHY.
510 */
511 writel(readl(USB_USBCMD) | ASYNC_INTR_CTRL | ULPI_STP_CTRL, USB_USBCMD);
512
513 if (motg->pdata->phy_type == SNPS_28NM_INTEGRATED_PHY &&
514 motg->pdata->otg_control == OTG_PMIC_CONTROL)
515 writel(readl(USB_PHY_CTRL) | PHY_RETEN, USB_PHY_CTRL);
516
517 clk_disable(motg->pclk);
518 clk_disable(motg->clk);
519 if (motg->core_clk)
520 clk_disable(motg->core_clk);
521
522 if (!IS_ERR(motg->pclk_src))
523 clk_disable(motg->pclk_src);
524
525 if (motg->pdata->phy_type == SNPS_28NM_INTEGRATED_PHY &&
526 motg->pdata->otg_control == OTG_PMIC_CONTROL) {
527 msm_hsusb_ldo_set_mode(0);
528 msm_hsusb_config_vddcx(0);
529 }
530
531 if (device_may_wakeup(phy->dev))
532 enable_irq_wake(motg->irq);
533 if (bus)
534 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &(bus_to_hcd(bus))->flags);
535
536 atomic_set(&motg->in_lpm, 1);
537 enable_irq(motg->irq);
538
539 dev_info(phy->dev, "USB in low power mode\n");
540
541 return 0;
542}
543
544static int msm_otg_resume(struct msm_otg *motg)
545{
546 struct usb_phy *phy = &motg->phy;
547 struct usb_bus *bus = phy->otg->host;
548 int cnt = 0;
549 unsigned temp;
550
551 if (!atomic_read(&motg->in_lpm))
552 return 0;
553
554 if (!IS_ERR(motg->pclk_src))
555 clk_enable(motg->pclk_src);
556
557 clk_enable(motg->pclk);
558 clk_enable(motg->clk);
559 if (motg->core_clk)
560 clk_enable(motg->core_clk);
561
562 if (motg->pdata->phy_type == SNPS_28NM_INTEGRATED_PHY &&
563 motg->pdata->otg_control == OTG_PMIC_CONTROL) {
564 msm_hsusb_ldo_set_mode(1);
565 msm_hsusb_config_vddcx(1);
566 writel(readl(USB_PHY_CTRL) & ~PHY_RETEN, USB_PHY_CTRL);
567 }
568
569 temp = readl(USB_USBCMD);
570 temp &= ~ASYNC_INTR_CTRL;
571 temp &= ~ULPI_STP_CTRL;
572 writel(temp, USB_USBCMD);
573
574 /*
575 * PHY comes out of low power mode (LPM) in case of wakeup
576 * from asynchronous interrupt.
577 */
578 if (!(readl(USB_PORTSC) & PORTSC_PHCD))
579 goto skip_phy_resume;
580
581 writel(readl(USB_PORTSC) & ~PORTSC_PHCD, USB_PORTSC);
582 while (cnt < PHY_RESUME_TIMEOUT_USEC) {
583 if (!(readl(USB_PORTSC) & PORTSC_PHCD))
584 break;
585 udelay(1);
586 cnt++;
587 }
588
589 if (cnt >= PHY_RESUME_TIMEOUT_USEC) {
590 /*
591 * This is a fatal error. Reset the link and
592 * PHY. USB state can not be restored. Re-insertion
593 * of USB cable is the only way to get USB working.
594 */
595 dev_err(phy->dev, "Unable to resume USB."
596 "Re-plugin the cable\n");
597 msm_otg_reset(phy);
598 }
599
600skip_phy_resume:
601 if (device_may_wakeup(phy->dev))
602 disable_irq_wake(motg->irq);
603 if (bus)
604 set_bit(HCD_FLAG_HW_ACCESSIBLE, &(bus_to_hcd(bus))->flags);
605
606 atomic_set(&motg->in_lpm, 0);
607
608 if (motg->async_int) {
609 motg->async_int = 0;
610 pm_runtime_put(phy->dev);
611 enable_irq(motg->irq);
612 }
613
614 dev_info(phy->dev, "USB exited from low power mode\n");
615
616 return 0;
617}
618#endif
619
620static void msm_otg_notify_charger(struct msm_otg *motg, unsigned mA)
621{
622 if (motg->cur_power == mA)
623 return;
624
625 /* TODO: Notify PMIC about available current */
626 dev_info(motg->phy.dev, "Avail curr from USB = %u\n", mA);
627 motg->cur_power = mA;
628}
629
630static int msm_otg_set_power(struct usb_phy *phy, unsigned mA)
631{
632 struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
633
634 /*
635 * Gadget driver uses set_power method to notify about the
636 * available current based on suspend/configured states.
637 *
638 * IDEV_CHG can be drawn irrespective of suspend/un-configured
639 * states when CDP/ACA is connected.
640 */
641 if (motg->chg_type == USB_SDP_CHARGER)
642 msm_otg_notify_charger(motg, mA);
643
644 return 0;
645}
646
647static void msm_otg_start_host(struct usb_phy *phy, int on)
648{
649 struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
650 struct msm_otg_platform_data *pdata = motg->pdata;
651 struct usb_hcd *hcd;
652
653 if (!phy->otg->host)
654 return;
655
656 hcd = bus_to_hcd(phy->otg->host);
657
658 if (on) {
659 dev_dbg(phy->dev, "host on\n");
660
661 if (pdata->vbus_power)
662 pdata->vbus_power(1);
663 /*
664 * Some boards have a switch cotrolled by gpio
665 * to enable/disable internal HUB. Enable internal
666 * HUB before kicking the host.
667 */
668 if (pdata->setup_gpio)
669 pdata->setup_gpio(OTG_STATE_A_HOST);
670#ifdef CONFIG_USB
671 usb_add_hcd(hcd, hcd->irq, IRQF_SHARED);
672#endif
673 } else {
674 dev_dbg(phy->dev, "host off\n");
675
676#ifdef CONFIG_USB
677 usb_remove_hcd(hcd);
678#endif
679 if (pdata->setup_gpio)
680 pdata->setup_gpio(OTG_STATE_UNDEFINED);
681 if (pdata->vbus_power)
682 pdata->vbus_power(0);
683 }
684}
685
686static int msm_otg_set_host(struct usb_otg *otg, struct usb_bus *host)
687{
688 struct msm_otg *motg = container_of(otg->phy, struct msm_otg, phy);
689 struct usb_hcd *hcd;
690
691 /*
692 * Fail host registration if this board can support
693 * only peripheral configuration.
694 */
695 if (motg->pdata->mode == USB_PERIPHERAL) {
696 dev_info(otg->phy->dev, "Host mode is not supported\n");
697 return -ENODEV;
698 }
699
700 if (!host) {
701 if (otg->phy->state == OTG_STATE_A_HOST) {
702 pm_runtime_get_sync(otg->phy->dev);
703 msm_otg_start_host(otg->phy, 0);
704 otg->host = NULL;
705 otg->phy->state = OTG_STATE_UNDEFINED;
706 schedule_work(&motg->sm_work);
707 } else {
708 otg->host = NULL;
709 }
710
711 return 0;
712 }
713
714 hcd = bus_to_hcd(host);
715 hcd->power_budget = motg->pdata->power_budget;
716
717 otg->host = host;
718 dev_dbg(otg->phy->dev, "host driver registered w/ tranceiver\n");
719
720 /*
721 * Kick the state machine work, if peripheral is not supported
722 * or peripheral is already registered with us.
723 */
724 if (motg->pdata->mode == USB_HOST || otg->gadget) {
725 pm_runtime_get_sync(otg->phy->dev);
726 schedule_work(&motg->sm_work);
727 }
728
729 return 0;
730}
731
732static void msm_otg_start_peripheral(struct usb_phy *phy, int on)
733{
734 struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
735 struct msm_otg_platform_data *pdata = motg->pdata;
736
737 if (!phy->otg->gadget)
738 return;
739
740 if (on) {
741 dev_dbg(phy->dev, "gadget on\n");
742 /*
743 * Some boards have a switch cotrolled by gpio
744 * to enable/disable internal HUB. Disable internal
745 * HUB before kicking the gadget.
746 */
747 if (pdata->setup_gpio)
748 pdata->setup_gpio(OTG_STATE_B_PERIPHERAL);
749 usb_gadget_vbus_connect(phy->otg->gadget);
750 } else {
751 dev_dbg(phy->dev, "gadget off\n");
752 usb_gadget_vbus_disconnect(phy->otg->gadget);
753 if (pdata->setup_gpio)
754 pdata->setup_gpio(OTG_STATE_UNDEFINED);
755 }
756
757}
758
759static int msm_otg_set_peripheral(struct usb_otg *otg,
760 struct usb_gadget *gadget)
761{
762 struct msm_otg *motg = container_of(otg->phy, struct msm_otg, phy);
763
764 /*
765 * Fail peripheral registration if this board can support
766 * only host configuration.
767 */
768 if (motg->pdata->mode == USB_HOST) {
769 dev_info(otg->phy->dev, "Peripheral mode is not supported\n");
770 return -ENODEV;
771 }
772
773 if (!gadget) {
774 if (otg->phy->state == OTG_STATE_B_PERIPHERAL) {
775 pm_runtime_get_sync(otg->phy->dev);
776 msm_otg_start_peripheral(otg->phy, 0);
777 otg->gadget = NULL;
778 otg->phy->state = OTG_STATE_UNDEFINED;
779 schedule_work(&motg->sm_work);
780 } else {
781 otg->gadget = NULL;
782 }
783
784 return 0;
785 }
786 otg->gadget = gadget;
787 dev_dbg(otg->phy->dev, "peripheral driver registered w/ tranceiver\n");
788
789 /*
790 * Kick the state machine work, if host is not supported
791 * or host is already registered with us.
792 */
793 if (motg->pdata->mode == USB_PERIPHERAL || otg->host) {
794 pm_runtime_get_sync(otg->phy->dev);
795 schedule_work(&motg->sm_work);
796 }
797
798 return 0;
799}
800
801static bool msm_chg_check_secondary_det(struct msm_otg *motg)
802{
803 struct usb_phy *phy = &motg->phy;
804 u32 chg_det;
805 bool ret = false;
806
807 switch (motg->pdata->phy_type) {
808 case CI_45NM_INTEGRATED_PHY:
809 chg_det = ulpi_read(phy, 0x34);
810 ret = chg_det & (1 << 4);
811 break;
812 case SNPS_28NM_INTEGRATED_PHY:
813 chg_det = ulpi_read(phy, 0x87);
814 ret = chg_det & 1;
815 break;
816 default:
817 break;
818 }
819 return ret;
820}
821
822static void msm_chg_enable_secondary_det(struct msm_otg *motg)
823{
824 struct usb_phy *phy = &motg->phy;
825 u32 chg_det;
826
827 switch (motg->pdata->phy_type) {
828 case CI_45NM_INTEGRATED_PHY:
829 chg_det = ulpi_read(phy, 0x34);
830 /* Turn off charger block */
831 chg_det |= ~(1 << 1);
832 ulpi_write(phy, chg_det, 0x34);
833 udelay(20);
834 /* control chg block via ULPI */
835 chg_det &= ~(1 << 3);
836 ulpi_write(phy, chg_det, 0x34);
837 /* put it in host mode for enabling D- source */
838 chg_det &= ~(1 << 2);
839 ulpi_write(phy, chg_det, 0x34);
840 /* Turn on chg detect block */
841 chg_det &= ~(1 << 1);
842 ulpi_write(phy, chg_det, 0x34);
843 udelay(20);
844 /* enable chg detection */
845 chg_det &= ~(1 << 0);
846 ulpi_write(phy, chg_det, 0x34);
847 break;
848 case SNPS_28NM_INTEGRATED_PHY:
849 /*
850 * Configure DM as current source, DP as current sink
851 * and enable battery charging comparators.
852 */
853 ulpi_write(phy, 0x8, 0x85);
854 ulpi_write(phy, 0x2, 0x85);
855 ulpi_write(phy, 0x1, 0x85);
856 break;
857 default:
858 break;
859 }
860}
861
862static bool msm_chg_check_primary_det(struct msm_otg *motg)
863{
864 struct usb_phy *phy = &motg->phy;
865 u32 chg_det;
866 bool ret = false;
867
868 switch (motg->pdata->phy_type) {
869 case CI_45NM_INTEGRATED_PHY:
870 chg_det = ulpi_read(phy, 0x34);
871 ret = chg_det & (1 << 4);
872 break;
873 case SNPS_28NM_INTEGRATED_PHY:
874 chg_det = ulpi_read(phy, 0x87);
875 ret = chg_det & 1;
876 break;
877 default:
878 break;
879 }
880 return ret;
881}
882
883static void msm_chg_enable_primary_det(struct msm_otg *motg)
884{
885 struct usb_phy *phy = &motg->phy;
886 u32 chg_det;
887
888 switch (motg->pdata->phy_type) {
889 case CI_45NM_INTEGRATED_PHY:
890 chg_det = ulpi_read(phy, 0x34);
891 /* enable chg detection */
892 chg_det &= ~(1 << 0);
893 ulpi_write(phy, chg_det, 0x34);
894 break;
895 case SNPS_28NM_INTEGRATED_PHY:
896 /*
897 * Configure DP as current source, DM as current sink
898 * and enable battery charging comparators.
899 */
900 ulpi_write(phy, 0x2, 0x85);
901 ulpi_write(phy, 0x1, 0x85);
902 break;
903 default:
904 break;
905 }
906}
907
908static bool msm_chg_check_dcd(struct msm_otg *motg)
909{
910 struct usb_phy *phy = &motg->phy;
911 u32 line_state;
912 bool ret = false;
913
914 switch (motg->pdata->phy_type) {
915 case CI_45NM_INTEGRATED_PHY:
916 line_state = ulpi_read(phy, 0x15);
917 ret = !(line_state & 1);
918 break;
919 case SNPS_28NM_INTEGRATED_PHY:
920 line_state = ulpi_read(phy, 0x87);
921 ret = line_state & 2;
922 break;
923 default:
924 break;
925 }
926 return ret;
927}
928
929static void msm_chg_disable_dcd(struct msm_otg *motg)
930{
931 struct usb_phy *phy = &motg->phy;
932 u32 chg_det;
933
934 switch (motg->pdata->phy_type) {
935 case CI_45NM_INTEGRATED_PHY:
936 chg_det = ulpi_read(phy, 0x34);
937 chg_det &= ~(1 << 5);
938 ulpi_write(phy, chg_det, 0x34);
939 break;
940 case SNPS_28NM_INTEGRATED_PHY:
941 ulpi_write(phy, 0x10, 0x86);
942 break;
943 default:
944 break;
945 }
946}
947
948static void msm_chg_enable_dcd(struct msm_otg *motg)
949{
950 struct usb_phy *phy = &motg->phy;
951 u32 chg_det;
952
953 switch (motg->pdata->phy_type) {
954 case CI_45NM_INTEGRATED_PHY:
955 chg_det = ulpi_read(phy, 0x34);
956 /* Turn on D+ current source */
957 chg_det |= (1 << 5);
958 ulpi_write(phy, chg_det, 0x34);
959 break;
960 case SNPS_28NM_INTEGRATED_PHY:
961 /* Data contact detection enable */
962 ulpi_write(phy, 0x10, 0x85);
963 break;
964 default:
965 break;
966 }
967}
968
969static void msm_chg_block_on(struct msm_otg *motg)
970{
971 struct usb_phy *phy = &motg->phy;
972 u32 func_ctrl, chg_det;
973
974 /* put the controller in non-driving mode */
975 func_ctrl = ulpi_read(phy, ULPI_FUNC_CTRL);
976 func_ctrl &= ~ULPI_FUNC_CTRL_OPMODE_MASK;
977 func_ctrl |= ULPI_FUNC_CTRL_OPMODE_NONDRIVING;
978 ulpi_write(phy, func_ctrl, ULPI_FUNC_CTRL);
979
980 switch (motg->pdata->phy_type) {
981 case CI_45NM_INTEGRATED_PHY:
982 chg_det = ulpi_read(phy, 0x34);
983 /* control chg block via ULPI */
984 chg_det &= ~(1 << 3);
985 ulpi_write(phy, chg_det, 0x34);
986 /* Turn on chg detect block */
987 chg_det &= ~(1 << 1);
988 ulpi_write(phy, chg_det, 0x34);
989 udelay(20);
990 break;
991 case SNPS_28NM_INTEGRATED_PHY:
992 /* Clear charger detecting control bits */
993 ulpi_write(phy, 0x3F, 0x86);
994 /* Clear alt interrupt latch and enable bits */
995 ulpi_write(phy, 0x1F, 0x92);
996 ulpi_write(phy, 0x1F, 0x95);
997 udelay(100);
998 break;
999 default:
1000 break;
1001 }
1002}
1003
1004static void msm_chg_block_off(struct msm_otg *motg)
1005{
1006 struct usb_phy *phy = &motg->phy;
1007 u32 func_ctrl, chg_det;
1008
1009 switch (motg->pdata->phy_type) {
1010 case CI_45NM_INTEGRATED_PHY:
1011 chg_det = ulpi_read(phy, 0x34);
1012 /* Turn off charger block */
1013 chg_det |= ~(1 << 1);
1014 ulpi_write(phy, chg_det, 0x34);
1015 break;
1016 case SNPS_28NM_INTEGRATED_PHY:
1017 /* Clear charger detecting control bits */
1018 ulpi_write(phy, 0x3F, 0x86);
1019 /* Clear alt interrupt latch and enable bits */
1020 ulpi_write(phy, 0x1F, 0x92);
1021 ulpi_write(phy, 0x1F, 0x95);
1022 break;
1023 default:
1024 break;
1025 }
1026
1027 /* put the controller in normal mode */
1028 func_ctrl = ulpi_read(phy, ULPI_FUNC_CTRL);
1029 func_ctrl &= ~ULPI_FUNC_CTRL_OPMODE_MASK;
1030 func_ctrl |= ULPI_FUNC_CTRL_OPMODE_NORMAL;
1031 ulpi_write(phy, func_ctrl, ULPI_FUNC_CTRL);
1032}
1033
1034#define MSM_CHG_DCD_POLL_TIME (100 * HZ/1000) /* 100 msec */
1035#define MSM_CHG_DCD_MAX_RETRIES 6 /* Tdcd_tmout = 6 * 100 msec */
1036#define MSM_CHG_PRIMARY_DET_TIME (40 * HZ/1000) /* TVDPSRC_ON */
1037#define MSM_CHG_SECONDARY_DET_TIME (40 * HZ/1000) /* TVDMSRC_ON */
1038static void msm_chg_detect_work(struct work_struct *w)
1039{
1040 struct msm_otg *motg = container_of(w, struct msm_otg, chg_work.work);
1041 struct usb_phy *phy = &motg->phy;
1042 bool is_dcd, tmout, vout;
1043 unsigned long delay;
1044
1045 dev_dbg(phy->dev, "chg detection work\n");
1046 switch (motg->chg_state) {
1047 case USB_CHG_STATE_UNDEFINED:
1048 pm_runtime_get_sync(phy->dev);
1049 msm_chg_block_on(motg);
1050 msm_chg_enable_dcd(motg);
1051 motg->chg_state = USB_CHG_STATE_WAIT_FOR_DCD;
1052 motg->dcd_retries = 0;
1053 delay = MSM_CHG_DCD_POLL_TIME;
1054 break;
1055 case USB_CHG_STATE_WAIT_FOR_DCD:
1056 is_dcd = msm_chg_check_dcd(motg);
1057 tmout = ++motg->dcd_retries == MSM_CHG_DCD_MAX_RETRIES;
1058 if (is_dcd || tmout) {
1059 msm_chg_disable_dcd(motg);
1060 msm_chg_enable_primary_det(motg);
1061 delay = MSM_CHG_PRIMARY_DET_TIME;
1062 motg->chg_state = USB_CHG_STATE_DCD_DONE;
1063 } else {
1064 delay = MSM_CHG_DCD_POLL_TIME;
1065 }
1066 break;
1067 case USB_CHG_STATE_DCD_DONE:
1068 vout = msm_chg_check_primary_det(motg);
1069 if (vout) {
1070 msm_chg_enable_secondary_det(motg);
1071 delay = MSM_CHG_SECONDARY_DET_TIME;
1072 motg->chg_state = USB_CHG_STATE_PRIMARY_DONE;
1073 } else {
1074 motg->chg_type = USB_SDP_CHARGER;
1075 motg->chg_state = USB_CHG_STATE_DETECTED;
1076 delay = 0;
1077 }
1078 break;
1079 case USB_CHG_STATE_PRIMARY_DONE:
1080 vout = msm_chg_check_secondary_det(motg);
1081 if (vout)
1082 motg->chg_type = USB_DCP_CHARGER;
1083 else
1084 motg->chg_type = USB_CDP_CHARGER;
1085 motg->chg_state = USB_CHG_STATE_SECONDARY_DONE;
1086 /* fall through */
1087 case USB_CHG_STATE_SECONDARY_DONE:
1088 motg->chg_state = USB_CHG_STATE_DETECTED;
1089 case USB_CHG_STATE_DETECTED:
1090 msm_chg_block_off(motg);
1091 dev_dbg(phy->dev, "charger = %d\n", motg->chg_type);
1092 schedule_work(&motg->sm_work);
1093 return;
1094 default:
1095 return;
1096 }
1097
1098 schedule_delayed_work(&motg->chg_work, delay);
1099}
1100
1101/*
1102 * We support OTG, Peripheral only and Host only configurations. In case
1103 * of OTG, mode switch (host-->peripheral/peripheral-->host) can happen
1104 * via Id pin status or user request (debugfs). Id/BSV interrupts are not
1105 * enabled when switch is controlled by user and default mode is supplied
1106 * by board file, which can be changed by userspace later.
1107 */
1108static void msm_otg_init_sm(struct msm_otg *motg)
1109{
1110 struct msm_otg_platform_data *pdata = motg->pdata;
1111 u32 otgsc = readl(USB_OTGSC);
1112
1113 switch (pdata->mode) {
1114 case USB_OTG:
1115 if (pdata->otg_control == OTG_PHY_CONTROL) {
1116 if (otgsc & OTGSC_ID)
1117 set_bit(ID, &motg->inputs);
1118 else
1119 clear_bit(ID, &motg->inputs);
1120
1121 if (otgsc & OTGSC_BSV)
1122 set_bit(B_SESS_VLD, &motg->inputs);
1123 else
1124 clear_bit(B_SESS_VLD, &motg->inputs);
1125 } else if (pdata->otg_control == OTG_USER_CONTROL) {
1126 if (pdata->default_mode == USB_HOST) {
1127 clear_bit(ID, &motg->inputs);
1128 } else if (pdata->default_mode == USB_PERIPHERAL) {
1129 set_bit(ID, &motg->inputs);
1130 set_bit(B_SESS_VLD, &motg->inputs);
1131 } else {
1132 set_bit(ID, &motg->inputs);
1133 clear_bit(B_SESS_VLD, &motg->inputs);
1134 }
1135 }
1136 break;
1137 case USB_HOST:
1138 clear_bit(ID, &motg->inputs);
1139 break;
1140 case USB_PERIPHERAL:
1141 set_bit(ID, &motg->inputs);
1142 if (otgsc & OTGSC_BSV)
1143 set_bit(B_SESS_VLD, &motg->inputs);
1144 else
1145 clear_bit(B_SESS_VLD, &motg->inputs);
1146 break;
1147 default:
1148 break;
1149 }
1150}
1151
1152static void msm_otg_sm_work(struct work_struct *w)
1153{
1154 struct msm_otg *motg = container_of(w, struct msm_otg, sm_work);
1155 struct usb_otg *otg = motg->phy.otg;
1156
1157 switch (otg->phy->state) {
1158 case OTG_STATE_UNDEFINED:
1159 dev_dbg(otg->phy->dev, "OTG_STATE_UNDEFINED state\n");
1160 msm_otg_reset(otg->phy);
1161 msm_otg_init_sm(motg);
1162 otg->phy->state = OTG_STATE_B_IDLE;
1163 /* FALL THROUGH */
1164 case OTG_STATE_B_IDLE:
1165 dev_dbg(otg->phy->dev, "OTG_STATE_B_IDLE state\n");
1166 if (!test_bit(ID, &motg->inputs) && otg->host) {
1167 /* disable BSV bit */
1168 writel(readl(USB_OTGSC) & ~OTGSC_BSVIE, USB_OTGSC);
1169 msm_otg_start_host(otg->phy, 1);
1170 otg->phy->state = OTG_STATE_A_HOST;
1171 } else if (test_bit(B_SESS_VLD, &motg->inputs)) {
1172 switch (motg->chg_state) {
1173 case USB_CHG_STATE_UNDEFINED:
1174 msm_chg_detect_work(&motg->chg_work.work);
1175 break;
1176 case USB_CHG_STATE_DETECTED:
1177 switch (motg->chg_type) {
1178 case USB_DCP_CHARGER:
1179 msm_otg_notify_charger(motg,
1180 IDEV_CHG_MAX);
1181 break;
1182 case USB_CDP_CHARGER:
1183 msm_otg_notify_charger(motg,
1184 IDEV_CHG_MAX);
1185 msm_otg_start_peripheral(otg->phy, 1);
1186 otg->phy->state
1187 = OTG_STATE_B_PERIPHERAL;
1188 break;
1189 case USB_SDP_CHARGER:
1190 msm_otg_notify_charger(motg, IUNIT);
1191 msm_otg_start_peripheral(otg->phy, 1);
1192 otg->phy->state
1193 = OTG_STATE_B_PERIPHERAL;
1194 break;
1195 default:
1196 break;
1197 }
1198 break;
1199 default:
1200 break;
1201 }
1202 } else {
1203 /*
1204 * If charger detection work is pending, decrement
1205 * the pm usage counter to balance with the one that
1206 * is incremented in charger detection work.
1207 */
1208 if (cancel_delayed_work_sync(&motg->chg_work)) {
1209 pm_runtime_put_sync(otg->phy->dev);
1210 msm_otg_reset(otg->phy);
1211 }
1212 msm_otg_notify_charger(motg, 0);
1213 motg->chg_state = USB_CHG_STATE_UNDEFINED;
1214 motg->chg_type = USB_INVALID_CHARGER;
1215 }
1216 pm_runtime_put_sync(otg->phy->dev);
1217 break;
1218 case OTG_STATE_B_PERIPHERAL:
1219 dev_dbg(otg->phy->dev, "OTG_STATE_B_PERIPHERAL state\n");
1220 if (!test_bit(B_SESS_VLD, &motg->inputs) ||
1221 !test_bit(ID, &motg->inputs)) {
1222 msm_otg_notify_charger(motg, 0);
1223 msm_otg_start_peripheral(otg->phy, 0);
1224 motg->chg_state = USB_CHG_STATE_UNDEFINED;
1225 motg->chg_type = USB_INVALID_CHARGER;
1226 otg->phy->state = OTG_STATE_B_IDLE;
1227 msm_otg_reset(otg->phy);
1228 schedule_work(w);
1229 }
1230 break;
1231 case OTG_STATE_A_HOST:
1232 dev_dbg(otg->phy->dev, "OTG_STATE_A_HOST state\n");
1233 if (test_bit(ID, &motg->inputs)) {
1234 msm_otg_start_host(otg->phy, 0);
1235 otg->phy->state = OTG_STATE_B_IDLE;
1236 msm_otg_reset(otg->phy);
1237 schedule_work(w);
1238 }
1239 break;
1240 default:
1241 break;
1242 }
1243}
1244
1245static irqreturn_t msm_otg_irq(int irq, void *data)
1246{
1247 struct msm_otg *motg = data;
1248 struct usb_phy *phy = &motg->phy;
1249 u32 otgsc = 0;
1250
1251 if (atomic_read(&motg->in_lpm)) {
1252 disable_irq_nosync(irq);
1253 motg->async_int = 1;
1254 pm_runtime_get(phy->dev);
1255 return IRQ_HANDLED;
1256 }
1257
1258 otgsc = readl(USB_OTGSC);
1259 if (!(otgsc & (OTGSC_IDIS | OTGSC_BSVIS)))
1260 return IRQ_NONE;
1261
1262 if ((otgsc & OTGSC_IDIS) && (otgsc & OTGSC_IDIE)) {
1263 if (otgsc & OTGSC_ID)
1264 set_bit(ID, &motg->inputs);
1265 else
1266 clear_bit(ID, &motg->inputs);
1267 dev_dbg(phy->dev, "ID set/clear\n");
1268 pm_runtime_get_noresume(phy->dev);
1269 } else if ((otgsc & OTGSC_BSVIS) && (otgsc & OTGSC_BSVIE)) {
1270 if (otgsc & OTGSC_BSV)
1271 set_bit(B_SESS_VLD, &motg->inputs);
1272 else
1273 clear_bit(B_SESS_VLD, &motg->inputs);
1274 dev_dbg(phy->dev, "BSV set/clear\n");
1275 pm_runtime_get_noresume(phy->dev);
1276 }
1277
1278 writel(otgsc, USB_OTGSC);
1279 schedule_work(&motg->sm_work);
1280 return IRQ_HANDLED;
1281}
1282
1283static int msm_otg_mode_show(struct seq_file *s, void *unused)
1284{
1285 struct msm_otg *motg = s->private;
1286 struct usb_otg *otg = motg->phy.otg;
1287
1288 switch (otg->phy->state) {
1289 case OTG_STATE_A_HOST:
1290 seq_printf(s, "host\n");
1291 break;
1292 case OTG_STATE_B_PERIPHERAL:
1293 seq_printf(s, "peripheral\n");
1294 break;
1295 default:
1296 seq_printf(s, "none\n");
1297 break;
1298 }
1299
1300 return 0;
1301}
1302
1303static int msm_otg_mode_open(struct inode *inode, struct file *file)
1304{
1305 return single_open(file, msm_otg_mode_show, inode->i_private);
1306}
1307
1308static ssize_t msm_otg_mode_write(struct file *file, const char __user *ubuf,
1309 size_t count, loff_t *ppos)
1310{
1311 struct seq_file *s = file->private_data;
1312 struct msm_otg *motg = s->private;
1313 char buf[16];
1314 struct usb_otg *otg = motg->phy.otg;
1315 int status = count;
1316 enum usb_mode_type req_mode;
1317
1318 memset(buf, 0x00, sizeof(buf));
1319
1320 if (copy_from_user(&buf, ubuf, min_t(size_t, sizeof(buf) - 1, count))) {
1321 status = -EFAULT;
1322 goto out;
1323 }
1324
1325 if (!strncmp(buf, "host", 4)) {
1326 req_mode = USB_HOST;
1327 } else if (!strncmp(buf, "peripheral", 10)) {
1328 req_mode = USB_PERIPHERAL;
1329 } else if (!strncmp(buf, "none", 4)) {
1330 req_mode = USB_NONE;
1331 } else {
1332 status = -EINVAL;
1333 goto out;
1334 }
1335
1336 switch (req_mode) {
1337 case USB_NONE:
1338 switch (otg->phy->state) {
1339 case OTG_STATE_A_HOST:
1340 case OTG_STATE_B_PERIPHERAL:
1341 set_bit(ID, &motg->inputs);
1342 clear_bit(B_SESS_VLD, &motg->inputs);
1343 break;
1344 default:
1345 goto out;
1346 }
1347 break;
1348 case USB_PERIPHERAL:
1349 switch (otg->phy->state) {
1350 case OTG_STATE_B_IDLE:
1351 case OTG_STATE_A_HOST:
1352 set_bit(ID, &motg->inputs);
1353 set_bit(B_SESS_VLD, &motg->inputs);
1354 break;
1355 default:
1356 goto out;
1357 }
1358 break;
1359 case USB_HOST:
1360 switch (otg->phy->state) {
1361 case OTG_STATE_B_IDLE:
1362 case OTG_STATE_B_PERIPHERAL:
1363 clear_bit(ID, &motg->inputs);
1364 break;
1365 default:
1366 goto out;
1367 }
1368 break;
1369 default:
1370 goto out;
1371 }
1372
1373 pm_runtime_get_sync(otg->phy->dev);
1374 schedule_work(&motg->sm_work);
1375out:
1376 return status;
1377}
1378
1379const struct file_operations msm_otg_mode_fops = {
1380 .open = msm_otg_mode_open,
1381 .read = seq_read,
1382 .write = msm_otg_mode_write,
1383 .llseek = seq_lseek,
1384 .release = single_release,
1385};
1386
1387static struct dentry *msm_otg_dbg_root;
1388static struct dentry *msm_otg_dbg_mode;
1389
1390static int msm_otg_debugfs_init(struct msm_otg *motg)
1391{
1392 msm_otg_dbg_root = debugfs_create_dir("msm_otg", NULL);
1393
1394 if (!msm_otg_dbg_root || IS_ERR(msm_otg_dbg_root))
1395 return -ENODEV;
1396
1397 msm_otg_dbg_mode = debugfs_create_file("mode", S_IRUGO | S_IWUSR,
1398 msm_otg_dbg_root, motg, &msm_otg_mode_fops);
1399 if (!msm_otg_dbg_mode) {
1400 debugfs_remove(msm_otg_dbg_root);
1401 msm_otg_dbg_root = NULL;
1402 return -ENODEV;
1403 }
1404
1405 return 0;
1406}
1407
1408static void msm_otg_debugfs_cleanup(void)
1409{
1410 debugfs_remove(msm_otg_dbg_mode);
1411 debugfs_remove(msm_otg_dbg_root);
1412}
1413
1414static int __init msm_otg_probe(struct platform_device *pdev)
1415{
1416 int ret = 0;
1417 struct resource *res;
1418 struct msm_otg *motg;
1419 struct usb_phy *phy;
1420
1421 dev_info(&pdev->dev, "msm_otg probe\n");
1422 if (!pdev->dev.platform_data) {
1423 dev_err(&pdev->dev, "No platform data given. Bailing out\n");
1424 return -ENODEV;
1425 }
1426
1427 motg = kzalloc(sizeof(struct msm_otg), GFP_KERNEL);
1428 if (!motg) {
1429 dev_err(&pdev->dev, "unable to allocate msm_otg\n");
1430 return -ENOMEM;
1431 }
1432
1433 motg->phy.otg = kzalloc(sizeof(struct usb_otg), GFP_KERNEL);
1434 if (!motg->phy.otg) {
1435 dev_err(&pdev->dev, "unable to allocate msm_otg\n");
1436 return -ENOMEM;
1437 }
1438
1439 motg->pdata = pdev->dev.platform_data;
1440 phy = &motg->phy;
1441 phy->dev = &pdev->dev;
1442
1443 motg->phy_reset_clk = clk_get(&pdev->dev, "usb_phy_clk");
1444 if (IS_ERR(motg->phy_reset_clk)) {
1445 dev_err(&pdev->dev, "failed to get usb_phy_clk\n");
1446 ret = PTR_ERR(motg->phy_reset_clk);
1447 goto free_motg;
1448 }
1449
1450 motg->clk = clk_get(&pdev->dev, "usb_hs_clk");
1451 if (IS_ERR(motg->clk)) {
1452 dev_err(&pdev->dev, "failed to get usb_hs_clk\n");
1453 ret = PTR_ERR(motg->clk);
1454 goto put_phy_reset_clk;
1455 }
1456 clk_set_rate(motg->clk, 60000000);
1457
1458 /*
1459 * If USB Core is running its protocol engine based on CORE CLK,
1460 * CORE CLK must be running at >55Mhz for correct HSUSB
1461 * operation and USB core cannot tolerate frequency changes on
1462 * CORE CLK. For such USB cores, vote for maximum clk frequency
1463 * on pclk source
1464 */
1465 if (motg->pdata->pclk_src_name) {
1466 motg->pclk_src = clk_get(&pdev->dev,
1467 motg->pdata->pclk_src_name);
1468 if (IS_ERR(motg->pclk_src))
1469 goto put_clk;
1470 clk_set_rate(motg->pclk_src, INT_MAX);
1471 clk_enable(motg->pclk_src);
1472 } else
1473 motg->pclk_src = ERR_PTR(-ENOENT);
1474
1475
1476 motg->pclk = clk_get(&pdev->dev, "usb_hs_pclk");
1477 if (IS_ERR(motg->pclk)) {
1478 dev_err(&pdev->dev, "failed to get usb_hs_pclk\n");
1479 ret = PTR_ERR(motg->pclk);
1480 goto put_pclk_src;
1481 }
1482
1483 /*
1484 * USB core clock is not present on all MSM chips. This
1485 * clock is introduced to remove the dependency on AXI
1486 * bus frequency.
1487 */
1488 motg->core_clk = clk_get(&pdev->dev, "usb_hs_core_clk");
1489 if (IS_ERR(motg->core_clk))
1490 motg->core_clk = NULL;
1491
1492 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1493 if (!res) {
1494 dev_err(&pdev->dev, "failed to get platform resource mem\n");
1495 ret = -ENODEV;
1496 goto put_core_clk;
1497 }
1498
1499 motg->regs = ioremap(res->start, resource_size(res));
1500 if (!motg->regs) {
1501 dev_err(&pdev->dev, "ioremap failed\n");
1502 ret = -ENOMEM;
1503 goto put_core_clk;
1504 }
1505 dev_info(&pdev->dev, "OTG regs = %p\n", motg->regs);
1506
1507 motg->irq = platform_get_irq(pdev, 0);
1508 if (!motg->irq) {
1509 dev_err(&pdev->dev, "platform_get_irq failed\n");
1510 ret = -ENODEV;
1511 goto free_regs;
1512 }
1513
1514 clk_enable(motg->clk);
1515 clk_enable(motg->pclk);
1516
1517 ret = msm_hsusb_init_vddcx(motg, 1);
1518 if (ret) {
1519 dev_err(&pdev->dev, "hsusb vddcx configuration failed\n");
1520 goto free_regs;
1521 }
1522
1523 ret = msm_hsusb_ldo_init(motg, 1);
1524 if (ret) {
1525 dev_err(&pdev->dev, "hsusb vreg configuration failed\n");
1526 goto vddcx_exit;
1527 }
1528 ret = msm_hsusb_ldo_set_mode(1);
1529 if (ret) {
1530 dev_err(&pdev->dev, "hsusb vreg enable failed\n");
1531 goto ldo_exit;
1532 }
1533
1534 if (motg->core_clk)
1535 clk_enable(motg->core_clk);
1536
1537 writel(0, USB_USBINTR);
1538 writel(0, USB_OTGSC);
1539
1540 INIT_WORK(&motg->sm_work, msm_otg_sm_work);
1541 INIT_DELAYED_WORK(&motg->chg_work, msm_chg_detect_work);
1542 ret = request_irq(motg->irq, msm_otg_irq, IRQF_SHARED,
1543 "msm_otg", motg);
1544 if (ret) {
1545 dev_err(&pdev->dev, "request irq failed\n");
1546 goto disable_clks;
1547 }
1548
1549 phy->init = msm_otg_reset;
1550 phy->set_power = msm_otg_set_power;
1551
1552 phy->io_ops = &msm_otg_io_ops;
1553
1554 phy->otg->phy = &motg->phy;
1555 phy->otg->set_host = msm_otg_set_host;
1556 phy->otg->set_peripheral = msm_otg_set_peripheral;
1557
1558 ret = usb_add_phy(&motg->phy, USB_PHY_TYPE_USB2);
1559 if (ret) {
1560 dev_err(&pdev->dev, "usb_add_phy failed\n");
1561 goto free_irq;
1562 }
1563
1564 platform_set_drvdata(pdev, motg);
1565 device_init_wakeup(&pdev->dev, 1);
1566
1567 if (motg->pdata->mode == USB_OTG &&
1568 motg->pdata->otg_control == OTG_USER_CONTROL) {
1569 ret = msm_otg_debugfs_init(motg);
1570 if (ret)
1571 dev_dbg(&pdev->dev, "mode debugfs file is"
1572 "not available\n");
1573 }
1574
1575 pm_runtime_set_active(&pdev->dev);
1576 pm_runtime_enable(&pdev->dev);
1577
1578 return 0;
1579free_irq:
1580 free_irq(motg->irq, motg);
1581disable_clks:
1582 clk_disable(motg->pclk);
1583 clk_disable(motg->clk);
1584ldo_exit:
1585 msm_hsusb_ldo_init(motg, 0);
1586vddcx_exit:
1587 msm_hsusb_init_vddcx(motg, 0);
1588free_regs:
1589 iounmap(motg->regs);
1590put_core_clk:
1591 if (motg->core_clk)
1592 clk_put(motg->core_clk);
1593 clk_put(motg->pclk);
1594put_pclk_src:
1595 if (!IS_ERR(motg->pclk_src)) {
1596 clk_disable(motg->pclk_src);
1597 clk_put(motg->pclk_src);
1598 }
1599put_clk:
1600 clk_put(motg->clk);
1601put_phy_reset_clk:
1602 clk_put(motg->phy_reset_clk);
1603free_motg:
1604 kfree(motg->phy.otg);
1605 kfree(motg);
1606 return ret;
1607}
1608
1609static int msm_otg_remove(struct platform_device *pdev)
1610{
1611 struct msm_otg *motg = platform_get_drvdata(pdev);
1612 struct usb_phy *phy = &motg->phy;
1613 int cnt = 0;
1614
1615 if (phy->otg->host || phy->otg->gadget)
1616 return -EBUSY;
1617
1618 msm_otg_debugfs_cleanup();
1619 cancel_delayed_work_sync(&motg->chg_work);
1620 cancel_work_sync(&motg->sm_work);
1621
1622 pm_runtime_resume(&pdev->dev);
1623
1624 device_init_wakeup(&pdev->dev, 0);
1625 pm_runtime_disable(&pdev->dev);
1626
1627 usb_remove_phy(phy);
1628 free_irq(motg->irq, motg);
1629
1630 /*
1631 * Put PHY in low power mode.
1632 */
1633 ulpi_read(phy, 0x14);
1634 ulpi_write(phy, 0x08, 0x09);
1635
1636 writel(readl(USB_PORTSC) | PORTSC_PHCD, USB_PORTSC);
1637 while (cnt < PHY_SUSPEND_TIMEOUT_USEC) {
1638 if (readl(USB_PORTSC) & PORTSC_PHCD)
1639 break;
1640 udelay(1);
1641 cnt++;
1642 }
1643 if (cnt >= PHY_SUSPEND_TIMEOUT_USEC)
1644 dev_err(phy->dev, "Unable to suspend PHY\n");
1645
1646 clk_disable(motg->pclk);
1647 clk_disable(motg->clk);
1648 if (motg->core_clk)
1649 clk_disable(motg->core_clk);
1650 if (!IS_ERR(motg->pclk_src)) {
1651 clk_disable(motg->pclk_src);
1652 clk_put(motg->pclk_src);
1653 }
1654 msm_hsusb_ldo_init(motg, 0);
1655
1656 iounmap(motg->regs);
1657 pm_runtime_set_suspended(&pdev->dev);
1658
1659 clk_put(motg->phy_reset_clk);
1660 clk_put(motg->pclk);
1661 clk_put(motg->clk);
1662 if (motg->core_clk)
1663 clk_put(motg->core_clk);
1664
1665 kfree(motg->phy.otg);
1666 kfree(motg);
1667
1668 return 0;
1669}
1670
1671#ifdef CONFIG_PM_RUNTIME
1672static int msm_otg_runtime_idle(struct device *dev)
1673{
1674 struct msm_otg *motg = dev_get_drvdata(dev);
1675 struct usb_otg *otg = motg->phy.otg;
1676
1677 dev_dbg(dev, "OTG runtime idle\n");
1678
1679 /*
1680 * It is observed some times that a spurious interrupt
1681 * comes when PHY is put into LPM immediately after PHY reset.
1682 * This 1 sec delay also prevents entering into LPM immediately
1683 * after asynchronous interrupt.
1684 */
1685 if (otg->phy->state != OTG_STATE_UNDEFINED)
1686 pm_schedule_suspend(dev, 1000);
1687
1688 return -EAGAIN;
1689}
1690
1691static int msm_otg_runtime_suspend(struct device *dev)
1692{
1693 struct msm_otg *motg = dev_get_drvdata(dev);
1694
1695 dev_dbg(dev, "OTG runtime suspend\n");
1696 return msm_otg_suspend(motg);
1697}
1698
1699static int msm_otg_runtime_resume(struct device *dev)
1700{
1701 struct msm_otg *motg = dev_get_drvdata(dev);
1702
1703 dev_dbg(dev, "OTG runtime resume\n");
1704 return msm_otg_resume(motg);
1705}
1706#endif
1707
1708#ifdef CONFIG_PM_SLEEP
1709static int msm_otg_pm_suspend(struct device *dev)
1710{
1711 struct msm_otg *motg = dev_get_drvdata(dev);
1712
1713 dev_dbg(dev, "OTG PM suspend\n");
1714 return msm_otg_suspend(motg);
1715}
1716
1717static int msm_otg_pm_resume(struct device *dev)
1718{
1719 struct msm_otg *motg = dev_get_drvdata(dev);
1720 int ret;
1721
1722 dev_dbg(dev, "OTG PM resume\n");
1723
1724 ret = msm_otg_resume(motg);
1725 if (ret)
1726 return ret;
1727
1728 /*
1729 * Runtime PM Documentation recommends bringing the
1730 * device to full powered state upon resume.
1731 */
1732 pm_runtime_disable(dev);
1733 pm_runtime_set_active(dev);
1734 pm_runtime_enable(dev);
1735
1736 return 0;
1737}
1738#endif
1739
1740#ifdef CONFIG_PM
1741static const struct dev_pm_ops msm_otg_dev_pm_ops = {
1742 SET_SYSTEM_SLEEP_PM_OPS(msm_otg_pm_suspend, msm_otg_pm_resume)
1743 SET_RUNTIME_PM_OPS(msm_otg_runtime_suspend, msm_otg_runtime_resume,
1744 msm_otg_runtime_idle)
1745};
1746#endif
1747
1748static struct platform_driver msm_otg_driver = {
1749 .remove = msm_otg_remove,
1750 .driver = {
1751 .name = DRIVER_NAME,
1752 .owner = THIS_MODULE,
1753#ifdef CONFIG_PM
1754 .pm = &msm_otg_dev_pm_ops,
1755#endif
1756 },
1757};
1758
1759module_platform_driver_probe(msm_otg_driver, msm_otg_probe);
1760
1761MODULE_LICENSE("GPL v2");
1762MODULE_DESCRIPTION("MSM USB transceiver driver");
diff --git a/drivers/usb/phy/mv_u3d_phy.c b/drivers/usb/phy/phy-mv-u3d-usb.c
index bafd67f1f134..f7838a43347c 100644
--- a/drivers/usb/phy/mv_u3d_phy.c
+++ b/drivers/usb/phy/phy-mv-u3d-usb.c
@@ -15,7 +15,7 @@
15#include <linux/usb/otg.h> 15#include <linux/usb/otg.h>
16#include <linux/platform_data/mv_usb.h> 16#include <linux/platform_data/mv_usb.h>
17 17
18#include "mv_u3d_phy.h" 18#include "phy-mv-u3d-usb.h"
19 19
20/* 20/*
21 * struct mv_u3d_phy - transceiver driver state 21 * struct mv_u3d_phy - transceiver driver state
diff --git a/drivers/usb/phy/mv_u3d_phy.h b/drivers/usb/phy/phy-mv-u3d-usb.h
index 2a658cb9a527..2a658cb9a527 100644
--- a/drivers/usb/phy/mv_u3d_phy.h
+++ b/drivers/usb/phy/phy-mv-u3d-usb.h
diff --git a/drivers/usb/phy/phy-mv-usb.c b/drivers/usb/phy/phy-mv-usb.c
new file mode 100644
index 000000000000..c987bbe27851
--- /dev/null
+++ b/drivers/usb/phy/phy-mv-usb.c
@@ -0,0 +1,909 @@
1/*
2 * Copyright (C) 2011 Marvell International Ltd. All rights reserved.
3 * Author: Chao Xie <chao.xie@marvell.com>
4 * Neil Zhang <zhangwm@marvell.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12#include <linux/module.h>
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/io.h>
16#include <linux/uaccess.h>
17#include <linux/device.h>
18#include <linux/proc_fs.h>
19#include <linux/clk.h>
20#include <linux/workqueue.h>
21#include <linux/platform_device.h>
22
23#include <linux/usb.h>
24#include <linux/usb/ch9.h>
25#include <linux/usb/otg.h>
26#include <linux/usb/gadget.h>
27#include <linux/usb/hcd.h>
28#include <linux/platform_data/mv_usb.h>
29
30#include "phy-mv-usb.h"
31
32#define DRIVER_DESC "Marvell USB OTG transceiver driver"
33#define DRIVER_VERSION "Jan 20, 2010"
34
35MODULE_DESCRIPTION(DRIVER_DESC);
36MODULE_VERSION(DRIVER_VERSION);
37MODULE_LICENSE("GPL");
38
39static const char driver_name[] = "mv-otg";
40
41static char *state_string[] = {
42 "undefined",
43 "b_idle",
44 "b_srp_init",
45 "b_peripheral",
46 "b_wait_acon",
47 "b_host",
48 "a_idle",
49 "a_wait_vrise",
50 "a_wait_bcon",
51 "a_host",
52 "a_suspend",
53 "a_peripheral",
54 "a_wait_vfall",
55 "a_vbus_err"
56};
57
58static int mv_otg_set_vbus(struct usb_otg *otg, bool on)
59{
60 struct mv_otg *mvotg = container_of(otg->phy, struct mv_otg, phy);
61 if (mvotg->pdata->set_vbus == NULL)
62 return -ENODEV;
63
64 return mvotg->pdata->set_vbus(on);
65}
66
67static int mv_otg_set_host(struct usb_otg *otg,
68 struct usb_bus *host)
69{
70 otg->host = host;
71
72 return 0;
73}
74
75static int mv_otg_set_peripheral(struct usb_otg *otg,
76 struct usb_gadget *gadget)
77{
78 otg->gadget = gadget;
79
80 return 0;
81}
82
83static void mv_otg_run_state_machine(struct mv_otg *mvotg,
84 unsigned long delay)
85{
86 dev_dbg(&mvotg->pdev->dev, "transceiver is updated\n");
87 if (!mvotg->qwork)
88 return;
89
90 queue_delayed_work(mvotg->qwork, &mvotg->work, delay);
91}
92
93static void mv_otg_timer_await_bcon(unsigned long data)
94{
95 struct mv_otg *mvotg = (struct mv_otg *) data;
96
97 mvotg->otg_ctrl.a_wait_bcon_timeout = 1;
98
99 dev_info(&mvotg->pdev->dev, "B Device No Response!\n");
100
101 if (spin_trylock(&mvotg->wq_lock)) {
102 mv_otg_run_state_machine(mvotg, 0);
103 spin_unlock(&mvotg->wq_lock);
104 }
105}
106
107static int mv_otg_cancel_timer(struct mv_otg *mvotg, unsigned int id)
108{
109 struct timer_list *timer;
110
111 if (id >= OTG_TIMER_NUM)
112 return -EINVAL;
113
114 timer = &mvotg->otg_ctrl.timer[id];
115
116 if (timer_pending(timer))
117 del_timer(timer);
118
119 return 0;
120}
121
122static int mv_otg_set_timer(struct mv_otg *mvotg, unsigned int id,
123 unsigned long interval,
124 void (*callback) (unsigned long))
125{
126 struct timer_list *timer;
127
128 if (id >= OTG_TIMER_NUM)
129 return -EINVAL;
130
131 timer = &mvotg->otg_ctrl.timer[id];
132 if (timer_pending(timer)) {
133 dev_err(&mvotg->pdev->dev, "Timer%d is already running\n", id);
134 return -EBUSY;
135 }
136
137 init_timer(timer);
138 timer->data = (unsigned long) mvotg;
139 timer->function = callback;
140 timer->expires = jiffies + interval;
141 add_timer(timer);
142
143 return 0;
144}
145
146static int mv_otg_reset(struct mv_otg *mvotg)
147{
148 unsigned int loops;
149 u32 tmp;
150
151 /* Stop the controller */
152 tmp = readl(&mvotg->op_regs->usbcmd);
153 tmp &= ~USBCMD_RUN_STOP;
154 writel(tmp, &mvotg->op_regs->usbcmd);
155
156 /* Reset the controller to get default values */
157 writel(USBCMD_CTRL_RESET, &mvotg->op_regs->usbcmd);
158
159 loops = 500;
160 while (readl(&mvotg->op_regs->usbcmd) & USBCMD_CTRL_RESET) {
161 if (loops == 0) {
162 dev_err(&mvotg->pdev->dev,
163 "Wait for RESET completed TIMEOUT\n");
164 return -ETIMEDOUT;
165 }
166 loops--;
167 udelay(20);
168 }
169
170 writel(0x0, &mvotg->op_regs->usbintr);
171 tmp = readl(&mvotg->op_regs->usbsts);
172 writel(tmp, &mvotg->op_regs->usbsts);
173
174 return 0;
175}
176
177static void mv_otg_init_irq(struct mv_otg *mvotg)
178{
179 u32 otgsc;
180
181 mvotg->irq_en = OTGSC_INTR_A_SESSION_VALID
182 | OTGSC_INTR_A_VBUS_VALID;
183 mvotg->irq_status = OTGSC_INTSTS_A_SESSION_VALID
184 | OTGSC_INTSTS_A_VBUS_VALID;
185
186 if (mvotg->pdata->vbus == NULL) {
187 mvotg->irq_en |= OTGSC_INTR_B_SESSION_VALID
188 | OTGSC_INTR_B_SESSION_END;
189 mvotg->irq_status |= OTGSC_INTSTS_B_SESSION_VALID
190 | OTGSC_INTSTS_B_SESSION_END;
191 }
192
193 if (mvotg->pdata->id == NULL) {
194 mvotg->irq_en |= OTGSC_INTR_USB_ID;
195 mvotg->irq_status |= OTGSC_INTSTS_USB_ID;
196 }
197
198 otgsc = readl(&mvotg->op_regs->otgsc);
199 otgsc |= mvotg->irq_en;
200 writel(otgsc, &mvotg->op_regs->otgsc);
201}
202
203static void mv_otg_start_host(struct mv_otg *mvotg, int on)
204{
205#ifdef CONFIG_USB
206 struct usb_otg *otg = mvotg->phy.otg;
207 struct usb_hcd *hcd;
208
209 if (!otg->host)
210 return;
211
212 dev_info(&mvotg->pdev->dev, "%s host\n", on ? "start" : "stop");
213
214 hcd = bus_to_hcd(otg->host);
215
216 if (on)
217 usb_add_hcd(hcd, hcd->irq, IRQF_SHARED);
218 else
219 usb_remove_hcd(hcd);
220#endif /* CONFIG_USB */
221}
222
223static void mv_otg_start_periphrals(struct mv_otg *mvotg, int on)
224{
225 struct usb_otg *otg = mvotg->phy.otg;
226
227 if (!otg->gadget)
228 return;
229
230 dev_info(mvotg->phy.dev, "gadget %s\n", on ? "on" : "off");
231
232 if (on)
233 usb_gadget_vbus_connect(otg->gadget);
234 else
235 usb_gadget_vbus_disconnect(otg->gadget);
236}
237
238static void otg_clock_enable(struct mv_otg *mvotg)
239{
240 clk_prepare_enable(mvotg->clk);
241}
242
243static void otg_clock_disable(struct mv_otg *mvotg)
244{
245 clk_disable_unprepare(mvotg->clk);
246}
247
248static int mv_otg_enable_internal(struct mv_otg *mvotg)
249{
250 int retval = 0;
251
252 if (mvotg->active)
253 return 0;
254
255 dev_dbg(&mvotg->pdev->dev, "otg enabled\n");
256
257 otg_clock_enable(mvotg);
258 if (mvotg->pdata->phy_init) {
259 retval = mvotg->pdata->phy_init(mvotg->phy_regs);
260 if (retval) {
261 dev_err(&mvotg->pdev->dev,
262 "init phy error %d\n", retval);
263 otg_clock_disable(mvotg);
264 return retval;
265 }
266 }
267 mvotg->active = 1;
268
269 return 0;
270
271}
272
273static int mv_otg_enable(struct mv_otg *mvotg)
274{
275 if (mvotg->clock_gating)
276 return mv_otg_enable_internal(mvotg);
277
278 return 0;
279}
280
281static void mv_otg_disable_internal(struct mv_otg *mvotg)
282{
283 if (mvotg->active) {
284 dev_dbg(&mvotg->pdev->dev, "otg disabled\n");
285 if (mvotg->pdata->phy_deinit)
286 mvotg->pdata->phy_deinit(mvotg->phy_regs);
287 otg_clock_disable(mvotg);
288 mvotg->active = 0;
289 }
290}
291
292static void mv_otg_disable(struct mv_otg *mvotg)
293{
294 if (mvotg->clock_gating)
295 mv_otg_disable_internal(mvotg);
296}
297
298static void mv_otg_update_inputs(struct mv_otg *mvotg)
299{
300 struct mv_otg_ctrl *otg_ctrl = &mvotg->otg_ctrl;
301 u32 otgsc;
302
303 otgsc = readl(&mvotg->op_regs->otgsc);
304
305 if (mvotg->pdata->vbus) {
306 if (mvotg->pdata->vbus->poll() == VBUS_HIGH) {
307 otg_ctrl->b_sess_vld = 1;
308 otg_ctrl->b_sess_end = 0;
309 } else {
310 otg_ctrl->b_sess_vld = 0;
311 otg_ctrl->b_sess_end = 1;
312 }
313 } else {
314 otg_ctrl->b_sess_vld = !!(otgsc & OTGSC_STS_B_SESSION_VALID);
315 otg_ctrl->b_sess_end = !!(otgsc & OTGSC_STS_B_SESSION_END);
316 }
317
318 if (mvotg->pdata->id)
319 otg_ctrl->id = !!mvotg->pdata->id->poll();
320 else
321 otg_ctrl->id = !!(otgsc & OTGSC_STS_USB_ID);
322
323 if (mvotg->pdata->otg_force_a_bus_req && !otg_ctrl->id)
324 otg_ctrl->a_bus_req = 1;
325
326 otg_ctrl->a_sess_vld = !!(otgsc & OTGSC_STS_A_SESSION_VALID);
327 otg_ctrl->a_vbus_vld = !!(otgsc & OTGSC_STS_A_VBUS_VALID);
328
329 dev_dbg(&mvotg->pdev->dev, "%s: ", __func__);
330 dev_dbg(&mvotg->pdev->dev, "id %d\n", otg_ctrl->id);
331 dev_dbg(&mvotg->pdev->dev, "b_sess_vld %d\n", otg_ctrl->b_sess_vld);
332 dev_dbg(&mvotg->pdev->dev, "b_sess_end %d\n", otg_ctrl->b_sess_end);
333 dev_dbg(&mvotg->pdev->dev, "a_vbus_vld %d\n", otg_ctrl->a_vbus_vld);
334 dev_dbg(&mvotg->pdev->dev, "a_sess_vld %d\n", otg_ctrl->a_sess_vld);
335}
336
337static void mv_otg_update_state(struct mv_otg *mvotg)
338{
339 struct mv_otg_ctrl *otg_ctrl = &mvotg->otg_ctrl;
340 struct usb_phy *phy = &mvotg->phy;
341 int old_state = phy->state;
342
343 switch (old_state) {
344 case OTG_STATE_UNDEFINED:
345 phy->state = OTG_STATE_B_IDLE;
346 /* FALL THROUGH */
347 case OTG_STATE_B_IDLE:
348 if (otg_ctrl->id == 0)
349 phy->state = OTG_STATE_A_IDLE;
350 else if (otg_ctrl->b_sess_vld)
351 phy->state = OTG_STATE_B_PERIPHERAL;
352 break;
353 case OTG_STATE_B_PERIPHERAL:
354 if (!otg_ctrl->b_sess_vld || otg_ctrl->id == 0)
355 phy->state = OTG_STATE_B_IDLE;
356 break;
357 case OTG_STATE_A_IDLE:
358 if (otg_ctrl->id)
359 phy->state = OTG_STATE_B_IDLE;
360 else if (!(otg_ctrl->a_bus_drop) &&
361 (otg_ctrl->a_bus_req || otg_ctrl->a_srp_det))
362 phy->state = OTG_STATE_A_WAIT_VRISE;
363 break;
364 case OTG_STATE_A_WAIT_VRISE:
365 if (otg_ctrl->a_vbus_vld)
366 phy->state = OTG_STATE_A_WAIT_BCON;
367 break;
368 case OTG_STATE_A_WAIT_BCON:
369 if (otg_ctrl->id || otg_ctrl->a_bus_drop
370 || otg_ctrl->a_wait_bcon_timeout) {
371 mv_otg_cancel_timer(mvotg, A_WAIT_BCON_TIMER);
372 mvotg->otg_ctrl.a_wait_bcon_timeout = 0;
373 phy->state = OTG_STATE_A_WAIT_VFALL;
374 otg_ctrl->a_bus_req = 0;
375 } else if (!otg_ctrl->a_vbus_vld) {
376 mv_otg_cancel_timer(mvotg, A_WAIT_BCON_TIMER);
377 mvotg->otg_ctrl.a_wait_bcon_timeout = 0;
378 phy->state = OTG_STATE_A_VBUS_ERR;
379 } else if (otg_ctrl->b_conn) {
380 mv_otg_cancel_timer(mvotg, A_WAIT_BCON_TIMER);
381 mvotg->otg_ctrl.a_wait_bcon_timeout = 0;
382 phy->state = OTG_STATE_A_HOST;
383 }
384 break;
385 case OTG_STATE_A_HOST:
386 if (otg_ctrl->id || !otg_ctrl->b_conn
387 || otg_ctrl->a_bus_drop)
388 phy->state = OTG_STATE_A_WAIT_BCON;
389 else if (!otg_ctrl->a_vbus_vld)
390 phy->state = OTG_STATE_A_VBUS_ERR;
391 break;
392 case OTG_STATE_A_WAIT_VFALL:
393 if (otg_ctrl->id
394 || (!otg_ctrl->b_conn && otg_ctrl->a_sess_vld)
395 || otg_ctrl->a_bus_req)
396 phy->state = OTG_STATE_A_IDLE;
397 break;
398 case OTG_STATE_A_VBUS_ERR:
399 if (otg_ctrl->id || otg_ctrl->a_clr_err
400 || otg_ctrl->a_bus_drop) {
401 otg_ctrl->a_clr_err = 0;
402 phy->state = OTG_STATE_A_WAIT_VFALL;
403 }
404 break;
405 default:
406 break;
407 }
408}
409
410static void mv_otg_work(struct work_struct *work)
411{
412 struct mv_otg *mvotg;
413 struct usb_phy *phy;
414 struct usb_otg *otg;
415 int old_state;
416
417 mvotg = container_of(to_delayed_work(work), struct mv_otg, work);
418
419run:
420 /* work queue is single thread, or we need spin_lock to protect */
421 phy = &mvotg->phy;
422 otg = phy->otg;
423 old_state = phy->state;
424
425 if (!mvotg->active)
426 return;
427
428 mv_otg_update_inputs(mvotg);
429 mv_otg_update_state(mvotg);
430
431 if (old_state != phy->state) {
432 dev_info(&mvotg->pdev->dev, "change from state %s to %s\n",
433 state_string[old_state],
434 state_string[phy->state]);
435
436 switch (phy->state) {
437 case OTG_STATE_B_IDLE:
438 otg->default_a = 0;
439 if (old_state == OTG_STATE_B_PERIPHERAL)
440 mv_otg_start_periphrals(mvotg, 0);
441 mv_otg_reset(mvotg);
442 mv_otg_disable(mvotg);
443 break;
444 case OTG_STATE_B_PERIPHERAL:
445 mv_otg_enable(mvotg);
446 mv_otg_start_periphrals(mvotg, 1);
447 break;
448 case OTG_STATE_A_IDLE:
449 otg->default_a = 1;
450 mv_otg_enable(mvotg);
451 if (old_state == OTG_STATE_A_WAIT_VFALL)
452 mv_otg_start_host(mvotg, 0);
453 mv_otg_reset(mvotg);
454 break;
455 case OTG_STATE_A_WAIT_VRISE:
456 mv_otg_set_vbus(otg, 1);
457 break;
458 case OTG_STATE_A_WAIT_BCON:
459 if (old_state != OTG_STATE_A_HOST)
460 mv_otg_start_host(mvotg, 1);
461 mv_otg_set_timer(mvotg, A_WAIT_BCON_TIMER,
462 T_A_WAIT_BCON,
463 mv_otg_timer_await_bcon);
464 /*
465 * Now, we directly enter A_HOST. So set b_conn = 1
466 * here. In fact, it need host driver to notify us.
467 */
468 mvotg->otg_ctrl.b_conn = 1;
469 break;
470 case OTG_STATE_A_HOST:
471 break;
472 case OTG_STATE_A_WAIT_VFALL:
473 /*
474 * Now, we has exited A_HOST. So set b_conn = 0
475 * here. In fact, it need host driver to notify us.
476 */
477 mvotg->otg_ctrl.b_conn = 0;
478 mv_otg_set_vbus(otg, 0);
479 break;
480 case OTG_STATE_A_VBUS_ERR:
481 break;
482 default:
483 break;
484 }
485 goto run;
486 }
487}
488
489static irqreturn_t mv_otg_irq(int irq, void *dev)
490{
491 struct mv_otg *mvotg = dev;
492 u32 otgsc;
493
494 otgsc = readl(&mvotg->op_regs->otgsc);
495 writel(otgsc, &mvotg->op_regs->otgsc);
496
497 /*
498 * if we have vbus, then the vbus detection for B-device
499 * will be done by mv_otg_inputs_irq().
500 */
501 if (mvotg->pdata->vbus)
502 if ((otgsc & OTGSC_STS_USB_ID) &&
503 !(otgsc & OTGSC_INTSTS_USB_ID))
504 return IRQ_NONE;
505
506 if ((otgsc & mvotg->irq_status) == 0)
507 return IRQ_NONE;
508
509 mv_otg_run_state_machine(mvotg, 0);
510
511 return IRQ_HANDLED;
512}
513
514static irqreturn_t mv_otg_inputs_irq(int irq, void *dev)
515{
516 struct mv_otg *mvotg = dev;
517
518 /* The clock may disabled at this time */
519 if (!mvotg->active) {
520 mv_otg_enable(mvotg);
521 mv_otg_init_irq(mvotg);
522 }
523
524 mv_otg_run_state_machine(mvotg, 0);
525
526 return IRQ_HANDLED;
527}
528
529static ssize_t
530get_a_bus_req(struct device *dev, struct device_attribute *attr, char *buf)
531{
532 struct mv_otg *mvotg = dev_get_drvdata(dev);
533 return scnprintf(buf, PAGE_SIZE, "%d\n",
534 mvotg->otg_ctrl.a_bus_req);
535}
536
537static ssize_t
538set_a_bus_req(struct device *dev, struct device_attribute *attr,
539 const char *buf, size_t count)
540{
541 struct mv_otg *mvotg = dev_get_drvdata(dev);
542
543 if (count > 2)
544 return -1;
545
546 /* We will use this interface to change to A device */
547 if (mvotg->phy.state != OTG_STATE_B_IDLE
548 && mvotg->phy.state != OTG_STATE_A_IDLE)
549 return -1;
550
551 /* The clock may disabled and we need to set irq for ID detected */
552 mv_otg_enable(mvotg);
553 mv_otg_init_irq(mvotg);
554
555 if (buf[0] == '1') {
556 mvotg->otg_ctrl.a_bus_req = 1;
557 mvotg->otg_ctrl.a_bus_drop = 0;
558 dev_dbg(&mvotg->pdev->dev,
559 "User request: a_bus_req = 1\n");
560
561 if (spin_trylock(&mvotg->wq_lock)) {
562 mv_otg_run_state_machine(mvotg, 0);
563 spin_unlock(&mvotg->wq_lock);
564 }
565 }
566
567 return count;
568}
569
570static DEVICE_ATTR(a_bus_req, S_IRUGO | S_IWUSR, get_a_bus_req,
571 set_a_bus_req);
572
573static ssize_t
574set_a_clr_err(struct device *dev, struct device_attribute *attr,
575 const char *buf, size_t count)
576{
577 struct mv_otg *mvotg = dev_get_drvdata(dev);
578 if (!mvotg->phy.otg->default_a)
579 return -1;
580
581 if (count > 2)
582 return -1;
583
584 if (buf[0] == '1') {
585 mvotg->otg_ctrl.a_clr_err = 1;
586 dev_dbg(&mvotg->pdev->dev,
587 "User request: a_clr_err = 1\n");
588 }
589
590 if (spin_trylock(&mvotg->wq_lock)) {
591 mv_otg_run_state_machine(mvotg, 0);
592 spin_unlock(&mvotg->wq_lock);
593 }
594
595 return count;
596}
597
598static DEVICE_ATTR(a_clr_err, S_IWUSR, NULL, set_a_clr_err);
599
600static ssize_t
601get_a_bus_drop(struct device *dev, struct device_attribute *attr,
602 char *buf)
603{
604 struct mv_otg *mvotg = dev_get_drvdata(dev);
605 return scnprintf(buf, PAGE_SIZE, "%d\n",
606 mvotg->otg_ctrl.a_bus_drop);
607}
608
609static ssize_t
610set_a_bus_drop(struct device *dev, struct device_attribute *attr,
611 const char *buf, size_t count)
612{
613 struct mv_otg *mvotg = dev_get_drvdata(dev);
614 if (!mvotg->phy.otg->default_a)
615 return -1;
616
617 if (count > 2)
618 return -1;
619
620 if (buf[0] == '0') {
621 mvotg->otg_ctrl.a_bus_drop = 0;
622 dev_dbg(&mvotg->pdev->dev,
623 "User request: a_bus_drop = 0\n");
624 } else if (buf[0] == '1') {
625 mvotg->otg_ctrl.a_bus_drop = 1;
626 mvotg->otg_ctrl.a_bus_req = 0;
627 dev_dbg(&mvotg->pdev->dev,
628 "User request: a_bus_drop = 1\n");
629 dev_dbg(&mvotg->pdev->dev,
630 "User request: and a_bus_req = 0\n");
631 }
632
633 if (spin_trylock(&mvotg->wq_lock)) {
634 mv_otg_run_state_machine(mvotg, 0);
635 spin_unlock(&mvotg->wq_lock);
636 }
637
638 return count;
639}
640
641static DEVICE_ATTR(a_bus_drop, S_IRUGO | S_IWUSR,
642 get_a_bus_drop, set_a_bus_drop);
643
644static struct attribute *inputs_attrs[] = {
645 &dev_attr_a_bus_req.attr,
646 &dev_attr_a_clr_err.attr,
647 &dev_attr_a_bus_drop.attr,
648 NULL,
649};
650
651static struct attribute_group inputs_attr_group = {
652 .name = "inputs",
653 .attrs = inputs_attrs,
654};
655
656int mv_otg_remove(struct platform_device *pdev)
657{
658 struct mv_otg *mvotg = platform_get_drvdata(pdev);
659
660 sysfs_remove_group(&mvotg->pdev->dev.kobj, &inputs_attr_group);
661
662 if (mvotg->qwork) {
663 flush_workqueue(mvotg->qwork);
664 destroy_workqueue(mvotg->qwork);
665 }
666
667 mv_otg_disable(mvotg);
668
669 usb_remove_phy(&mvotg->phy);
670 platform_set_drvdata(pdev, NULL);
671
672 return 0;
673}
674
675static int mv_otg_probe(struct platform_device *pdev)
676{
677 struct mv_usb_platform_data *pdata = pdev->dev.platform_data;
678 struct mv_otg *mvotg;
679 struct usb_otg *otg;
680 struct resource *r;
681 int retval = 0, i;
682
683 if (pdata == NULL) {
684 dev_err(&pdev->dev, "failed to get platform data\n");
685 return -ENODEV;
686 }
687
688 mvotg = devm_kzalloc(&pdev->dev, sizeof(*mvotg), GFP_KERNEL);
689 if (!mvotg) {
690 dev_err(&pdev->dev, "failed to allocate memory!\n");
691 return -ENOMEM;
692 }
693
694 otg = devm_kzalloc(&pdev->dev, sizeof(*otg), GFP_KERNEL);
695 if (!otg)
696 return -ENOMEM;
697
698 platform_set_drvdata(pdev, mvotg);
699
700 mvotg->pdev = pdev;
701 mvotg->pdata = pdata;
702
703 mvotg->clk = devm_clk_get(&pdev->dev, NULL);
704 if (IS_ERR(mvotg->clk))
705 return PTR_ERR(mvotg->clk);
706
707 mvotg->qwork = create_singlethread_workqueue("mv_otg_queue");
708 if (!mvotg->qwork) {
709 dev_dbg(&pdev->dev, "cannot create workqueue for OTG\n");
710 return -ENOMEM;
711 }
712
713 INIT_DELAYED_WORK(&mvotg->work, mv_otg_work);
714
715 /* OTG common part */
716 mvotg->pdev = pdev;
717 mvotg->phy.dev = &pdev->dev;
718 mvotg->phy.otg = otg;
719 mvotg->phy.label = driver_name;
720 mvotg->phy.state = OTG_STATE_UNDEFINED;
721
722 otg->phy = &mvotg->phy;
723 otg->set_host = mv_otg_set_host;
724 otg->set_peripheral = mv_otg_set_peripheral;
725 otg->set_vbus = mv_otg_set_vbus;
726
727 for (i = 0; i < OTG_TIMER_NUM; i++)
728 init_timer(&mvotg->otg_ctrl.timer[i]);
729
730 r = platform_get_resource_byname(mvotg->pdev,
731 IORESOURCE_MEM, "phyregs");
732 if (r == NULL) {
733 dev_err(&pdev->dev, "no phy I/O memory resource defined\n");
734 retval = -ENODEV;
735 goto err_destroy_workqueue;
736 }
737
738 mvotg->phy_regs = devm_ioremap(&pdev->dev, r->start, resource_size(r));
739 if (mvotg->phy_regs == NULL) {
740 dev_err(&pdev->dev, "failed to map phy I/O memory\n");
741 retval = -EFAULT;
742 goto err_destroy_workqueue;
743 }
744
745 r = platform_get_resource_byname(mvotg->pdev,
746 IORESOURCE_MEM, "capregs");
747 if (r == NULL) {
748 dev_err(&pdev->dev, "no I/O memory resource defined\n");
749 retval = -ENODEV;
750 goto err_destroy_workqueue;
751 }
752
753 mvotg->cap_regs = devm_ioremap(&pdev->dev, r->start, resource_size(r));
754 if (mvotg->cap_regs == NULL) {
755 dev_err(&pdev->dev, "failed to map I/O memory\n");
756 retval = -EFAULT;
757 goto err_destroy_workqueue;
758 }
759
760 /* we will acces controller register, so enable the udc controller */
761 retval = mv_otg_enable_internal(mvotg);
762 if (retval) {
763 dev_err(&pdev->dev, "mv otg enable error %d\n", retval);
764 goto err_destroy_workqueue;
765 }
766
767 mvotg->op_regs =
768 (struct mv_otg_regs __iomem *) ((unsigned long) mvotg->cap_regs
769 + (readl(mvotg->cap_regs) & CAPLENGTH_MASK));
770
771 if (pdata->id) {
772 retval = devm_request_threaded_irq(&pdev->dev, pdata->id->irq,
773 NULL, mv_otg_inputs_irq,
774 IRQF_ONESHOT, "id", mvotg);
775 if (retval) {
776 dev_info(&pdev->dev,
777 "Failed to request irq for ID\n");
778 pdata->id = NULL;
779 }
780 }
781
782 if (pdata->vbus) {
783 mvotg->clock_gating = 1;
784 retval = devm_request_threaded_irq(&pdev->dev, pdata->vbus->irq,
785 NULL, mv_otg_inputs_irq,
786 IRQF_ONESHOT, "vbus", mvotg);
787 if (retval) {
788 dev_info(&pdev->dev,
789 "Failed to request irq for VBUS, "
790 "disable clock gating\n");
791 mvotg->clock_gating = 0;
792 pdata->vbus = NULL;
793 }
794 }
795
796 if (pdata->disable_otg_clock_gating)
797 mvotg->clock_gating = 0;
798
799 mv_otg_reset(mvotg);
800 mv_otg_init_irq(mvotg);
801
802 r = platform_get_resource(mvotg->pdev, IORESOURCE_IRQ, 0);
803 if (r == NULL) {
804 dev_err(&pdev->dev, "no IRQ resource defined\n");
805 retval = -ENODEV;
806 goto err_disable_clk;
807 }
808
809 mvotg->irq = r->start;
810 if (devm_request_irq(&pdev->dev, mvotg->irq, mv_otg_irq, IRQF_SHARED,
811 driver_name, mvotg)) {
812 dev_err(&pdev->dev, "Request irq %d for OTG failed\n",
813 mvotg->irq);
814 mvotg->irq = 0;
815 retval = -ENODEV;
816 goto err_disable_clk;
817 }
818
819 retval = usb_add_phy(&mvotg->phy, USB_PHY_TYPE_USB2);
820 if (retval < 0) {
821 dev_err(&pdev->dev, "can't register transceiver, %d\n",
822 retval);
823 goto err_disable_clk;
824 }
825
826 retval = sysfs_create_group(&pdev->dev.kobj, &inputs_attr_group);
827 if (retval < 0) {
828 dev_dbg(&pdev->dev,
829 "Can't register sysfs attr group: %d\n", retval);
830 goto err_remove_phy;
831 }
832
833 spin_lock_init(&mvotg->wq_lock);
834 if (spin_trylock(&mvotg->wq_lock)) {
835 mv_otg_run_state_machine(mvotg, 2 * HZ);
836 spin_unlock(&mvotg->wq_lock);
837 }
838
839 dev_info(&pdev->dev,
840 "successful probe OTG device %s clock gating.\n",
841 mvotg->clock_gating ? "with" : "without");
842
843 return 0;
844
845err_remove_phy:
846 usb_remove_phy(&mvotg->phy);
847err_disable_clk:
848 mv_otg_disable_internal(mvotg);
849err_destroy_workqueue:
850 flush_workqueue(mvotg->qwork);
851 destroy_workqueue(mvotg->qwork);
852
853 platform_set_drvdata(pdev, NULL);
854
855 return retval;
856}
857
858#ifdef CONFIG_PM
859static int mv_otg_suspend(struct platform_device *pdev, pm_message_t state)
860{
861 struct mv_otg *mvotg = platform_get_drvdata(pdev);
862
863 if (mvotg->phy.state != OTG_STATE_B_IDLE) {
864 dev_info(&pdev->dev,
865 "OTG state is not B_IDLE, it is %d!\n",
866 mvotg->phy.state);
867 return -EAGAIN;
868 }
869
870 if (!mvotg->clock_gating)
871 mv_otg_disable_internal(mvotg);
872
873 return 0;
874}
875
876static int mv_otg_resume(struct platform_device *pdev)
877{
878 struct mv_otg *mvotg = platform_get_drvdata(pdev);
879 u32 otgsc;
880
881 if (!mvotg->clock_gating) {
882 mv_otg_enable_internal(mvotg);
883
884 otgsc = readl(&mvotg->op_regs->otgsc);
885 otgsc |= mvotg->irq_en;
886 writel(otgsc, &mvotg->op_regs->otgsc);
887
888 if (spin_trylock(&mvotg->wq_lock)) {
889 mv_otg_run_state_machine(mvotg, 0);
890 spin_unlock(&mvotg->wq_lock);
891 }
892 }
893 return 0;
894}
895#endif
896
897static struct platform_driver mv_otg_driver = {
898 .probe = mv_otg_probe,
899 .remove = __exit_p(mv_otg_remove),
900 .driver = {
901 .owner = THIS_MODULE,
902 .name = driver_name,
903 },
904#ifdef CONFIG_PM
905 .suspend = mv_otg_suspend,
906 .resume = mv_otg_resume,
907#endif
908};
909module_platform_driver(mv_otg_driver);
diff --git a/drivers/usb/phy/phy-mv-usb.h b/drivers/usb/phy/phy-mv-usb.h
new file mode 100644
index 000000000000..551da6eb0ba8
--- /dev/null
+++ b/drivers/usb/phy/phy-mv-usb.h
@@ -0,0 +1,164 @@
1/*
2 * Copyright (C) 2011 Marvell International Ltd. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
8 */
9
10#ifndef __MV_USB_OTG_CONTROLLER__
11#define __MV_USB_OTG_CONTROLLER__
12
13#include <linux/types.h>
14
15/* Command Register Bit Masks */
16#define USBCMD_RUN_STOP (0x00000001)
17#define USBCMD_CTRL_RESET (0x00000002)
18
19/* otgsc Register Bit Masks */
20#define OTGSC_CTRL_VUSB_DISCHARGE 0x00000001
21#define OTGSC_CTRL_VUSB_CHARGE 0x00000002
22#define OTGSC_CTRL_OTG_TERM 0x00000008
23#define OTGSC_CTRL_DATA_PULSING 0x00000010
24#define OTGSC_STS_USB_ID 0x00000100
25#define OTGSC_STS_A_VBUS_VALID 0x00000200
26#define OTGSC_STS_A_SESSION_VALID 0x00000400
27#define OTGSC_STS_B_SESSION_VALID 0x00000800
28#define OTGSC_STS_B_SESSION_END 0x00001000
29#define OTGSC_STS_1MS_TOGGLE 0x00002000
30#define OTGSC_STS_DATA_PULSING 0x00004000
31#define OTGSC_INTSTS_USB_ID 0x00010000
32#define OTGSC_INTSTS_A_VBUS_VALID 0x00020000
33#define OTGSC_INTSTS_A_SESSION_VALID 0x00040000
34#define OTGSC_INTSTS_B_SESSION_VALID 0x00080000
35#define OTGSC_INTSTS_B_SESSION_END 0x00100000
36#define OTGSC_INTSTS_1MS 0x00200000
37#define OTGSC_INTSTS_DATA_PULSING 0x00400000
38#define OTGSC_INTR_USB_ID 0x01000000
39#define OTGSC_INTR_A_VBUS_VALID 0x02000000
40#define OTGSC_INTR_A_SESSION_VALID 0x04000000
41#define OTGSC_INTR_B_SESSION_VALID 0x08000000
42#define OTGSC_INTR_B_SESSION_END 0x10000000
43#define OTGSC_INTR_1MS_TIMER 0x20000000
44#define OTGSC_INTR_DATA_PULSING 0x40000000
45
46#define CAPLENGTH_MASK (0xff)
47
48/* Timer's interval, unit 10ms */
49#define T_A_WAIT_VRISE 100
50#define T_A_WAIT_BCON 2000
51#define T_A_AIDL_BDIS 100
52#define T_A_BIDL_ADIS 20
53#define T_B_ASE0_BRST 400
54#define T_B_SE0_SRP 300
55#define T_B_SRP_FAIL 2000
56#define T_B_DATA_PLS 10
57#define T_B_SRP_INIT 100
58#define T_A_SRP_RSPNS 10
59#define T_A_DRV_RSM 5
60
61enum otg_function {
62 OTG_B_DEVICE = 0,
63 OTG_A_DEVICE
64};
65
66enum mv_otg_timer {
67 A_WAIT_BCON_TIMER = 0,
68 OTG_TIMER_NUM
69};
70
71/* PXA OTG state machine */
72struct mv_otg_ctrl {
73 /* internal variables */
74 u8 a_set_b_hnp_en; /* A-Device set b_hnp_en */
75 u8 b_srp_done;
76 u8 b_hnp_en;
77
78 /* OTG inputs */
79 u8 a_bus_drop;
80 u8 a_bus_req;
81 u8 a_clr_err;
82 u8 a_bus_resume;
83 u8 a_bus_suspend;
84 u8 a_conn;
85 u8 a_sess_vld;
86 u8 a_srp_det;
87 u8 a_vbus_vld;
88 u8 b_bus_req; /* B-Device Require Bus */
89 u8 b_bus_resume;
90 u8 b_bus_suspend;
91 u8 b_conn;
92 u8 b_se0_srp;
93 u8 b_sess_end;
94 u8 b_sess_vld;
95 u8 id;
96 u8 a_suspend_req;
97
98 /*Timer event */
99 u8 a_aidl_bdis_timeout;
100 u8 b_ase0_brst_timeout;
101 u8 a_bidl_adis_timeout;
102 u8 a_wait_bcon_timeout;
103
104 struct timer_list timer[OTG_TIMER_NUM];
105};
106
107#define VUSBHS_MAX_PORTS 8
108
109struct mv_otg_regs {
110 u32 usbcmd; /* Command register */
111 u32 usbsts; /* Status register */
112 u32 usbintr; /* Interrupt enable */
113 u32 frindex; /* Frame index */
114 u32 reserved1[1];
115 u32 deviceaddr; /* Device Address */
116 u32 eplistaddr; /* Endpoint List Address */
117 u32 ttctrl; /* HOST TT status and control */
118 u32 burstsize; /* Programmable Burst Size */
119 u32 txfilltuning; /* Host Transmit Pre-Buffer Packet Tuning */
120 u32 reserved[4];
121 u32 epnak; /* Endpoint NAK */
122 u32 epnaken; /* Endpoint NAK Enable */
123 u32 configflag; /* Configured Flag register */
124 u32 portsc[VUSBHS_MAX_PORTS]; /* Port Status/Control x, x = 1..8 */
125 u32 otgsc;
126 u32 usbmode; /* USB Host/Device mode */
127 u32 epsetupstat; /* Endpoint Setup Status */
128 u32 epprime; /* Endpoint Initialize */
129 u32 epflush; /* Endpoint De-initialize */
130 u32 epstatus; /* Endpoint Status */
131 u32 epcomplete; /* Endpoint Interrupt On Complete */
132 u32 epctrlx[16]; /* Endpoint Control, where x = 0.. 15 */
133 u32 mcr; /* Mux Control */
134 u32 isr; /* Interrupt Status */
135 u32 ier; /* Interrupt Enable */
136};
137
138struct mv_otg {
139 struct usb_phy phy;
140 struct mv_otg_ctrl otg_ctrl;
141
142 /* base address */
143 void __iomem *phy_regs;
144 void __iomem *cap_regs;
145 struct mv_otg_regs __iomem *op_regs;
146
147 struct platform_device *pdev;
148 int irq;
149 u32 irq_status;
150 u32 irq_en;
151
152 struct delayed_work work;
153 struct workqueue_struct *qwork;
154
155 spinlock_t wq_lock;
156
157 struct mv_usb_platform_data *pdata;
158
159 unsigned int active;
160 unsigned int clock_gating;
161 struct clk *clk;
162};
163
164#endif
diff --git a/drivers/usb/phy/phy-mxs-usb.c b/drivers/usb/phy/phy-mxs-usb.c
new file mode 100644
index 000000000000..9d4381e64d51
--- /dev/null
+++ b/drivers/usb/phy/phy-mxs-usb.c
@@ -0,0 +1,220 @@
1/*
2 * Copyright 2012 Freescale Semiconductor, Inc.
3 * Copyright (C) 2012 Marek Vasut <marex@denx.de>
4 * on behalf of DENX Software Engineering GmbH
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14#include <linux/module.h>
15#include <linux/kernel.h>
16#include <linux/platform_device.h>
17#include <linux/clk.h>
18#include <linux/usb/otg.h>
19#include <linux/stmp_device.h>
20#include <linux/delay.h>
21#include <linux/err.h>
22#include <linux/io.h>
23
24#define DRIVER_NAME "mxs_phy"
25
26#define HW_USBPHY_PWD 0x00
27#define HW_USBPHY_CTRL 0x30
28#define HW_USBPHY_CTRL_SET 0x34
29#define HW_USBPHY_CTRL_CLR 0x38
30
31#define BM_USBPHY_CTRL_SFTRST BIT(31)
32#define BM_USBPHY_CTRL_CLKGATE BIT(30)
33#define BM_USBPHY_CTRL_ENUTMILEVEL3 BIT(15)
34#define BM_USBPHY_CTRL_ENUTMILEVEL2 BIT(14)
35#define BM_USBPHY_CTRL_ENHOSTDISCONDETECT BIT(1)
36
37struct mxs_phy {
38 struct usb_phy phy;
39 struct clk *clk;
40};
41
42#define to_mxs_phy(p) container_of((p), struct mxs_phy, phy)
43
44static void mxs_phy_hw_init(struct mxs_phy *mxs_phy)
45{
46 void __iomem *base = mxs_phy->phy.io_priv;
47
48 stmp_reset_block(base + HW_USBPHY_CTRL);
49
50 /* Power up the PHY */
51 writel(0, base + HW_USBPHY_PWD);
52
53 /* enable FS/LS device */
54 writel(BM_USBPHY_CTRL_ENUTMILEVEL2 |
55 BM_USBPHY_CTRL_ENUTMILEVEL3,
56 base + HW_USBPHY_CTRL_SET);
57}
58
59static int mxs_phy_init(struct usb_phy *phy)
60{
61 struct mxs_phy *mxs_phy = to_mxs_phy(phy);
62
63 clk_prepare_enable(mxs_phy->clk);
64 mxs_phy_hw_init(mxs_phy);
65
66 return 0;
67}
68
69static void mxs_phy_shutdown(struct usb_phy *phy)
70{
71 struct mxs_phy *mxs_phy = to_mxs_phy(phy);
72
73 writel(BM_USBPHY_CTRL_CLKGATE,
74 phy->io_priv + HW_USBPHY_CTRL_SET);
75
76 clk_disable_unprepare(mxs_phy->clk);
77}
78
79static int mxs_phy_suspend(struct usb_phy *x, int suspend)
80{
81 struct mxs_phy *mxs_phy = to_mxs_phy(x);
82
83 if (suspend) {
84 writel(0xffffffff, x->io_priv + HW_USBPHY_PWD);
85 writel(BM_USBPHY_CTRL_CLKGATE,
86 x->io_priv + HW_USBPHY_CTRL_SET);
87 clk_disable_unprepare(mxs_phy->clk);
88 } else {
89 clk_prepare_enable(mxs_phy->clk);
90 writel(BM_USBPHY_CTRL_CLKGATE,
91 x->io_priv + HW_USBPHY_CTRL_CLR);
92 writel(0, x->io_priv + HW_USBPHY_PWD);
93 }
94
95 return 0;
96}
97
98static int mxs_phy_on_connect(struct usb_phy *phy,
99 enum usb_device_speed speed)
100{
101 dev_dbg(phy->dev, "%s speed device has connected\n",
102 (speed == USB_SPEED_HIGH) ? "high" : "non-high");
103
104 if (speed == USB_SPEED_HIGH)
105 writel(BM_USBPHY_CTRL_ENHOSTDISCONDETECT,
106 phy->io_priv + HW_USBPHY_CTRL_SET);
107
108 return 0;
109}
110
111static int mxs_phy_on_disconnect(struct usb_phy *phy,
112 enum usb_device_speed speed)
113{
114 dev_dbg(phy->dev, "%s speed device has disconnected\n",
115 (speed == USB_SPEED_HIGH) ? "high" : "non-high");
116
117 if (speed == USB_SPEED_HIGH)
118 writel(BM_USBPHY_CTRL_ENHOSTDISCONDETECT,
119 phy->io_priv + HW_USBPHY_CTRL_CLR);
120
121 return 0;
122}
123
124static int mxs_phy_probe(struct platform_device *pdev)
125{
126 struct resource *res;
127 void __iomem *base;
128 struct clk *clk;
129 struct mxs_phy *mxs_phy;
130 int ret;
131
132 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
133 if (!res) {
134 dev_err(&pdev->dev, "can't get device resources\n");
135 return -ENOENT;
136 }
137
138 base = devm_ioremap_resource(&pdev->dev, res);
139 if (IS_ERR(base))
140 return PTR_ERR(base);
141
142 clk = devm_clk_get(&pdev->dev, NULL);
143 if (IS_ERR(clk)) {
144 dev_err(&pdev->dev,
145 "can't get the clock, err=%ld", PTR_ERR(clk));
146 return PTR_ERR(clk);
147 }
148
149 mxs_phy = devm_kzalloc(&pdev->dev, sizeof(*mxs_phy), GFP_KERNEL);
150 if (!mxs_phy) {
151 dev_err(&pdev->dev, "Failed to allocate USB PHY structure!\n");
152 return -ENOMEM;
153 }
154
155 mxs_phy->phy.io_priv = base;
156 mxs_phy->phy.dev = &pdev->dev;
157 mxs_phy->phy.label = DRIVER_NAME;
158 mxs_phy->phy.init = mxs_phy_init;
159 mxs_phy->phy.shutdown = mxs_phy_shutdown;
160 mxs_phy->phy.set_suspend = mxs_phy_suspend;
161 mxs_phy->phy.notify_connect = mxs_phy_on_connect;
162 mxs_phy->phy.notify_disconnect = mxs_phy_on_disconnect;
163
164 ATOMIC_INIT_NOTIFIER_HEAD(&mxs_phy->phy.notifier);
165
166 mxs_phy->clk = clk;
167
168 platform_set_drvdata(pdev, &mxs_phy->phy);
169
170 ret = usb_add_phy_dev(&mxs_phy->phy);
171 if (ret)
172 return ret;
173
174 return 0;
175}
176
177static int mxs_phy_remove(struct platform_device *pdev)
178{
179 struct mxs_phy *mxs_phy = platform_get_drvdata(pdev);
180
181 usb_remove_phy(&mxs_phy->phy);
182
183 platform_set_drvdata(pdev, NULL);
184
185 return 0;
186}
187
188static const struct of_device_id mxs_phy_dt_ids[] = {
189 { .compatible = "fsl,imx23-usbphy", },
190 { /* sentinel */ }
191};
192MODULE_DEVICE_TABLE(of, mxs_phy_dt_ids);
193
194static struct platform_driver mxs_phy_driver = {
195 .probe = mxs_phy_probe,
196 .remove = mxs_phy_remove,
197 .driver = {
198 .name = DRIVER_NAME,
199 .owner = THIS_MODULE,
200 .of_match_table = mxs_phy_dt_ids,
201 },
202};
203
204static int __init mxs_phy_module_init(void)
205{
206 return platform_driver_register(&mxs_phy_driver);
207}
208postcore_initcall(mxs_phy_module_init);
209
210static void __exit mxs_phy_module_exit(void)
211{
212 platform_driver_unregister(&mxs_phy_driver);
213}
214module_exit(mxs_phy_module_exit);
215
216MODULE_ALIAS("platform:mxs-usb-phy");
217MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
218MODULE_AUTHOR("Richard Zhao <richard.zhao@freescale.com>");
219MODULE_DESCRIPTION("Freescale MXS USB PHY driver");
220MODULE_LICENSE("GPL");
diff --git a/drivers/usb/phy/phy-nop.c b/drivers/usb/phy/phy-nop.c
new file mode 100644
index 000000000000..2b10cc969bbb
--- /dev/null
+++ b/drivers/usb/phy/phy-nop.c
@@ -0,0 +1,294 @@
1/*
2 * drivers/usb/otg/nop-usb-xceiv.c
3 *
4 * NOP USB transceiver for all USB transceiver which are either built-in
5 * into USB IP or which are mostly autonomous.
6 *
7 * Copyright (C) 2009 Texas Instruments Inc
8 * Author: Ajay Kumar Gupta <ajay.gupta@ti.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 *
24 * Current status:
25 * This provides a "nop" transceiver for PHYs which are
26 * autonomous such as isp1504, isp1707, etc.
27 */
28
29#include <linux/module.h>
30#include <linux/platform_device.h>
31#include <linux/dma-mapping.h>
32#include <linux/usb/otg.h>
33#include <linux/usb/nop-usb-xceiv.h>
34#include <linux/slab.h>
35#include <linux/clk.h>
36#include <linux/regulator/consumer.h>
37#include <linux/of.h>
38
39struct nop_usb_xceiv {
40 struct usb_phy phy;
41 struct device *dev;
42 struct clk *clk;
43 struct regulator *vcc;
44 struct regulator *reset;
45};
46
47static struct platform_device *pd;
48
49void usb_nop_xceiv_register(void)
50{
51 if (pd)
52 return;
53 pd = platform_device_register_simple("nop_usb_xceiv", -1, NULL, 0);
54 if (!pd) {
55 printk(KERN_ERR "Unable to register usb nop transceiver\n");
56 return;
57 }
58}
59EXPORT_SYMBOL(usb_nop_xceiv_register);
60
61void usb_nop_xceiv_unregister(void)
62{
63 platform_device_unregister(pd);
64 pd = NULL;
65}
66EXPORT_SYMBOL(usb_nop_xceiv_unregister);
67
68static int nop_set_suspend(struct usb_phy *x, int suspend)
69{
70 return 0;
71}
72
73static int nop_init(struct usb_phy *phy)
74{
75 struct nop_usb_xceiv *nop = dev_get_drvdata(phy->dev);
76
77 if (!IS_ERR(nop->vcc)) {
78 if (regulator_enable(nop->vcc))
79 dev_err(phy->dev, "Failed to enable power\n");
80 }
81
82 if (!IS_ERR(nop->clk))
83 clk_enable(nop->clk);
84
85 if (!IS_ERR(nop->reset)) {
86 /* De-assert RESET */
87 if (regulator_enable(nop->reset))
88 dev_err(phy->dev, "Failed to de-assert reset\n");
89 }
90
91 return 0;
92}
93
94static void nop_shutdown(struct usb_phy *phy)
95{
96 struct nop_usb_xceiv *nop = dev_get_drvdata(phy->dev);
97
98 if (!IS_ERR(nop->reset)) {
99 /* Assert RESET */
100 if (regulator_disable(nop->reset))
101 dev_err(phy->dev, "Failed to assert reset\n");
102 }
103
104 if (!IS_ERR(nop->clk))
105 clk_disable(nop->clk);
106
107 if (!IS_ERR(nop->vcc)) {
108 if (regulator_disable(nop->vcc))
109 dev_err(phy->dev, "Failed to disable power\n");
110 }
111}
112
113static int nop_set_peripheral(struct usb_otg *otg, struct usb_gadget *gadget)
114{
115 if (!otg)
116 return -ENODEV;
117
118 if (!gadget) {
119 otg->gadget = NULL;
120 return -ENODEV;
121 }
122
123 otg->gadget = gadget;
124 otg->phy->state = OTG_STATE_B_IDLE;
125 return 0;
126}
127
128static int nop_set_host(struct usb_otg *otg, struct usb_bus *host)
129{
130 if (!otg)
131 return -ENODEV;
132
133 if (!host) {
134 otg->host = NULL;
135 return -ENODEV;
136 }
137
138 otg->host = host;
139 return 0;
140}
141
142static int nop_usb_xceiv_probe(struct platform_device *pdev)
143{
144 struct device *dev = &pdev->dev;
145 struct nop_usb_xceiv_platform_data *pdata = pdev->dev.platform_data;
146 struct nop_usb_xceiv *nop;
147 enum usb_phy_type type = USB_PHY_TYPE_USB2;
148 int err;
149 u32 clk_rate = 0;
150 bool needs_vcc = false;
151 bool needs_reset = false;
152
153 nop = devm_kzalloc(&pdev->dev, sizeof(*nop), GFP_KERNEL);
154 if (!nop)
155 return -ENOMEM;
156
157 nop->phy.otg = devm_kzalloc(&pdev->dev, sizeof(*nop->phy.otg),
158 GFP_KERNEL);
159 if (!nop->phy.otg)
160 return -ENOMEM;
161
162 if (dev->of_node) {
163 struct device_node *node = dev->of_node;
164
165 if (of_property_read_u32(node, "clock-frequency", &clk_rate))
166 clk_rate = 0;
167
168 needs_vcc = of_property_read_bool(node, "vcc-supply");
169 needs_reset = of_property_read_bool(node, "reset-supply");
170
171 } else if (pdata) {
172 type = pdata->type;
173 clk_rate = pdata->clk_rate;
174 needs_vcc = pdata->needs_vcc;
175 needs_reset = pdata->needs_reset;
176 }
177
178 nop->clk = devm_clk_get(&pdev->dev, "main_clk");
179 if (IS_ERR(nop->clk)) {
180 dev_dbg(&pdev->dev, "Can't get phy clock: %ld\n",
181 PTR_ERR(nop->clk));
182 }
183
184 if (!IS_ERR(nop->clk) && clk_rate) {
185 err = clk_set_rate(nop->clk, clk_rate);
186 if (err) {
187 dev_err(&pdev->dev, "Error setting clock rate\n");
188 return err;
189 }
190 }
191
192 if (!IS_ERR(nop->clk)) {
193 err = clk_prepare(nop->clk);
194 if (err) {
195 dev_err(&pdev->dev, "Error preparing clock\n");
196 return err;
197 }
198 }
199
200 nop->vcc = devm_regulator_get(&pdev->dev, "vcc");
201 if (IS_ERR(nop->vcc)) {
202 dev_dbg(&pdev->dev, "Error getting vcc regulator: %ld\n",
203 PTR_ERR(nop->vcc));
204 if (needs_vcc)
205 return -EPROBE_DEFER;
206 }
207
208 nop->reset = devm_regulator_get(&pdev->dev, "reset");
209 if (IS_ERR(nop->reset)) {
210 dev_dbg(&pdev->dev, "Error getting reset regulator: %ld\n",
211 PTR_ERR(nop->reset));
212 if (needs_reset)
213 return -EPROBE_DEFER;
214 }
215
216 nop->dev = &pdev->dev;
217 nop->phy.dev = nop->dev;
218 nop->phy.label = "nop-xceiv";
219 nop->phy.set_suspend = nop_set_suspend;
220 nop->phy.init = nop_init;
221 nop->phy.shutdown = nop_shutdown;
222 nop->phy.state = OTG_STATE_UNDEFINED;
223 nop->phy.type = type;
224
225 nop->phy.otg->phy = &nop->phy;
226 nop->phy.otg->set_host = nop_set_host;
227 nop->phy.otg->set_peripheral = nop_set_peripheral;
228
229 err = usb_add_phy_dev(&nop->phy);
230 if (err) {
231 dev_err(&pdev->dev, "can't register transceiver, err: %d\n",
232 err);
233 goto err_add;
234 }
235
236 platform_set_drvdata(pdev, nop);
237
238 ATOMIC_INIT_NOTIFIER_HEAD(&nop->phy.notifier);
239
240 return 0;
241
242err_add:
243 if (!IS_ERR(nop->clk))
244 clk_unprepare(nop->clk);
245 return err;
246}
247
248static int nop_usb_xceiv_remove(struct platform_device *pdev)
249{
250 struct nop_usb_xceiv *nop = platform_get_drvdata(pdev);
251
252 if (!IS_ERR(nop->clk))
253 clk_unprepare(nop->clk);
254
255 usb_remove_phy(&nop->phy);
256
257 platform_set_drvdata(pdev, NULL);
258
259 return 0;
260}
261
262static const struct of_device_id nop_xceiv_dt_ids[] = {
263 { .compatible = "usb-nop-xceiv" },
264 { }
265};
266
267MODULE_DEVICE_TABLE(of, nop_xceiv_dt_ids);
268
269static struct platform_driver nop_usb_xceiv_driver = {
270 .probe = nop_usb_xceiv_probe,
271 .remove = nop_usb_xceiv_remove,
272 .driver = {
273 .name = "nop_usb_xceiv",
274 .owner = THIS_MODULE,
275 .of_match_table = of_match_ptr(nop_xceiv_dt_ids),
276 },
277};
278
279static int __init nop_usb_xceiv_init(void)
280{
281 return platform_driver_register(&nop_usb_xceiv_driver);
282}
283subsys_initcall(nop_usb_xceiv_init);
284
285static void __exit nop_usb_xceiv_exit(void)
286{
287 platform_driver_unregister(&nop_usb_xceiv_driver);
288}
289module_exit(nop_usb_xceiv_exit);
290
291MODULE_ALIAS("platform:nop_usb_xceiv");
292MODULE_AUTHOR("Texas Instruments Inc");
293MODULE_DESCRIPTION("NOP USB Transceiver driver");
294MODULE_LICENSE("GPL");
diff --git a/drivers/usb/phy/omap-control-usb.c b/drivers/usb/phy/phy-omap-control.c
index 1419ceda9759..1419ceda9759 100644
--- a/drivers/usb/phy/omap-control-usb.c
+++ b/drivers/usb/phy/phy-omap-control.c
diff --git a/drivers/usb/phy/omap-usb2.c b/drivers/usb/phy/phy-omap-usb2.c
index 844ab68f08d0..844ab68f08d0 100644
--- a/drivers/usb/phy/omap-usb2.c
+++ b/drivers/usb/phy/phy-omap-usb2.c
diff --git a/drivers/usb/phy/omap-usb3.c b/drivers/usb/phy/phy-omap-usb3.c
index a6e60b1e102e..a6e60b1e102e 100644
--- a/drivers/usb/phy/omap-usb3.c
+++ b/drivers/usb/phy/phy-omap-usb3.c
diff --git a/drivers/usb/phy/rcar-phy.c b/drivers/usb/phy/phy-rcar-usb.c
index a35681b0c501..a35681b0c501 100644
--- a/drivers/usb/phy/rcar-phy.c
+++ b/drivers/usb/phy/phy-rcar-usb.c
diff --git a/drivers/usb/phy/phy-samsung-usb.c b/drivers/usb/phy/phy-samsung-usb.c
new file mode 100644
index 000000000000..7b118ee5f5e4
--- /dev/null
+++ b/drivers/usb/phy/phy-samsung-usb.c
@@ -0,0 +1,236 @@
1/* linux/drivers/usb/phy/phy-samsung-usb.c
2 *
3 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * Author: Praveen Paneri <p.paneri@samsung.com>
7 *
8 * Samsung USB-PHY helper driver with common function calls;
9 * interacts with Samsung USB 2.0 PHY controller driver and later
10 * with Samsung USB 3.0 PHY driver.
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 */
21
22#include <linux/module.h>
23#include <linux/platform_device.h>
24#include <linux/clk.h>
25#include <linux/device.h>
26#include <linux/err.h>
27#include <linux/io.h>
28#include <linux/of.h>
29#include <linux/of_address.h>
30#include <linux/usb/samsung_usb_phy.h>
31
32#include "phy-samsung-usb.h"
33
34int samsung_usbphy_parse_dt(struct samsung_usbphy *sphy)
35{
36 struct device_node *usbphy_sys;
37
38 /* Getting node for system controller interface for usb-phy */
39 usbphy_sys = of_get_child_by_name(sphy->dev->of_node, "usbphy-sys");
40 if (!usbphy_sys) {
41 dev_err(sphy->dev, "No sys-controller interface for usb-phy\n");
42 return -ENODEV;
43 }
44
45 sphy->pmuregs = of_iomap(usbphy_sys, 0);
46
47 if (sphy->pmuregs == NULL) {
48 dev_err(sphy->dev, "Can't get usb-phy pmu control register\n");
49 goto err0;
50 }
51
52 sphy->sysreg = of_iomap(usbphy_sys, 1);
53
54 /*
55 * Not returning error code here, since this situation is not fatal.
56 * Few SoCs may not have this switch available
57 */
58 if (sphy->sysreg == NULL)
59 dev_warn(sphy->dev, "Can't get usb-phy sysreg cfg register\n");
60
61 of_node_put(usbphy_sys);
62
63 return 0;
64
65err0:
66 of_node_put(usbphy_sys);
67 return -ENXIO;
68}
69EXPORT_SYMBOL_GPL(samsung_usbphy_parse_dt);
70
71/*
72 * Set isolation here for phy.
73 * Here 'on = true' would mean USB PHY block is isolated, hence
74 * de-activated and vice-versa.
75 */
76void samsung_usbphy_set_isolation(struct samsung_usbphy *sphy, bool on)
77{
78 void __iomem *reg = NULL;
79 u32 reg_val;
80 u32 en_mask = 0;
81
82 if (!sphy->pmuregs) {
83 dev_warn(sphy->dev, "Can't set pmu isolation\n");
84 return;
85 }
86
87 switch (sphy->drv_data->cpu_type) {
88 case TYPE_S3C64XX:
89 /*
90 * Do nothing: We will add here once S3C64xx goes for DT support
91 */
92 break;
93 case TYPE_EXYNOS4210:
94 /*
95 * Fall through since exynos4210 and exynos5250 have similar
96 * register architecture: two separate registers for host and
97 * device phy control with enable bit at position 0.
98 */
99 case TYPE_EXYNOS5250:
100 if (sphy->phy_type == USB_PHY_TYPE_DEVICE) {
101 reg = sphy->pmuregs +
102 sphy->drv_data->devphy_reg_offset;
103 en_mask = sphy->drv_data->devphy_en_mask;
104 } else if (sphy->phy_type == USB_PHY_TYPE_HOST) {
105 reg = sphy->pmuregs +
106 sphy->drv_data->hostphy_reg_offset;
107 en_mask = sphy->drv_data->hostphy_en_mask;
108 }
109 break;
110 default:
111 dev_err(sphy->dev, "Invalid SoC type\n");
112 return;
113 }
114
115 reg_val = readl(reg);
116
117 if (on)
118 reg_val &= ~en_mask;
119 else
120 reg_val |= en_mask;
121
122 writel(reg_val, reg);
123}
124EXPORT_SYMBOL_GPL(samsung_usbphy_set_isolation);
125
126/*
127 * Configure the mode of working of usb-phy here: HOST/DEVICE.
128 */
129void samsung_usbphy_cfg_sel(struct samsung_usbphy *sphy)
130{
131 u32 reg;
132
133 if (!sphy->sysreg) {
134 dev_warn(sphy->dev, "Can't configure specified phy mode\n");
135 return;
136 }
137
138 reg = readl(sphy->sysreg);
139
140 if (sphy->phy_type == USB_PHY_TYPE_DEVICE)
141 reg &= ~EXYNOS_USB20PHY_CFG_HOST_LINK;
142 else if (sphy->phy_type == USB_PHY_TYPE_HOST)
143 reg |= EXYNOS_USB20PHY_CFG_HOST_LINK;
144
145 writel(reg, sphy->sysreg);
146}
147EXPORT_SYMBOL_GPL(samsung_usbphy_cfg_sel);
148
149/*
150 * PHYs are different for USB Device and USB Host.
151 * This make sure that correct PHY type is selected before
152 * any operation on PHY.
153 */
154int samsung_usbphy_set_type(struct usb_phy *phy,
155 enum samsung_usb_phy_type phy_type)
156{
157 struct samsung_usbphy *sphy = phy_to_sphy(phy);
158
159 sphy->phy_type = phy_type;
160
161 return 0;
162}
163EXPORT_SYMBOL_GPL(samsung_usbphy_set_type);
164
165/*
166 * Returns reference clock frequency selection value
167 */
168int samsung_usbphy_get_refclk_freq(struct samsung_usbphy *sphy)
169{
170 struct clk *ref_clk;
171 int refclk_freq = 0;
172
173 /*
174 * In exynos5250 USB host and device PHY use
175 * external crystal clock XXTI
176 */
177 if (sphy->drv_data->cpu_type == TYPE_EXYNOS5250)
178 ref_clk = devm_clk_get(sphy->dev, "ext_xtal");
179 else
180 ref_clk = devm_clk_get(sphy->dev, "xusbxti");
181 if (IS_ERR(ref_clk)) {
182 dev_err(sphy->dev, "Failed to get reference clock\n");
183 return PTR_ERR(ref_clk);
184 }
185
186 if (sphy->drv_data->cpu_type == TYPE_EXYNOS5250) {
187 /* set clock frequency for PLL */
188 switch (clk_get_rate(ref_clk)) {
189 case 9600 * KHZ:
190 refclk_freq = FSEL_CLKSEL_9600K;
191 break;
192 case 10 * MHZ:
193 refclk_freq = FSEL_CLKSEL_10M;
194 break;
195 case 12 * MHZ:
196 refclk_freq = FSEL_CLKSEL_12M;
197 break;
198 case 19200 * KHZ:
199 refclk_freq = FSEL_CLKSEL_19200K;
200 break;
201 case 20 * MHZ:
202 refclk_freq = FSEL_CLKSEL_20M;
203 break;
204 case 50 * MHZ:
205 refclk_freq = FSEL_CLKSEL_50M;
206 break;
207 case 24 * MHZ:
208 default:
209 /* default reference clock */
210 refclk_freq = FSEL_CLKSEL_24M;
211 break;
212 }
213 } else {
214 switch (clk_get_rate(ref_clk)) {
215 case 12 * MHZ:
216 refclk_freq = PHYCLK_CLKSEL_12M;
217 break;
218 case 24 * MHZ:
219 refclk_freq = PHYCLK_CLKSEL_24M;
220 break;
221 case 48 * MHZ:
222 refclk_freq = PHYCLK_CLKSEL_48M;
223 break;
224 default:
225 if (sphy->drv_data->cpu_type == TYPE_S3C64XX)
226 refclk_freq = PHYCLK_CLKSEL_48M;
227 else
228 refclk_freq = PHYCLK_CLKSEL_24M;
229 break;
230 }
231 }
232 clk_put(ref_clk);
233
234 return refclk_freq;
235}
236EXPORT_SYMBOL_GPL(samsung_usbphy_get_refclk_freq);
diff --git a/drivers/usb/phy/phy-samsung-usb.h b/drivers/usb/phy/phy-samsung-usb.h
new file mode 100644
index 000000000000..70a9cae5e37f
--- /dev/null
+++ b/drivers/usb/phy/phy-samsung-usb.h
@@ -0,0 +1,327 @@
1/* linux/drivers/usb/phy/phy-samsung-usb.h
2 *
3 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * Samsung USB-PHY transceiver; talks to S3C HS OTG controller, EHCI-S5P and
7 * OHCI-EXYNOS controllers.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19#include <linux/usb/phy.h>
20
21/* Register definitions */
22
23#define SAMSUNG_PHYPWR (0x00)
24
25#define PHYPWR_NORMAL_MASK (0x19 << 0)
26#define PHYPWR_OTG_DISABLE (0x1 << 4)
27#define PHYPWR_ANALOG_POWERDOWN (0x1 << 3)
28#define PHYPWR_FORCE_SUSPEND (0x1 << 1)
29/* For Exynos4 */
30#define PHYPWR_NORMAL_MASK_PHY0 (0x39 << 0)
31#define PHYPWR_SLEEP_PHY0 (0x1 << 5)
32
33#define SAMSUNG_PHYCLK (0x04)
34
35#define PHYCLK_MODE_USB11 (0x1 << 6)
36#define PHYCLK_EXT_OSC (0x1 << 5)
37#define PHYCLK_COMMON_ON_N (0x1 << 4)
38#define PHYCLK_ID_PULL (0x1 << 2)
39#define PHYCLK_CLKSEL_MASK (0x3 << 0)
40#define PHYCLK_CLKSEL_48M (0x0 << 0)
41#define PHYCLK_CLKSEL_12M (0x2 << 0)
42#define PHYCLK_CLKSEL_24M (0x3 << 0)
43
44#define SAMSUNG_RSTCON (0x08)
45
46#define RSTCON_PHYLINK_SWRST (0x1 << 2)
47#define RSTCON_HLINK_SWRST (0x1 << 1)
48#define RSTCON_SWRST (0x1 << 0)
49
50/* EXYNOS5 */
51#define EXYNOS5_PHY_HOST_CTRL0 (0x00)
52
53#define HOST_CTRL0_PHYSWRSTALL (0x1 << 31)
54
55#define HOST_CTRL0_REFCLKSEL_MASK (0x3 << 19)
56#define HOST_CTRL0_REFCLKSEL_XTAL (0x0 << 19)
57#define HOST_CTRL0_REFCLKSEL_EXTL (0x1 << 19)
58#define HOST_CTRL0_REFCLKSEL_CLKCORE (0x2 << 19)
59
60#define HOST_CTRL0_FSEL_MASK (0x7 << 16)
61#define HOST_CTRL0_FSEL(_x) ((_x) << 16)
62
63#define FSEL_CLKSEL_50M (0x7)
64#define FSEL_CLKSEL_24M (0x5)
65#define FSEL_CLKSEL_20M (0x4)
66#define FSEL_CLKSEL_19200K (0x3)
67#define FSEL_CLKSEL_12M (0x2)
68#define FSEL_CLKSEL_10M (0x1)
69#define FSEL_CLKSEL_9600K (0x0)
70
71#define HOST_CTRL0_TESTBURNIN (0x1 << 11)
72#define HOST_CTRL0_RETENABLE (0x1 << 10)
73#define HOST_CTRL0_COMMONON_N (0x1 << 9)
74#define HOST_CTRL0_SIDDQ (0x1 << 6)
75#define HOST_CTRL0_FORCESLEEP (0x1 << 5)
76#define HOST_CTRL0_FORCESUSPEND (0x1 << 4)
77#define HOST_CTRL0_WORDINTERFACE (0x1 << 3)
78#define HOST_CTRL0_UTMISWRST (0x1 << 2)
79#define HOST_CTRL0_LINKSWRST (0x1 << 1)
80#define HOST_CTRL0_PHYSWRST (0x1 << 0)
81
82#define EXYNOS5_PHY_HOST_TUNE0 (0x04)
83
84#define EXYNOS5_PHY_HSIC_CTRL1 (0x10)
85
86#define EXYNOS5_PHY_HSIC_TUNE1 (0x14)
87
88#define EXYNOS5_PHY_HSIC_CTRL2 (0x20)
89
90#define EXYNOS5_PHY_HSIC_TUNE2 (0x24)
91
92#define HSIC_CTRL_REFCLKSEL_MASK (0x3 << 23)
93#define HSIC_CTRL_REFCLKSEL (0x2 << 23)
94
95#define HSIC_CTRL_REFCLKDIV_MASK (0x7f << 16)
96#define HSIC_CTRL_REFCLKDIV(_x) ((_x) << 16)
97#define HSIC_CTRL_REFCLKDIV_12 (0x24 << 16)
98#define HSIC_CTRL_REFCLKDIV_15 (0x1c << 16)
99#define HSIC_CTRL_REFCLKDIV_16 (0x1a << 16)
100#define HSIC_CTRL_REFCLKDIV_19_2 (0x15 << 16)
101#define HSIC_CTRL_REFCLKDIV_20 (0x14 << 16)
102
103#define HSIC_CTRL_SIDDQ (0x1 << 6)
104#define HSIC_CTRL_FORCESLEEP (0x1 << 5)
105#define HSIC_CTRL_FORCESUSPEND (0x1 << 4)
106#define HSIC_CTRL_WORDINTERFACE (0x1 << 3)
107#define HSIC_CTRL_UTMISWRST (0x1 << 2)
108#define HSIC_CTRL_PHYSWRST (0x1 << 0)
109
110#define EXYNOS5_PHY_HOST_EHCICTRL (0x30)
111
112#define HOST_EHCICTRL_ENAINCRXALIGN (0x1 << 29)
113#define HOST_EHCICTRL_ENAINCR4 (0x1 << 28)
114#define HOST_EHCICTRL_ENAINCR8 (0x1 << 27)
115#define HOST_EHCICTRL_ENAINCR16 (0x1 << 26)
116
117#define EXYNOS5_PHY_HOST_OHCICTRL (0x34)
118
119#define HOST_OHCICTRL_SUSPLGCY (0x1 << 3)
120#define HOST_OHCICTRL_APPSTARTCLK (0x1 << 2)
121#define HOST_OHCICTRL_CNTSEL (0x1 << 1)
122#define HOST_OHCICTRL_CLKCKTRST (0x1 << 0)
123
124#define EXYNOS5_PHY_OTG_SYS (0x38)
125
126#define OTG_SYS_PHYLINK_SWRESET (0x1 << 14)
127#define OTG_SYS_LINKSWRST_UOTG (0x1 << 13)
128#define OTG_SYS_PHY0_SWRST (0x1 << 12)
129
130#define OTG_SYS_REFCLKSEL_MASK (0x3 << 9)
131#define OTG_SYS_REFCLKSEL_XTAL (0x0 << 9)
132#define OTG_SYS_REFCLKSEL_EXTL (0x1 << 9)
133#define OTG_SYS_REFCLKSEL_CLKCORE (0x2 << 9)
134
135#define OTG_SYS_IDPULLUP_UOTG (0x1 << 8)
136#define OTG_SYS_COMMON_ON (0x1 << 7)
137
138#define OTG_SYS_FSEL_MASK (0x7 << 4)
139#define OTG_SYS_FSEL(_x) ((_x) << 4)
140
141#define OTG_SYS_FORCESLEEP (0x1 << 3)
142#define OTG_SYS_OTGDISABLE (0x1 << 2)
143#define OTG_SYS_SIDDQ_UOTG (0x1 << 1)
144#define OTG_SYS_FORCESUSPEND (0x1 << 0)
145
146#define EXYNOS5_PHY_OTG_TUNE (0x40)
147
148/* EXYNOS5: USB 3.0 DRD */
149#define EXYNOS5_DRD_LINKSYSTEM (0x04)
150
151#define LINKSYSTEM_FLADJ_MASK (0x3f << 1)
152#define LINKSYSTEM_FLADJ(_x) ((_x) << 1)
153#define LINKSYSTEM_XHCI_VERSION_CONTROL (0x1 << 27)
154
155#define EXYNOS5_DRD_PHYUTMI (0x08)
156
157#define PHYUTMI_OTGDISABLE (0x1 << 6)
158#define PHYUTMI_FORCESUSPEND (0x1 << 1)
159#define PHYUTMI_FORCESLEEP (0x1 << 0)
160
161#define EXYNOS5_DRD_PHYPIPE (0x0c)
162
163#define EXYNOS5_DRD_PHYCLKRST (0x10)
164
165#define PHYCLKRST_SSC_REFCLKSEL_MASK (0xff << 23)
166#define PHYCLKRST_SSC_REFCLKSEL(_x) ((_x) << 23)
167
168#define PHYCLKRST_SSC_RANGE_MASK (0x03 << 21)
169#define PHYCLKRST_SSC_RANGE(_x) ((_x) << 21)
170
171#define PHYCLKRST_SSC_EN (0x1 << 20)
172#define PHYCLKRST_REF_SSP_EN (0x1 << 19)
173#define PHYCLKRST_REF_CLKDIV2 (0x1 << 18)
174
175#define PHYCLKRST_MPLL_MULTIPLIER_MASK (0x7f << 11)
176#define PHYCLKRST_MPLL_MULTIPLIER_100MHZ_REF (0x19 << 11)
177#define PHYCLKRST_MPLL_MULTIPLIER_50M_REF (0x02 << 11)
178#define PHYCLKRST_MPLL_MULTIPLIER_24MHZ_REF (0x68 << 11)
179#define PHYCLKRST_MPLL_MULTIPLIER_20MHZ_REF (0x7d << 11)
180#define PHYCLKRST_MPLL_MULTIPLIER_19200KHZ_REF (0x02 << 11)
181
182#define PHYCLKRST_FSEL_MASK (0x3f << 5)
183#define PHYCLKRST_FSEL(_x) ((_x) << 5)
184#define PHYCLKRST_FSEL_PAD_100MHZ (0x27 << 5)
185#define PHYCLKRST_FSEL_PAD_24MHZ (0x2a << 5)
186#define PHYCLKRST_FSEL_PAD_20MHZ (0x31 << 5)
187#define PHYCLKRST_FSEL_PAD_19_2MHZ (0x38 << 5)
188
189#define PHYCLKRST_RETENABLEN (0x1 << 4)
190
191#define PHYCLKRST_REFCLKSEL_MASK (0x03 << 2)
192#define PHYCLKRST_REFCLKSEL_PAD_REFCLK (0x2 << 2)
193#define PHYCLKRST_REFCLKSEL_EXT_REFCLK (0x3 << 2)
194
195#define PHYCLKRST_PORTRESET (0x1 << 1)
196#define PHYCLKRST_COMMONONN (0x1 << 0)
197
198#define EXYNOS5_DRD_PHYREG0 (0x14)
199#define EXYNOS5_DRD_PHYREG1 (0x18)
200
201#define EXYNOS5_DRD_PHYPARAM0 (0x1c)
202
203#define PHYPARAM0_REF_USE_PAD (0x1 << 31)
204#define PHYPARAM0_REF_LOSLEVEL_MASK (0x1f << 26)
205#define PHYPARAM0_REF_LOSLEVEL (0x9 << 26)
206
207#define EXYNOS5_DRD_PHYPARAM1 (0x20)
208
209#define PHYPARAM1_PCS_TXDEEMPH_MASK (0x1f << 0)
210#define PHYPARAM1_PCS_TXDEEMPH (0x1c)
211
212#define EXYNOS5_DRD_PHYTERM (0x24)
213
214#define EXYNOS5_DRD_PHYTEST (0x28)
215
216#define PHYTEST_POWERDOWN_SSP (0x1 << 3)
217#define PHYTEST_POWERDOWN_HSP (0x1 << 2)
218
219#define EXYNOS5_DRD_PHYADP (0x2c)
220
221#define EXYNOS5_DRD_PHYBATCHG (0x30)
222
223#define PHYBATCHG_UTMI_CLKSEL (0x1 << 2)
224
225#define EXYNOS5_DRD_PHYRESUME (0x34)
226#define EXYNOS5_DRD_LINKPORT (0x44)
227
228#ifndef MHZ
229#define MHZ (1000*1000)
230#endif
231
232#ifndef KHZ
233#define KHZ (1000)
234#endif
235
236#define EXYNOS_USBHOST_PHY_CTRL_OFFSET (0x4)
237#define S3C64XX_USBPHY_ENABLE (0x1 << 16)
238#define EXYNOS_USBPHY_ENABLE (0x1 << 0)
239#define EXYNOS_USB20PHY_CFG_HOST_LINK (0x1 << 0)
240
241enum samsung_cpu_type {
242 TYPE_S3C64XX,
243 TYPE_EXYNOS4210,
244 TYPE_EXYNOS5250,
245};
246
247/*
248 * struct samsung_usbphy_drvdata - driver data for various SoC variants
249 * @cpu_type: machine identifier
250 * @devphy_en_mask: device phy enable mask for PHY CONTROL register
251 * @hostphy_en_mask: host phy enable mask for PHY CONTROL register
252 * @devphy_reg_offset: offset to DEVICE PHY CONTROL register from
253 * mapped address of system controller.
254 * @hostphy_reg_offset: offset to HOST PHY CONTROL register from
255 * mapped address of system controller.
256 *
257 * Here we have a separate mask for device type phy.
258 * Having different masks for host and device type phy helps
259 * in setting independent masks in case of SoCs like S5PV210,
260 * in which PHY0 and PHY1 enable bits belong to same register
261 * placed at position 0 and 1 respectively.
262 * Although for newer SoCs like exynos these bits belong to
263 * different registers altogether placed at position 0.
264 */
265struct samsung_usbphy_drvdata {
266 int cpu_type;
267 int devphy_en_mask;
268 int hostphy_en_mask;
269 u32 devphy_reg_offset;
270 u32 hostphy_reg_offset;
271};
272
273/*
274 * struct samsung_usbphy - transceiver driver state
275 * @phy: transceiver structure
276 * @plat: platform data
277 * @dev: The parent device supplied to the probe function
278 * @clk: usb phy clock
279 * @regs: usb phy controller registers memory base
280 * @pmuregs: USB device PHY_CONTROL register memory base
281 * @sysreg: USB2.0 PHY_CFG register memory base
282 * @ref_clk_freq: reference clock frequency selection
283 * @drv_data: driver data available for different SoCs
284 * @phy_type: Samsung SoCs specific phy types: #HOST
285 * #DEVICE
286 * @phy_usage: usage count for phy
287 * @lock: lock for phy operations
288 */
289struct samsung_usbphy {
290 struct usb_phy phy;
291 struct samsung_usbphy_data *plat;
292 struct device *dev;
293 struct clk *clk;
294 void __iomem *regs;
295 void __iomem *pmuregs;
296 void __iomem *sysreg;
297 int ref_clk_freq;
298 const struct samsung_usbphy_drvdata *drv_data;
299 enum samsung_usb_phy_type phy_type;
300 atomic_t phy_usage;
301 spinlock_t lock;
302};
303
304#define phy_to_sphy(x) container_of((x), struct samsung_usbphy, phy)
305
306static const struct of_device_id samsung_usbphy_dt_match[];
307
308static inline const struct samsung_usbphy_drvdata
309*samsung_usbphy_get_driver_data(struct platform_device *pdev)
310{
311 if (pdev->dev.of_node) {
312 const struct of_device_id *match;
313 match = of_match_node(samsung_usbphy_dt_match,
314 pdev->dev.of_node);
315 return match->data;
316 }
317
318 return (struct samsung_usbphy_drvdata *)
319 platform_get_device_id(pdev)->driver_data;
320}
321
322extern int samsung_usbphy_parse_dt(struct samsung_usbphy *sphy);
323extern void samsung_usbphy_set_isolation(struct samsung_usbphy *sphy, bool on);
324extern void samsung_usbphy_cfg_sel(struct samsung_usbphy *sphy);
325extern int samsung_usbphy_set_type(struct usb_phy *phy,
326 enum samsung_usb_phy_type phy_type);
327extern int samsung_usbphy_get_refclk_freq(struct samsung_usbphy *sphy);
diff --git a/drivers/usb/phy/phy-samsung-usb2.c b/drivers/usb/phy/phy-samsung-usb2.c
new file mode 100644
index 000000000000..45ffe036dacc
--- /dev/null
+++ b/drivers/usb/phy/phy-samsung-usb2.c
@@ -0,0 +1,509 @@
1/* linux/drivers/usb/phy/phy-samsung-usb2.c
2 *
3 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * Author: Praveen Paneri <p.paneri@samsung.com>
7 *
8 * Samsung USB2.0 PHY transceiver; talks to S3C HS OTG controller, EHCI-S5P and
9 * OHCI-EXYNOS controllers.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 */
20
21#include <linux/module.h>
22#include <linux/platform_device.h>
23#include <linux/clk.h>
24#include <linux/delay.h>
25#include <linux/device.h>
26#include <linux/err.h>
27#include <linux/io.h>
28#include <linux/of.h>
29#include <linux/usb/otg.h>
30#include <linux/usb/samsung_usb_phy.h>
31#include <linux/platform_data/samsung-usbphy.h>
32
33#include "phy-samsung-usb.h"
34
35static int samsung_usbphy_set_host(struct usb_otg *otg, struct usb_bus *host)
36{
37 if (!otg)
38 return -ENODEV;
39
40 if (!otg->host)
41 otg->host = host;
42
43 return 0;
44}
45
46static bool exynos5_phyhost_is_on(void __iomem *regs)
47{
48 u32 reg;
49
50 reg = readl(regs + EXYNOS5_PHY_HOST_CTRL0);
51
52 return !(reg & HOST_CTRL0_SIDDQ);
53}
54
55static void samsung_exynos5_usb2phy_enable(struct samsung_usbphy *sphy)
56{
57 void __iomem *regs = sphy->regs;
58 u32 phyclk = sphy->ref_clk_freq;
59 u32 phyhost;
60 u32 phyotg;
61 u32 phyhsic;
62 u32 ehcictrl;
63 u32 ohcictrl;
64
65 /*
66 * phy_usage helps in keeping usage count for phy
67 * so that the first consumer enabling the phy is also
68 * the last consumer to disable it.
69 */
70
71 atomic_inc(&sphy->phy_usage);
72
73 if (exynos5_phyhost_is_on(regs)) {
74 dev_info(sphy->dev, "Already power on PHY\n");
75 return;
76 }
77
78 /* Host configuration */
79 phyhost = readl(regs + EXYNOS5_PHY_HOST_CTRL0);
80
81 /* phy reference clock configuration */
82 phyhost &= ~HOST_CTRL0_FSEL_MASK;
83 phyhost |= HOST_CTRL0_FSEL(phyclk);
84
85 /* host phy reset */
86 phyhost &= ~(HOST_CTRL0_PHYSWRST |
87 HOST_CTRL0_PHYSWRSTALL |
88 HOST_CTRL0_SIDDQ |
89 /* Enable normal mode of operation */
90 HOST_CTRL0_FORCESUSPEND |
91 HOST_CTRL0_FORCESLEEP);
92
93 /* Link reset */
94 phyhost |= (HOST_CTRL0_LINKSWRST |
95 HOST_CTRL0_UTMISWRST |
96 /* COMMON Block configuration during suspend */
97 HOST_CTRL0_COMMONON_N);
98 writel(phyhost, regs + EXYNOS5_PHY_HOST_CTRL0);
99 udelay(10);
100 phyhost &= ~(HOST_CTRL0_LINKSWRST |
101 HOST_CTRL0_UTMISWRST);
102 writel(phyhost, regs + EXYNOS5_PHY_HOST_CTRL0);
103
104 /* OTG configuration */
105 phyotg = readl(regs + EXYNOS5_PHY_OTG_SYS);
106
107 /* phy reference clock configuration */
108 phyotg &= ~OTG_SYS_FSEL_MASK;
109 phyotg |= OTG_SYS_FSEL(phyclk);
110
111 /* Enable normal mode of operation */
112 phyotg &= ~(OTG_SYS_FORCESUSPEND |
113 OTG_SYS_SIDDQ_UOTG |
114 OTG_SYS_FORCESLEEP |
115 OTG_SYS_REFCLKSEL_MASK |
116 /* COMMON Block configuration during suspend */
117 OTG_SYS_COMMON_ON);
118
119 /* OTG phy & link reset */
120 phyotg |= (OTG_SYS_PHY0_SWRST |
121 OTG_SYS_LINKSWRST_UOTG |
122 OTG_SYS_PHYLINK_SWRESET |
123 OTG_SYS_OTGDISABLE |
124 /* Set phy refclk */
125 OTG_SYS_REFCLKSEL_CLKCORE);
126
127 writel(phyotg, regs + EXYNOS5_PHY_OTG_SYS);
128 udelay(10);
129 phyotg &= ~(OTG_SYS_PHY0_SWRST |
130 OTG_SYS_LINKSWRST_UOTG |
131 OTG_SYS_PHYLINK_SWRESET);
132 writel(phyotg, regs + EXYNOS5_PHY_OTG_SYS);
133
134 /* HSIC phy configuration */
135 phyhsic = (HSIC_CTRL_REFCLKDIV_12 |
136 HSIC_CTRL_REFCLKSEL |
137 HSIC_CTRL_PHYSWRST);
138 writel(phyhsic, regs + EXYNOS5_PHY_HSIC_CTRL1);
139 writel(phyhsic, regs + EXYNOS5_PHY_HSIC_CTRL2);
140 udelay(10);
141 phyhsic &= ~HSIC_CTRL_PHYSWRST;
142 writel(phyhsic, regs + EXYNOS5_PHY_HSIC_CTRL1);
143 writel(phyhsic, regs + EXYNOS5_PHY_HSIC_CTRL2);
144
145 udelay(80);
146
147 /* enable EHCI DMA burst */
148 ehcictrl = readl(regs + EXYNOS5_PHY_HOST_EHCICTRL);
149 ehcictrl |= (HOST_EHCICTRL_ENAINCRXALIGN |
150 HOST_EHCICTRL_ENAINCR4 |
151 HOST_EHCICTRL_ENAINCR8 |
152 HOST_EHCICTRL_ENAINCR16);
153 writel(ehcictrl, regs + EXYNOS5_PHY_HOST_EHCICTRL);
154
155 /* set ohci_suspend_on_n */
156 ohcictrl = readl(regs + EXYNOS5_PHY_HOST_OHCICTRL);
157 ohcictrl |= HOST_OHCICTRL_SUSPLGCY;
158 writel(ohcictrl, regs + EXYNOS5_PHY_HOST_OHCICTRL);
159}
160
161static void samsung_usb2phy_enable(struct samsung_usbphy *sphy)
162{
163 void __iomem *regs = sphy->regs;
164 u32 phypwr;
165 u32 phyclk;
166 u32 rstcon;
167
168 /* set clock frequency for PLL */
169 phyclk = sphy->ref_clk_freq;
170 phypwr = readl(regs + SAMSUNG_PHYPWR);
171 rstcon = readl(regs + SAMSUNG_RSTCON);
172
173 switch (sphy->drv_data->cpu_type) {
174 case TYPE_S3C64XX:
175 phyclk &= ~PHYCLK_COMMON_ON_N;
176 phypwr &= ~PHYPWR_NORMAL_MASK;
177 rstcon |= RSTCON_SWRST;
178 break;
179 case TYPE_EXYNOS4210:
180 phypwr &= ~PHYPWR_NORMAL_MASK_PHY0;
181 rstcon |= RSTCON_SWRST;
182 default:
183 break;
184 }
185
186 writel(phyclk, regs + SAMSUNG_PHYCLK);
187 /* Configure PHY0 for normal operation*/
188 writel(phypwr, regs + SAMSUNG_PHYPWR);
189 /* reset all ports of PHY and Link */
190 writel(rstcon, regs + SAMSUNG_RSTCON);
191 udelay(10);
192 rstcon &= ~RSTCON_SWRST;
193 writel(rstcon, regs + SAMSUNG_RSTCON);
194}
195
196static void samsung_exynos5_usb2phy_disable(struct samsung_usbphy *sphy)
197{
198 void __iomem *regs = sphy->regs;
199 u32 phyhost;
200 u32 phyotg;
201 u32 phyhsic;
202
203 if (atomic_dec_return(&sphy->phy_usage) > 0) {
204 dev_info(sphy->dev, "still being used\n");
205 return;
206 }
207
208 phyhsic = (HSIC_CTRL_REFCLKDIV_12 |
209 HSIC_CTRL_REFCLKSEL |
210 HSIC_CTRL_SIDDQ |
211 HSIC_CTRL_FORCESLEEP |
212 HSIC_CTRL_FORCESUSPEND);
213 writel(phyhsic, regs + EXYNOS5_PHY_HSIC_CTRL1);
214 writel(phyhsic, regs + EXYNOS5_PHY_HSIC_CTRL2);
215
216 phyhost = readl(regs + EXYNOS5_PHY_HOST_CTRL0);
217 phyhost |= (HOST_CTRL0_SIDDQ |
218 HOST_CTRL0_FORCESUSPEND |
219 HOST_CTRL0_FORCESLEEP |
220 HOST_CTRL0_PHYSWRST |
221 HOST_CTRL0_PHYSWRSTALL);
222 writel(phyhost, regs + EXYNOS5_PHY_HOST_CTRL0);
223
224 phyotg = readl(regs + EXYNOS5_PHY_OTG_SYS);
225 phyotg |= (OTG_SYS_FORCESUSPEND |
226 OTG_SYS_SIDDQ_UOTG |
227 OTG_SYS_FORCESLEEP);
228 writel(phyotg, regs + EXYNOS5_PHY_OTG_SYS);
229}
230
231static void samsung_usb2phy_disable(struct samsung_usbphy *sphy)
232{
233 void __iomem *regs = sphy->regs;
234 u32 phypwr;
235
236 phypwr = readl(regs + SAMSUNG_PHYPWR);
237
238 switch (sphy->drv_data->cpu_type) {
239 case TYPE_S3C64XX:
240 phypwr |= PHYPWR_NORMAL_MASK;
241 break;
242 case TYPE_EXYNOS4210:
243 phypwr |= PHYPWR_NORMAL_MASK_PHY0;
244 default:
245 break;
246 }
247
248 /* Disable analog and otg block power */
249 writel(phypwr, regs + SAMSUNG_PHYPWR);
250}
251
252/*
253 * The function passed to the usb driver for phy initialization
254 */
255static int samsung_usb2phy_init(struct usb_phy *phy)
256{
257 struct samsung_usbphy *sphy;
258 struct usb_bus *host = NULL;
259 unsigned long flags;
260 int ret = 0;
261
262 sphy = phy_to_sphy(phy);
263
264 host = phy->otg->host;
265
266 /* Enable the phy clock */
267 ret = clk_prepare_enable(sphy->clk);
268 if (ret) {
269 dev_err(sphy->dev, "%s: clk_prepare_enable failed\n", __func__);
270 return ret;
271 }
272
273 spin_lock_irqsave(&sphy->lock, flags);
274
275 if (host) {
276 /* setting default phy-type for USB 2.0 */
277 if (!strstr(dev_name(host->controller), "ehci") ||
278 !strstr(dev_name(host->controller), "ohci"))
279 samsung_usbphy_set_type(&sphy->phy, USB_PHY_TYPE_HOST);
280 } else {
281 samsung_usbphy_set_type(&sphy->phy, USB_PHY_TYPE_DEVICE);
282 }
283
284 /* Disable phy isolation */
285 if (sphy->plat && sphy->plat->pmu_isolation)
286 sphy->plat->pmu_isolation(false);
287 else
288 samsung_usbphy_set_isolation(sphy, false);
289
290 /* Selecting Host/OTG mode; After reset USB2.0PHY_CFG: HOST */
291 samsung_usbphy_cfg_sel(sphy);
292
293 /* Initialize usb phy registers */
294 if (sphy->drv_data->cpu_type == TYPE_EXYNOS5250)
295 samsung_exynos5_usb2phy_enable(sphy);
296 else
297 samsung_usb2phy_enable(sphy);
298
299 spin_unlock_irqrestore(&sphy->lock, flags);
300
301 /* Disable the phy clock */
302 clk_disable_unprepare(sphy->clk);
303
304 return ret;
305}
306
307/*
308 * The function passed to the usb driver for phy shutdown
309 */
310static void samsung_usb2phy_shutdown(struct usb_phy *phy)
311{
312 struct samsung_usbphy *sphy;
313 struct usb_bus *host = NULL;
314 unsigned long flags;
315
316 sphy = phy_to_sphy(phy);
317
318 host = phy->otg->host;
319
320 if (clk_prepare_enable(sphy->clk)) {
321 dev_err(sphy->dev, "%s: clk_prepare_enable failed\n", __func__);
322 return;
323 }
324
325 spin_lock_irqsave(&sphy->lock, flags);
326
327 if (host) {
328 /* setting default phy-type for USB 2.0 */
329 if (!strstr(dev_name(host->controller), "ehci") ||
330 !strstr(dev_name(host->controller), "ohci"))
331 samsung_usbphy_set_type(&sphy->phy, USB_PHY_TYPE_HOST);
332 } else {
333 samsung_usbphy_set_type(&sphy->phy, USB_PHY_TYPE_DEVICE);
334 }
335
336 /* De-initialize usb phy registers */
337 if (sphy->drv_data->cpu_type == TYPE_EXYNOS5250)
338 samsung_exynos5_usb2phy_disable(sphy);
339 else
340 samsung_usb2phy_disable(sphy);
341
342 /* Enable phy isolation */
343 if (sphy->plat && sphy->plat->pmu_isolation)
344 sphy->plat->pmu_isolation(true);
345 else
346 samsung_usbphy_set_isolation(sphy, true);
347
348 spin_unlock_irqrestore(&sphy->lock, flags);
349
350 clk_disable_unprepare(sphy->clk);
351}
352
353static int samsung_usb2phy_probe(struct platform_device *pdev)
354{
355 struct samsung_usbphy *sphy;
356 struct usb_otg *otg;
357 struct samsung_usbphy_data *pdata = pdev->dev.platform_data;
358 const struct samsung_usbphy_drvdata *drv_data;
359 struct device *dev = &pdev->dev;
360 struct resource *phy_mem;
361 void __iomem *phy_base;
362 struct clk *clk;
363 int ret;
364
365 phy_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
366 if (!phy_mem) {
367 dev_err(dev, "%s: missing mem resource\n", __func__);
368 return -ENODEV;
369 }
370
371 phy_base = devm_ioremap_resource(dev, phy_mem);
372 if (IS_ERR(phy_base))
373 return PTR_ERR(phy_base);
374
375 sphy = devm_kzalloc(dev, sizeof(*sphy), GFP_KERNEL);
376 if (!sphy)
377 return -ENOMEM;
378
379 otg = devm_kzalloc(dev, sizeof(*otg), GFP_KERNEL);
380 if (!otg)
381 return -ENOMEM;
382
383 drv_data = samsung_usbphy_get_driver_data(pdev);
384
385 if (drv_data->cpu_type == TYPE_EXYNOS5250)
386 clk = devm_clk_get(dev, "usbhost");
387 else
388 clk = devm_clk_get(dev, "otg");
389
390 if (IS_ERR(clk)) {
391 dev_err(dev, "Failed to get otg clock\n");
392 return PTR_ERR(clk);
393 }
394
395 sphy->dev = dev;
396
397 if (dev->of_node) {
398 ret = samsung_usbphy_parse_dt(sphy);
399 if (ret < 0)
400 return ret;
401 } else {
402 if (!pdata) {
403 dev_err(dev, "no platform data specified\n");
404 return -EINVAL;
405 }
406 }
407
408 sphy->plat = pdata;
409 sphy->regs = phy_base;
410 sphy->clk = clk;
411 sphy->drv_data = drv_data;
412 sphy->phy.dev = sphy->dev;
413 sphy->phy.label = "samsung-usb2phy";
414 sphy->phy.init = samsung_usb2phy_init;
415 sphy->phy.shutdown = samsung_usb2phy_shutdown;
416 sphy->ref_clk_freq = samsung_usbphy_get_refclk_freq(sphy);
417
418 sphy->phy.otg = otg;
419 sphy->phy.otg->phy = &sphy->phy;
420 sphy->phy.otg->set_host = samsung_usbphy_set_host;
421
422 spin_lock_init(&sphy->lock);
423
424 platform_set_drvdata(pdev, sphy);
425
426 return usb_add_phy(&sphy->phy, USB_PHY_TYPE_USB2);
427}
428
429static int samsung_usb2phy_remove(struct platform_device *pdev)
430{
431 struct samsung_usbphy *sphy = platform_get_drvdata(pdev);
432
433 usb_remove_phy(&sphy->phy);
434
435 if (sphy->pmuregs)
436 iounmap(sphy->pmuregs);
437 if (sphy->sysreg)
438 iounmap(sphy->sysreg);
439
440 return 0;
441}
442
443static const struct samsung_usbphy_drvdata usb2phy_s3c64xx = {
444 .cpu_type = TYPE_S3C64XX,
445 .devphy_en_mask = S3C64XX_USBPHY_ENABLE,
446};
447
448static const struct samsung_usbphy_drvdata usb2phy_exynos4 = {
449 .cpu_type = TYPE_EXYNOS4210,
450 .devphy_en_mask = EXYNOS_USBPHY_ENABLE,
451 .hostphy_en_mask = EXYNOS_USBPHY_ENABLE,
452};
453
454static struct samsung_usbphy_drvdata usb2phy_exynos5 = {
455 .cpu_type = TYPE_EXYNOS5250,
456 .hostphy_en_mask = EXYNOS_USBPHY_ENABLE,
457 .hostphy_reg_offset = EXYNOS_USBHOST_PHY_CTRL_OFFSET,
458};
459
460#ifdef CONFIG_OF
461static const struct of_device_id samsung_usbphy_dt_match[] = {
462 {
463 .compatible = "samsung,s3c64xx-usb2phy",
464 .data = &usb2phy_s3c64xx,
465 }, {
466 .compatible = "samsung,exynos4210-usb2phy",
467 .data = &usb2phy_exynos4,
468 }, {
469 .compatible = "samsung,exynos5250-usb2phy",
470 .data = &usb2phy_exynos5
471 },
472 {},
473};
474MODULE_DEVICE_TABLE(of, samsung_usbphy_dt_match);
475#endif
476
477static struct platform_device_id samsung_usbphy_driver_ids[] = {
478 {
479 .name = "s3c64xx-usb2phy",
480 .driver_data = (unsigned long)&usb2phy_s3c64xx,
481 }, {
482 .name = "exynos4210-usb2phy",
483 .driver_data = (unsigned long)&usb2phy_exynos4,
484 }, {
485 .name = "exynos5250-usb2phy",
486 .driver_data = (unsigned long)&usb2phy_exynos5,
487 },
488 {},
489};
490
491MODULE_DEVICE_TABLE(platform, samsung_usbphy_driver_ids);
492
493static struct platform_driver samsung_usb2phy_driver = {
494 .probe = samsung_usb2phy_probe,
495 .remove = samsung_usb2phy_remove,
496 .id_table = samsung_usbphy_driver_ids,
497 .driver = {
498 .name = "samsung-usb2phy",
499 .owner = THIS_MODULE,
500 .of_match_table = of_match_ptr(samsung_usbphy_dt_match),
501 },
502};
503
504module_platform_driver(samsung_usb2phy_driver);
505
506MODULE_DESCRIPTION("Samsung USB 2.0 phy controller");
507MODULE_AUTHOR("Praveen Paneri <p.paneri@samsung.com>");
508MODULE_LICENSE("GPL");
509MODULE_ALIAS("platform:samsung-usb2phy");
diff --git a/drivers/usb/phy/phy-samsung-usb3.c b/drivers/usb/phy/phy-samsung-usb3.c
new file mode 100644
index 000000000000..133f3d0c554f
--- /dev/null
+++ b/drivers/usb/phy/phy-samsung-usb3.c
@@ -0,0 +1,347 @@
1/* linux/drivers/usb/phy/phy-samsung-usb3.c
2 *
3 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * Author: Vivek Gautam <gautam.vivek@samsung.com>
7 *
8 * Samsung USB 3.0 PHY transceiver; talks to DWC3 controller.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 */
19
20#include <linux/module.h>
21#include <linux/platform_device.h>
22#include <linux/clk.h>
23#include <linux/delay.h>
24#include <linux/err.h>
25#include <linux/io.h>
26#include <linux/of.h>
27#include <linux/usb/samsung_usb_phy.h>
28#include <linux/platform_data/samsung-usbphy.h>
29
30#include "phy-samsung-usb.h"
31
32/*
33 * Sets the phy clk as EXTREFCLK (XXTI) which is internal clock from clock core.
34 */
35static u32 samsung_usb3phy_set_refclk(struct samsung_usbphy *sphy)
36{
37 u32 reg;
38 u32 refclk;
39
40 refclk = sphy->ref_clk_freq;
41
42 reg = PHYCLKRST_REFCLKSEL_EXT_REFCLK |
43 PHYCLKRST_FSEL(refclk);
44
45 switch (refclk) {
46 case FSEL_CLKSEL_50M:
47 reg |= (PHYCLKRST_MPLL_MULTIPLIER_50M_REF |
48 PHYCLKRST_SSC_REFCLKSEL(0x00));
49 break;
50 case FSEL_CLKSEL_20M:
51 reg |= (PHYCLKRST_MPLL_MULTIPLIER_20MHZ_REF |
52 PHYCLKRST_SSC_REFCLKSEL(0x00));
53 break;
54 case FSEL_CLKSEL_19200K:
55 reg |= (PHYCLKRST_MPLL_MULTIPLIER_19200KHZ_REF |
56 PHYCLKRST_SSC_REFCLKSEL(0x88));
57 break;
58 case FSEL_CLKSEL_24M:
59 default:
60 reg |= (PHYCLKRST_MPLL_MULTIPLIER_24MHZ_REF |
61 PHYCLKRST_SSC_REFCLKSEL(0x88));
62 break;
63 }
64
65 return reg;
66}
67
68static int samsung_exynos5_usb3phy_enable(struct samsung_usbphy *sphy)
69{
70 void __iomem *regs = sphy->regs;
71 u32 phyparam0;
72 u32 phyparam1;
73 u32 linksystem;
74 u32 phybatchg;
75 u32 phytest;
76 u32 phyclkrst;
77
78 /* Reset USB 3.0 PHY */
79 writel(0x0, regs + EXYNOS5_DRD_PHYREG0);
80
81 phyparam0 = readl(regs + EXYNOS5_DRD_PHYPARAM0);
82 /* Select PHY CLK source */
83 phyparam0 &= ~PHYPARAM0_REF_USE_PAD;
84 /* Set Loss-of-Signal Detector sensitivity */
85 phyparam0 &= ~PHYPARAM0_REF_LOSLEVEL_MASK;
86 phyparam0 |= PHYPARAM0_REF_LOSLEVEL;
87 writel(phyparam0, regs + EXYNOS5_DRD_PHYPARAM0);
88
89 writel(0x0, regs + EXYNOS5_DRD_PHYRESUME);
90
91 /*
92 * Setting the Frame length Adj value[6:1] to default 0x20
93 * See xHCI 1.0 spec, 5.2.4
94 */
95 linksystem = LINKSYSTEM_XHCI_VERSION_CONTROL |
96 LINKSYSTEM_FLADJ(0x20);
97 writel(linksystem, regs + EXYNOS5_DRD_LINKSYSTEM);
98
99 phyparam1 = readl(regs + EXYNOS5_DRD_PHYPARAM1);
100 /* Set Tx De-Emphasis level */
101 phyparam1 &= ~PHYPARAM1_PCS_TXDEEMPH_MASK;
102 phyparam1 |= PHYPARAM1_PCS_TXDEEMPH;
103 writel(phyparam1, regs + EXYNOS5_DRD_PHYPARAM1);
104
105 phybatchg = readl(regs + EXYNOS5_DRD_PHYBATCHG);
106 phybatchg |= PHYBATCHG_UTMI_CLKSEL;
107 writel(phybatchg, regs + EXYNOS5_DRD_PHYBATCHG);
108
109 /* PHYTEST POWERDOWN Control */
110 phytest = readl(regs + EXYNOS5_DRD_PHYTEST);
111 phytest &= ~(PHYTEST_POWERDOWN_SSP |
112 PHYTEST_POWERDOWN_HSP);
113 writel(phytest, regs + EXYNOS5_DRD_PHYTEST);
114
115 /* UTMI Power Control */
116 writel(PHYUTMI_OTGDISABLE, regs + EXYNOS5_DRD_PHYUTMI);
117
118 phyclkrst = samsung_usb3phy_set_refclk(sphy);
119
120 phyclkrst |= PHYCLKRST_PORTRESET |
121 /* Digital power supply in normal operating mode */
122 PHYCLKRST_RETENABLEN |
123 /* Enable ref clock for SS function */
124 PHYCLKRST_REF_SSP_EN |
125 /* Enable spread spectrum */
126 PHYCLKRST_SSC_EN |
127 /* Power down HS Bias and PLL blocks in suspend mode */
128 PHYCLKRST_COMMONONN;
129
130 writel(phyclkrst, regs + EXYNOS5_DRD_PHYCLKRST);
131
132 udelay(10);
133
134 phyclkrst &= ~(PHYCLKRST_PORTRESET);
135 writel(phyclkrst, regs + EXYNOS5_DRD_PHYCLKRST);
136
137 return 0;
138}
139
140static void samsung_exynos5_usb3phy_disable(struct samsung_usbphy *sphy)
141{
142 u32 phyutmi;
143 u32 phyclkrst;
144 u32 phytest;
145 void __iomem *regs = sphy->regs;
146
147 phyutmi = PHYUTMI_OTGDISABLE |
148 PHYUTMI_FORCESUSPEND |
149 PHYUTMI_FORCESLEEP;
150 writel(phyutmi, regs + EXYNOS5_DRD_PHYUTMI);
151
152 /* Resetting the PHYCLKRST enable bits to reduce leakage current */
153 phyclkrst = readl(regs + EXYNOS5_DRD_PHYCLKRST);
154 phyclkrst &= ~(PHYCLKRST_REF_SSP_EN |
155 PHYCLKRST_SSC_EN |
156 PHYCLKRST_COMMONONN);
157 writel(phyclkrst, regs + EXYNOS5_DRD_PHYCLKRST);
158
159 /* Control PHYTEST to remove leakage current */
160 phytest = readl(regs + EXYNOS5_DRD_PHYTEST);
161 phytest |= (PHYTEST_POWERDOWN_SSP |
162 PHYTEST_POWERDOWN_HSP);
163 writel(phytest, regs + EXYNOS5_DRD_PHYTEST);
164}
165
166static int samsung_usb3phy_init(struct usb_phy *phy)
167{
168 struct samsung_usbphy *sphy;
169 unsigned long flags;
170 int ret = 0;
171
172 sphy = phy_to_sphy(phy);
173
174 /* Enable the phy clock */
175 ret = clk_prepare_enable(sphy->clk);
176 if (ret) {
177 dev_err(sphy->dev, "%s: clk_prepare_enable failed\n", __func__);
178 return ret;
179 }
180
181 spin_lock_irqsave(&sphy->lock, flags);
182
183 /* setting default phy-type for USB 3.0 */
184 samsung_usbphy_set_type(&sphy->phy, USB_PHY_TYPE_DEVICE);
185
186 /* Disable phy isolation */
187 samsung_usbphy_set_isolation(sphy, false);
188
189 /* Initialize usb phy registers */
190 samsung_exynos5_usb3phy_enable(sphy);
191
192 spin_unlock_irqrestore(&sphy->lock, flags);
193
194 /* Disable the phy clock */
195 clk_disable_unprepare(sphy->clk);
196
197 return ret;
198}
199
200/*
201 * The function passed to the usb driver for phy shutdown
202 */
203static void samsung_usb3phy_shutdown(struct usb_phy *phy)
204{
205 struct samsung_usbphy *sphy;
206 unsigned long flags;
207
208 sphy = phy_to_sphy(phy);
209
210 if (clk_prepare_enable(sphy->clk)) {
211 dev_err(sphy->dev, "%s: clk_prepare_enable failed\n", __func__);
212 return;
213 }
214
215 spin_lock_irqsave(&sphy->lock, flags);
216
217 /* setting default phy-type for USB 3.0 */
218 samsung_usbphy_set_type(&sphy->phy, USB_PHY_TYPE_DEVICE);
219
220 /* De-initialize usb phy registers */
221 samsung_exynos5_usb3phy_disable(sphy);
222
223 /* Enable phy isolation */
224 samsung_usbphy_set_isolation(sphy, true);
225
226 spin_unlock_irqrestore(&sphy->lock, flags);
227
228 clk_disable_unprepare(sphy->clk);
229}
230
231static int samsung_usb3phy_probe(struct platform_device *pdev)
232{
233 struct samsung_usbphy *sphy;
234 struct samsung_usbphy_data *pdata = pdev->dev.platform_data;
235 struct device *dev = &pdev->dev;
236 struct resource *phy_mem;
237 void __iomem *phy_base;
238 struct clk *clk;
239 int ret;
240
241 phy_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
242 if (!phy_mem) {
243 dev_err(dev, "%s: missing mem resource\n", __func__);
244 return -ENODEV;
245 }
246
247 phy_base = devm_ioremap_resource(dev, phy_mem);
248 if (IS_ERR(phy_base))
249 return PTR_ERR(phy_base);
250
251 sphy = devm_kzalloc(dev, sizeof(*sphy), GFP_KERNEL);
252 if (!sphy)
253 return -ENOMEM;
254
255 clk = devm_clk_get(dev, "usbdrd30");
256 if (IS_ERR(clk)) {
257 dev_err(dev, "Failed to get device clock\n");
258 return PTR_ERR(clk);
259 }
260
261 sphy->dev = dev;
262
263 if (dev->of_node) {
264 ret = samsung_usbphy_parse_dt(sphy);
265 if (ret < 0)
266 return ret;
267 } else {
268 if (!pdata) {
269 dev_err(dev, "no platform data specified\n");
270 return -EINVAL;
271 }
272 }
273
274 sphy->plat = pdata;
275 sphy->regs = phy_base;
276 sphy->clk = clk;
277 sphy->phy.dev = sphy->dev;
278 sphy->phy.label = "samsung-usb3phy";
279 sphy->phy.init = samsung_usb3phy_init;
280 sphy->phy.shutdown = samsung_usb3phy_shutdown;
281 sphy->drv_data = samsung_usbphy_get_driver_data(pdev);
282 sphy->ref_clk_freq = samsung_usbphy_get_refclk_freq(sphy);
283
284 spin_lock_init(&sphy->lock);
285
286 platform_set_drvdata(pdev, sphy);
287
288 return usb_add_phy(&sphy->phy, USB_PHY_TYPE_USB3);
289}
290
291static int samsung_usb3phy_remove(struct platform_device *pdev)
292{
293 struct samsung_usbphy *sphy = platform_get_drvdata(pdev);
294
295 usb_remove_phy(&sphy->phy);
296
297 if (sphy->pmuregs)
298 iounmap(sphy->pmuregs);
299 if (sphy->sysreg)
300 iounmap(sphy->sysreg);
301
302 return 0;
303}
304
305static struct samsung_usbphy_drvdata usb3phy_exynos5 = {
306 .cpu_type = TYPE_EXYNOS5250,
307 .devphy_en_mask = EXYNOS_USBPHY_ENABLE,
308};
309
310#ifdef CONFIG_OF
311static const struct of_device_id samsung_usbphy_dt_match[] = {
312 {
313 .compatible = "samsung,exynos5250-usb3phy",
314 .data = &usb3phy_exynos5
315 },
316 {},
317};
318MODULE_DEVICE_TABLE(of, samsung_usbphy_dt_match);
319#endif
320
321static struct platform_device_id samsung_usbphy_driver_ids[] = {
322 {
323 .name = "exynos5250-usb3phy",
324 .driver_data = (unsigned long)&usb3phy_exynos5,
325 },
326 {},
327};
328
329MODULE_DEVICE_TABLE(platform, samsung_usbphy_driver_ids);
330
331static struct platform_driver samsung_usb3phy_driver = {
332 .probe = samsung_usb3phy_probe,
333 .remove = samsung_usb3phy_remove,
334 .id_table = samsung_usbphy_driver_ids,
335 .driver = {
336 .name = "samsung-usb3phy",
337 .owner = THIS_MODULE,
338 .of_match_table = of_match_ptr(samsung_usbphy_dt_match),
339 },
340};
341
342module_platform_driver(samsung_usb3phy_driver);
343
344MODULE_DESCRIPTION("Samsung USB 3.0 phy controller");
345MODULE_AUTHOR("Vivek Gautam <gautam.vivek@samsung.com>");
346MODULE_LICENSE("GPL");
347MODULE_ALIAS("platform:samsung-usb3phy");
diff --git a/drivers/usb/phy/tegra_usb_phy.c b/drivers/usb/phy/phy-tegra-usb.c
index 5487d38481af..5487d38481af 100644
--- a/drivers/usb/phy/tegra_usb_phy.c
+++ b/drivers/usb/phy/phy-tegra-usb.c
diff --git a/drivers/usb/phy/phy-twl4030-usb.c b/drivers/usb/phy/phy-twl4030-usb.c
new file mode 100644
index 000000000000..8f78d2d40722
--- /dev/null
+++ b/drivers/usb/phy/phy-twl4030-usb.c
@@ -0,0 +1,794 @@
1/*
2 * twl4030_usb - TWL4030 USB transceiver, talking to OMAP OTG controller
3 *
4 * Copyright (C) 2004-2007 Texas Instruments
5 * Copyright (C) 2008 Nokia Corporation
6 * Contact: Felipe Balbi <felipe.balbi@nokia.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 *
22 * Current status:
23 * - HS USB ULPI mode works.
24 * - 3-pin mode support may be added in future.
25 */
26
27#include <linux/module.h>
28#include <linux/init.h>
29#include <linux/interrupt.h>
30#include <linux/platform_device.h>
31#include <linux/spinlock.h>
32#include <linux/workqueue.h>
33#include <linux/io.h>
34#include <linux/delay.h>
35#include <linux/usb/otg.h>
36#include <linux/usb/musb-omap.h>
37#include <linux/usb/ulpi.h>
38#include <linux/i2c/twl.h>
39#include <linux/regulator/consumer.h>
40#include <linux/err.h>
41#include <linux/slab.h>
42
43/* Register defines */
44
45#define MCPC_CTRL 0x30
46#define MCPC_CTRL_RTSOL (1 << 7)
47#define MCPC_CTRL_EXTSWR (1 << 6)
48#define MCPC_CTRL_EXTSWC (1 << 5)
49#define MCPC_CTRL_VOICESW (1 << 4)
50#define MCPC_CTRL_OUT64K (1 << 3)
51#define MCPC_CTRL_RTSCTSSW (1 << 2)
52#define MCPC_CTRL_HS_UART (1 << 0)
53
54#define MCPC_IO_CTRL 0x33
55#define MCPC_IO_CTRL_MICBIASEN (1 << 5)
56#define MCPC_IO_CTRL_CTS_NPU (1 << 4)
57#define MCPC_IO_CTRL_RXD_PU (1 << 3)
58#define MCPC_IO_CTRL_TXDTYP (1 << 2)
59#define MCPC_IO_CTRL_CTSTYP (1 << 1)
60#define MCPC_IO_CTRL_RTSTYP (1 << 0)
61
62#define MCPC_CTRL2 0x36
63#define MCPC_CTRL2_MCPC_CK_EN (1 << 0)
64
65#define OTHER_FUNC_CTRL 0x80
66#define OTHER_FUNC_CTRL_BDIS_ACON_EN (1 << 4)
67#define OTHER_FUNC_CTRL_FIVEWIRE_MODE (1 << 2)
68
69#define OTHER_IFC_CTRL 0x83
70#define OTHER_IFC_CTRL_OE_INT_EN (1 << 6)
71#define OTHER_IFC_CTRL_CEA2011_MODE (1 << 5)
72#define OTHER_IFC_CTRL_FSLSSERIALMODE_4PIN (1 << 4)
73#define OTHER_IFC_CTRL_HIZ_ULPI_60MHZ_OUT (1 << 3)
74#define OTHER_IFC_CTRL_HIZ_ULPI (1 << 2)
75#define OTHER_IFC_CTRL_ALT_INT_REROUTE (1 << 0)
76
77#define OTHER_INT_EN_RISE 0x86
78#define OTHER_INT_EN_FALL 0x89
79#define OTHER_INT_STS 0x8C
80#define OTHER_INT_LATCH 0x8D
81#define OTHER_INT_VB_SESS_VLD (1 << 7)
82#define OTHER_INT_DM_HI (1 << 6) /* not valid for "latch" reg */
83#define OTHER_INT_DP_HI (1 << 5) /* not valid for "latch" reg */
84#define OTHER_INT_BDIS_ACON (1 << 3) /* not valid for "fall" regs */
85#define OTHER_INT_MANU (1 << 1)
86#define OTHER_INT_ABNORMAL_STRESS (1 << 0)
87
88#define ID_STATUS 0x96
89#define ID_RES_FLOAT (1 << 4)
90#define ID_RES_440K (1 << 3)
91#define ID_RES_200K (1 << 2)
92#define ID_RES_102K (1 << 1)
93#define ID_RES_GND (1 << 0)
94
95#define POWER_CTRL 0xAC
96#define POWER_CTRL_OTG_ENAB (1 << 5)
97
98#define OTHER_IFC_CTRL2 0xAF
99#define OTHER_IFC_CTRL2_ULPI_STP_LOW (1 << 4)
100#define OTHER_IFC_CTRL2_ULPI_TXEN_POL (1 << 3)
101#define OTHER_IFC_CTRL2_ULPI_4PIN_2430 (1 << 2)
102#define OTHER_IFC_CTRL2_USB_INT_OUTSEL_MASK (3 << 0) /* bits 0 and 1 */
103#define OTHER_IFC_CTRL2_USB_INT_OUTSEL_INT1N (0 << 0)
104#define OTHER_IFC_CTRL2_USB_INT_OUTSEL_INT2N (1 << 0)
105
106#define REG_CTRL_EN 0xB2
107#define REG_CTRL_ERROR 0xB5
108#define ULPI_I2C_CONFLICT_INTEN (1 << 0)
109
110#define OTHER_FUNC_CTRL2 0xB8
111#define OTHER_FUNC_CTRL2_VBAT_TIMER_EN (1 << 0)
112
113/* following registers do not have separate _clr and _set registers */
114#define VBUS_DEBOUNCE 0xC0
115#define ID_DEBOUNCE 0xC1
116#define VBAT_TIMER 0xD3
117#define PHY_PWR_CTRL 0xFD
118#define PHY_PWR_PHYPWD (1 << 0)
119#define PHY_CLK_CTRL 0xFE
120#define PHY_CLK_CTRL_CLOCKGATING_EN (1 << 2)
121#define PHY_CLK_CTRL_CLK32K_EN (1 << 1)
122#define REQ_PHY_DPLL_CLK (1 << 0)
123#define PHY_CLK_CTRL_STS 0xFF
124#define PHY_DPLL_CLK (1 << 0)
125
126/* In module TWL_MODULE_PM_MASTER */
127#define STS_HW_CONDITIONS 0x0F
128
129/* In module TWL_MODULE_PM_RECEIVER */
130#define VUSB_DEDICATED1 0x7D
131#define VUSB_DEDICATED2 0x7E
132#define VUSB1V5_DEV_GRP 0x71
133#define VUSB1V5_TYPE 0x72
134#define VUSB1V5_REMAP 0x73
135#define VUSB1V8_DEV_GRP 0x74
136#define VUSB1V8_TYPE 0x75
137#define VUSB1V8_REMAP 0x76
138#define VUSB3V1_DEV_GRP 0x77
139#define VUSB3V1_TYPE 0x78
140#define VUSB3V1_REMAP 0x79
141
142/* In module TWL4030_MODULE_INTBR */
143#define PMBR1 0x0D
144#define GPIO_USB_4PIN_ULPI_2430C (3 << 0)
145
146struct twl4030_usb {
147 struct usb_phy phy;
148 struct device *dev;
149
150 /* TWL4030 internal USB regulator supplies */
151 struct regulator *usb1v5;
152 struct regulator *usb1v8;
153 struct regulator *usb3v1;
154
155 /* for vbus reporting with irqs disabled */
156 spinlock_t lock;
157
158 /* pin configuration */
159 enum twl4030_usb_mode usb_mode;
160
161 int irq;
162 enum omap_musb_vbus_id_status linkstat;
163 bool vbus_supplied;
164 u8 asleep;
165 bool irq_enabled;
166
167 struct delayed_work id_workaround_work;
168};
169
170/* internal define on top of container_of */
171#define phy_to_twl(x) container_of((x), struct twl4030_usb, phy)
172
173/*-------------------------------------------------------------------------*/
174
175static int twl4030_i2c_write_u8_verify(struct twl4030_usb *twl,
176 u8 module, u8 data, u8 address)
177{
178 u8 check;
179
180 if ((twl_i2c_write_u8(module, data, address) >= 0) &&
181 (twl_i2c_read_u8(module, &check, address) >= 0) &&
182 (check == data))
183 return 0;
184 dev_dbg(twl->dev, "Write%d[%d,0x%x] wrote %02x but read %02x\n",
185 1, module, address, check, data);
186
187 /* Failed once: Try again */
188 if ((twl_i2c_write_u8(module, data, address) >= 0) &&
189 (twl_i2c_read_u8(module, &check, address) >= 0) &&
190 (check == data))
191 return 0;
192 dev_dbg(twl->dev, "Write%d[%d,0x%x] wrote %02x but read %02x\n",
193 2, module, address, check, data);
194
195 /* Failed again: Return error */
196 return -EBUSY;
197}
198
199#define twl4030_usb_write_verify(twl, address, data) \
200 twl4030_i2c_write_u8_verify(twl, TWL_MODULE_USB, (data), (address))
201
202static inline int twl4030_usb_write(struct twl4030_usb *twl,
203 u8 address, u8 data)
204{
205 int ret = 0;
206
207 ret = twl_i2c_write_u8(TWL_MODULE_USB, data, address);
208 if (ret < 0)
209 dev_dbg(twl->dev,
210 "TWL4030:USB:Write[0x%x] Error %d\n", address, ret);
211 return ret;
212}
213
214static inline int twl4030_readb(struct twl4030_usb *twl, u8 module, u8 address)
215{
216 u8 data;
217 int ret = 0;
218
219 ret = twl_i2c_read_u8(module, &data, address);
220 if (ret >= 0)
221 ret = data;
222 else
223 dev_dbg(twl->dev,
224 "TWL4030:readb[0x%x,0x%x] Error %d\n",
225 module, address, ret);
226
227 return ret;
228}
229
230static inline int twl4030_usb_read(struct twl4030_usb *twl, u8 address)
231{
232 return twl4030_readb(twl, TWL_MODULE_USB, address);
233}
234
235/*-------------------------------------------------------------------------*/
236
237static inline int
238twl4030_usb_set_bits(struct twl4030_usb *twl, u8 reg, u8 bits)
239{
240 return twl4030_usb_write(twl, ULPI_SET(reg), bits);
241}
242
243static inline int
244twl4030_usb_clear_bits(struct twl4030_usb *twl, u8 reg, u8 bits)
245{
246 return twl4030_usb_write(twl, ULPI_CLR(reg), bits);
247}
248
249/*-------------------------------------------------------------------------*/
250
251static bool twl4030_is_driving_vbus(struct twl4030_usb *twl)
252{
253 int ret;
254
255 ret = twl4030_usb_read(twl, PHY_CLK_CTRL_STS);
256 if (ret < 0 || !(ret & PHY_DPLL_CLK))
257 /*
258 * if clocks are off, registers are not updated,
259 * but we can assume we don't drive VBUS in this case
260 */
261 return false;
262
263 ret = twl4030_usb_read(twl, ULPI_OTG_CTRL);
264 if (ret < 0)
265 return false;
266
267 return (ret & (ULPI_OTG_DRVVBUS | ULPI_OTG_CHRGVBUS)) ? true : false;
268}
269
270static enum omap_musb_vbus_id_status
271 twl4030_usb_linkstat(struct twl4030_usb *twl)
272{
273 int status;
274 enum omap_musb_vbus_id_status linkstat = OMAP_MUSB_UNKNOWN;
275
276 twl->vbus_supplied = false;
277
278 /*
279 * For ID/VBUS sensing, see manual section 15.4.8 ...
280 * except when using only battery backup power, two
281 * comparators produce VBUS_PRES and ID_PRES signals,
282 * which don't match docs elsewhere. But ... BIT(7)
283 * and BIT(2) of STS_HW_CONDITIONS, respectively, do
284 * seem to match up. If either is true the USB_PRES
285 * signal is active, the OTG module is activated, and
286 * its interrupt may be raised (may wake the system).
287 */
288 status = twl4030_readb(twl, TWL_MODULE_PM_MASTER, STS_HW_CONDITIONS);
289 if (status < 0)
290 dev_err(twl->dev, "USB link status err %d\n", status);
291 else if (status & (BIT(7) | BIT(2))) {
292 if (status & BIT(7)) {
293 if (twl4030_is_driving_vbus(twl))
294 status &= ~BIT(7);
295 else
296 twl->vbus_supplied = true;
297 }
298
299 if (status & BIT(2))
300 linkstat = OMAP_MUSB_ID_GROUND;
301 else if (status & BIT(7))
302 linkstat = OMAP_MUSB_VBUS_VALID;
303 else
304 linkstat = OMAP_MUSB_VBUS_OFF;
305 } else {
306 if (twl->linkstat != OMAP_MUSB_UNKNOWN)
307 linkstat = OMAP_MUSB_VBUS_OFF;
308 }
309
310 dev_dbg(twl->dev, "HW_CONDITIONS 0x%02x/%d; link %d\n",
311 status, status, linkstat);
312
313 /* REVISIT this assumes host and peripheral controllers
314 * are registered, and that both are active...
315 */
316
317 return linkstat;
318}
319
320static void twl4030_usb_set_mode(struct twl4030_usb *twl, int mode)
321{
322 twl->usb_mode = mode;
323
324 switch (mode) {
325 case T2_USB_MODE_ULPI:
326 twl4030_usb_clear_bits(twl, ULPI_IFC_CTRL,
327 ULPI_IFC_CTRL_CARKITMODE);
328 twl4030_usb_set_bits(twl, POWER_CTRL, POWER_CTRL_OTG_ENAB);
329 twl4030_usb_clear_bits(twl, ULPI_FUNC_CTRL,
330 ULPI_FUNC_CTRL_XCVRSEL_MASK |
331 ULPI_FUNC_CTRL_OPMODE_MASK);
332 break;
333 case -1:
334 /* FIXME: power on defaults */
335 break;
336 default:
337 dev_err(twl->dev, "unsupported T2 transceiver mode %d\n",
338 mode);
339 break;
340 };
341}
342
343static void twl4030_i2c_access(struct twl4030_usb *twl, int on)
344{
345 unsigned long timeout;
346 int val = twl4030_usb_read(twl, PHY_CLK_CTRL);
347
348 if (val >= 0) {
349 if (on) {
350 /* enable DPLL to access PHY registers over I2C */
351 val |= REQ_PHY_DPLL_CLK;
352 WARN_ON(twl4030_usb_write_verify(twl, PHY_CLK_CTRL,
353 (u8)val) < 0);
354
355 timeout = jiffies + HZ;
356 while (!(twl4030_usb_read(twl, PHY_CLK_CTRL_STS) &
357 PHY_DPLL_CLK)
358 && time_before(jiffies, timeout))
359 udelay(10);
360 if (!(twl4030_usb_read(twl, PHY_CLK_CTRL_STS) &
361 PHY_DPLL_CLK))
362 dev_err(twl->dev, "Timeout setting T2 HSUSB "
363 "PHY DPLL clock\n");
364 } else {
365 /* let ULPI control the DPLL clock */
366 val &= ~REQ_PHY_DPLL_CLK;
367 WARN_ON(twl4030_usb_write_verify(twl, PHY_CLK_CTRL,
368 (u8)val) < 0);
369 }
370 }
371}
372
373static void __twl4030_phy_power(struct twl4030_usb *twl, int on)
374{
375 u8 pwr = twl4030_usb_read(twl, PHY_PWR_CTRL);
376
377 if (on)
378 pwr &= ~PHY_PWR_PHYPWD;
379 else
380 pwr |= PHY_PWR_PHYPWD;
381
382 WARN_ON(twl4030_usb_write_verify(twl, PHY_PWR_CTRL, pwr) < 0);
383}
384
385static void twl4030_phy_power(struct twl4030_usb *twl, int on)
386{
387 int ret;
388
389 if (on) {
390 ret = regulator_enable(twl->usb3v1);
391 if (ret)
392 dev_err(twl->dev, "Failed to enable usb3v1\n");
393
394 ret = regulator_enable(twl->usb1v8);
395 if (ret)
396 dev_err(twl->dev, "Failed to enable usb1v8\n");
397
398 /*
399 * Disabling usb3v1 regulator (= writing 0 to VUSB3V1_DEV_GRP
400 * in twl4030) resets the VUSB_DEDICATED2 register. This reset
401 * enables VUSB3V1_SLEEP bit that remaps usb3v1 ACTIVE state to
402 * SLEEP. We work around this by clearing the bit after usv3v1
403 * is re-activated. This ensures that VUSB3V1 is really active.
404 */
405 twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB_DEDICATED2);
406
407 ret = regulator_enable(twl->usb1v5);
408 if (ret)
409 dev_err(twl->dev, "Failed to enable usb1v5\n");
410
411 __twl4030_phy_power(twl, 1);
412 twl4030_usb_write(twl, PHY_CLK_CTRL,
413 twl4030_usb_read(twl, PHY_CLK_CTRL) |
414 (PHY_CLK_CTRL_CLOCKGATING_EN |
415 PHY_CLK_CTRL_CLK32K_EN));
416 } else {
417 __twl4030_phy_power(twl, 0);
418 regulator_disable(twl->usb1v5);
419 regulator_disable(twl->usb1v8);
420 regulator_disable(twl->usb3v1);
421 }
422}
423
424static void twl4030_phy_suspend(struct twl4030_usb *twl, int controller_off)
425{
426 if (twl->asleep)
427 return;
428
429 twl4030_phy_power(twl, 0);
430 twl->asleep = 1;
431 dev_dbg(twl->dev, "%s\n", __func__);
432}
433
434static void __twl4030_phy_resume(struct twl4030_usb *twl)
435{
436 twl4030_phy_power(twl, 1);
437 twl4030_i2c_access(twl, 1);
438 twl4030_usb_set_mode(twl, twl->usb_mode);
439 if (twl->usb_mode == T2_USB_MODE_ULPI)
440 twl4030_i2c_access(twl, 0);
441}
442
443static void twl4030_phy_resume(struct twl4030_usb *twl)
444{
445 if (!twl->asleep)
446 return;
447 __twl4030_phy_resume(twl);
448 twl->asleep = 0;
449 dev_dbg(twl->dev, "%s\n", __func__);
450
451 /*
452 * XXX When VBUS gets driven after musb goes to A mode,
453 * ID_PRES related interrupts no longer arrive, why?
454 * Register itself is updated fine though, so we must poll.
455 */
456 if (twl->linkstat == OMAP_MUSB_ID_GROUND) {
457 cancel_delayed_work(&twl->id_workaround_work);
458 schedule_delayed_work(&twl->id_workaround_work, HZ);
459 }
460}
461
462static int twl4030_usb_ldo_init(struct twl4030_usb *twl)
463{
464 /* Enable writing to power configuration registers */
465 twl_i2c_write_u8(TWL_MODULE_PM_MASTER, TWL4030_PM_MASTER_KEY_CFG1,
466 TWL4030_PM_MASTER_PROTECT_KEY);
467
468 twl_i2c_write_u8(TWL_MODULE_PM_MASTER, TWL4030_PM_MASTER_KEY_CFG2,
469 TWL4030_PM_MASTER_PROTECT_KEY);
470
471 /* Keep VUSB3V1 LDO in sleep state until VBUS/ID change detected*/
472 /*twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB_DEDICATED2);*/
473
474 /* input to VUSB3V1 LDO is from VBAT, not VBUS */
475 twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0x14, VUSB_DEDICATED1);
476
477 /* Initialize 3.1V regulator */
478 twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB3V1_DEV_GRP);
479
480 twl->usb3v1 = devm_regulator_get(twl->dev, "usb3v1");
481 if (IS_ERR(twl->usb3v1))
482 return -ENODEV;
483
484 twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB3V1_TYPE);
485
486 /* Initialize 1.5V regulator */
487 twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB1V5_DEV_GRP);
488
489 twl->usb1v5 = devm_regulator_get(twl->dev, "usb1v5");
490 if (IS_ERR(twl->usb1v5))
491 return -ENODEV;
492
493 twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB1V5_TYPE);
494
495 /* Initialize 1.8V regulator */
496 twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB1V8_DEV_GRP);
497
498 twl->usb1v8 = devm_regulator_get(twl->dev, "usb1v8");
499 if (IS_ERR(twl->usb1v8))
500 return -ENODEV;
501
502 twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB1V8_TYPE);
503
504 /* disable access to power configuration registers */
505 twl_i2c_write_u8(TWL_MODULE_PM_MASTER, 0,
506 TWL4030_PM_MASTER_PROTECT_KEY);
507
508 return 0;
509}
510
511static ssize_t twl4030_usb_vbus_show(struct device *dev,
512 struct device_attribute *attr, char *buf)
513{
514 struct twl4030_usb *twl = dev_get_drvdata(dev);
515 unsigned long flags;
516 int ret = -EINVAL;
517
518 spin_lock_irqsave(&twl->lock, flags);
519 ret = sprintf(buf, "%s\n",
520 twl->vbus_supplied ? "on" : "off");
521 spin_unlock_irqrestore(&twl->lock, flags);
522
523 return ret;
524}
525static DEVICE_ATTR(vbus, 0444, twl4030_usb_vbus_show, NULL);
526
527static irqreturn_t twl4030_usb_irq(int irq, void *_twl)
528{
529 struct twl4030_usb *twl = _twl;
530 enum omap_musb_vbus_id_status status;
531 bool status_changed = false;
532
533 status = twl4030_usb_linkstat(twl);
534
535 spin_lock_irq(&twl->lock);
536 if (status >= 0 && status != twl->linkstat) {
537 twl->linkstat = status;
538 status_changed = true;
539 }
540 spin_unlock_irq(&twl->lock);
541
542 if (status_changed) {
543 /* FIXME add a set_power() method so that B-devices can
544 * configure the charger appropriately. It's not always
545 * correct to consume VBUS power, and how much current to
546 * consume is a function of the USB configuration chosen
547 * by the host.
548 *
549 * REVISIT usb_gadget_vbus_connect(...) as needed, ditto
550 * its disconnect() sibling, when changing to/from the
551 * USB_LINK_VBUS state. musb_hdrc won't care until it
552 * starts to handle softconnect right.
553 */
554 omap_musb_mailbox(status);
555 }
556 sysfs_notify(&twl->dev->kobj, NULL, "vbus");
557
558 return IRQ_HANDLED;
559}
560
561static void twl4030_id_workaround_work(struct work_struct *work)
562{
563 struct twl4030_usb *twl = container_of(work, struct twl4030_usb,
564 id_workaround_work.work);
565 enum omap_musb_vbus_id_status status;
566 bool status_changed = false;
567
568 status = twl4030_usb_linkstat(twl);
569
570 spin_lock_irq(&twl->lock);
571 if (status >= 0 && status != twl->linkstat) {
572 twl->linkstat = status;
573 status_changed = true;
574 }
575 spin_unlock_irq(&twl->lock);
576
577 if (status_changed) {
578 dev_dbg(twl->dev, "handle missing status change to %d\n",
579 status);
580 omap_musb_mailbox(status);
581 }
582
583 /* don't schedule during sleep - irq works right then */
584 if (status == OMAP_MUSB_ID_GROUND && !twl->asleep) {
585 cancel_delayed_work(&twl->id_workaround_work);
586 schedule_delayed_work(&twl->id_workaround_work, HZ);
587 }
588}
589
590static int twl4030_usb_phy_init(struct usb_phy *phy)
591{
592 struct twl4030_usb *twl = phy_to_twl(phy);
593 enum omap_musb_vbus_id_status status;
594
595 /*
596 * Start in sleep state, we'll get called through set_suspend()
597 * callback when musb is runtime resumed and it's time to start.
598 */
599 __twl4030_phy_power(twl, 0);
600 twl->asleep = 1;
601
602 status = twl4030_usb_linkstat(twl);
603 twl->linkstat = status;
604
605 if (status == OMAP_MUSB_ID_GROUND || status == OMAP_MUSB_VBUS_VALID)
606 omap_musb_mailbox(twl->linkstat);
607
608 sysfs_notify(&twl->dev->kobj, NULL, "vbus");
609 return 0;
610}
611
612static int twl4030_set_suspend(struct usb_phy *x, int suspend)
613{
614 struct twl4030_usb *twl = phy_to_twl(x);
615
616 if (suspend)
617 twl4030_phy_suspend(twl, 1);
618 else
619 twl4030_phy_resume(twl);
620
621 return 0;
622}
623
624static int twl4030_set_peripheral(struct usb_otg *otg,
625 struct usb_gadget *gadget)
626{
627 if (!otg)
628 return -ENODEV;
629
630 otg->gadget = gadget;
631 if (!gadget)
632 otg->phy->state = OTG_STATE_UNDEFINED;
633
634 return 0;
635}
636
637static int twl4030_set_host(struct usb_otg *otg, struct usb_bus *host)
638{
639 if (!otg)
640 return -ENODEV;
641
642 otg->host = host;
643 if (!host)
644 otg->phy->state = OTG_STATE_UNDEFINED;
645
646 return 0;
647}
648
649static int twl4030_usb_probe(struct platform_device *pdev)
650{
651 struct twl4030_usb_data *pdata = pdev->dev.platform_data;
652 struct twl4030_usb *twl;
653 int status, err;
654 struct usb_otg *otg;
655 struct device_node *np = pdev->dev.of_node;
656
657 twl = devm_kzalloc(&pdev->dev, sizeof *twl, GFP_KERNEL);
658 if (!twl)
659 return -ENOMEM;
660
661 if (np)
662 of_property_read_u32(np, "usb_mode",
663 (enum twl4030_usb_mode *)&twl->usb_mode);
664 else if (pdata)
665 twl->usb_mode = pdata->usb_mode;
666 else {
667 dev_err(&pdev->dev, "twl4030 initialized without pdata\n");
668 return -EINVAL;
669 }
670
671 otg = devm_kzalloc(&pdev->dev, sizeof *otg, GFP_KERNEL);
672 if (!otg)
673 return -ENOMEM;
674
675 twl->dev = &pdev->dev;
676 twl->irq = platform_get_irq(pdev, 0);
677 twl->vbus_supplied = false;
678 twl->asleep = 1;
679 twl->linkstat = OMAP_MUSB_UNKNOWN;
680
681 twl->phy.dev = twl->dev;
682 twl->phy.label = "twl4030";
683 twl->phy.otg = otg;
684 twl->phy.type = USB_PHY_TYPE_USB2;
685 twl->phy.set_suspend = twl4030_set_suspend;
686 twl->phy.init = twl4030_usb_phy_init;
687
688 otg->phy = &twl->phy;
689 otg->set_host = twl4030_set_host;
690 otg->set_peripheral = twl4030_set_peripheral;
691
692 /* init spinlock for workqueue */
693 spin_lock_init(&twl->lock);
694
695 INIT_DELAYED_WORK(&twl->id_workaround_work, twl4030_id_workaround_work);
696
697 err = twl4030_usb_ldo_init(twl);
698 if (err) {
699 dev_err(&pdev->dev, "ldo init failed\n");
700 return err;
701 }
702 usb_add_phy_dev(&twl->phy);
703
704 platform_set_drvdata(pdev, twl);
705 if (device_create_file(&pdev->dev, &dev_attr_vbus))
706 dev_warn(&pdev->dev, "could not create sysfs file\n");
707
708 /* Our job is to use irqs and status from the power module
709 * to keep the transceiver disabled when nothing's connected.
710 *
711 * FIXME we actually shouldn't start enabling it until the
712 * USB controller drivers have said they're ready, by calling
713 * set_host() and/or set_peripheral() ... OTG_capable boards
714 * need both handles, otherwise just one suffices.
715 */
716 twl->irq_enabled = true;
717 status = devm_request_threaded_irq(twl->dev, twl->irq, NULL,
718 twl4030_usb_irq, IRQF_TRIGGER_FALLING |
719 IRQF_TRIGGER_RISING | IRQF_ONESHOT, "twl4030_usb", twl);
720 if (status < 0) {
721 dev_dbg(&pdev->dev, "can't get IRQ %d, err %d\n",
722 twl->irq, status);
723 return status;
724 }
725
726 dev_info(&pdev->dev, "Initialized TWL4030 USB module\n");
727 return 0;
728}
729
730static int twl4030_usb_remove(struct platform_device *pdev)
731{
732 struct twl4030_usb *twl = platform_get_drvdata(pdev);
733 int val;
734
735 cancel_delayed_work(&twl->id_workaround_work);
736 device_remove_file(twl->dev, &dev_attr_vbus);
737
738 /* set transceiver mode to power on defaults */
739 twl4030_usb_set_mode(twl, -1);
740
741 /* autogate 60MHz ULPI clock,
742 * clear dpll clock request for i2c access,
743 * disable 32KHz
744 */
745 val = twl4030_usb_read(twl, PHY_CLK_CTRL);
746 if (val >= 0) {
747 val |= PHY_CLK_CTRL_CLOCKGATING_EN;
748 val &= ~(PHY_CLK_CTRL_CLK32K_EN | REQ_PHY_DPLL_CLK);
749 twl4030_usb_write(twl, PHY_CLK_CTRL, (u8)val);
750 }
751
752 /* disable complete OTG block */
753 twl4030_usb_clear_bits(twl, POWER_CTRL, POWER_CTRL_OTG_ENAB);
754
755 if (!twl->asleep)
756 twl4030_phy_power(twl, 0);
757
758 return 0;
759}
760
761#ifdef CONFIG_OF
762static const struct of_device_id twl4030_usb_id_table[] = {
763 { .compatible = "ti,twl4030-usb" },
764 {}
765};
766MODULE_DEVICE_TABLE(of, twl4030_usb_id_table);
767#endif
768
769static struct platform_driver twl4030_usb_driver = {
770 .probe = twl4030_usb_probe,
771 .remove = twl4030_usb_remove,
772 .driver = {
773 .name = "twl4030_usb",
774 .owner = THIS_MODULE,
775 .of_match_table = of_match_ptr(twl4030_usb_id_table),
776 },
777};
778
779static int __init twl4030_usb_init(void)
780{
781 return platform_driver_register(&twl4030_usb_driver);
782}
783subsys_initcall(twl4030_usb_init);
784
785static void __exit twl4030_usb_exit(void)
786{
787 platform_driver_unregister(&twl4030_usb_driver);
788}
789module_exit(twl4030_usb_exit);
790
791MODULE_ALIAS("platform:twl4030_usb");
792MODULE_AUTHOR("Texas Instruments, Inc, Nokia Corporation");
793MODULE_DESCRIPTION("TWL4030 USB transceiver driver");
794MODULE_LICENSE("GPL");
diff --git a/drivers/usb/phy/phy-twl6030-usb.c b/drivers/usb/phy/phy-twl6030-usb.c
new file mode 100644
index 000000000000..9de7ada90a8b
--- /dev/null
+++ b/drivers/usb/phy/phy-twl6030-usb.c
@@ -0,0 +1,453 @@
1/*
2 * twl6030_usb - TWL6030 USB transceiver, talking to OMAP OTG driver.
3 *
4 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * Author: Hema HK <hemahk@ti.com>
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 *
21 */
22
23#include <linux/module.h>
24#include <linux/init.h>
25#include <linux/interrupt.h>
26#include <linux/platform_device.h>
27#include <linux/io.h>
28#include <linux/usb/musb-omap.h>
29#include <linux/usb/phy_companion.h>
30#include <linux/usb/omap_usb.h>
31#include <linux/i2c/twl.h>
32#include <linux/regulator/consumer.h>
33#include <linux/err.h>
34#include <linux/slab.h>
35#include <linux/delay.h>
36
37/* usb register definitions */
38#define USB_VENDOR_ID_LSB 0x00
39#define USB_VENDOR_ID_MSB 0x01
40#define USB_PRODUCT_ID_LSB 0x02
41#define USB_PRODUCT_ID_MSB 0x03
42#define USB_VBUS_CTRL_SET 0x04
43#define USB_VBUS_CTRL_CLR 0x05
44#define USB_ID_CTRL_SET 0x06
45#define USB_ID_CTRL_CLR 0x07
46#define USB_VBUS_INT_SRC 0x08
47#define USB_VBUS_INT_LATCH_SET 0x09
48#define USB_VBUS_INT_LATCH_CLR 0x0A
49#define USB_VBUS_INT_EN_LO_SET 0x0B
50#define USB_VBUS_INT_EN_LO_CLR 0x0C
51#define USB_VBUS_INT_EN_HI_SET 0x0D
52#define USB_VBUS_INT_EN_HI_CLR 0x0E
53#define USB_ID_INT_SRC 0x0F
54#define USB_ID_INT_LATCH_SET 0x10
55#define USB_ID_INT_LATCH_CLR 0x11
56
57#define USB_ID_INT_EN_LO_SET 0x12
58#define USB_ID_INT_EN_LO_CLR 0x13
59#define USB_ID_INT_EN_HI_SET 0x14
60#define USB_ID_INT_EN_HI_CLR 0x15
61#define USB_OTG_ADP_CTRL 0x16
62#define USB_OTG_ADP_HIGH 0x17
63#define USB_OTG_ADP_LOW 0x18
64#define USB_OTG_ADP_RISE 0x19
65#define USB_OTG_REVISION 0x1A
66
67/* to be moved to LDO */
68#define TWL6030_MISC2 0xE5
69#define TWL6030_CFG_LDO_PD2 0xF5
70#define TWL6030_BACKUP_REG 0xFA
71
72#define STS_HW_CONDITIONS 0x21
73
74/* In module TWL6030_MODULE_PM_MASTER */
75#define STS_HW_CONDITIONS 0x21
76#define STS_USB_ID BIT(2)
77
78/* In module TWL6030_MODULE_PM_RECEIVER */
79#define VUSB_CFG_TRANS 0x71
80#define VUSB_CFG_STATE 0x72
81#define VUSB_CFG_VOLTAGE 0x73
82
83/* in module TWL6030_MODULE_MAIN_CHARGE */
84
85#define CHARGERUSB_CTRL1 0x8
86
87#define CONTROLLER_STAT1 0x03
88#define VBUS_DET BIT(2)
89
90struct twl6030_usb {
91 struct phy_companion comparator;
92 struct device *dev;
93
94 /* for vbus reporting with irqs disabled */
95 spinlock_t lock;
96
97 struct regulator *usb3v3;
98
99 /* used to set vbus, in atomic path */
100 struct work_struct set_vbus_work;
101
102 int irq1;
103 int irq2;
104 enum omap_musb_vbus_id_status linkstat;
105 u8 asleep;
106 bool irq_enabled;
107 bool vbus_enable;
108 const char *regulator;
109};
110
111#define comparator_to_twl(x) container_of((x), struct twl6030_usb, comparator)
112
113/*-------------------------------------------------------------------------*/
114
115static inline int twl6030_writeb(struct twl6030_usb *twl, u8 module,
116 u8 data, u8 address)
117{
118 int ret = 0;
119
120 ret = twl_i2c_write_u8(module, data, address);
121 if (ret < 0)
122 dev_err(twl->dev,
123 "Write[0x%x] Error %d\n", address, ret);
124 return ret;
125}
126
127static inline u8 twl6030_readb(struct twl6030_usb *twl, u8 module, u8 address)
128{
129 u8 data, ret = 0;
130
131 ret = twl_i2c_read_u8(module, &data, address);
132 if (ret >= 0)
133 ret = data;
134 else
135 dev_err(twl->dev,
136 "readb[0x%x,0x%x] Error %d\n",
137 module, address, ret);
138 return ret;
139}
140
141static int twl6030_start_srp(struct phy_companion *comparator)
142{
143 struct twl6030_usb *twl = comparator_to_twl(comparator);
144
145 twl6030_writeb(twl, TWL_MODULE_USB, 0x24, USB_VBUS_CTRL_SET);
146 twl6030_writeb(twl, TWL_MODULE_USB, 0x84, USB_VBUS_CTRL_SET);
147
148 mdelay(100);
149 twl6030_writeb(twl, TWL_MODULE_USB, 0xa0, USB_VBUS_CTRL_CLR);
150
151 return 0;
152}
153
154static int twl6030_usb_ldo_init(struct twl6030_usb *twl)
155{
156 /* Set to OTG_REV 1.3 and turn on the ID_WAKEUP_COMP */
157 twl6030_writeb(twl, TWL6030_MODULE_ID0 , 0x1, TWL6030_BACKUP_REG);
158
159 /* Program CFG_LDO_PD2 register and set VUSB bit */
160 twl6030_writeb(twl, TWL6030_MODULE_ID0 , 0x1, TWL6030_CFG_LDO_PD2);
161
162 /* Program MISC2 register and set bit VUSB_IN_VBAT */
163 twl6030_writeb(twl, TWL6030_MODULE_ID0 , 0x10, TWL6030_MISC2);
164
165 twl->usb3v3 = regulator_get(twl->dev, twl->regulator);
166 if (IS_ERR(twl->usb3v3))
167 return -ENODEV;
168
169 /* Program the USB_VBUS_CTRL_SET and set VBUS_ACT_COMP bit */
170 twl6030_writeb(twl, TWL_MODULE_USB, 0x4, USB_VBUS_CTRL_SET);
171
172 /*
173 * Program the USB_ID_CTRL_SET register to enable GND drive
174 * and the ID comparators
175 */
176 twl6030_writeb(twl, TWL_MODULE_USB, 0x14, USB_ID_CTRL_SET);
177
178 return 0;
179}
180
181static ssize_t twl6030_usb_vbus_show(struct device *dev,
182 struct device_attribute *attr, char *buf)
183{
184 struct twl6030_usb *twl = dev_get_drvdata(dev);
185 unsigned long flags;
186 int ret = -EINVAL;
187
188 spin_lock_irqsave(&twl->lock, flags);
189
190 switch (twl->linkstat) {
191 case OMAP_MUSB_VBUS_VALID:
192 ret = snprintf(buf, PAGE_SIZE, "vbus\n");
193 break;
194 case OMAP_MUSB_ID_GROUND:
195 ret = snprintf(buf, PAGE_SIZE, "id\n");
196 break;
197 case OMAP_MUSB_VBUS_OFF:
198 ret = snprintf(buf, PAGE_SIZE, "none\n");
199 break;
200 default:
201 ret = snprintf(buf, PAGE_SIZE, "UNKNOWN\n");
202 }
203 spin_unlock_irqrestore(&twl->lock, flags);
204
205 return ret;
206}
207static DEVICE_ATTR(vbus, 0444, twl6030_usb_vbus_show, NULL);
208
209static irqreturn_t twl6030_usb_irq(int irq, void *_twl)
210{
211 struct twl6030_usb *twl = _twl;
212 enum omap_musb_vbus_id_status status = OMAP_MUSB_UNKNOWN;
213 u8 vbus_state, hw_state;
214 int ret;
215
216 hw_state = twl6030_readb(twl, TWL6030_MODULE_ID0, STS_HW_CONDITIONS);
217
218 vbus_state = twl6030_readb(twl, TWL_MODULE_MAIN_CHARGE,
219 CONTROLLER_STAT1);
220 if (!(hw_state & STS_USB_ID)) {
221 if (vbus_state & VBUS_DET) {
222 ret = regulator_enable(twl->usb3v3);
223 if (ret)
224 dev_err(twl->dev, "Failed to enable usb3v3\n");
225
226 twl->asleep = 1;
227 status = OMAP_MUSB_VBUS_VALID;
228 twl->linkstat = status;
229 omap_musb_mailbox(status);
230 } else {
231 if (twl->linkstat != OMAP_MUSB_UNKNOWN) {
232 status = OMAP_MUSB_VBUS_OFF;
233 twl->linkstat = status;
234 omap_musb_mailbox(status);
235 if (twl->asleep) {
236 regulator_disable(twl->usb3v3);
237 twl->asleep = 0;
238 }
239 }
240 }
241 }
242 sysfs_notify(&twl->dev->kobj, NULL, "vbus");
243
244 return IRQ_HANDLED;
245}
246
247static irqreturn_t twl6030_usbotg_irq(int irq, void *_twl)
248{
249 struct twl6030_usb *twl = _twl;
250 enum omap_musb_vbus_id_status status = OMAP_MUSB_UNKNOWN;
251 u8 hw_state;
252 int ret;
253
254 hw_state = twl6030_readb(twl, TWL6030_MODULE_ID0, STS_HW_CONDITIONS);
255
256 if (hw_state & STS_USB_ID) {
257 ret = regulator_enable(twl->usb3v3);
258 if (ret)
259 dev_err(twl->dev, "Failed to enable usb3v3\n");
260
261 twl->asleep = 1;
262 twl6030_writeb(twl, TWL_MODULE_USB, 0x1, USB_ID_INT_EN_HI_CLR);
263 twl6030_writeb(twl, TWL_MODULE_USB, 0x10, USB_ID_INT_EN_HI_SET);
264 status = OMAP_MUSB_ID_GROUND;
265 twl->linkstat = status;
266 omap_musb_mailbox(status);
267 } else {
268 twl6030_writeb(twl, TWL_MODULE_USB, 0x10, USB_ID_INT_EN_HI_CLR);
269 twl6030_writeb(twl, TWL_MODULE_USB, 0x1, USB_ID_INT_EN_HI_SET);
270 }
271 twl6030_writeb(twl, TWL_MODULE_USB, status, USB_ID_INT_LATCH_CLR);
272
273 return IRQ_HANDLED;
274}
275
276static int twl6030_enable_irq(struct twl6030_usb *twl)
277{
278 twl6030_writeb(twl, TWL_MODULE_USB, 0x1, USB_ID_INT_EN_HI_SET);
279 twl6030_interrupt_unmask(0x05, REG_INT_MSK_LINE_C);
280 twl6030_interrupt_unmask(0x05, REG_INT_MSK_STS_C);
281
282 twl6030_interrupt_unmask(TWL6030_CHARGER_CTRL_INT_MASK,
283 REG_INT_MSK_LINE_C);
284 twl6030_interrupt_unmask(TWL6030_CHARGER_CTRL_INT_MASK,
285 REG_INT_MSK_STS_C);
286 twl6030_usb_irq(twl->irq2, twl);
287 twl6030_usbotg_irq(twl->irq1, twl);
288
289 return 0;
290}
291
292static void otg_set_vbus_work(struct work_struct *data)
293{
294 struct twl6030_usb *twl = container_of(data, struct twl6030_usb,
295 set_vbus_work);
296
297 /*
298 * Start driving VBUS. Set OPA_MODE bit in CHARGERUSB_CTRL1
299 * register. This enables boost mode.
300 */
301
302 if (twl->vbus_enable)
303 twl6030_writeb(twl, TWL_MODULE_MAIN_CHARGE , 0x40,
304 CHARGERUSB_CTRL1);
305 else
306 twl6030_writeb(twl, TWL_MODULE_MAIN_CHARGE , 0x00,
307 CHARGERUSB_CTRL1);
308}
309
310static int twl6030_set_vbus(struct phy_companion *comparator, bool enabled)
311{
312 struct twl6030_usb *twl = comparator_to_twl(comparator);
313
314 twl->vbus_enable = enabled;
315 schedule_work(&twl->set_vbus_work);
316
317 return 0;
318}
319
320static int twl6030_usb_probe(struct platform_device *pdev)
321{
322 u32 ret;
323 struct twl6030_usb *twl;
324 int status, err;
325 struct device_node *np = pdev->dev.of_node;
326 struct device *dev = &pdev->dev;
327 struct twl4030_usb_data *pdata = dev->platform_data;
328
329 twl = devm_kzalloc(dev, sizeof *twl, GFP_KERNEL);
330 if (!twl)
331 return -ENOMEM;
332
333 twl->dev = &pdev->dev;
334 twl->irq1 = platform_get_irq(pdev, 0);
335 twl->irq2 = platform_get_irq(pdev, 1);
336 twl->linkstat = OMAP_MUSB_UNKNOWN;
337
338 twl->comparator.set_vbus = twl6030_set_vbus;
339 twl->comparator.start_srp = twl6030_start_srp;
340
341 ret = omap_usb2_set_comparator(&twl->comparator);
342 if (ret == -ENODEV) {
343 dev_info(&pdev->dev, "phy not ready, deferring probe");
344 return -EPROBE_DEFER;
345 }
346
347 if (np) {
348 twl->regulator = "usb";
349 } else if (pdata) {
350 if (pdata->features & TWL6025_SUBCLASS)
351 twl->regulator = "ldousb";
352 else
353 twl->regulator = "vusb";
354 } else {
355 dev_err(&pdev->dev, "twl6030 initialized without pdata\n");
356 return -EINVAL;
357 }
358
359 /* init spinlock for workqueue */
360 spin_lock_init(&twl->lock);
361
362 err = twl6030_usb_ldo_init(twl);
363 if (err) {
364 dev_err(&pdev->dev, "ldo init failed\n");
365 return err;
366 }
367
368 platform_set_drvdata(pdev, twl);
369 if (device_create_file(&pdev->dev, &dev_attr_vbus))
370 dev_warn(&pdev->dev, "could not create sysfs file\n");
371
372 INIT_WORK(&twl->set_vbus_work, otg_set_vbus_work);
373
374 twl->irq_enabled = true;
375 status = request_threaded_irq(twl->irq1, NULL, twl6030_usbotg_irq,
376 IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING | IRQF_ONESHOT,
377 "twl6030_usb", twl);
378 if (status < 0) {
379 dev_err(&pdev->dev, "can't get IRQ %d, err %d\n",
380 twl->irq1, status);
381 device_remove_file(twl->dev, &dev_attr_vbus);
382 return status;
383 }
384
385 status = request_threaded_irq(twl->irq2, NULL, twl6030_usb_irq,
386 IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING | IRQF_ONESHOT,
387 "twl6030_usb", twl);
388 if (status < 0) {
389 dev_err(&pdev->dev, "can't get IRQ %d, err %d\n",
390 twl->irq2, status);
391 free_irq(twl->irq1, twl);
392 device_remove_file(twl->dev, &dev_attr_vbus);
393 return status;
394 }
395
396 twl->asleep = 0;
397 twl6030_enable_irq(twl);
398 dev_info(&pdev->dev, "Initialized TWL6030 USB module\n");
399
400 return 0;
401}
402
403static int twl6030_usb_remove(struct platform_device *pdev)
404{
405 struct twl6030_usb *twl = platform_get_drvdata(pdev);
406
407 twl6030_interrupt_mask(TWL6030_USBOTG_INT_MASK,
408 REG_INT_MSK_LINE_C);
409 twl6030_interrupt_mask(TWL6030_USBOTG_INT_MASK,
410 REG_INT_MSK_STS_C);
411 free_irq(twl->irq1, twl);
412 free_irq(twl->irq2, twl);
413 regulator_put(twl->usb3v3);
414 device_remove_file(twl->dev, &dev_attr_vbus);
415 cancel_work_sync(&twl->set_vbus_work);
416
417 return 0;
418}
419
420#ifdef CONFIG_OF
421static const struct of_device_id twl6030_usb_id_table[] = {
422 { .compatible = "ti,twl6030-usb" },
423 {}
424};
425MODULE_DEVICE_TABLE(of, twl6030_usb_id_table);
426#endif
427
428static struct platform_driver twl6030_usb_driver = {
429 .probe = twl6030_usb_probe,
430 .remove = twl6030_usb_remove,
431 .driver = {
432 .name = "twl6030_usb",
433 .owner = THIS_MODULE,
434 .of_match_table = of_match_ptr(twl6030_usb_id_table),
435 },
436};
437
438static int __init twl6030_usb_init(void)
439{
440 return platform_driver_register(&twl6030_usb_driver);
441}
442subsys_initcall(twl6030_usb_init);
443
444static void __exit twl6030_usb_exit(void)
445{
446 platform_driver_unregister(&twl6030_usb_driver);
447}
448module_exit(twl6030_usb_exit);
449
450MODULE_ALIAS("platform:twl6030_usb");
451MODULE_AUTHOR("Hema HK <hemahk@ti.com>");
452MODULE_DESCRIPTION("TWL6030 USB transceiver driver");
453MODULE_LICENSE("GPL");
diff --git a/drivers/usb/phy/phy-ulpi-viewport.c b/drivers/usb/phy/phy-ulpi-viewport.c
new file mode 100644
index 000000000000..c5ba7e5423fc
--- /dev/null
+++ b/drivers/usb/phy/phy-ulpi-viewport.c
@@ -0,0 +1,80 @@
1/*
2 * Copyright (C) 2011 Google, Inc.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 */
14
15#include <linux/kernel.h>
16#include <linux/usb.h>
17#include <linux/io.h>
18#include <linux/usb/otg.h>
19#include <linux/usb/ulpi.h>
20
21#define ULPI_VIEW_WAKEUP (1 << 31)
22#define ULPI_VIEW_RUN (1 << 30)
23#define ULPI_VIEW_WRITE (1 << 29)
24#define ULPI_VIEW_READ (0 << 29)
25#define ULPI_VIEW_ADDR(x) (((x) & 0xff) << 16)
26#define ULPI_VIEW_DATA_READ(x) (((x) >> 8) & 0xff)
27#define ULPI_VIEW_DATA_WRITE(x) ((x) & 0xff)
28
29static int ulpi_viewport_wait(void __iomem *view, u32 mask)
30{
31 unsigned long usec = 2000;
32
33 while (usec--) {
34 if (!(readl(view) & mask))
35 return 0;
36
37 udelay(1);
38 };
39
40 return -ETIMEDOUT;
41}
42
43static int ulpi_viewport_read(struct usb_phy *otg, u32 reg)
44{
45 int ret;
46 void __iomem *view = otg->io_priv;
47
48 writel(ULPI_VIEW_WAKEUP | ULPI_VIEW_WRITE, view);
49 ret = ulpi_viewport_wait(view, ULPI_VIEW_WAKEUP);
50 if (ret)
51 return ret;
52
53 writel(ULPI_VIEW_RUN | ULPI_VIEW_READ | ULPI_VIEW_ADDR(reg), view);
54 ret = ulpi_viewport_wait(view, ULPI_VIEW_RUN);
55 if (ret)
56 return ret;
57
58 return ULPI_VIEW_DATA_READ(readl(view));
59}
60
61static int ulpi_viewport_write(struct usb_phy *otg, u32 val, u32 reg)
62{
63 int ret;
64 void __iomem *view = otg->io_priv;
65
66 writel(ULPI_VIEW_WAKEUP | ULPI_VIEW_WRITE, view);
67 ret = ulpi_viewport_wait(view, ULPI_VIEW_WAKEUP);
68 if (ret)
69 return ret;
70
71 writel(ULPI_VIEW_RUN | ULPI_VIEW_WRITE | ULPI_VIEW_DATA_WRITE(val) |
72 ULPI_VIEW_ADDR(reg), view);
73
74 return ulpi_viewport_wait(view, ULPI_VIEW_RUN);
75}
76
77struct usb_phy_io_ops ulpi_viewport_access_ops = {
78 .read = ulpi_viewport_read,
79 .write = ulpi_viewport_write,
80};
diff --git a/drivers/usb/phy/phy-ulpi.c b/drivers/usb/phy/phy-ulpi.c
new file mode 100644
index 000000000000..217339dd7a90
--- /dev/null
+++ b/drivers/usb/phy/phy-ulpi.c
@@ -0,0 +1,283 @@
1/*
2 * Generic ULPI USB transceiver support
3 *
4 * Copyright (C) 2009 Daniel Mack <daniel@caiaq.de>
5 *
6 * Based on sources from
7 *
8 * Sascha Hauer <s.hauer@pengutronix.de>
9 * Freescale Semiconductors
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25
26#include <linux/kernel.h>
27#include <linux/slab.h>
28#include <linux/export.h>
29#include <linux/usb.h>
30#include <linux/usb/otg.h>
31#include <linux/usb/ulpi.h>
32
33
34struct ulpi_info {
35 unsigned int id;
36 char *name;
37};
38
39#define ULPI_ID(vendor, product) (((vendor) << 16) | (product))
40#define ULPI_INFO(_id, _name) \
41 { \
42 .id = (_id), \
43 .name = (_name), \
44 }
45
46/* ULPI hardcoded IDs, used for probing */
47static struct ulpi_info ulpi_ids[] = {
48 ULPI_INFO(ULPI_ID(0x04cc, 0x1504), "NXP ISP1504"),
49 ULPI_INFO(ULPI_ID(0x0424, 0x0006), "SMSC USB331x"),
50};
51
52static int ulpi_set_otg_flags(struct usb_phy *phy)
53{
54 unsigned int flags = ULPI_OTG_CTRL_DP_PULLDOWN |
55 ULPI_OTG_CTRL_DM_PULLDOWN;
56
57 if (phy->flags & ULPI_OTG_ID_PULLUP)
58 flags |= ULPI_OTG_CTRL_ID_PULLUP;
59
60 /*
61 * ULPI Specification rev.1.1 default
62 * for Dp/DmPulldown is enabled.
63 */
64 if (phy->flags & ULPI_OTG_DP_PULLDOWN_DIS)
65 flags &= ~ULPI_OTG_CTRL_DP_PULLDOWN;
66
67 if (phy->flags & ULPI_OTG_DM_PULLDOWN_DIS)
68 flags &= ~ULPI_OTG_CTRL_DM_PULLDOWN;
69
70 if (phy->flags & ULPI_OTG_EXTVBUSIND)
71 flags |= ULPI_OTG_CTRL_EXTVBUSIND;
72
73 return usb_phy_io_write(phy, flags, ULPI_OTG_CTRL);
74}
75
76static int ulpi_set_fc_flags(struct usb_phy *phy)
77{
78 unsigned int flags = 0;
79
80 /*
81 * ULPI Specification rev.1.1 default
82 * for XcvrSelect is Full Speed.
83 */
84 if (phy->flags & ULPI_FC_HS)
85 flags |= ULPI_FUNC_CTRL_HIGH_SPEED;
86 else if (phy->flags & ULPI_FC_LS)
87 flags |= ULPI_FUNC_CTRL_LOW_SPEED;
88 else if (phy->flags & ULPI_FC_FS4LS)
89 flags |= ULPI_FUNC_CTRL_FS4LS;
90 else
91 flags |= ULPI_FUNC_CTRL_FULL_SPEED;
92
93 if (phy->flags & ULPI_FC_TERMSEL)
94 flags |= ULPI_FUNC_CTRL_TERMSELECT;
95
96 /*
97 * ULPI Specification rev.1.1 default
98 * for OpMode is Normal Operation.
99 */
100 if (phy->flags & ULPI_FC_OP_NODRV)
101 flags |= ULPI_FUNC_CTRL_OPMODE_NONDRIVING;
102 else if (phy->flags & ULPI_FC_OP_DIS_NRZI)
103 flags |= ULPI_FUNC_CTRL_OPMODE_DISABLE_NRZI;
104 else if (phy->flags & ULPI_FC_OP_NSYNC_NEOP)
105 flags |= ULPI_FUNC_CTRL_OPMODE_NOSYNC_NOEOP;
106 else
107 flags |= ULPI_FUNC_CTRL_OPMODE_NORMAL;
108
109 /*
110 * ULPI Specification rev.1.1 default
111 * for SuspendM is Powered.
112 */
113 flags |= ULPI_FUNC_CTRL_SUSPENDM;
114
115 return usb_phy_io_write(phy, flags, ULPI_FUNC_CTRL);
116}
117
118static int ulpi_set_ic_flags(struct usb_phy *phy)
119{
120 unsigned int flags = 0;
121
122 if (phy->flags & ULPI_IC_AUTORESUME)
123 flags |= ULPI_IFC_CTRL_AUTORESUME;
124
125 if (phy->flags & ULPI_IC_EXTVBUS_INDINV)
126 flags |= ULPI_IFC_CTRL_EXTERNAL_VBUS;
127
128 if (phy->flags & ULPI_IC_IND_PASSTHRU)
129 flags |= ULPI_IFC_CTRL_PASSTHRU;
130
131 if (phy->flags & ULPI_IC_PROTECT_DIS)
132 flags |= ULPI_IFC_CTRL_PROTECT_IFC_DISABLE;
133
134 return usb_phy_io_write(phy, flags, ULPI_IFC_CTRL);
135}
136
137static int ulpi_set_flags(struct usb_phy *phy)
138{
139 int ret;
140
141 ret = ulpi_set_otg_flags(phy);
142 if (ret)
143 return ret;
144
145 ret = ulpi_set_ic_flags(phy);
146 if (ret)
147 return ret;
148
149 return ulpi_set_fc_flags(phy);
150}
151
152static int ulpi_check_integrity(struct usb_phy *phy)
153{
154 int ret, i;
155 unsigned int val = 0x55;
156
157 for (i = 0; i < 2; i++) {
158 ret = usb_phy_io_write(phy, val, ULPI_SCRATCH);
159 if (ret < 0)
160 return ret;
161
162 ret = usb_phy_io_read(phy, ULPI_SCRATCH);
163 if (ret < 0)
164 return ret;
165
166 if (ret != val) {
167 pr_err("ULPI integrity check: failed!");
168 return -ENODEV;
169 }
170 val = val << 1;
171 }
172
173 pr_info("ULPI integrity check: passed.\n");
174
175 return 0;
176}
177
178static int ulpi_init(struct usb_phy *phy)
179{
180 int i, vid, pid, ret;
181 u32 ulpi_id = 0;
182
183 for (i = 0; i < 4; i++) {
184 ret = usb_phy_io_read(phy, ULPI_PRODUCT_ID_HIGH - i);
185 if (ret < 0)
186 return ret;
187 ulpi_id = (ulpi_id << 8) | ret;
188 }
189 vid = ulpi_id & 0xffff;
190 pid = ulpi_id >> 16;
191
192 pr_info("ULPI transceiver vendor/product ID 0x%04x/0x%04x\n", vid, pid);
193
194 for (i = 0; i < ARRAY_SIZE(ulpi_ids); i++) {
195 if (ulpi_ids[i].id == ULPI_ID(vid, pid)) {
196 pr_info("Found %s ULPI transceiver.\n",
197 ulpi_ids[i].name);
198 break;
199 }
200 }
201
202 ret = ulpi_check_integrity(phy);
203 if (ret)
204 return ret;
205
206 return ulpi_set_flags(phy);
207}
208
209static int ulpi_set_host(struct usb_otg *otg, struct usb_bus *host)
210{
211 struct usb_phy *phy = otg->phy;
212 unsigned int flags = usb_phy_io_read(phy, ULPI_IFC_CTRL);
213
214 if (!host) {
215 otg->host = NULL;
216 return 0;
217 }
218
219 otg->host = host;
220
221 flags &= ~(ULPI_IFC_CTRL_6_PIN_SERIAL_MODE |
222 ULPI_IFC_CTRL_3_PIN_SERIAL_MODE |
223 ULPI_IFC_CTRL_CARKITMODE);
224
225 if (phy->flags & ULPI_IC_6PIN_SERIAL)
226 flags |= ULPI_IFC_CTRL_6_PIN_SERIAL_MODE;
227 else if (phy->flags & ULPI_IC_3PIN_SERIAL)
228 flags |= ULPI_IFC_CTRL_3_PIN_SERIAL_MODE;
229 else if (phy->flags & ULPI_IC_CARKIT)
230 flags |= ULPI_IFC_CTRL_CARKITMODE;
231
232 return usb_phy_io_write(phy, flags, ULPI_IFC_CTRL);
233}
234
235static int ulpi_set_vbus(struct usb_otg *otg, bool on)
236{
237 struct usb_phy *phy = otg->phy;
238 unsigned int flags = usb_phy_io_read(phy, ULPI_OTG_CTRL);
239
240 flags &= ~(ULPI_OTG_CTRL_DRVVBUS | ULPI_OTG_CTRL_DRVVBUS_EXT);
241
242 if (on) {
243 if (phy->flags & ULPI_OTG_DRVVBUS)
244 flags |= ULPI_OTG_CTRL_DRVVBUS;
245
246 if (phy->flags & ULPI_OTG_DRVVBUS_EXT)
247 flags |= ULPI_OTG_CTRL_DRVVBUS_EXT;
248 }
249
250 return usb_phy_io_write(phy, flags, ULPI_OTG_CTRL);
251}
252
253struct usb_phy *
254otg_ulpi_create(struct usb_phy_io_ops *ops,
255 unsigned int flags)
256{
257 struct usb_phy *phy;
258 struct usb_otg *otg;
259
260 phy = kzalloc(sizeof(*phy), GFP_KERNEL);
261 if (!phy)
262 return NULL;
263
264 otg = kzalloc(sizeof(*otg), GFP_KERNEL);
265 if (!otg) {
266 kfree(phy);
267 return NULL;
268 }
269
270 phy->label = "ULPI";
271 phy->flags = flags;
272 phy->io_ops = ops;
273 phy->otg = otg;
274 phy->init = ulpi_init;
275
276 otg->phy = phy;
277 otg->set_host = ulpi_set_host;
278 otg->set_vbus = ulpi_set_vbus;
279
280 return phy;
281}
282EXPORT_SYMBOL_GPL(otg_ulpi_create);
283
diff --git a/drivers/usb/phy/phy.c b/drivers/usb/phy/phy.c
new file mode 100644
index 000000000000..f52c006417ff
--- /dev/null
+++ b/drivers/usb/phy/phy.c
@@ -0,0 +1,438 @@
1/*
2 * phy.c -- USB phy handling
3 *
4 * Copyright (C) 2004-2013 Texas Instruments
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11#include <linux/kernel.h>
12#include <linux/export.h>
13#include <linux/err.h>
14#include <linux/device.h>
15#include <linux/module.h>
16#include <linux/slab.h>
17#include <linux/of.h>
18
19#include <linux/usb/phy.h>
20
21static LIST_HEAD(phy_list);
22static LIST_HEAD(phy_bind_list);
23static DEFINE_SPINLOCK(phy_lock);
24
25static struct usb_phy *__usb_find_phy(struct list_head *list,
26 enum usb_phy_type type)
27{
28 struct usb_phy *phy = NULL;
29
30 list_for_each_entry(phy, list, head) {
31 if (phy->type != type)
32 continue;
33
34 return phy;
35 }
36
37 return ERR_PTR(-ENODEV);
38}
39
40static struct usb_phy *__usb_find_phy_dev(struct device *dev,
41 struct list_head *list, u8 index)
42{
43 struct usb_phy_bind *phy_bind = NULL;
44
45 list_for_each_entry(phy_bind, list, list) {
46 if (!(strcmp(phy_bind->dev_name, dev_name(dev))) &&
47 phy_bind->index == index) {
48 if (phy_bind->phy)
49 return phy_bind->phy;
50 else
51 return ERR_PTR(-EPROBE_DEFER);
52 }
53 }
54
55 return ERR_PTR(-ENODEV);
56}
57
58static struct usb_phy *__of_usb_find_phy(struct device_node *node)
59{
60 struct usb_phy *phy;
61
62 list_for_each_entry(phy, &phy_list, head) {
63 if (node != phy->dev->of_node)
64 continue;
65
66 return phy;
67 }
68
69 return ERR_PTR(-ENODEV);
70}
71
72static void devm_usb_phy_release(struct device *dev, void *res)
73{
74 struct usb_phy *phy = *(struct usb_phy **)res;
75
76 usb_put_phy(phy);
77}
78
79static int devm_usb_phy_match(struct device *dev, void *res, void *match_data)
80{
81 return res == match_data;
82}
83
84/**
85 * devm_usb_get_phy - find the USB PHY
86 * @dev - device that requests this phy
87 * @type - the type of the phy the controller requires
88 *
89 * Gets the phy using usb_get_phy(), and associates a device with it using
90 * devres. On driver detach, release function is invoked on the devres data,
91 * then, devres data is freed.
92 *
93 * For use by USB host and peripheral drivers.
94 */
95struct usb_phy *devm_usb_get_phy(struct device *dev, enum usb_phy_type type)
96{
97 struct usb_phy **ptr, *phy;
98
99 ptr = devres_alloc(devm_usb_phy_release, sizeof(*ptr), GFP_KERNEL);
100 if (!ptr)
101 return NULL;
102
103 phy = usb_get_phy(type);
104 if (!IS_ERR(phy)) {
105 *ptr = phy;
106 devres_add(dev, ptr);
107 } else
108 devres_free(ptr);
109
110 return phy;
111}
112EXPORT_SYMBOL_GPL(devm_usb_get_phy);
113
114/**
115 * usb_get_phy - find the USB PHY
116 * @type - the type of the phy the controller requires
117 *
118 * Returns the phy driver, after getting a refcount to it; or
119 * -ENODEV if there is no such phy. The caller is responsible for
120 * calling usb_put_phy() to release that count.
121 *
122 * For use by USB host and peripheral drivers.
123 */
124struct usb_phy *usb_get_phy(enum usb_phy_type type)
125{
126 struct usb_phy *phy = NULL;
127 unsigned long flags;
128
129 spin_lock_irqsave(&phy_lock, flags);
130
131 phy = __usb_find_phy(&phy_list, type);
132 if (IS_ERR(phy) || !try_module_get(phy->dev->driver->owner)) {
133 pr_err("unable to find transceiver of type %s\n",
134 usb_phy_type_string(type));
135 goto err0;
136 }
137
138 get_device(phy->dev);
139
140err0:
141 spin_unlock_irqrestore(&phy_lock, flags);
142
143 return phy;
144}
145EXPORT_SYMBOL_GPL(usb_get_phy);
146
147 /**
148 * devm_usb_get_phy_by_phandle - find the USB PHY by phandle
149 * @dev - device that requests this phy
150 * @phandle - name of the property holding the phy phandle value
151 * @index - the index of the phy
152 *
153 * Returns the phy driver associated with the given phandle value,
154 * after getting a refcount to it, -ENODEV if there is no such phy or
155 * -EPROBE_DEFER if there is a phandle to the phy, but the device is
156 * not yet loaded. While at that, it also associates the device with
157 * the phy using devres. On driver detach, release function is invoked
158 * on the devres data, then, devres data is freed.
159 *
160 * For use by USB host and peripheral drivers.
161 */
162struct usb_phy *devm_usb_get_phy_by_phandle(struct device *dev,
163 const char *phandle, u8 index)
164{
165 struct usb_phy *phy = ERR_PTR(-ENOMEM), **ptr;
166 unsigned long flags;
167 struct device_node *node;
168
169 if (!dev->of_node) {
170 dev_dbg(dev, "device does not have a device node entry\n");
171 return ERR_PTR(-EINVAL);
172 }
173
174 node = of_parse_phandle(dev->of_node, phandle, index);
175 if (!node) {
176 dev_dbg(dev, "failed to get %s phandle in %s node\n", phandle,
177 dev->of_node->full_name);
178 return ERR_PTR(-ENODEV);
179 }
180
181 ptr = devres_alloc(devm_usb_phy_release, sizeof(*ptr), GFP_KERNEL);
182 if (!ptr) {
183 dev_dbg(dev, "failed to allocate memory for devres\n");
184 goto err0;
185 }
186
187 spin_lock_irqsave(&phy_lock, flags);
188
189 phy = __of_usb_find_phy(node);
190 if (IS_ERR(phy) || !try_module_get(phy->dev->driver->owner)) {
191 phy = ERR_PTR(-EPROBE_DEFER);
192 devres_free(ptr);
193 goto err1;
194 }
195
196 *ptr = phy;
197 devres_add(dev, ptr);
198
199 get_device(phy->dev);
200
201err1:
202 spin_unlock_irqrestore(&phy_lock, flags);
203
204err0:
205 of_node_put(node);
206
207 return phy;
208}
209EXPORT_SYMBOL_GPL(devm_usb_get_phy_by_phandle);
210
211/**
212 * usb_get_phy_dev - find the USB PHY
213 * @dev - device that requests this phy
214 * @index - the index of the phy
215 *
216 * Returns the phy driver, after getting a refcount to it; or
217 * -ENODEV if there is no such phy. The caller is responsible for
218 * calling usb_put_phy() to release that count.
219 *
220 * For use by USB host and peripheral drivers.
221 */
222struct usb_phy *usb_get_phy_dev(struct device *dev, u8 index)
223{
224 struct usb_phy *phy = NULL;
225 unsigned long flags;
226
227 spin_lock_irqsave(&phy_lock, flags);
228
229 phy = __usb_find_phy_dev(dev, &phy_bind_list, index);
230 if (IS_ERR(phy) || !try_module_get(phy->dev->driver->owner)) {
231 pr_err("unable to find transceiver\n");
232 goto err0;
233 }
234
235 get_device(phy->dev);
236
237err0:
238 spin_unlock_irqrestore(&phy_lock, flags);
239
240 return phy;
241}
242EXPORT_SYMBOL_GPL(usb_get_phy_dev);
243
244/**
245 * devm_usb_get_phy_dev - find the USB PHY using device ptr and index
246 * @dev - device that requests this phy
247 * @index - the index of the phy
248 *
249 * Gets the phy using usb_get_phy_dev(), and associates a device with it using
250 * devres. On driver detach, release function is invoked on the devres data,
251 * then, devres data is freed.
252 *
253 * For use by USB host and peripheral drivers.
254 */
255struct usb_phy *devm_usb_get_phy_dev(struct device *dev, u8 index)
256{
257 struct usb_phy **ptr, *phy;
258
259 ptr = devres_alloc(devm_usb_phy_release, sizeof(*ptr), GFP_KERNEL);
260 if (!ptr)
261 return NULL;
262
263 phy = usb_get_phy_dev(dev, index);
264 if (!IS_ERR(phy)) {
265 *ptr = phy;
266 devres_add(dev, ptr);
267 } else
268 devres_free(ptr);
269
270 return phy;
271}
272EXPORT_SYMBOL_GPL(devm_usb_get_phy_dev);
273
274/**
275 * devm_usb_put_phy - release the USB PHY
276 * @dev - device that wants to release this phy
277 * @phy - the phy returned by devm_usb_get_phy()
278 *
279 * destroys the devres associated with this phy and invokes usb_put_phy
280 * to release the phy.
281 *
282 * For use by USB host and peripheral drivers.
283 */
284void devm_usb_put_phy(struct device *dev, struct usb_phy *phy)
285{
286 int r;
287
288 r = devres_destroy(dev, devm_usb_phy_release, devm_usb_phy_match, phy);
289 dev_WARN_ONCE(dev, r, "couldn't find PHY resource\n");
290}
291EXPORT_SYMBOL_GPL(devm_usb_put_phy);
292
293/**
294 * usb_put_phy - release the USB PHY
295 * @x: the phy returned by usb_get_phy()
296 *
297 * Releases a refcount the caller received from usb_get_phy().
298 *
299 * For use by USB host and peripheral drivers.
300 */
301void usb_put_phy(struct usb_phy *x)
302{
303 if (x) {
304 struct module *owner = x->dev->driver->owner;
305
306 put_device(x->dev);
307 module_put(owner);
308 }
309}
310EXPORT_SYMBOL_GPL(usb_put_phy);
311
312/**
313 * usb_add_phy - declare the USB PHY
314 * @x: the USB phy to be used; or NULL
315 * @type - the type of this PHY
316 *
317 * This call is exclusively for use by phy drivers, which
318 * coordinate the activities of drivers for host and peripheral
319 * controllers, and in some cases for VBUS current regulation.
320 */
321int usb_add_phy(struct usb_phy *x, enum usb_phy_type type)
322{
323 int ret = 0;
324 unsigned long flags;
325 struct usb_phy *phy;
326
327 if (x->type != USB_PHY_TYPE_UNDEFINED) {
328 dev_err(x->dev, "not accepting initialized PHY %s\n", x->label);
329 return -EINVAL;
330 }
331
332 spin_lock_irqsave(&phy_lock, flags);
333
334 list_for_each_entry(phy, &phy_list, head) {
335 if (phy->type == type) {
336 ret = -EBUSY;
337 dev_err(x->dev, "transceiver type %s already exists\n",
338 usb_phy_type_string(type));
339 goto out;
340 }
341 }
342
343 x->type = type;
344 list_add_tail(&x->head, &phy_list);
345
346out:
347 spin_unlock_irqrestore(&phy_lock, flags);
348 return ret;
349}
350EXPORT_SYMBOL_GPL(usb_add_phy);
351
352/**
353 * usb_add_phy_dev - declare the USB PHY
354 * @x: the USB phy to be used; or NULL
355 *
356 * This call is exclusively for use by phy drivers, which
357 * coordinate the activities of drivers for host and peripheral
358 * controllers, and in some cases for VBUS current regulation.
359 */
360int usb_add_phy_dev(struct usb_phy *x)
361{
362 struct usb_phy_bind *phy_bind;
363 unsigned long flags;
364
365 if (!x->dev) {
366 dev_err(x->dev, "no device provided for PHY\n");
367 return -EINVAL;
368 }
369
370 spin_lock_irqsave(&phy_lock, flags);
371 list_for_each_entry(phy_bind, &phy_bind_list, list)
372 if (!(strcmp(phy_bind->phy_dev_name, dev_name(x->dev))))
373 phy_bind->phy = x;
374
375 list_add_tail(&x->head, &phy_list);
376
377 spin_unlock_irqrestore(&phy_lock, flags);
378 return 0;
379}
380EXPORT_SYMBOL_GPL(usb_add_phy_dev);
381
382/**
383 * usb_remove_phy - remove the OTG PHY
384 * @x: the USB OTG PHY to be removed;
385 *
386 * This reverts the effects of usb_add_phy
387 */
388void usb_remove_phy(struct usb_phy *x)
389{
390 unsigned long flags;
391 struct usb_phy_bind *phy_bind;
392
393 spin_lock_irqsave(&phy_lock, flags);
394 if (x) {
395 list_for_each_entry(phy_bind, &phy_bind_list, list)
396 if (phy_bind->phy == x)
397 phy_bind->phy = NULL;
398 list_del(&x->head);
399 }
400 spin_unlock_irqrestore(&phy_lock, flags);
401}
402EXPORT_SYMBOL_GPL(usb_remove_phy);
403
404/**
405 * usb_bind_phy - bind the phy and the controller that uses the phy
406 * @dev_name: the device name of the device that will bind to the phy
407 * @index: index to specify the port number
408 * @phy_dev_name: the device name of the phy
409 *
410 * Fills the phy_bind structure with the dev_name and phy_dev_name. This will
411 * be used when the phy driver registers the phy and when the controller
412 * requests this phy.
413 *
414 * To be used by platform specific initialization code.
415 */
416int __init usb_bind_phy(const char *dev_name, u8 index,
417 const char *phy_dev_name)
418{
419 struct usb_phy_bind *phy_bind;
420 unsigned long flags;
421
422 phy_bind = kzalloc(sizeof(*phy_bind), GFP_KERNEL);
423 if (!phy_bind) {
424 pr_err("phy_bind(): No memory for phy_bind");
425 return -ENOMEM;
426 }
427
428 phy_bind->dev_name = dev_name;
429 phy_bind->phy_dev_name = phy_dev_name;
430 phy_bind->index = index;
431
432 spin_lock_irqsave(&phy_lock, flags);
433 list_add_tail(&phy_bind->list, &phy_bind_list);
434 spin_unlock_irqrestore(&phy_lock, flags);
435
436 return 0;
437}
438EXPORT_SYMBOL_GPL(usb_bind_phy);
diff --git a/drivers/usb/phy/samsung-usbphy.c b/drivers/usb/phy/samsung-usbphy.c
deleted file mode 100644
index 967101ec15fd..000000000000
--- a/drivers/usb/phy/samsung-usbphy.c
+++ /dev/null
@@ -1,928 +0,0 @@
1/* linux/drivers/usb/phy/samsung-usbphy.c
2 *
3 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * Author: Praveen Paneri <p.paneri@samsung.com>
7 *
8 * Samsung USB2.0 PHY transceiver; talks to S3C HS OTG controller, EHCI-S5P and
9 * OHCI-EXYNOS controllers.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 */
20
21#include <linux/module.h>
22#include <linux/platform_device.h>
23#include <linux/clk.h>
24#include <linux/delay.h>
25#include <linux/device.h>
26#include <linux/err.h>
27#include <linux/io.h>
28#include <linux/of.h>
29#include <linux/of_address.h>
30#include <linux/usb/otg.h>
31#include <linux/usb/samsung_usb_phy.h>
32#include <linux/platform_data/samsung-usbphy.h>
33
34/* Register definitions */
35
36#define SAMSUNG_PHYPWR (0x00)
37
38#define PHYPWR_NORMAL_MASK (0x19 << 0)
39#define PHYPWR_OTG_DISABLE (0x1 << 4)
40#define PHYPWR_ANALOG_POWERDOWN (0x1 << 3)
41#define PHYPWR_FORCE_SUSPEND (0x1 << 1)
42/* For Exynos4 */
43#define PHYPWR_NORMAL_MASK_PHY0 (0x39 << 0)
44#define PHYPWR_SLEEP_PHY0 (0x1 << 5)
45
46#define SAMSUNG_PHYCLK (0x04)
47
48#define PHYCLK_MODE_USB11 (0x1 << 6)
49#define PHYCLK_EXT_OSC (0x1 << 5)
50#define PHYCLK_COMMON_ON_N (0x1 << 4)
51#define PHYCLK_ID_PULL (0x1 << 2)
52#define PHYCLK_CLKSEL_MASK (0x3 << 0)
53#define PHYCLK_CLKSEL_48M (0x0 << 0)
54#define PHYCLK_CLKSEL_12M (0x2 << 0)
55#define PHYCLK_CLKSEL_24M (0x3 << 0)
56
57#define SAMSUNG_RSTCON (0x08)
58
59#define RSTCON_PHYLINK_SWRST (0x1 << 2)
60#define RSTCON_HLINK_SWRST (0x1 << 1)
61#define RSTCON_SWRST (0x1 << 0)
62
63/* EXYNOS5 */
64#define EXYNOS5_PHY_HOST_CTRL0 (0x00)
65
66#define HOST_CTRL0_PHYSWRSTALL (0x1 << 31)
67
68#define HOST_CTRL0_REFCLKSEL_MASK (0x3 << 19)
69#define HOST_CTRL0_REFCLKSEL_XTAL (0x0 << 19)
70#define HOST_CTRL0_REFCLKSEL_EXTL (0x1 << 19)
71#define HOST_CTRL0_REFCLKSEL_CLKCORE (0x2 << 19)
72
73#define HOST_CTRL0_FSEL_MASK (0x7 << 16)
74#define HOST_CTRL0_FSEL(_x) ((_x) << 16)
75
76#define FSEL_CLKSEL_50M (0x7)
77#define FSEL_CLKSEL_24M (0x5)
78#define FSEL_CLKSEL_20M (0x4)
79#define FSEL_CLKSEL_19200K (0x3)
80#define FSEL_CLKSEL_12M (0x2)
81#define FSEL_CLKSEL_10M (0x1)
82#define FSEL_CLKSEL_9600K (0x0)
83
84#define HOST_CTRL0_TESTBURNIN (0x1 << 11)
85#define HOST_CTRL0_RETENABLE (0x1 << 10)
86#define HOST_CTRL0_COMMONON_N (0x1 << 9)
87#define HOST_CTRL0_SIDDQ (0x1 << 6)
88#define HOST_CTRL0_FORCESLEEP (0x1 << 5)
89#define HOST_CTRL0_FORCESUSPEND (0x1 << 4)
90#define HOST_CTRL0_WORDINTERFACE (0x1 << 3)
91#define HOST_CTRL0_UTMISWRST (0x1 << 2)
92#define HOST_CTRL0_LINKSWRST (0x1 << 1)
93#define HOST_CTRL0_PHYSWRST (0x1 << 0)
94
95#define EXYNOS5_PHY_HOST_TUNE0 (0x04)
96
97#define EXYNOS5_PHY_HSIC_CTRL1 (0x10)
98
99#define EXYNOS5_PHY_HSIC_TUNE1 (0x14)
100
101#define EXYNOS5_PHY_HSIC_CTRL2 (0x20)
102
103#define EXYNOS5_PHY_HSIC_TUNE2 (0x24)
104
105#define HSIC_CTRL_REFCLKSEL_MASK (0x3 << 23)
106#define HSIC_CTRL_REFCLKSEL (0x2 << 23)
107
108#define HSIC_CTRL_REFCLKDIV_MASK (0x7f << 16)
109#define HSIC_CTRL_REFCLKDIV(_x) ((_x) << 16)
110#define HSIC_CTRL_REFCLKDIV_12 (0x24 << 16)
111#define HSIC_CTRL_REFCLKDIV_15 (0x1c << 16)
112#define HSIC_CTRL_REFCLKDIV_16 (0x1a << 16)
113#define HSIC_CTRL_REFCLKDIV_19_2 (0x15 << 16)
114#define HSIC_CTRL_REFCLKDIV_20 (0x14 << 16)
115
116#define HSIC_CTRL_SIDDQ (0x1 << 6)
117#define HSIC_CTRL_FORCESLEEP (0x1 << 5)
118#define HSIC_CTRL_FORCESUSPEND (0x1 << 4)
119#define HSIC_CTRL_WORDINTERFACE (0x1 << 3)
120#define HSIC_CTRL_UTMISWRST (0x1 << 2)
121#define HSIC_CTRL_PHYSWRST (0x1 << 0)
122
123#define EXYNOS5_PHY_HOST_EHCICTRL (0x30)
124
125#define HOST_EHCICTRL_ENAINCRXALIGN (0x1 << 29)
126#define HOST_EHCICTRL_ENAINCR4 (0x1 << 28)
127#define HOST_EHCICTRL_ENAINCR8 (0x1 << 27)
128#define HOST_EHCICTRL_ENAINCR16 (0x1 << 26)
129
130#define EXYNOS5_PHY_HOST_OHCICTRL (0x34)
131
132#define HOST_OHCICTRL_SUSPLGCY (0x1 << 3)
133#define HOST_OHCICTRL_APPSTARTCLK (0x1 << 2)
134#define HOST_OHCICTRL_CNTSEL (0x1 << 1)
135#define HOST_OHCICTRL_CLKCKTRST (0x1 << 0)
136
137#define EXYNOS5_PHY_OTG_SYS (0x38)
138
139#define OTG_SYS_PHYLINK_SWRESET (0x1 << 14)
140#define OTG_SYS_LINKSWRST_UOTG (0x1 << 13)
141#define OTG_SYS_PHY0_SWRST (0x1 << 12)
142
143#define OTG_SYS_REFCLKSEL_MASK (0x3 << 9)
144#define OTG_SYS_REFCLKSEL_XTAL (0x0 << 9)
145#define OTG_SYS_REFCLKSEL_EXTL (0x1 << 9)
146#define OTG_SYS_REFCLKSEL_CLKCORE (0x2 << 9)
147
148#define OTG_SYS_IDPULLUP_UOTG (0x1 << 8)
149#define OTG_SYS_COMMON_ON (0x1 << 7)
150
151#define OTG_SYS_FSEL_MASK (0x7 << 4)
152#define OTG_SYS_FSEL(_x) ((_x) << 4)
153
154#define OTG_SYS_FORCESLEEP (0x1 << 3)
155#define OTG_SYS_OTGDISABLE (0x1 << 2)
156#define OTG_SYS_SIDDQ_UOTG (0x1 << 1)
157#define OTG_SYS_FORCESUSPEND (0x1 << 0)
158
159#define EXYNOS5_PHY_OTG_TUNE (0x40)
160
161#ifndef MHZ
162#define MHZ (1000*1000)
163#endif
164
165#ifndef KHZ
166#define KHZ (1000)
167#endif
168
169#define EXYNOS_USBHOST_PHY_CTRL_OFFSET (0x4)
170#define S3C64XX_USBPHY_ENABLE (0x1 << 16)
171#define EXYNOS_USBPHY_ENABLE (0x1 << 0)
172#define EXYNOS_USB20PHY_CFG_HOST_LINK (0x1 << 0)
173
174enum samsung_cpu_type {
175 TYPE_S3C64XX,
176 TYPE_EXYNOS4210,
177 TYPE_EXYNOS5250,
178};
179
180/*
181 * struct samsung_usbphy_drvdata - driver data for various SoC variants
182 * @cpu_type: machine identifier
183 * @devphy_en_mask: device phy enable mask for PHY CONTROL register
184 * @hostphy_en_mask: host phy enable mask for PHY CONTROL register
185 * @devphy_reg_offset: offset to DEVICE PHY CONTROL register from
186 * mapped address of system controller.
187 * @hostphy_reg_offset: offset to HOST PHY CONTROL register from
188 * mapped address of system controller.
189 *
190 * Here we have a separate mask for device type phy.
191 * Having different masks for host and device type phy helps
192 * in setting independent masks in case of SoCs like S5PV210,
193 * in which PHY0 and PHY1 enable bits belong to same register
194 * placed at position 0 and 1 respectively.
195 * Although for newer SoCs like exynos these bits belong to
196 * different registers altogether placed at position 0.
197 */
198struct samsung_usbphy_drvdata {
199 int cpu_type;
200 int devphy_en_mask;
201 int hostphy_en_mask;
202 u32 devphy_reg_offset;
203 u32 hostphy_reg_offset;
204};
205
206/*
207 * struct samsung_usbphy - transceiver driver state
208 * @phy: transceiver structure
209 * @plat: platform data
210 * @dev: The parent device supplied to the probe function
211 * @clk: usb phy clock
212 * @regs: usb phy controller registers memory base
213 * @pmuregs: USB device PHY_CONTROL register memory base
214 * @sysreg: USB2.0 PHY_CFG register memory base
215 * @ref_clk_freq: reference clock frequency selection
216 * @drv_data: driver data available for different SoCs
217 * @phy_type: Samsung SoCs specific phy types: #HOST
218 * #DEVICE
219 * @phy_usage: usage count for phy
220 * @lock: lock for phy operations
221 */
222struct samsung_usbphy {
223 struct usb_phy phy;
224 struct samsung_usbphy_data *plat;
225 struct device *dev;
226 struct clk *clk;
227 void __iomem *regs;
228 void __iomem *pmuregs;
229 void __iomem *sysreg;
230 int ref_clk_freq;
231 const struct samsung_usbphy_drvdata *drv_data;
232 enum samsung_usb_phy_type phy_type;
233 atomic_t phy_usage;
234 spinlock_t lock;
235};
236
237#define phy_to_sphy(x) container_of((x), struct samsung_usbphy, phy)
238
239int samsung_usbphy_set_host(struct usb_otg *otg, struct usb_bus *host)
240{
241 if (!otg)
242 return -ENODEV;
243
244 if (!otg->host)
245 otg->host = host;
246
247 return 0;
248}
249
250static int samsung_usbphy_parse_dt(struct samsung_usbphy *sphy)
251{
252 struct device_node *usbphy_sys;
253
254 /* Getting node for system controller interface for usb-phy */
255 usbphy_sys = of_get_child_by_name(sphy->dev->of_node, "usbphy-sys");
256 if (!usbphy_sys) {
257 dev_err(sphy->dev, "No sys-controller interface for usb-phy\n");
258 return -ENODEV;
259 }
260
261 sphy->pmuregs = of_iomap(usbphy_sys, 0);
262
263 if (sphy->pmuregs == NULL) {
264 dev_err(sphy->dev, "Can't get usb-phy pmu control register\n");
265 goto err0;
266 }
267
268 sphy->sysreg = of_iomap(usbphy_sys, 1);
269
270 /*
271 * Not returning error code here, since this situation is not fatal.
272 * Few SoCs may not have this switch available
273 */
274 if (sphy->sysreg == NULL)
275 dev_warn(sphy->dev, "Can't get usb-phy sysreg cfg register\n");
276
277 of_node_put(usbphy_sys);
278
279 return 0;
280
281err0:
282 of_node_put(usbphy_sys);
283 return -ENXIO;
284}
285
286/*
287 * Set isolation here for phy.
288 * Here 'on = true' would mean USB PHY block is isolated, hence
289 * de-activated and vice-versa.
290 */
291static void samsung_usbphy_set_isolation(struct samsung_usbphy *sphy, bool on)
292{
293 void __iomem *reg = NULL;
294 u32 reg_val;
295 u32 en_mask = 0;
296
297 if (!sphy->pmuregs) {
298 dev_warn(sphy->dev, "Can't set pmu isolation\n");
299 return;
300 }
301
302 switch (sphy->drv_data->cpu_type) {
303 case TYPE_S3C64XX:
304 /*
305 * Do nothing: We will add here once S3C64xx goes for DT support
306 */
307 break;
308 case TYPE_EXYNOS4210:
309 /*
310 * Fall through since exynos4210 and exynos5250 have similar
311 * register architecture: two separate registers for host and
312 * device phy control with enable bit at position 0.
313 */
314 case TYPE_EXYNOS5250:
315 if (sphy->phy_type == USB_PHY_TYPE_DEVICE) {
316 reg = sphy->pmuregs +
317 sphy->drv_data->devphy_reg_offset;
318 en_mask = sphy->drv_data->devphy_en_mask;
319 } else if (sphy->phy_type == USB_PHY_TYPE_HOST) {
320 reg = sphy->pmuregs +
321 sphy->drv_data->hostphy_reg_offset;
322 en_mask = sphy->drv_data->hostphy_en_mask;
323 }
324 break;
325 default:
326 dev_err(sphy->dev, "Invalid SoC type\n");
327 return;
328 }
329
330 reg_val = readl(reg);
331
332 if (on)
333 reg_val &= ~en_mask;
334 else
335 reg_val |= en_mask;
336
337 writel(reg_val, reg);
338}
339
340/*
341 * Configure the mode of working of usb-phy here: HOST/DEVICE.
342 */
343static void samsung_usbphy_cfg_sel(struct samsung_usbphy *sphy)
344{
345 u32 reg;
346
347 if (!sphy->sysreg) {
348 dev_warn(sphy->dev, "Can't configure specified phy mode\n");
349 return;
350 }
351
352 reg = readl(sphy->sysreg);
353
354 if (sphy->phy_type == USB_PHY_TYPE_DEVICE)
355 reg &= ~EXYNOS_USB20PHY_CFG_HOST_LINK;
356 else if (sphy->phy_type == USB_PHY_TYPE_HOST)
357 reg |= EXYNOS_USB20PHY_CFG_HOST_LINK;
358
359 writel(reg, sphy->sysreg);
360}
361
362/*
363 * PHYs are different for USB Device and USB Host.
364 * This make sure that correct PHY type is selected before
365 * any operation on PHY.
366 */
367static int samsung_usbphy_set_type(struct usb_phy *phy,
368 enum samsung_usb_phy_type phy_type)
369{
370 struct samsung_usbphy *sphy = phy_to_sphy(phy);
371
372 sphy->phy_type = phy_type;
373
374 return 0;
375}
376
377/*
378 * Returns reference clock frequency selection value
379 */
380static int samsung_usbphy_get_refclk_freq(struct samsung_usbphy *sphy)
381{
382 struct clk *ref_clk;
383 int refclk_freq = 0;
384
385 /*
386 * In exynos5250 USB host and device PHY use
387 * external crystal clock XXTI
388 */
389 if (sphy->drv_data->cpu_type == TYPE_EXYNOS5250)
390 ref_clk = clk_get(sphy->dev, "ext_xtal");
391 else
392 ref_clk = clk_get(sphy->dev, "xusbxti");
393 if (IS_ERR(ref_clk)) {
394 dev_err(sphy->dev, "Failed to get reference clock\n");
395 return PTR_ERR(ref_clk);
396 }
397
398 if (sphy->drv_data->cpu_type == TYPE_EXYNOS5250) {
399 /* set clock frequency for PLL */
400 switch (clk_get_rate(ref_clk)) {
401 case 9600 * KHZ:
402 refclk_freq = FSEL_CLKSEL_9600K;
403 break;
404 case 10 * MHZ:
405 refclk_freq = FSEL_CLKSEL_10M;
406 break;
407 case 12 * MHZ:
408 refclk_freq = FSEL_CLKSEL_12M;
409 break;
410 case 19200 * KHZ:
411 refclk_freq = FSEL_CLKSEL_19200K;
412 break;
413 case 20 * MHZ:
414 refclk_freq = FSEL_CLKSEL_20M;
415 break;
416 case 50 * MHZ:
417 refclk_freq = FSEL_CLKSEL_50M;
418 break;
419 case 24 * MHZ:
420 default:
421 /* default reference clock */
422 refclk_freq = FSEL_CLKSEL_24M;
423 break;
424 }
425 } else {
426 switch (clk_get_rate(ref_clk)) {
427 case 12 * MHZ:
428 refclk_freq = PHYCLK_CLKSEL_12M;
429 break;
430 case 24 * MHZ:
431 refclk_freq = PHYCLK_CLKSEL_24M;
432 break;
433 case 48 * MHZ:
434 refclk_freq = PHYCLK_CLKSEL_48M;
435 break;
436 default:
437 if (sphy->drv_data->cpu_type == TYPE_S3C64XX)
438 refclk_freq = PHYCLK_CLKSEL_48M;
439 else
440 refclk_freq = PHYCLK_CLKSEL_24M;
441 break;
442 }
443 }
444 clk_put(ref_clk);
445
446 return refclk_freq;
447}
448
449static bool exynos5_phyhost_is_on(void *regs)
450{
451 u32 reg;
452
453 reg = readl(regs + EXYNOS5_PHY_HOST_CTRL0);
454
455 return !(reg & HOST_CTRL0_SIDDQ);
456}
457
458static void samsung_exynos5_usbphy_enable(struct samsung_usbphy *sphy)
459{
460 void __iomem *regs = sphy->regs;
461 u32 phyclk = sphy->ref_clk_freq;
462 u32 phyhost;
463 u32 phyotg;
464 u32 phyhsic;
465 u32 ehcictrl;
466 u32 ohcictrl;
467
468 /*
469 * phy_usage helps in keeping usage count for phy
470 * so that the first consumer enabling the phy is also
471 * the last consumer to disable it.
472 */
473
474 atomic_inc(&sphy->phy_usage);
475
476 if (exynos5_phyhost_is_on(regs)) {
477 dev_info(sphy->dev, "Already power on PHY\n");
478 return;
479 }
480
481 /* Host configuration */
482 phyhost = readl(regs + EXYNOS5_PHY_HOST_CTRL0);
483
484 /* phy reference clock configuration */
485 phyhost &= ~HOST_CTRL0_FSEL_MASK;
486 phyhost |= HOST_CTRL0_FSEL(phyclk);
487
488 /* host phy reset */
489 phyhost &= ~(HOST_CTRL0_PHYSWRST |
490 HOST_CTRL0_PHYSWRSTALL |
491 HOST_CTRL0_SIDDQ |
492 /* Enable normal mode of operation */
493 HOST_CTRL0_FORCESUSPEND |
494 HOST_CTRL0_FORCESLEEP);
495
496 /* Link reset */
497 phyhost |= (HOST_CTRL0_LINKSWRST |
498 HOST_CTRL0_UTMISWRST |
499 /* COMMON Block configuration during suspend */
500 HOST_CTRL0_COMMONON_N);
501 writel(phyhost, regs + EXYNOS5_PHY_HOST_CTRL0);
502 udelay(10);
503 phyhost &= ~(HOST_CTRL0_LINKSWRST |
504 HOST_CTRL0_UTMISWRST);
505 writel(phyhost, regs + EXYNOS5_PHY_HOST_CTRL0);
506
507 /* OTG configuration */
508 phyotg = readl(regs + EXYNOS5_PHY_OTG_SYS);
509
510 /* phy reference clock configuration */
511 phyotg &= ~OTG_SYS_FSEL_MASK;
512 phyotg |= OTG_SYS_FSEL(phyclk);
513
514 /* Enable normal mode of operation */
515 phyotg &= ~(OTG_SYS_FORCESUSPEND |
516 OTG_SYS_SIDDQ_UOTG |
517 OTG_SYS_FORCESLEEP |
518 OTG_SYS_REFCLKSEL_MASK |
519 /* COMMON Block configuration during suspend */
520 OTG_SYS_COMMON_ON);
521
522 /* OTG phy & link reset */
523 phyotg |= (OTG_SYS_PHY0_SWRST |
524 OTG_SYS_LINKSWRST_UOTG |
525 OTG_SYS_PHYLINK_SWRESET |
526 OTG_SYS_OTGDISABLE |
527 /* Set phy refclk */
528 OTG_SYS_REFCLKSEL_CLKCORE);
529
530 writel(phyotg, regs + EXYNOS5_PHY_OTG_SYS);
531 udelay(10);
532 phyotg &= ~(OTG_SYS_PHY0_SWRST |
533 OTG_SYS_LINKSWRST_UOTG |
534 OTG_SYS_PHYLINK_SWRESET);
535 writel(phyotg, regs + EXYNOS5_PHY_OTG_SYS);
536
537 /* HSIC phy configuration */
538 phyhsic = (HSIC_CTRL_REFCLKDIV_12 |
539 HSIC_CTRL_REFCLKSEL |
540 HSIC_CTRL_PHYSWRST);
541 writel(phyhsic, regs + EXYNOS5_PHY_HSIC_CTRL1);
542 writel(phyhsic, regs + EXYNOS5_PHY_HSIC_CTRL2);
543 udelay(10);
544 phyhsic &= ~HSIC_CTRL_PHYSWRST;
545 writel(phyhsic, regs + EXYNOS5_PHY_HSIC_CTRL1);
546 writel(phyhsic, regs + EXYNOS5_PHY_HSIC_CTRL2);
547
548 udelay(80);
549
550 /* enable EHCI DMA burst */
551 ehcictrl = readl(regs + EXYNOS5_PHY_HOST_EHCICTRL);
552 ehcictrl |= (HOST_EHCICTRL_ENAINCRXALIGN |
553 HOST_EHCICTRL_ENAINCR4 |
554 HOST_EHCICTRL_ENAINCR8 |
555 HOST_EHCICTRL_ENAINCR16);
556 writel(ehcictrl, regs + EXYNOS5_PHY_HOST_EHCICTRL);
557
558 /* set ohci_suspend_on_n */
559 ohcictrl = readl(regs + EXYNOS5_PHY_HOST_OHCICTRL);
560 ohcictrl |= HOST_OHCICTRL_SUSPLGCY;
561 writel(ohcictrl, regs + EXYNOS5_PHY_HOST_OHCICTRL);
562}
563
564static void samsung_usbphy_enable(struct samsung_usbphy *sphy)
565{
566 void __iomem *regs = sphy->regs;
567 u32 phypwr;
568 u32 phyclk;
569 u32 rstcon;
570
571 /* set clock frequency for PLL */
572 phyclk = sphy->ref_clk_freq;
573 phypwr = readl(regs + SAMSUNG_PHYPWR);
574 rstcon = readl(regs + SAMSUNG_RSTCON);
575
576 switch (sphy->drv_data->cpu_type) {
577 case TYPE_S3C64XX:
578 phyclk &= ~PHYCLK_COMMON_ON_N;
579 phypwr &= ~PHYPWR_NORMAL_MASK;
580 rstcon |= RSTCON_SWRST;
581 break;
582 case TYPE_EXYNOS4210:
583 phypwr &= ~PHYPWR_NORMAL_MASK_PHY0;
584 rstcon |= RSTCON_SWRST;
585 default:
586 break;
587 }
588
589 writel(phyclk, regs + SAMSUNG_PHYCLK);
590 /* Configure PHY0 for normal operation*/
591 writel(phypwr, regs + SAMSUNG_PHYPWR);
592 /* reset all ports of PHY and Link */
593 writel(rstcon, regs + SAMSUNG_RSTCON);
594 udelay(10);
595 rstcon &= ~RSTCON_SWRST;
596 writel(rstcon, regs + SAMSUNG_RSTCON);
597}
598
599static void samsung_exynos5_usbphy_disable(struct samsung_usbphy *sphy)
600{
601 void __iomem *regs = sphy->regs;
602 u32 phyhost;
603 u32 phyotg;
604 u32 phyhsic;
605
606 if (atomic_dec_return(&sphy->phy_usage) > 0) {
607 dev_info(sphy->dev, "still being used\n");
608 return;
609 }
610
611 phyhsic = (HSIC_CTRL_REFCLKDIV_12 |
612 HSIC_CTRL_REFCLKSEL |
613 HSIC_CTRL_SIDDQ |
614 HSIC_CTRL_FORCESLEEP |
615 HSIC_CTRL_FORCESUSPEND);
616 writel(phyhsic, regs + EXYNOS5_PHY_HSIC_CTRL1);
617 writel(phyhsic, regs + EXYNOS5_PHY_HSIC_CTRL2);
618
619 phyhost = readl(regs + EXYNOS5_PHY_HOST_CTRL0);
620 phyhost |= (HOST_CTRL0_SIDDQ |
621 HOST_CTRL0_FORCESUSPEND |
622 HOST_CTRL0_FORCESLEEP |
623 HOST_CTRL0_PHYSWRST |
624 HOST_CTRL0_PHYSWRSTALL);
625 writel(phyhost, regs + EXYNOS5_PHY_HOST_CTRL0);
626
627 phyotg = readl(regs + EXYNOS5_PHY_OTG_SYS);
628 phyotg |= (OTG_SYS_FORCESUSPEND |
629 OTG_SYS_SIDDQ_UOTG |
630 OTG_SYS_FORCESLEEP);
631 writel(phyotg, regs + EXYNOS5_PHY_OTG_SYS);
632}
633
634static void samsung_usbphy_disable(struct samsung_usbphy *sphy)
635{
636 void __iomem *regs = sphy->regs;
637 u32 phypwr;
638
639 phypwr = readl(regs + SAMSUNG_PHYPWR);
640
641 switch (sphy->drv_data->cpu_type) {
642 case TYPE_S3C64XX:
643 phypwr |= PHYPWR_NORMAL_MASK;
644 break;
645 case TYPE_EXYNOS4210:
646 phypwr |= PHYPWR_NORMAL_MASK_PHY0;
647 default:
648 break;
649 }
650
651 /* Disable analog and otg block power */
652 writel(phypwr, regs + SAMSUNG_PHYPWR);
653}
654
655/*
656 * The function passed to the usb driver for phy initialization
657 */
658static int samsung_usbphy_init(struct usb_phy *phy)
659{
660 struct samsung_usbphy *sphy;
661 struct usb_bus *host = NULL;
662 unsigned long flags;
663 int ret = 0;
664
665 sphy = phy_to_sphy(phy);
666
667 host = phy->otg->host;
668
669 /* Enable the phy clock */
670 ret = clk_prepare_enable(sphy->clk);
671 if (ret) {
672 dev_err(sphy->dev, "%s: clk_prepare_enable failed\n", __func__);
673 return ret;
674 }
675
676 spin_lock_irqsave(&sphy->lock, flags);
677
678 if (host) {
679 /* setting default phy-type for USB 2.0 */
680 if (!strstr(dev_name(host->controller), "ehci") ||
681 !strstr(dev_name(host->controller), "ohci"))
682 samsung_usbphy_set_type(&sphy->phy, USB_PHY_TYPE_HOST);
683 } else {
684 samsung_usbphy_set_type(&sphy->phy, USB_PHY_TYPE_DEVICE);
685 }
686
687 /* Disable phy isolation */
688 if (sphy->plat && sphy->plat->pmu_isolation)
689 sphy->plat->pmu_isolation(false);
690 else
691 samsung_usbphy_set_isolation(sphy, false);
692
693 /* Selecting Host/OTG mode; After reset USB2.0PHY_CFG: HOST */
694 samsung_usbphy_cfg_sel(sphy);
695
696 /* Initialize usb phy registers */
697 if (sphy->drv_data->cpu_type == TYPE_EXYNOS5250)
698 samsung_exynos5_usbphy_enable(sphy);
699 else
700 samsung_usbphy_enable(sphy);
701
702 spin_unlock_irqrestore(&sphy->lock, flags);
703
704 /* Disable the phy clock */
705 clk_disable_unprepare(sphy->clk);
706
707 return ret;
708}
709
710/*
711 * The function passed to the usb driver for phy shutdown
712 */
713static void samsung_usbphy_shutdown(struct usb_phy *phy)
714{
715 struct samsung_usbphy *sphy;
716 struct usb_bus *host = NULL;
717 unsigned long flags;
718
719 sphy = phy_to_sphy(phy);
720
721 host = phy->otg->host;
722
723 if (clk_prepare_enable(sphy->clk)) {
724 dev_err(sphy->dev, "%s: clk_prepare_enable failed\n", __func__);
725 return;
726 }
727
728 spin_lock_irqsave(&sphy->lock, flags);
729
730 if (host) {
731 /* setting default phy-type for USB 2.0 */
732 if (!strstr(dev_name(host->controller), "ehci") ||
733 !strstr(dev_name(host->controller), "ohci"))
734 samsung_usbphy_set_type(&sphy->phy, USB_PHY_TYPE_HOST);
735 } else {
736 samsung_usbphy_set_type(&sphy->phy, USB_PHY_TYPE_DEVICE);
737 }
738
739 /* De-initialize usb phy registers */
740 if (sphy->drv_data->cpu_type == TYPE_EXYNOS5250)
741 samsung_exynos5_usbphy_disable(sphy);
742 else
743 samsung_usbphy_disable(sphy);
744
745 /* Enable phy isolation */
746 if (sphy->plat && sphy->plat->pmu_isolation)
747 sphy->plat->pmu_isolation(true);
748 else
749 samsung_usbphy_set_isolation(sphy, true);
750
751 spin_unlock_irqrestore(&sphy->lock, flags);
752
753 clk_disable_unprepare(sphy->clk);
754}
755
756static const struct of_device_id samsung_usbphy_dt_match[];
757
758static inline const struct samsung_usbphy_drvdata
759*samsung_usbphy_get_driver_data(struct platform_device *pdev)
760{
761 if (pdev->dev.of_node) {
762 const struct of_device_id *match;
763 match = of_match_node(samsung_usbphy_dt_match,
764 pdev->dev.of_node);
765 return match->data;
766 }
767
768 return (struct samsung_usbphy_drvdata *)
769 platform_get_device_id(pdev)->driver_data;
770}
771
772static int samsung_usbphy_probe(struct platform_device *pdev)
773{
774 struct samsung_usbphy *sphy;
775 struct usb_otg *otg;
776 struct samsung_usbphy_data *pdata = pdev->dev.platform_data;
777 const struct samsung_usbphy_drvdata *drv_data;
778 struct device *dev = &pdev->dev;
779 struct resource *phy_mem;
780 void __iomem *phy_base;
781 struct clk *clk;
782 int ret;
783
784 phy_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
785 if (!phy_mem) {
786 dev_err(dev, "%s: missing mem resource\n", __func__);
787 return -ENODEV;
788 }
789
790 phy_base = devm_ioremap_resource(dev, phy_mem);
791 if (IS_ERR(phy_base))
792 return PTR_ERR(phy_base);
793
794 sphy = devm_kzalloc(dev, sizeof(*sphy), GFP_KERNEL);
795 if (!sphy)
796 return -ENOMEM;
797
798 otg = devm_kzalloc(dev, sizeof(*otg), GFP_KERNEL);
799 if (!otg)
800 return -ENOMEM;
801
802 drv_data = samsung_usbphy_get_driver_data(pdev);
803
804 if (drv_data->cpu_type == TYPE_EXYNOS5250)
805 clk = devm_clk_get(dev, "usbhost");
806 else
807 clk = devm_clk_get(dev, "otg");
808
809 if (IS_ERR(clk)) {
810 dev_err(dev, "Failed to get otg clock\n");
811 return PTR_ERR(clk);
812 }
813
814 sphy->dev = dev;
815
816 if (dev->of_node) {
817 ret = samsung_usbphy_parse_dt(sphy);
818 if (ret < 0)
819 return ret;
820 } else {
821 if (!pdata) {
822 dev_err(dev, "no platform data specified\n");
823 return -EINVAL;
824 }
825 }
826
827 sphy->plat = pdata;
828 sphy->regs = phy_base;
829 sphy->clk = clk;
830 sphy->drv_data = drv_data;
831 sphy->phy.dev = sphy->dev;
832 sphy->phy.label = "samsung-usbphy";
833 sphy->phy.init = samsung_usbphy_init;
834 sphy->phy.shutdown = samsung_usbphy_shutdown;
835 sphy->ref_clk_freq = samsung_usbphy_get_refclk_freq(sphy);
836
837 sphy->phy.otg = otg;
838 sphy->phy.otg->phy = &sphy->phy;
839 sphy->phy.otg->set_host = samsung_usbphy_set_host;
840
841 spin_lock_init(&sphy->lock);
842
843 platform_set_drvdata(pdev, sphy);
844
845 return usb_add_phy(&sphy->phy, USB_PHY_TYPE_USB2);
846}
847
848static int samsung_usbphy_remove(struct platform_device *pdev)
849{
850 struct samsung_usbphy *sphy = platform_get_drvdata(pdev);
851
852 usb_remove_phy(&sphy->phy);
853
854 if (sphy->pmuregs)
855 iounmap(sphy->pmuregs);
856 if (sphy->sysreg)
857 iounmap(sphy->sysreg);
858
859 return 0;
860}
861
862static const struct samsung_usbphy_drvdata usbphy_s3c64xx = {
863 .cpu_type = TYPE_S3C64XX,
864 .devphy_en_mask = S3C64XX_USBPHY_ENABLE,
865};
866
867static const struct samsung_usbphy_drvdata usbphy_exynos4 = {
868 .cpu_type = TYPE_EXYNOS4210,
869 .devphy_en_mask = EXYNOS_USBPHY_ENABLE,
870 .hostphy_en_mask = EXYNOS_USBPHY_ENABLE,
871};
872
873static struct samsung_usbphy_drvdata usbphy_exynos5 = {
874 .cpu_type = TYPE_EXYNOS5250,
875 .hostphy_en_mask = EXYNOS_USBPHY_ENABLE,
876 .hostphy_reg_offset = EXYNOS_USBHOST_PHY_CTRL_OFFSET,
877};
878
879#ifdef CONFIG_OF
880static const struct of_device_id samsung_usbphy_dt_match[] = {
881 {
882 .compatible = "samsung,s3c64xx-usbphy",
883 .data = &usbphy_s3c64xx,
884 }, {
885 .compatible = "samsung,exynos4210-usbphy",
886 .data = &usbphy_exynos4,
887 }, {
888 .compatible = "samsung,exynos5250-usbphy",
889 .data = &usbphy_exynos5
890 },
891 {},
892};
893MODULE_DEVICE_TABLE(of, samsung_usbphy_dt_match);
894#endif
895
896static struct platform_device_id samsung_usbphy_driver_ids[] = {
897 {
898 .name = "s3c64xx-usbphy",
899 .driver_data = (unsigned long)&usbphy_s3c64xx,
900 }, {
901 .name = "exynos4210-usbphy",
902 .driver_data = (unsigned long)&usbphy_exynos4,
903 }, {
904 .name = "exynos5250-usbphy",
905 .driver_data = (unsigned long)&usbphy_exynos5,
906 },
907 {},
908};
909
910MODULE_DEVICE_TABLE(platform, samsung_usbphy_driver_ids);
911
912static struct platform_driver samsung_usbphy_driver = {
913 .probe = samsung_usbphy_probe,
914 .remove = samsung_usbphy_remove,
915 .id_table = samsung_usbphy_driver_ids,
916 .driver = {
917 .name = "samsung-usbphy",
918 .owner = THIS_MODULE,
919 .of_match_table = of_match_ptr(samsung_usbphy_dt_match),
920 },
921};
922
923module_platform_driver(samsung_usbphy_driver);
924
925MODULE_DESCRIPTION("Samsung USB phy controller");
926MODULE_AUTHOR("Praveen Paneri <p.paneri@samsung.com>");
927MODULE_LICENSE("GPL");
928MODULE_ALIAS("platform:samsung-usbphy");
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-22 16:57:40 -0500