usb: phy: samsung: Add support HSIC on Exynos4X12

This patch adds to enable High Speed Inter Chip on Exynos4X12. Both channels
are controlled by usbphy driver based on the patch series of usbphy driver
submitted by Tomasz Figa.

[1] https://patchwork.kernel.org/patch/2576121
[2] https://patchwork.kernel.org/patch/2576131
[3] https://patchwork.kernel.org/patch/2576141
[4] https://patchwork.kernel.org/patch/2576151
[5] https://patchwork.kernel.org/patch/2576161
[6] https://patchwork.kernel.org/patch/2576171

Signed-off-by: Dongjin Kim <tobetter@gmail.com>
Cc: Tomasz Figa <t.figa@samsung.com>
Cc: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>

1 files changed, 11 insertions, 2 deletions

diff --git a/drivers/usb/phy/phy-samsung-usb2.c b/drivers/usb/phy/phy-samsung-usb2.c
index 03180c06bfca..1011c16ade7e 100644
--- a/drivers/usb/phy/phy-samsung-usb2.c
+++ b/drivers/usb/phy/phy-samsung-usb2.c
@@ -176,8 +176,12 @@ static void samsung_usb2phy_enable(struct samsung_usbphy *sphy)
                 phypwr &= ~PHYPWR_NORMAL_MASK;
                 rstcon |= RSTCON_SWRST;
                 break;
-        case TYPE_EXYNOS4210:
         case TYPE_EXYNOS4X12:
+                phypwr &= ~(PHYPWR_NORMAL_MASK_HSIC0 |
+                                PHYPWR_NORMAL_MASK_HSIC1 |
+                                PHYPWR_NORMAL_MASK_PHY1);
+                rstcon |= RSTCON_HOSTPHY_SWRST;
+        case TYPE_EXYNOS4210:
                 phypwr &= ~PHYPWR_NORMAL_MASK_PHY0;
                 rstcon |= RSTCON_SWRST;
         default:
@@ -190,6 +194,8 @@ static void samsung_usb2phy_enable(struct samsung_usbphy *sphy)
         /* reset all ports of PHY and Link */
         writel(rstcon, regs + SAMSUNG_RSTCON);
         udelay(10);
+        if (sphy->drv_data->cpu_type == TYPE_EXYNOS4X12)
+                rstcon &= ~RSTCON_HOSTPHY_SWRST;
         rstcon &= ~RSTCON_SWRST;
         writel(rstcon, regs + SAMSUNG_RSTCON);
 }
@@ -240,8 +246,11 @@ static void samsung_usb2phy_disable(struct samsung_usbphy *sphy)
         case TYPE_S3C64XX:
                 phypwr |= PHYPWR_NORMAL_MASK;
                 break;
-        case TYPE_EXYNOS4210:
         case TYPE_EXYNOS4X12:
+                phypwr |= (PHYPWR_NORMAL_MASK_HSIC0 |
+                                PHYPWR_NORMAL_MASK_HSIC1 |
+                                PHYPWR_NORMAL_MASK_PHY1);
+        case TYPE_EXYNOS4210:
                 phypwr |= PHYPWR_NORMAL_MASK_PHY0;
         default:
                 break;