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authorLinus Torvalds <torvalds@linux-foundation.org>2008-10-17 18:43:52 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2008-10-17 18:43:52 -0400
commit0cfd81031a26717fe14380d18275f8e217571615 (patch)
tree78a84e4cb97e7f45eb77dc0fbd8857a5dd717869 /drivers/usb/musb
parentf7ea4a4ba84f382e8eb143e435551de0feee5b4b (diff)
parent802f389a2cc6e2771b8de915ac241456d41eb79e (diff)
Merge git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb-2.6
* git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb-2.6: (94 commits) USB: remove err() macro from more usb drivers USB: remove err() macro from usb misc drivers USB: remove err() macro from usb core code USB: remove err() macro from usb class drivers USB: remove use of err() in drivers/usb/serial USB: remove info() macro from usb mtd drivers USB: remove info() macro from usb input drivers USB: remove info() macro from usb network drivers USB: remove info() macro from remaining usb drivers USB: remove info() macro from usb/misc drivers USB: remove info() macro from usb/serial drivers USB: remove warn macro from HID core USB: remove warn() macro from usb drivers USB: remove warn() macro from usb net drivers USB: remove warn() macro from usb media drivers USB: remove warn() macro from usb input drivers usb/fsl_qe_udc: clear data toggle on clear halt request usb/fsl_qe_udc: fix response to get status request fsl_usb2_udc: Fix oops on probe failure. fsl_usb2_udc: Add a wmb before priming endpoint. ...
Diffstat (limited to 'drivers/usb/musb')
-rw-r--r--drivers/usb/musb/Kconfig4
-rw-r--r--drivers/usb/musb/cppi_dma.h4
-rw-r--r--drivers/usb/musb/davinci.c20
-rw-r--r--drivers/usb/musb/musb_core.c41
-rw-r--r--drivers/usb/musb/musb_gadget_ep0.c24
-rw-r--r--drivers/usb/musb/musb_host.c19
-rw-r--r--drivers/usb/musb/musb_io.h4
-rw-r--r--drivers/usb/musb/musbhsdma.c306
8 files changed, 215 insertions, 207 deletions
diff --git a/drivers/usb/musb/Kconfig b/drivers/usb/musb/Kconfig
index 58b2b8fc9439..4b9542bbb35c 100644
--- a/drivers/usb/musb/Kconfig
+++ b/drivers/usb/musb/Kconfig
@@ -33,10 +33,6 @@ config USB_MUSB_SOC
33 default y if ARCH_DAVINCI 33 default y if ARCH_DAVINCI
34 default y if ARCH_OMAP2430 34 default y if ARCH_OMAP2430
35 default y if ARCH_OMAP34XX 35 default y if ARCH_OMAP34XX
36 help
37 Use a static <asm/arch/hdrc_cnf.h> file to describe how the
38 controller is configured (endpoints, mechanisms, etc) on the
39 current iteration of a given system-on-chip.
40 36
41comment "DaVinci 644x USB support" 37comment "DaVinci 644x USB support"
42 depends on USB_MUSB_HDRC && ARCH_DAVINCI 38 depends on USB_MUSB_HDRC && ARCH_DAVINCI
diff --git a/drivers/usb/musb/cppi_dma.h b/drivers/usb/musb/cppi_dma.h
index fc5216b5d2c5..729b4071787b 100644
--- a/drivers/usb/musb/cppi_dma.h
+++ b/drivers/usb/musb/cppi_dma.h
@@ -119,8 +119,8 @@ struct cppi {
119 void __iomem *mregs; /* Mentor regs */ 119 void __iomem *mregs; /* Mentor regs */
120 void __iomem *tibase; /* TI/CPPI regs */ 120 void __iomem *tibase; /* TI/CPPI regs */
121 121
122 struct cppi_channel tx[MUSB_C_NUM_EPT - 1]; 122 struct cppi_channel tx[4];
123 struct cppi_channel rx[MUSB_C_NUM_EPR - 1]; 123 struct cppi_channel rx[4];
124 124
125 struct dma_pool *pool; 125 struct dma_pool *pool;
126 126
diff --git a/drivers/usb/musb/davinci.c b/drivers/usb/musb/davinci.c
index 75baf181a8cd..dfb3bcbe00fc 100644
--- a/drivers/usb/musb/davinci.c
+++ b/drivers/usb/musb/davinci.c
@@ -30,6 +30,7 @@
30#include <linux/delay.h> 30#include <linux/delay.h>
31#include <linux/clk.h> 31#include <linux/clk.h>
32#include <linux/io.h> 32#include <linux/io.h>
33#include <linux/gpio.h>
33 34
34#include <asm/arch/hardware.h> 35#include <asm/arch/hardware.h>
35#include <asm/arch/memory.h> 36#include <asm/arch/memory.h>
@@ -39,7 +40,7 @@
39#include "musb_core.h" 40#include "musb_core.h"
40 41
41#ifdef CONFIG_MACH_DAVINCI_EVM 42#ifdef CONFIG_MACH_DAVINCI_EVM
42#include <asm/arch/i2c-client.h> 43#define GPIO_nVBUS_DRV 87
43#endif 44#endif
44 45
45#include "davinci.h" 46#include "davinci.h"
@@ -138,7 +139,6 @@ static int vbus_state = -1;
138/* VBUS SWITCHING IS BOARD-SPECIFIC */ 139/* VBUS SWITCHING IS BOARD-SPECIFIC */
139 140
140#ifdef CONFIG_MACH_DAVINCI_EVM 141#ifdef CONFIG_MACH_DAVINCI_EVM
141#ifndef CONFIG_MACH_DAVINCI_EVM_OTG
142 142
143/* I2C operations are always synchronous, and require a task context. 143/* I2C operations are always synchronous, and require a task context.
144 * With unloaded systems, using the shared workqueue seems to suffice 144 * With unloaded systems, using the shared workqueue seems to suffice
@@ -146,12 +146,11 @@ static int vbus_state = -1;
146 */ 146 */
147static void evm_deferred_drvvbus(struct work_struct *ignored) 147static void evm_deferred_drvvbus(struct work_struct *ignored)
148{ 148{
149 davinci_i2c_expander_op(0x3a, USB_DRVVBUS, vbus_state); 149 gpio_set_value_cansleep(GPIO_nVBUS_DRV, vbus_state);
150 vbus_state = !vbus_state; 150 vbus_state = !vbus_state;
151} 151}
152static DECLARE_WORK(evm_vbus_work, evm_deferred_drvvbus); 152static DECLARE_WORK(evm_vbus_work, evm_deferred_drvvbus);
153 153
154#endif /* modified board */
155#endif /* EVM */ 154#endif /* EVM */
156 155
157static void davinci_source_power(struct musb *musb, int is_on, int immediate) 156static void davinci_source_power(struct musb *musb, int is_on, int immediate)
@@ -165,21 +164,10 @@ static void davinci_source_power(struct musb *musb, int is_on, int immediate)
165 164
166#ifdef CONFIG_MACH_DAVINCI_EVM 165#ifdef CONFIG_MACH_DAVINCI_EVM
167 if (machine_is_davinci_evm()) { 166 if (machine_is_davinci_evm()) {
168#ifdef CONFIG_MACH_DAVINCI_EVM_OTG
169 /* modified EVM board switching VBUS with GPIO(6) not I2C
170 * NOTE: PINMUX0.RGB888 (bit23) must be clear
171 */
172 if (is_on)
173 gpio_set(GPIO(6));
174 else
175 gpio_clear(GPIO(6));
176 immediate = 1;
177#else
178 if (immediate) 167 if (immediate)
179 davinci_i2c_expander_op(0x3a, USB_DRVVBUS, !is_on); 168 gpio_set_value_cansleep(GPIO_nVBUS_DRV, vbus_state);
180 else 169 else
181 schedule_work(&evm_vbus_work); 170 schedule_work(&evm_vbus_work);
182#endif
183 } 171 }
184#endif 172#endif
185 if (immediate) 173 if (immediate)
diff --git a/drivers/usb/musb/musb_core.c b/drivers/usb/musb/musb_core.c
index 128e949db47c..4a35745b30be 100644
--- a/drivers/usb/musb/musb_core.c
+++ b/drivers/usb/musb/musb_core.c
@@ -82,9 +82,9 @@
82/* 82/*
83 * This gets many kinds of configuration information: 83 * This gets many kinds of configuration information:
84 * - Kconfig for everything user-configurable 84 * - Kconfig for everything user-configurable
85 * - <asm/arch/hdrc_cnf.h> for SOC or family details
86 * - platform_device for addressing, irq, and platform_data 85 * - platform_device for addressing, irq, and platform_data
87 * - platform_data is mostly for board-specific informarion 86 * - platform_data is mostly for board-specific informarion
87 * (plus recentrly, SOC or family details)
88 * 88 *
89 * Most of the conditional compilation will (someday) vanish. 89 * Most of the conditional compilation will (someday) vanish.
90 */ 90 */
@@ -974,9 +974,9 @@ static void musb_shutdown(struct platform_device *pdev)
974/* 974/*
975 * The silicon either has hard-wired endpoint configurations, or else 975 * The silicon either has hard-wired endpoint configurations, or else
976 * "dynamic fifo" sizing. The driver has support for both, though at this 976 * "dynamic fifo" sizing. The driver has support for both, though at this
977 * writing only the dynamic sizing is very well tested. We use normal 977 * writing only the dynamic sizing is very well tested. Since we switched
978 * idioms to so both modes are compile-tested, but dead code elimination 978 * away from compile-time hardware parameters, we can no longer rely on
979 * leaves only the relevant one in the object file. 979 * dead code elimination to leave only the relevant one in the object file.
980 * 980 *
981 * We don't currently use dynamic fifo setup capability to do anything 981 * We don't currently use dynamic fifo setup capability to do anything
982 * more than selecting one of a bunch of predefined configurations. 982 * more than selecting one of a bunch of predefined configurations.
@@ -1806,6 +1806,7 @@ allocate_instance(struct device *dev,
1806 musb->ctrl_base = mbase; 1806 musb->ctrl_base = mbase;
1807 musb->nIrq = -ENODEV; 1807 musb->nIrq = -ENODEV;
1808 musb->config = config; 1808 musb->config = config;
1809 BUG_ON(musb->config->num_eps > MUSB_C_NUM_EPS);
1809 for (epnum = 0, ep = musb->endpoints; 1810 for (epnum = 0, ep = musb->endpoints;
1810 epnum < musb->config->num_eps; 1811 epnum < musb->config->num_eps;
1811 epnum++, ep++) { 1812 epnum++, ep++) {
@@ -2054,15 +2055,6 @@ bad_config:
2054 2055
2055 } 2056 }
2056 2057
2057 return 0;
2058
2059fail:
2060 if (musb->clock)
2061 clk_put(musb->clock);
2062 device_init_wakeup(dev, 0);
2063 musb_free(musb);
2064 return status;
2065
2066#ifdef CONFIG_SYSFS 2058#ifdef CONFIG_SYSFS
2067 status = device_create_file(dev, &dev_attr_mode); 2059 status = device_create_file(dev, &dev_attr_mode);
2068 status = device_create_file(dev, &dev_attr_vbus); 2060 status = device_create_file(dev, &dev_attr_vbus);
@@ -2071,12 +2063,31 @@ fail:
2071#endif /* CONFIG_USB_GADGET_MUSB_HDRC */ 2063#endif /* CONFIG_USB_GADGET_MUSB_HDRC */
2072 status = 0; 2064 status = 0;
2073#endif 2065#endif
2066 if (status)
2067 goto fail2;
2074 2068
2075 return status; 2069 return 0;
2076 2070
2077fail2: 2071fail2:
2072#ifdef CONFIG_SYSFS
2073 device_remove_file(musb->controller, &dev_attr_mode);
2074 device_remove_file(musb->controller, &dev_attr_vbus);
2075#ifdef CONFIG_USB_MUSB_OTG
2076 device_remove_file(musb->controller, &dev_attr_srp);
2077#endif
2078#endif
2078 musb_platform_exit(musb); 2079 musb_platform_exit(musb);
2079 goto fail; 2080fail:
2081 dev_err(musb->controller,
2082 "musb_init_controller failed with status %d\n", status);
2083
2084 if (musb->clock)
2085 clk_put(musb->clock);
2086 device_init_wakeup(dev, 0);
2087 musb_free(musb);
2088
2089 return status;
2090
2080} 2091}
2081 2092
2082/*-------------------------------------------------------------------------*/ 2093/*-------------------------------------------------------------------------*/
diff --git a/drivers/usb/musb/musb_gadget_ep0.c b/drivers/usb/musb/musb_gadget_ep0.c
index a57652fff39c..3f5e30ddfa27 100644
--- a/drivers/usb/musb/musb_gadget_ep0.c
+++ b/drivers/usb/musb/musb_gadget_ep0.c
@@ -437,7 +437,7 @@ static void ep0_rxstate(struct musb *musb)
437{ 437{
438 void __iomem *regs = musb->control_ep->regs; 438 void __iomem *regs = musb->control_ep->regs;
439 struct usb_request *req; 439 struct usb_request *req;
440 u16 tmp; 440 u16 count, csr;
441 441
442 req = next_ep0_request(musb); 442 req = next_ep0_request(musb);
443 443
@@ -449,35 +449,35 @@ static void ep0_rxstate(struct musb *musb)
449 unsigned len = req->length - req->actual; 449 unsigned len = req->length - req->actual;
450 450
451 /* read the buffer */ 451 /* read the buffer */
452 tmp = musb_readb(regs, MUSB_COUNT0); 452 count = musb_readb(regs, MUSB_COUNT0);
453 if (tmp > len) { 453 if (count > len) {
454 req->status = -EOVERFLOW; 454 req->status = -EOVERFLOW;
455 tmp = len; 455 count = len;
456 } 456 }
457 musb_read_fifo(&musb->endpoints[0], tmp, buf); 457 musb_read_fifo(&musb->endpoints[0], count, buf);
458 req->actual += tmp; 458 req->actual += count;
459 tmp = MUSB_CSR0_P_SVDRXPKTRDY; 459 csr = MUSB_CSR0_P_SVDRXPKTRDY;
460 if (tmp < 64 || req->actual == req->length) { 460 if (count < 64 || req->actual == req->length) {
461 musb->ep0_state = MUSB_EP0_STAGE_STATUSIN; 461 musb->ep0_state = MUSB_EP0_STAGE_STATUSIN;
462 tmp |= MUSB_CSR0_P_DATAEND; 462 csr |= MUSB_CSR0_P_DATAEND;
463 } else 463 } else
464 req = NULL; 464 req = NULL;
465 } else 465 } else
466 tmp = MUSB_CSR0_P_SVDRXPKTRDY | MUSB_CSR0_P_SENDSTALL; 466 csr = MUSB_CSR0_P_SVDRXPKTRDY | MUSB_CSR0_P_SENDSTALL;
467 467
468 468
469 /* Completion handler may choose to stall, e.g. because the 469 /* Completion handler may choose to stall, e.g. because the
470 * message just received holds invalid data. 470 * message just received holds invalid data.
471 */ 471 */
472 if (req) { 472 if (req) {
473 musb->ackpend = tmp; 473 musb->ackpend = csr;
474 musb_g_ep0_giveback(musb, req); 474 musb_g_ep0_giveback(musb, req);
475 if (!musb->ackpend) 475 if (!musb->ackpend)
476 return; 476 return;
477 musb->ackpend = 0; 477 musb->ackpend = 0;
478 } 478 }
479 musb_ep_select(musb->mregs, 0); 479 musb_ep_select(musb->mregs, 0);
480 musb_writew(regs, MUSB_CSR0, tmp); 480 musb_writew(regs, MUSB_CSR0, csr);
481} 481}
482 482
483/* 483/*
diff --git a/drivers/usb/musb/musb_host.c b/drivers/usb/musb/musb_host.c
index 8b4be012669a..3133990f04ec 100644
--- a/drivers/usb/musb/musb_host.c
+++ b/drivers/usb/musb/musb_host.c
@@ -108,7 +108,7 @@ static void musb_ep_program(struct musb *musb, u8 epnum,
108/* 108/*
109 * Clear TX fifo. Needed to avoid BABBLE errors. 109 * Clear TX fifo. Needed to avoid BABBLE errors.
110 */ 110 */
111static inline void musb_h_tx_flush_fifo(struct musb_hw_ep *ep) 111static void musb_h_tx_flush_fifo(struct musb_hw_ep *ep)
112{ 112{
113 void __iomem *epio = ep->regs; 113 void __iomem *epio = ep->regs;
114 u16 csr; 114 u16 csr;
@@ -291,6 +291,7 @@ __acquires(musb->lock)
291 urb->actual_length, urb->transfer_buffer_length 291 urb->actual_length, urb->transfer_buffer_length
292 ); 292 );
293 293
294 usb_hcd_unlink_urb_from_ep(musb_to_hcd(musb), urb);
294 spin_unlock(&musb->lock); 295 spin_unlock(&musb->lock);
295 usb_hcd_giveback_urb(musb_to_hcd(musb), urb, status); 296 usb_hcd_giveback_urb(musb_to_hcd(musb), urb, status);
296 spin_lock(&musb->lock); 297 spin_lock(&musb->lock);
@@ -353,8 +354,6 @@ musb_giveback(struct musb_qh *qh, struct urb *urb, int status)
353 break; 354 break;
354 } 355 }
355 356
356 usb_hcd_unlink_urb_from_ep(musb_to_hcd(musb), urb);
357
358 qh->is_ready = 0; 357 qh->is_ready = 0;
359 __musb_giveback(musb, urb, status); 358 __musb_giveback(musb, urb, status);
360 qh->is_ready = ready; 359 qh->is_ready = ready;
@@ -436,7 +435,7 @@ musb_advance_schedule(struct musb *musb, struct urb *urb,
436 } 435 }
437} 436}
438 437
439static inline u16 musb_h_flush_rxfifo(struct musb_hw_ep *hw_ep, u16 csr) 438static u16 musb_h_flush_rxfifo(struct musb_hw_ep *hw_ep, u16 csr)
440{ 439{
441 /* we don't want fifo to fill itself again; 440 /* we don't want fifo to fill itself again;
442 * ignore dma (various models), 441 * ignore dma (various models),
@@ -1005,7 +1004,7 @@ static bool musb_h_ep0_continue(struct musb *musb, u16 len, struct urb *urb)
1005 1004
1006/* 1005/*
1007 * Handle default endpoint interrupt as host. Only called in IRQ time 1006 * Handle default endpoint interrupt as host. Only called in IRQ time
1008 * from the LinuxIsr() interrupt service routine. 1007 * from musb_interrupt().
1009 * 1008 *
1010 * called with controller irqlocked 1009 * called with controller irqlocked
1011 */ 1010 */
@@ -1791,7 +1790,9 @@ static int musb_urb_enqueue(
1791 */ 1790 */
1792 qh = kzalloc(sizeof *qh, mem_flags); 1791 qh = kzalloc(sizeof *qh, mem_flags);
1793 if (!qh) { 1792 if (!qh) {
1793 spin_lock_irqsave(&musb->lock, flags);
1794 usb_hcd_unlink_urb_from_ep(hcd, urb); 1794 usb_hcd_unlink_urb_from_ep(hcd, urb);
1795 spin_unlock_irqrestore(&musb->lock, flags);
1795 return -ENOMEM; 1796 return -ENOMEM;
1796 } 1797 }
1797 1798
@@ -1873,7 +1874,11 @@ static int musb_urb_enqueue(
1873 /* set up tt info if needed */ 1874 /* set up tt info if needed */
1874 if (urb->dev->tt) { 1875 if (urb->dev->tt) {
1875 qh->h_port_reg = (u8) urb->dev->ttport; 1876 qh->h_port_reg = (u8) urb->dev->ttport;
1876 qh->h_addr_reg |= 0x80; 1877 if (urb->dev->tt->hub)
1878 qh->h_addr_reg =
1879 (u8) urb->dev->tt->hub->devnum;
1880 if (urb->dev->tt->multi)
1881 qh->h_addr_reg |= 0x80;
1877 } 1882 }
1878 } 1883 }
1879 } 1884 }
@@ -1903,7 +1908,9 @@ static int musb_urb_enqueue(
1903 1908
1904done: 1909done:
1905 if (ret != 0) { 1910 if (ret != 0) {
1911 spin_lock_irqsave(&musb->lock, flags);
1906 usb_hcd_unlink_urb_from_ep(hcd, urb); 1912 usb_hcd_unlink_urb_from_ep(hcd, urb);
1913 spin_unlock_irqrestore(&musb->lock, flags);
1907 kfree(qh); 1914 kfree(qh);
1908 } 1915 }
1909 return ret; 1916 return ret;
diff --git a/drivers/usb/musb/musb_io.h b/drivers/usb/musb/musb_io.h
index 6bbedae83af8..223f0a514094 100644
--- a/drivers/usb/musb/musb_io.h
+++ b/drivers/usb/musb/musb_io.h
@@ -37,7 +37,9 @@
37 37
38#include <linux/io.h> 38#include <linux/io.h>
39 39
40#ifndef CONFIG_ARM 40#if !defined(CONFIG_ARM) && !defined(CONFIG_SUPERH) \
41 && !defined(CONFIG_AVR32) && !defined(CONFIG_PPC32) \
42 && !defined(CONFIG_PPC64)
41static inline void readsl(const void __iomem *addr, void *buf, int len) 43static inline void readsl(const void __iomem *addr, void *buf, int len)
42 { insl((unsigned long)addr, buf, len); } 44 { insl((unsigned long)addr, buf, len); }
43static inline void readsw(const void __iomem *addr, void *buf, int len) 45static inline void readsw(const void __iomem *addr, void *buf, int len)
diff --git a/drivers/usb/musb/musbhsdma.c b/drivers/usb/musb/musbhsdma.c
index 9ba8fb7fcd24..8c734ef2c1ed 100644
--- a/drivers/usb/musb/musbhsdma.c
+++ b/drivers/usb/musb/musbhsdma.c
@@ -45,8 +45,8 @@
45#define MUSB_HSDMA_ADDRESS 0x8 45#define MUSB_HSDMA_ADDRESS 0x8
46#define MUSB_HSDMA_COUNT 0xc 46#define MUSB_HSDMA_COUNT 0xc
47 47
48#define MUSB_HSDMA_CHANNEL_OFFSET(_bChannel, _offset) \ 48#define MUSB_HSDMA_CHANNEL_OFFSET(_bchannel, _offset) \
49 (MUSB_HSDMA_BASE + (_bChannel << 4) + _offset) 49 (MUSB_HSDMA_BASE + (_bchannel << 4) + _offset)
50 50
51/* control register (16-bit): */ 51/* control register (16-bit): */
52#define MUSB_HSDMA_ENABLE_SHIFT 0 52#define MUSB_HSDMA_ENABLE_SHIFT 0
@@ -67,23 +67,23 @@
67struct musb_dma_controller; 67struct musb_dma_controller;
68 68
69struct musb_dma_channel { 69struct musb_dma_channel {
70 struct dma_channel Channel; 70 struct dma_channel channel;
71 struct musb_dma_controller *controller; 71 struct musb_dma_controller *controller;
72 u32 dwStartAddress; 72 u32 start_addr;
73 u32 len; 73 u32 len;
74 u16 wMaxPacketSize; 74 u16 max_packet_sz;
75 u8 bIndex; 75 u8 idx;
76 u8 epnum; 76 u8 epnum;
77 u8 transmit; 77 u8 transmit;
78}; 78};
79 79
80struct musb_dma_controller { 80struct musb_dma_controller {
81 struct dma_controller Controller; 81 struct dma_controller controller;
82 struct musb_dma_channel aChannel[MUSB_HSDMA_CHANNELS]; 82 struct musb_dma_channel channel[MUSB_HSDMA_CHANNELS];
83 void *pDmaPrivate; 83 void *private_data;
84 void __iomem *pCoreBase; 84 void __iomem *base;
85 u8 bChannelCount; 85 u8 channel_count;
86 u8 bmUsedChannels; 86 u8 used_channels;
87 u8 irq; 87 u8 irq;
88}; 88};
89 89
@@ -93,91 +93,91 @@ static int dma_controller_start(struct dma_controller *c)
93 return 0; 93 return 0;
94} 94}
95 95
96static void dma_channel_release(struct dma_channel *pChannel); 96static void dma_channel_release(struct dma_channel *channel);
97 97
98static int dma_controller_stop(struct dma_controller *c) 98static int dma_controller_stop(struct dma_controller *c)
99{ 99{
100 struct musb_dma_controller *controller = 100 struct musb_dma_controller *controller = container_of(c,
101 container_of(c, struct musb_dma_controller, Controller); 101 struct musb_dma_controller, controller);
102 struct musb *musb = (struct musb *) controller->pDmaPrivate; 102 struct musb *musb = controller->private_data;
103 struct dma_channel *pChannel; 103 struct dma_channel *channel;
104 u8 bBit; 104 u8 bit;
105 105
106 if (controller->bmUsedChannels != 0) { 106 if (controller->used_channels != 0) {
107 dev_err(musb->controller, 107 dev_err(musb->controller,
108 "Stopping DMA controller while channel active\n"); 108 "Stopping DMA controller while channel active\n");
109 109
110 for (bBit = 0; bBit < MUSB_HSDMA_CHANNELS; bBit++) { 110 for (bit = 0; bit < MUSB_HSDMA_CHANNELS; bit++) {
111 if (controller->bmUsedChannels & (1 << bBit)) { 111 if (controller->used_channels & (1 << bit)) {
112 pChannel = &controller->aChannel[bBit].Channel; 112 channel = &controller->channel[bit].channel;
113 dma_channel_release(pChannel); 113 dma_channel_release(channel);
114 114
115 if (!controller->bmUsedChannels) 115 if (!controller->used_channels)
116 break; 116 break;
117 } 117 }
118 } 118 }
119 } 119 }
120
120 return 0; 121 return 0;
121} 122}
122 123
123static struct dma_channel *dma_channel_allocate(struct dma_controller *c, 124static struct dma_channel *dma_channel_allocate(struct dma_controller *c,
124 struct musb_hw_ep *hw_ep, u8 transmit) 125 struct musb_hw_ep *hw_ep, u8 transmit)
125{ 126{
126 u8 bBit; 127 struct musb_dma_controller *controller = container_of(c,
127 struct dma_channel *pChannel = NULL; 128 struct musb_dma_controller, controller);
128 struct musb_dma_channel *pImplChannel = NULL; 129 struct musb_dma_channel *musb_channel = NULL;
129 struct musb_dma_controller *controller = 130 struct dma_channel *channel = NULL;
130 container_of(c, struct musb_dma_controller, Controller); 131 u8 bit;
131 132
132 for (bBit = 0; bBit < MUSB_HSDMA_CHANNELS; bBit++) { 133 for (bit = 0; bit < MUSB_HSDMA_CHANNELS; bit++) {
133 if (!(controller->bmUsedChannels & (1 << bBit))) { 134 if (!(controller->used_channels & (1 << bit))) {
134 controller->bmUsedChannels |= (1 << bBit); 135 controller->used_channels |= (1 << bit);
135 pImplChannel = &(controller->aChannel[bBit]); 136 musb_channel = &(controller->channel[bit]);
136 pImplChannel->controller = controller; 137 musb_channel->controller = controller;
137 pImplChannel->bIndex = bBit; 138 musb_channel->idx = bit;
138 pImplChannel->epnum = hw_ep->epnum; 139 musb_channel->epnum = hw_ep->epnum;
139 pImplChannel->transmit = transmit; 140 musb_channel->transmit = transmit;
140 pChannel = &(pImplChannel->Channel); 141 channel = &(musb_channel->channel);
141 pChannel->private_data = pImplChannel; 142 channel->private_data = musb_channel;
142 pChannel->status = MUSB_DMA_STATUS_FREE; 143 channel->status = MUSB_DMA_STATUS_FREE;
143 pChannel->max_len = 0x10000; 144 channel->max_len = 0x10000;
144 /* Tx => mode 1; Rx => mode 0 */ 145 /* Tx => mode 1; Rx => mode 0 */
145 pChannel->desired_mode = transmit; 146 channel->desired_mode = transmit;
146 pChannel->actual_len = 0; 147 channel->actual_len = 0;
147 break; 148 break;
148 } 149 }
149 } 150 }
150 return pChannel; 151
152 return channel;
151} 153}
152 154
153static void dma_channel_release(struct dma_channel *pChannel) 155static void dma_channel_release(struct dma_channel *channel)
154{ 156{
155 struct musb_dma_channel *pImplChannel = 157 struct musb_dma_channel *musb_channel = channel->private_data;
156 (struct musb_dma_channel *) pChannel->private_data;
157 158
158 pChannel->actual_len = 0; 159 channel->actual_len = 0;
159 pImplChannel->dwStartAddress = 0; 160 musb_channel->start_addr = 0;
160 pImplChannel->len = 0; 161 musb_channel->len = 0;
161 162
162 pImplChannel->controller->bmUsedChannels &= 163 musb_channel->controller->used_channels &=
163 ~(1 << pImplChannel->bIndex); 164 ~(1 << musb_channel->idx);
164 165
165 pChannel->status = MUSB_DMA_STATUS_UNKNOWN; 166 channel->status = MUSB_DMA_STATUS_UNKNOWN;
166} 167}
167 168
168static void configure_channel(struct dma_channel *pChannel, 169static void configure_channel(struct dma_channel *channel,
169 u16 packet_sz, u8 mode, 170 u16 packet_sz, u8 mode,
170 dma_addr_t dma_addr, u32 len) 171 dma_addr_t dma_addr, u32 len)
171{ 172{
172 struct musb_dma_channel *pImplChannel = 173 struct musb_dma_channel *musb_channel = channel->private_data;
173 (struct musb_dma_channel *) pChannel->private_data; 174 struct musb_dma_controller *controller = musb_channel->controller;
174 struct musb_dma_controller *controller = pImplChannel->controller; 175 void __iomem *mbase = controller->base;
175 void __iomem *mbase = controller->pCoreBase; 176 u8 bchannel = musb_channel->idx;
176 u8 bChannel = pImplChannel->bIndex;
177 u16 csr = 0; 177 u16 csr = 0;
178 178
179 DBG(4, "%p, pkt_sz %d, addr 0x%x, len %d, mode %d\n", 179 DBG(4, "%p, pkt_sz %d, addr 0x%x, len %d, mode %d\n",
180 pChannel, packet_sz, dma_addr, len, mode); 180 channel, packet_sz, dma_addr, len, mode);
181 181
182 if (mode) { 182 if (mode) {
183 csr |= 1 << MUSB_HSDMA_MODE1_SHIFT; 183 csr |= 1 << MUSB_HSDMA_MODE1_SHIFT;
@@ -195,180 +195,183 @@ static void configure_channel(struct dma_channel *pChannel,
195 } 195 }
196 } 196 }
197 197
198 csr |= (pImplChannel->epnum << MUSB_HSDMA_ENDPOINT_SHIFT) 198 csr |= (musb_channel->epnum << MUSB_HSDMA_ENDPOINT_SHIFT)
199 | (1 << MUSB_HSDMA_ENABLE_SHIFT) 199 | (1 << MUSB_HSDMA_ENABLE_SHIFT)
200 | (1 << MUSB_HSDMA_IRQENABLE_SHIFT) 200 | (1 << MUSB_HSDMA_IRQENABLE_SHIFT)
201 | (pImplChannel->transmit 201 | (musb_channel->transmit
202 ? (1 << MUSB_HSDMA_TRANSMIT_SHIFT) 202 ? (1 << MUSB_HSDMA_TRANSMIT_SHIFT)
203 : 0); 203 : 0);
204 204
205 /* address/count */ 205 /* address/count */
206 musb_writel(mbase, 206 musb_writel(mbase,
207 MUSB_HSDMA_CHANNEL_OFFSET(bChannel, MUSB_HSDMA_ADDRESS), 207 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDRESS),
208 dma_addr); 208 dma_addr);
209 musb_writel(mbase, 209 musb_writel(mbase,
210 MUSB_HSDMA_CHANNEL_OFFSET(bChannel, MUSB_HSDMA_COUNT), 210 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT),
211 len); 211 len);
212 212
213 /* control (this should start things) */ 213 /* control (this should start things) */
214 musb_writew(mbase, 214 musb_writew(mbase,
215 MUSB_HSDMA_CHANNEL_OFFSET(bChannel, MUSB_HSDMA_CONTROL), 215 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_CONTROL),
216 csr); 216 csr);
217} 217}
218 218
219static int dma_channel_program(struct dma_channel *pChannel, 219static int dma_channel_program(struct dma_channel *channel,
220 u16 packet_sz, u8 mode, 220 u16 packet_sz, u8 mode,
221 dma_addr_t dma_addr, u32 len) 221 dma_addr_t dma_addr, u32 len)
222{ 222{
223 struct musb_dma_channel *pImplChannel = 223 struct musb_dma_channel *musb_channel = channel->private_data;
224 (struct musb_dma_channel *) pChannel->private_data;
225 224
226 DBG(2, "ep%d-%s pkt_sz %d, dma_addr 0x%x length %d, mode %d\n", 225 DBG(2, "ep%d-%s pkt_sz %d, dma_addr 0x%x length %d, mode %d\n",
227 pImplChannel->epnum, 226 musb_channel->epnum,
228 pImplChannel->transmit ? "Tx" : "Rx", 227 musb_channel->transmit ? "Tx" : "Rx",
229 packet_sz, dma_addr, len, mode); 228 packet_sz, dma_addr, len, mode);
230 229
231 BUG_ON(pChannel->status == MUSB_DMA_STATUS_UNKNOWN || 230 BUG_ON(channel->status == MUSB_DMA_STATUS_UNKNOWN ||
232 pChannel->status == MUSB_DMA_STATUS_BUSY); 231 channel->status == MUSB_DMA_STATUS_BUSY);
233 232
234 pChannel->actual_len = 0; 233 channel->actual_len = 0;
235 pImplChannel->dwStartAddress = dma_addr; 234 musb_channel->start_addr = dma_addr;
236 pImplChannel->len = len; 235 musb_channel->len = len;
237 pImplChannel->wMaxPacketSize = packet_sz; 236 musb_channel->max_packet_sz = packet_sz;
238 pChannel->status = MUSB_DMA_STATUS_BUSY; 237 channel->status = MUSB_DMA_STATUS_BUSY;
239 238
240 if ((mode == 1) && (len >= packet_sz)) 239 if ((mode == 1) && (len >= packet_sz))
241 configure_channel(pChannel, packet_sz, 1, dma_addr, len); 240 configure_channel(channel, packet_sz, 1, dma_addr, len);
242 else 241 else
243 configure_channel(pChannel, packet_sz, 0, dma_addr, len); 242 configure_channel(channel, packet_sz, 0, dma_addr, len);
244 243
245 return true; 244 return true;
246} 245}
247 246
248static int dma_channel_abort(struct dma_channel *pChannel) 247static int dma_channel_abort(struct dma_channel *channel)
249{ 248{
250 struct musb_dma_channel *pImplChannel = 249 struct musb_dma_channel *musb_channel = channel->private_data;
251 (struct musb_dma_channel *) pChannel->private_data; 250 void __iomem *mbase = musb_channel->controller->base;
252 u8 bChannel = pImplChannel->bIndex; 251
253 void __iomem *mbase = pImplChannel->controller->pCoreBase; 252 u8 bchannel = musb_channel->idx;
254 u16 csr; 253 u16 csr;
255 254
256 if (pChannel->status == MUSB_DMA_STATUS_BUSY) { 255 if (channel->status == MUSB_DMA_STATUS_BUSY) {
257 if (pImplChannel->transmit) { 256 if (musb_channel->transmit) {
258 257
259 csr = musb_readw(mbase, 258 csr = musb_readw(mbase,
260 MUSB_EP_OFFSET(pImplChannel->epnum, 259 MUSB_EP_OFFSET(musb_channel->epnum,
261 MUSB_TXCSR)); 260 MUSB_TXCSR));
262 csr &= ~(MUSB_TXCSR_AUTOSET | 261 csr &= ~(MUSB_TXCSR_AUTOSET |
263 MUSB_TXCSR_DMAENAB | 262 MUSB_TXCSR_DMAENAB |
264 MUSB_TXCSR_DMAMODE); 263 MUSB_TXCSR_DMAMODE);
265 musb_writew(mbase, 264 musb_writew(mbase,
266 MUSB_EP_OFFSET(pImplChannel->epnum, 265 MUSB_EP_OFFSET(musb_channel->epnum, MUSB_TXCSR),
267 MUSB_TXCSR),
268 csr); 266 csr);
269 } else { 267 } else {
270 csr = musb_readw(mbase, 268 csr = musb_readw(mbase,
271 MUSB_EP_OFFSET(pImplChannel->epnum, 269 MUSB_EP_OFFSET(musb_channel->epnum,
272 MUSB_RXCSR)); 270 MUSB_RXCSR));
273 csr &= ~(MUSB_RXCSR_AUTOCLEAR | 271 csr &= ~(MUSB_RXCSR_AUTOCLEAR |
274 MUSB_RXCSR_DMAENAB | 272 MUSB_RXCSR_DMAENAB |
275 MUSB_RXCSR_DMAMODE); 273 MUSB_RXCSR_DMAMODE);
276 musb_writew(mbase, 274 musb_writew(mbase,
277 MUSB_EP_OFFSET(pImplChannel->epnum, 275 MUSB_EP_OFFSET(musb_channel->epnum, MUSB_RXCSR),
278 MUSB_RXCSR),
279 csr); 276 csr);
280 } 277 }
281 278
282 musb_writew(mbase, 279 musb_writew(mbase,
283 MUSB_HSDMA_CHANNEL_OFFSET(bChannel, MUSB_HSDMA_CONTROL), 280 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_CONTROL),
284 0); 281 0);
285 musb_writel(mbase, 282 musb_writel(mbase,
286 MUSB_HSDMA_CHANNEL_OFFSET(bChannel, MUSB_HSDMA_ADDRESS), 283 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDRESS),
287 0); 284 0);
288 musb_writel(mbase, 285 musb_writel(mbase,
289 MUSB_HSDMA_CHANNEL_OFFSET(bChannel, MUSB_HSDMA_COUNT), 286 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT),
290 0); 287 0);
291 288
292 pChannel->status = MUSB_DMA_STATUS_FREE; 289 channel->status = MUSB_DMA_STATUS_FREE;
293 } 290 }
291
294 return 0; 292 return 0;
295} 293}
296 294
297static irqreturn_t dma_controller_irq(int irq, void *private_data) 295static irqreturn_t dma_controller_irq(int irq, void *private_data)
298{ 296{
299 struct musb_dma_controller *controller = 297 struct musb_dma_controller *controller = private_data;
300 (struct musb_dma_controller *)private_data; 298 struct musb *musb = controller->private_data;
301 struct musb_dma_channel *pImplChannel; 299 struct musb_dma_channel *musb_channel;
302 struct musb *musb = controller->pDmaPrivate; 300 struct dma_channel *channel;
303 void __iomem *mbase = controller->pCoreBase; 301
304 struct dma_channel *pChannel; 302 void __iomem *mbase = controller->base;
305 u8 bChannel; 303
306 u16 csr;
307 u32 dwAddress;
308 u8 int_hsdma;
309 irqreturn_t retval = IRQ_NONE; 304 irqreturn_t retval = IRQ_NONE;
305
310 unsigned long flags; 306 unsigned long flags;
311 307
308 u8 bchannel;
309 u8 int_hsdma;
310
311 u32 addr;
312 u16 csr;
313
312 spin_lock_irqsave(&musb->lock, flags); 314 spin_lock_irqsave(&musb->lock, flags);
313 315
314 int_hsdma = musb_readb(mbase, MUSB_HSDMA_INTR); 316 int_hsdma = musb_readb(mbase, MUSB_HSDMA_INTR);
315 if (!int_hsdma) 317 if (!int_hsdma)
316 goto done; 318 goto done;
317 319
318 for (bChannel = 0; bChannel < MUSB_HSDMA_CHANNELS; bChannel++) { 320 for (bchannel = 0; bchannel < MUSB_HSDMA_CHANNELS; bchannel++) {
319 if (int_hsdma & (1 << bChannel)) { 321 if (int_hsdma & (1 << bchannel)) {
320 pImplChannel = (struct musb_dma_channel *) 322 musb_channel = (struct musb_dma_channel *)
321 &(controller->aChannel[bChannel]); 323 &(controller->channel[bchannel]);
322 pChannel = &pImplChannel->Channel; 324 channel = &musb_channel->channel;
323 325
324 csr = musb_readw(mbase, 326 csr = musb_readw(mbase,
325 MUSB_HSDMA_CHANNEL_OFFSET(bChannel, 327 MUSB_HSDMA_CHANNEL_OFFSET(bchannel,
326 MUSB_HSDMA_CONTROL)); 328 MUSB_HSDMA_CONTROL));
327 329
328 if (csr & (1 << MUSB_HSDMA_BUSERROR_SHIFT)) 330 if (csr & (1 << MUSB_HSDMA_BUSERROR_SHIFT)) {
329 pImplChannel->Channel.status = 331 musb_channel->channel.status =
330 MUSB_DMA_STATUS_BUS_ABORT; 332 MUSB_DMA_STATUS_BUS_ABORT;
331 else { 333 } else {
332 u8 devctl; 334 u8 devctl;
333 335
334 dwAddress = musb_readl(mbase, 336 addr = musb_readl(mbase,
335 MUSB_HSDMA_CHANNEL_OFFSET( 337 MUSB_HSDMA_CHANNEL_OFFSET(
336 bChannel, 338 bchannel,
337 MUSB_HSDMA_ADDRESS)); 339 MUSB_HSDMA_ADDRESS));
338 pChannel->actual_len = dwAddress 340 channel->actual_len = addr
339 - pImplChannel->dwStartAddress; 341 - musb_channel->start_addr;
340 342
341 DBG(2, "ch %p, 0x%x -> 0x%x (%d / %d) %s\n", 343 DBG(2, "ch %p, 0x%x -> 0x%x (%d / %d) %s\n",
342 pChannel, pImplChannel->dwStartAddress, 344 channel, musb_channel->start_addr,
343 dwAddress, pChannel->actual_len, 345 addr, channel->actual_len,
344 pImplChannel->len, 346 musb_channel->len,
345 (pChannel->actual_len 347 (channel->actual_len
346 < pImplChannel->len) ? 348 < musb_channel->len) ?
347 "=> reconfig 0" : "=> complete"); 349 "=> reconfig 0" : "=> complete");
348 350
349 devctl = musb_readb(mbase, MUSB_DEVCTL); 351 devctl = musb_readb(mbase, MUSB_DEVCTL);
350 352
351 pChannel->status = MUSB_DMA_STATUS_FREE; 353 channel->status = MUSB_DMA_STATUS_FREE;
352 354
353 /* completed */ 355 /* completed */
354 if ((devctl & MUSB_DEVCTL_HM) 356 if ((devctl & MUSB_DEVCTL_HM)
355 && (pImplChannel->transmit) 357 && (musb_channel->transmit)
356 && ((pChannel->desired_mode == 0) 358 && ((channel->desired_mode == 0)
357 || (pChannel->actual_len & 359 || (channel->actual_len &
358 (pImplChannel->wMaxPacketSize - 1))) 360 (musb_channel->max_packet_sz - 1)))
359 ) { 361 ) {
360 /* Send out the packet */ 362 /* Send out the packet */
361 musb_ep_select(mbase, 363 musb_ep_select(mbase,
362 pImplChannel->epnum); 364 musb_channel->epnum);
363 musb_writew(mbase, MUSB_EP_OFFSET( 365 musb_writew(mbase, MUSB_EP_OFFSET(
364 pImplChannel->epnum, 366 musb_channel->epnum,
365 MUSB_TXCSR), 367 MUSB_TXCSR),
366 MUSB_TXCSR_TXPKTRDY); 368 MUSB_TXCSR_TXPKTRDY);
367 } else 369 } else {
368 musb_dma_completion( 370 musb_dma_completion(
369 musb, 371 musb,
370 pImplChannel->epnum, 372 musb_channel->epnum,
371 pImplChannel->transmit); 373 musb_channel->transmit);
374 }
372 } 375 }
373 } 376 }
374 } 377 }
@@ -380,9 +383,9 @@ done:
380 383
381void dma_controller_destroy(struct dma_controller *c) 384void dma_controller_destroy(struct dma_controller *c)
382{ 385{
383 struct musb_dma_controller *controller; 386 struct musb_dma_controller *controller = container_of(c,
387 struct musb_dma_controller, controller);
384 388
385 controller = container_of(c, struct musb_dma_controller, Controller);
386 if (!controller) 389 if (!controller)
387 return; 390 return;
388 391
@@ -393,7 +396,7 @@ void dma_controller_destroy(struct dma_controller *c)
393} 396}
394 397
395struct dma_controller *__init 398struct dma_controller *__init
396dma_controller_create(struct musb *musb, void __iomem *pCoreBase) 399dma_controller_create(struct musb *musb, void __iomem *base)
397{ 400{
398 struct musb_dma_controller *controller; 401 struct musb_dma_controller *controller;
399 struct device *dev = musb->controller; 402 struct device *dev = musb->controller;
@@ -405,29 +408,30 @@ dma_controller_create(struct musb *musb, void __iomem *pCoreBase)
405 return NULL; 408 return NULL;
406 } 409 }
407 410
408 controller = kzalloc(sizeof(struct musb_dma_controller), GFP_KERNEL); 411 controller = kzalloc(sizeof(*controller), GFP_KERNEL);
409 if (!controller) 412 if (!controller)
410 return NULL; 413 return NULL;
411 414
412 controller->bChannelCount = MUSB_HSDMA_CHANNELS; 415 controller->channel_count = MUSB_HSDMA_CHANNELS;
413 controller->pDmaPrivate = musb; 416 controller->private_data = musb;
414 controller->pCoreBase = pCoreBase; 417 controller->base = base;
415 418
416 controller->Controller.start = dma_controller_start; 419 controller->controller.start = dma_controller_start;
417 controller->Controller.stop = dma_controller_stop; 420 controller->controller.stop = dma_controller_stop;
418 controller->Controller.channel_alloc = dma_channel_allocate; 421 controller->controller.channel_alloc = dma_channel_allocate;
419 controller->Controller.channel_release = dma_channel_release; 422 controller->controller.channel_release = dma_channel_release;
420 controller->Controller.channel_program = dma_channel_program; 423 controller->controller.channel_program = dma_channel_program;
421 controller->Controller.channel_abort = dma_channel_abort; 424 controller->controller.channel_abort = dma_channel_abort;
422 425
423 if (request_irq(irq, dma_controller_irq, IRQF_DISABLED, 426 if (request_irq(irq, dma_controller_irq, IRQF_DISABLED,
424 musb->controller->bus_id, &controller->Controller)) { 427 musb->controller->bus_id, &controller->controller)) {
425 dev_err(dev, "request_irq %d failed!\n", irq); 428 dev_err(dev, "request_irq %d failed!\n", irq);
426 dma_controller_destroy(&controller->Controller); 429 dma_controller_destroy(&controller->controller);
430
427 return NULL; 431 return NULL;
428 } 432 }
429 433
430 controller->irq = irq; 434 controller->irq = irq;
431 435
432 return &controller->Controller; 436 return &controller->controller;
433} 437}