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authorFelipe Balbi <balbi@ti.com>2011-05-11 05:44:08 -0400
committerFelipe Balbi <balbi@ti.com>2011-05-13 07:34:04 -0400
commit5c8a86e10a7c164f44537fabdc169fd8b4e7a440 (patch)
tree96fe3eb08b9ae01f62e45b725049d3f2aa6b7bba /drivers/usb/musb/tusb6010.c
parenta0885924326f79e157847010a9aaf49b058b30dc (diff)
usb: musb: drop unneeded musb_debug trickery
We have a generic way of enabling/disabling different debug messages on a driver called DYNAMIC_PRINTK. Anyone interested in enabling just part of the debug messages, please read the documentation under: Documentation/dynamic-debug-howto.txt for information on how to use that great infrastructure. Signed-off-by: Felipe Balbi <balbi@ti.com>
Diffstat (limited to 'drivers/usb/musb/tusb6010.c')
-rw-r--r--drivers/usb/musb/tusb6010.c48
1 files changed, 24 insertions, 24 deletions
diff --git a/drivers/usb/musb/tusb6010.c b/drivers/usb/musb/tusb6010.c
index 221feaaded72..2f683a67ebb4 100644
--- a/drivers/usb/musb/tusb6010.c
+++ b/drivers/usb/musb/tusb6010.c
@@ -106,7 +106,7 @@ static void tusb_wbus_quirk(struct musb *musb, int enabled)
106 tmp = phy_otg_ena & ~WBUS_QUIRK_MASK; 106 tmp = phy_otg_ena & ~WBUS_QUIRK_MASK;
107 tmp |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_TESTM2; 107 tmp |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_TESTM2;
108 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, tmp); 108 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, tmp);
109 DBG(2, "Enabled tusb wbus quirk ctrl %08x ena %08x\n", 109 dev_dbg(musb->controller, "Enabled tusb wbus quirk ctrl %08x ena %08x\n",
110 musb_readl(tbase, TUSB_PHY_OTG_CTRL), 110 musb_readl(tbase, TUSB_PHY_OTG_CTRL),
111 musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE)); 111 musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE));
112 } else if (musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE) 112 } else if (musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE)
@@ -115,7 +115,7 @@ static void tusb_wbus_quirk(struct musb *musb, int enabled)
115 musb_writel(tbase, TUSB_PHY_OTG_CTRL, tmp); 115 musb_writel(tbase, TUSB_PHY_OTG_CTRL, tmp);
116 tmp = TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ena; 116 tmp = TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ena;
117 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, tmp); 117 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, tmp);
118 DBG(2, "Disabled tusb wbus quirk ctrl %08x ena %08x\n", 118 dev_dbg(musb->controller, "Disabled tusb wbus quirk ctrl %08x ena %08x\n",
119 musb_readl(tbase, TUSB_PHY_OTG_CTRL), 119 musb_readl(tbase, TUSB_PHY_OTG_CTRL),
120 musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE)); 120 musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE));
121 phy_otg_ctrl = 0; 121 phy_otg_ctrl = 0;
@@ -178,7 +178,7 @@ void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *buf)
178 178
179 prefetch(buf); 179 prefetch(buf);
180 180
181 DBG(4, "%cX ep%d fifo %p count %d buf %p\n", 181 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
182 'T', epnum, fifo, len, buf); 182 'T', epnum, fifo, len, buf);
183 183
184 if (epnum) 184 if (epnum)
@@ -225,7 +225,7 @@ void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *buf)
225 void __iomem *fifo = hw_ep->fifo; 225 void __iomem *fifo = hw_ep->fifo;
226 u8 epnum = hw_ep->epnum; 226 u8 epnum = hw_ep->epnum;
227 227
228 DBG(4, "%cX ep%d fifo %p count %d buf %p\n", 228 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
229 'R', epnum, fifo, len, buf); 229 'R', epnum, fifo, len, buf);
230 230
231 if (epnum) 231 if (epnum)
@@ -304,7 +304,7 @@ static int tusb_draw_power(struct otg_transceiver *x, unsigned mA)
304 } 304 }
305 musb_writel(tbase, TUSB_PRCM_MNGMT, reg); 305 musb_writel(tbase, TUSB_PRCM_MNGMT, reg);
306 306
307 DBG(2, "draw max %d mA VBUS\n", mA); 307 dev_dbg(musb->controller, "draw max %d mA VBUS\n", mA);
308 return 0; 308 return 0;
309} 309}
310 310
@@ -374,7 +374,7 @@ static void tusb_allow_idle(struct musb *musb, u32 wakeup_enables)
374 reg |= TUSB_PRCM_MNGMT_PM_IDLE | TUSB_PRCM_MNGMT_DEV_IDLE; 374 reg |= TUSB_PRCM_MNGMT_PM_IDLE | TUSB_PRCM_MNGMT_DEV_IDLE;
375 musb_writel(tbase, TUSB_PRCM_MNGMT, reg); 375 musb_writel(tbase, TUSB_PRCM_MNGMT, reg);
376 376
377 DBG(6, "idle, wake on %02x\n", wakeup_enables); 377 dev_dbg(musb->controller, "idle, wake on %02x\n", wakeup_enables);
378} 378}
379 379
380/* 380/*
@@ -421,7 +421,7 @@ static void musb_do_idle(unsigned long _musb)
421 if ((musb->a_wait_bcon != 0) 421 if ((musb->a_wait_bcon != 0)
422 && (musb->idle_timeout == 0 422 && (musb->idle_timeout == 0
423 || time_after(jiffies, musb->idle_timeout))) { 423 || time_after(jiffies, musb->idle_timeout))) {
424 DBG(4, "Nothing connected %s, turning off VBUS\n", 424 dev_dbg(musb->controller, "Nothing connected %s, turning off VBUS\n",
425 otg_state_string(musb->xceiv->state)); 425 otg_state_string(musb->xceiv->state));
426 } 426 }
427 /* FALLTHROUGH */ 427 /* FALLTHROUGH */
@@ -481,7 +481,7 @@ static void tusb_musb_try_idle(struct musb *musb, unsigned long timeout)
481 /* Never idle if active, or when VBUS timeout is not set as host */ 481 /* Never idle if active, or when VBUS timeout is not set as host */
482 if (musb->is_active || ((musb->a_wait_bcon == 0) 482 if (musb->is_active || ((musb->a_wait_bcon == 0)
483 && (musb->xceiv->state == OTG_STATE_A_WAIT_BCON))) { 483 && (musb->xceiv->state == OTG_STATE_A_WAIT_BCON))) {
484 DBG(4, "%s active, deleting timer\n", 484 dev_dbg(musb->controller, "%s active, deleting timer\n",
485 otg_state_string(musb->xceiv->state)); 485 otg_state_string(musb->xceiv->state));
486 del_timer(&musb_idle_timer); 486 del_timer(&musb_idle_timer);
487 last_timer = jiffies; 487 last_timer = jiffies;
@@ -492,13 +492,13 @@ static void tusb_musb_try_idle(struct musb *musb, unsigned long timeout)
492 if (!timer_pending(&musb_idle_timer)) 492 if (!timer_pending(&musb_idle_timer))
493 last_timer = timeout; 493 last_timer = timeout;
494 else { 494 else {
495 DBG(4, "Longer idle timer already pending, ignoring\n"); 495 dev_dbg(musb->controller, "Longer idle timer already pending, ignoring\n");
496 return; 496 return;
497 } 497 }
498 } 498 }
499 last_timer = timeout; 499 last_timer = timeout;
500 500
501 DBG(4, "%s inactive, for idle timer for %lu ms\n", 501 dev_dbg(musb->controller, "%s inactive, for idle timer for %lu ms\n",
502 otg_state_string(musb->xceiv->state), 502 otg_state_string(musb->xceiv->state),
503 (unsigned long)jiffies_to_msecs(timeout - jiffies)); 503 (unsigned long)jiffies_to_msecs(timeout - jiffies));
504 mod_timer(&musb_idle_timer, timeout); 504 mod_timer(&musb_idle_timer, timeout);
@@ -573,7 +573,7 @@ static void tusb_musb_set_vbus(struct musb *musb, int is_on)
573 musb_writel(tbase, TUSB_DEV_CONF, conf); 573 musb_writel(tbase, TUSB_DEV_CONF, conf);
574 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl); 574 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
575 575
576 DBG(1, "VBUS %s, devctl %02x otg %3x conf %08x prcm %08x\n", 576 dev_dbg(musb->controller, "VBUS %s, devctl %02x otg %3x conf %08x prcm %08x\n",
577 otg_state_string(musb->xceiv->state), 577 otg_state_string(musb->xceiv->state),
578 musb_readb(musb->mregs, MUSB_DEVCTL), 578 musb_readb(musb->mregs, MUSB_DEVCTL),
579 musb_readl(tbase, TUSB_DEV_OTG_STAT), 579 musb_readl(tbase, TUSB_DEV_OTG_STAT),
@@ -634,7 +634,7 @@ static int tusb_musb_set_mode(struct musb *musb, u8 musb_mode)
634#endif 634#endif
635 635
636 default: 636 default:
637 DBG(2, "Trying to set mode %i\n", musb_mode); 637 dev_dbg(musb->controller, "Trying to set mode %i\n", musb_mode);
638 return -EINVAL; 638 return -EINVAL;
639 } 639 }
640 640
@@ -667,7 +667,7 @@ tusb_otg_ints(struct musb *musb, u32 int_src, void __iomem *tbase)
667 default_a = !(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS); 667 default_a = !(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS);
668 else 668 else
669 default_a = is_host_enabled(musb); 669 default_a = is_host_enabled(musb);
670 DBG(2, "Default-%c\n", default_a ? 'A' : 'B'); 670 dev_dbg(musb->controller, "Default-%c\n", default_a ? 'A' : 'B');
671 musb->xceiv->default_a = default_a; 671 musb->xceiv->default_a = default_a;
672 tusb_musb_set_vbus(musb, default_a); 672 tusb_musb_set_vbus(musb, default_a);
673 673
@@ -694,7 +694,7 @@ tusb_otg_ints(struct musb *musb, u32 int_src, void __iomem *tbase)
694#endif 694#endif
695 695
696 if (otg_stat & TUSB_DEV_OTG_STAT_SESS_END) { 696 if (otg_stat & TUSB_DEV_OTG_STAT_SESS_END) {
697 DBG(1, "Forcing disconnect (no interrupt)\n"); 697 dev_dbg(musb->controller, "Forcing disconnect (no interrupt)\n");
698 if (musb->xceiv->state != OTG_STATE_B_IDLE) { 698 if (musb->xceiv->state != OTG_STATE_B_IDLE) {
699 /* INTR_DISCONNECT can hide... */ 699 /* INTR_DISCONNECT can hide... */
700 musb->xceiv->state = OTG_STATE_B_IDLE; 700 musb->xceiv->state = OTG_STATE_B_IDLE;
@@ -702,18 +702,18 @@ tusb_otg_ints(struct musb *musb, u32 int_src, void __iomem *tbase)
702 } 702 }
703 musb->is_active = 0; 703 musb->is_active = 0;
704 } 704 }
705 DBG(2, "vbus change, %s, otg %03x\n", 705 dev_dbg(musb->controller, "vbus change, %s, otg %03x\n",
706 otg_state_string(musb->xceiv->state), otg_stat); 706 otg_state_string(musb->xceiv->state), otg_stat);
707 idle_timeout = jiffies + (1 * HZ); 707 idle_timeout = jiffies + (1 * HZ);
708 schedule_work(&musb->irq_work); 708 schedule_work(&musb->irq_work);
709 709
710 } else /* A-dev state machine */ { 710 } else /* A-dev state machine */ {
711 DBG(2, "vbus change, %s, otg %03x\n", 711 dev_dbg(musb->controller, "vbus change, %s, otg %03x\n",
712 otg_state_string(musb->xceiv->state), otg_stat); 712 otg_state_string(musb->xceiv->state), otg_stat);
713 713
714 switch (musb->xceiv->state) { 714 switch (musb->xceiv->state) {
715 case OTG_STATE_A_IDLE: 715 case OTG_STATE_A_IDLE:
716 DBG(2, "Got SRP, turning on VBUS\n"); 716 dev_dbg(musb->controller, "Got SRP, turning on VBUS\n");
717 musb_platform_set_vbus(musb, 1); 717 musb_platform_set_vbus(musb, 1);
718 718
719 /* CONNECT can wake if a_wait_bcon is set */ 719 /* CONNECT can wake if a_wait_bcon is set */
@@ -757,7 +757,7 @@ tusb_otg_ints(struct musb *musb, u32 int_src, void __iomem *tbase)
757 if (int_src & TUSB_INT_SRC_OTG_TIMEOUT) { 757 if (int_src & TUSB_INT_SRC_OTG_TIMEOUT) {
758 u8 devctl; 758 u8 devctl;
759 759
760 DBG(4, "%s timer, %03x\n", 760 dev_dbg(musb->controller, "%s timer, %03x\n",
761 otg_state_string(musb->xceiv->state), otg_stat); 761 otg_state_string(musb->xceiv->state), otg_stat);
762 762
763 switch (musb->xceiv->state) { 763 switch (musb->xceiv->state) {
@@ -769,7 +769,7 @@ tusb_otg_ints(struct musb *musb, u32 int_src, void __iomem *tbase)
769 if (otg_stat & TUSB_DEV_OTG_STAT_VBUS_VALID) { 769 if (otg_stat & TUSB_DEV_OTG_STAT_VBUS_VALID) {
770 if ((devctl & MUSB_DEVCTL_VBUS) 770 if ((devctl & MUSB_DEVCTL_VBUS)
771 != MUSB_DEVCTL_VBUS) { 771 != MUSB_DEVCTL_VBUS) {
772 DBG(2, "devctl %02x\n", devctl); 772 dev_dbg(musb->controller, "devctl %02x\n", devctl);
773 break; 773 break;
774 } 774 }
775 musb->xceiv->state = OTG_STATE_A_WAIT_BCON; 775 musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
@@ -814,7 +814,7 @@ static irqreturn_t tusb_musb_interrupt(int irq, void *__hci)
814 musb_writel(tbase, TUSB_INT_MASK, ~TUSB_INT_MASK_RESERVED_BITS); 814 musb_writel(tbase, TUSB_INT_MASK, ~TUSB_INT_MASK_RESERVED_BITS);
815 815
816 int_src = musb_readl(tbase, TUSB_INT_SRC) & ~TUSB_INT_SRC_RESERVED_BITS; 816 int_src = musb_readl(tbase, TUSB_INT_SRC) & ~TUSB_INT_SRC_RESERVED_BITS;
817 DBG(3, "TUSB IRQ %08x\n", int_src); 817 dev_dbg(musb->controller, "TUSB IRQ %08x\n", int_src);
818 818
819 musb->int_usb = (u8) int_src; 819 musb->int_usb = (u8) int_src;
820 820
@@ -835,7 +835,7 @@ static irqreturn_t tusb_musb_interrupt(int irq, void *__hci)
835 reg = musb_readl(tbase, TUSB_SCRATCH_PAD); 835 reg = musb_readl(tbase, TUSB_SCRATCH_PAD);
836 if (reg == i) 836 if (reg == i)
837 break; 837 break;
838 DBG(6, "TUSB NOR not ready\n"); 838 dev_dbg(musb->controller, "TUSB NOR not ready\n");
839 } 839 }
840 840
841 /* work around issue 13 (2nd half) */ 841 /* work around issue 13 (2nd half) */
@@ -847,7 +847,7 @@ static irqreturn_t tusb_musb_interrupt(int irq, void *__hci)
847 musb->is_active = 1; 847 musb->is_active = 1;
848 schedule_work(&musb->irq_work); 848 schedule_work(&musb->irq_work);
849 } 849 }
850 DBG(3, "wake %sactive %02x\n", 850 dev_dbg(musb->controller, "wake %sactive %02x\n",
851 musb->is_active ? "" : "in", reg); 851 musb->is_active ? "" : "in", reg);
852 852
853 /* REVISIT host side TUSB_PRCM_WHOSTDISCON, TUSB_PRCM_WBUS */ 853 /* REVISIT host side TUSB_PRCM_WHOSTDISCON, TUSB_PRCM_WBUS */
@@ -869,7 +869,7 @@ static irqreturn_t tusb_musb_interrupt(int irq, void *__hci)
869 u32 dma_src = musb_readl(tbase, TUSB_DMA_INT_SRC); 869 u32 dma_src = musb_readl(tbase, TUSB_DMA_INT_SRC);
870 u32 real_dma_src = musb_readl(tbase, TUSB_DMA_INT_MASK); 870 u32 real_dma_src = musb_readl(tbase, TUSB_DMA_INT_MASK);
871 871
872 DBG(3, "DMA IRQ %08x\n", dma_src); 872 dev_dbg(musb->controller, "DMA IRQ %08x\n", dma_src);
873 real_dma_src = ~real_dma_src & dma_src; 873 real_dma_src = ~real_dma_src & dma_src;
874 if (tusb_dma_omap() && real_dma_src) { 874 if (tusb_dma_omap() && real_dma_src) {
875 int tx_source = (real_dma_src & 0xffff); 875 int tx_source = (real_dma_src & 0xffff);
@@ -877,7 +877,7 @@ static irqreturn_t tusb_musb_interrupt(int irq, void *__hci)
877 877
878 for (i = 1; i <= 15; i++) { 878 for (i = 1; i <= 15; i++) {
879 if (tx_source & (1 << i)) { 879 if (tx_source & (1 << i)) {
880 DBG(3, "completing ep%i %s\n", i, "tx"); 880 dev_dbg(musb->controller, "completing ep%i %s\n", i, "tx");
881 musb_dma_completion(musb, i, 1); 881 musb_dma_completion(musb, i, 1);
882 } 882 }
883 } 883 }