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authorFelipe Balbi <felipe.balbi@nokia.com>2008-07-24 05:27:36 -0400
committerGreg Kroah-Hartman <gregkh@suse.de>2008-08-13 20:33:00 -0400
commit550a7375fe720924241f0eb76e4a5c1a3eb8c32f (patch)
treebf973b43f6248e085557dcc268ad04d6e438d030 /drivers/usb/musb/davinci.c
parentf331e40ee8e4861e1d82310b1af7cf75de7370ac (diff)
USB: Add MUSB and TUSB support
This patch adds support for MUSB and TUSB controllers integrated into omap2430 and davinci. It also adds support for external tusb6010 controller. Cc: David Brownell <dbrownell@users.sourceforge.net> Cc: Tony Lindgren <tony@atomide.com> Signed-off-by: Felipe Balbi <felipe.balbi@nokia.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'drivers/usb/musb/davinci.c')
-rw-r--r--drivers/usb/musb/davinci.c462
1 files changed, 462 insertions, 0 deletions
diff --git a/drivers/usb/musb/davinci.c b/drivers/usb/musb/davinci.c
new file mode 100644
index 000000000000..75baf181a8cd
--- /dev/null
+++ b/drivers/usb/musb/davinci.c
@@ -0,0 +1,462 @@
1/*
2 * Copyright (C) 2005-2006 by Texas Instruments
3 *
4 * This file is part of the Inventra Controller Driver for Linux.
5 *
6 * The Inventra Controller Driver for Linux is free software; you
7 * can redistribute it and/or modify it under the terms of the GNU
8 * General Public License version 2 as published by the Free Software
9 * Foundation.
10 *
11 * The Inventra Controller Driver for Linux is distributed in
12 * the hope that it will be useful, but WITHOUT ANY WARRANTY;
13 * without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 * License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with The Inventra Controller Driver for Linux ; if not,
19 * write to the Free Software Foundation, Inc., 59 Temple Place,
20 * Suite 330, Boston, MA 02111-1307 USA
21 *
22 */
23
24#include <linux/module.h>
25#include <linux/kernel.h>
26#include <linux/sched.h>
27#include <linux/slab.h>
28#include <linux/init.h>
29#include <linux/list.h>
30#include <linux/delay.h>
31#include <linux/clk.h>
32#include <linux/io.h>
33
34#include <asm/arch/hardware.h>
35#include <asm/arch/memory.h>
36#include <asm/arch/gpio.h>
37#include <asm/mach-types.h>
38
39#include "musb_core.h"
40
41#ifdef CONFIG_MACH_DAVINCI_EVM
42#include <asm/arch/i2c-client.h>
43#endif
44
45#include "davinci.h"
46#include "cppi_dma.h"
47
48
49/* REVISIT (PM) we should be able to keep the PHY in low power mode most
50 * of the time (24 MHZ oscillator and PLL off, etc) by setting POWER.D0
51 * and, when in host mode, autosuspending idle root ports... PHYPLLON
52 * (overriding SUSPENDM?) then likely needs to stay off.
53 */
54
55static inline void phy_on(void)
56{
57 /* start the on-chip PHY and its PLL */
58 __raw_writel(USBPHY_SESNDEN | USBPHY_VBDTCTEN | USBPHY_PHYPLLON,
59 (void __force __iomem *) IO_ADDRESS(USBPHY_CTL_PADDR));
60 while ((__raw_readl((void __force __iomem *)
61 IO_ADDRESS(USBPHY_CTL_PADDR))
62 & USBPHY_PHYCLKGD) == 0)
63 cpu_relax();
64}
65
66static inline void phy_off(void)
67{
68 /* powerdown the on-chip PHY and its oscillator */
69 __raw_writel(USBPHY_OSCPDWN | USBPHY_PHYPDWN, (void __force __iomem *)
70 IO_ADDRESS(USBPHY_CTL_PADDR));
71}
72
73static int dma_off = 1;
74
75void musb_platform_enable(struct musb *musb)
76{
77 u32 tmp, old, val;
78
79 /* workaround: setup irqs through both register sets */
80 tmp = (musb->epmask & DAVINCI_USB_TX_ENDPTS_MASK)
81 << DAVINCI_USB_TXINT_SHIFT;
82 musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_SET_REG, tmp);
83 old = tmp;
84 tmp = (musb->epmask & (0xfffe & DAVINCI_USB_RX_ENDPTS_MASK))
85 << DAVINCI_USB_RXINT_SHIFT;
86 musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_SET_REG, tmp);
87 tmp |= old;
88
89 val = ~MUSB_INTR_SOF;
90 tmp |= ((val & 0x01ff) << DAVINCI_USB_USBINT_SHIFT);
91 musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_SET_REG, tmp);
92
93 if (is_dma_capable() && !dma_off)
94 printk(KERN_WARNING "%s %s: dma not reactivated\n",
95 __FILE__, __func__);
96 else
97 dma_off = 0;
98
99 /* force a DRVVBUS irq so we can start polling for ID change */
100 if (is_otg_enabled(musb))
101 musb_writel(musb->ctrl_base, DAVINCI_USB_INT_SET_REG,
102 DAVINCI_INTR_DRVVBUS << DAVINCI_USB_USBINT_SHIFT);
103}
104
105/*
106 * Disable the HDRC and flush interrupts
107 */
108void musb_platform_disable(struct musb *musb)
109{
110 /* because we don't set CTRLR.UINT, "important" to:
111 * - not read/write INTRUSB/INTRUSBE
112 * - (except during initial setup, as workaround)
113 * - use INTSETR/INTCLRR instead
114 */
115 musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_CLR_REG,
116 DAVINCI_USB_USBINT_MASK
117 | DAVINCI_USB_TXINT_MASK
118 | DAVINCI_USB_RXINT_MASK);
119 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
120 musb_writel(musb->ctrl_base, DAVINCI_USB_EOI_REG, 0);
121
122 if (is_dma_capable() && !dma_off)
123 WARNING("dma still active\n");
124}
125
126
127/* REVISIT it's not clear whether DaVinci can support full OTG. */
128
129static int vbus_state = -1;
130
131#ifdef CONFIG_USB_MUSB_HDRC_HCD
132#define portstate(stmt) stmt
133#else
134#define portstate(stmt)
135#endif
136
137
138/* VBUS SWITCHING IS BOARD-SPECIFIC */
139
140#ifdef CONFIG_MACH_DAVINCI_EVM
141#ifndef CONFIG_MACH_DAVINCI_EVM_OTG
142
143/* I2C operations are always synchronous, and require a task context.
144 * With unloaded systems, using the shared workqueue seems to suffice
145 * to satisfy the 100msec A_WAIT_VRISE timeout...
146 */
147static void evm_deferred_drvvbus(struct work_struct *ignored)
148{
149 davinci_i2c_expander_op(0x3a, USB_DRVVBUS, vbus_state);
150 vbus_state = !vbus_state;
151}
152static DECLARE_WORK(evm_vbus_work, evm_deferred_drvvbus);
153
154#endif /* modified board */
155#endif /* EVM */
156
157static void davinci_source_power(struct musb *musb, int is_on, int immediate)
158{
159 if (is_on)
160 is_on = 1;
161
162 if (vbus_state == is_on)
163 return;
164 vbus_state = !is_on; /* 0/1 vs "-1 == unknown/init" */
165
166#ifdef CONFIG_MACH_DAVINCI_EVM
167 if (machine_is_davinci_evm()) {
168#ifdef CONFIG_MACH_DAVINCI_EVM_OTG
169 /* modified EVM board switching VBUS with GPIO(6) not I2C
170 * NOTE: PINMUX0.RGB888 (bit23) must be clear
171 */
172 if (is_on)
173 gpio_set(GPIO(6));
174 else
175 gpio_clear(GPIO(6));
176 immediate = 1;
177#else
178 if (immediate)
179 davinci_i2c_expander_op(0x3a, USB_DRVVBUS, !is_on);
180 else
181 schedule_work(&evm_vbus_work);
182#endif
183 }
184#endif
185 if (immediate)
186 vbus_state = is_on;
187}
188
189static void davinci_set_vbus(struct musb *musb, int is_on)
190{
191 WARN_ON(is_on && is_peripheral_active(musb));
192 davinci_source_power(musb, is_on, 0);
193}
194
195
196#define POLL_SECONDS 2
197
198static struct timer_list otg_workaround;
199
200static void otg_timer(unsigned long _musb)
201{
202 struct musb *musb = (void *)_musb;
203 void __iomem *mregs = musb->mregs;
204 u8 devctl;
205 unsigned long flags;
206
207 /* We poll because DaVinci's won't expose several OTG-critical
208 * status change events (from the transceiver) otherwise.
209 */
210 devctl = musb_readb(mregs, MUSB_DEVCTL);
211 DBG(7, "poll devctl %02x (%s)\n", devctl, otg_state_string(musb));
212
213 spin_lock_irqsave(&musb->lock, flags);
214 switch (musb->xceiv.state) {
215 case OTG_STATE_A_WAIT_VFALL:
216 /* Wait till VBUS falls below SessionEnd (~0.2V); the 1.3 RTL
217 * seems to mis-handle session "start" otherwise (or in our
218 * case "recover"), in routine "VBUS was valid by the time
219 * VBUSERR got reported during enumeration" cases.
220 */
221 if (devctl & MUSB_DEVCTL_VBUS) {
222 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
223 break;
224 }
225 musb->xceiv.state = OTG_STATE_A_WAIT_VRISE;
226 musb_writel(musb->ctrl_base, DAVINCI_USB_INT_SET_REG,
227 MUSB_INTR_VBUSERROR << DAVINCI_USB_USBINT_SHIFT);
228 break;
229 case OTG_STATE_B_IDLE:
230 if (!is_peripheral_enabled(musb))
231 break;
232
233 /* There's no ID-changed IRQ, so we have no good way to tell
234 * when to switch to the A-Default state machine (by setting
235 * the DEVCTL.SESSION flag).
236 *
237 * Workaround: whenever we're in B_IDLE, try setting the
238 * session flag every few seconds. If it works, ID was
239 * grounded and we're now in the A-Default state machine.
240 *
241 * NOTE setting the session flag is _supposed_ to trigger
242 * SRP, but clearly it doesn't.
243 */
244 musb_writeb(mregs, MUSB_DEVCTL,
245 devctl | MUSB_DEVCTL_SESSION);
246 devctl = musb_readb(mregs, MUSB_DEVCTL);
247 if (devctl & MUSB_DEVCTL_BDEVICE)
248 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
249 else
250 musb->xceiv.state = OTG_STATE_A_IDLE;
251 break;
252 default:
253 break;
254 }
255 spin_unlock_irqrestore(&musb->lock, flags);
256}
257
258static irqreturn_t davinci_interrupt(int irq, void *__hci)
259{
260 unsigned long flags;
261 irqreturn_t retval = IRQ_NONE;
262 struct musb *musb = __hci;
263 void __iomem *tibase = musb->ctrl_base;
264 u32 tmp;
265
266 spin_lock_irqsave(&musb->lock, flags);
267
268 /* NOTE: DaVinci shadows the Mentor IRQs. Don't manage them through
269 * the Mentor registers (except for setup), use the TI ones and EOI.
270 *
271 * Docs describe irq "vector" registers asociated with the CPPI and
272 * USB EOI registers. These hold a bitmask corresponding to the
273 * current IRQ, not an irq handler address. Would using those bits
274 * resolve some of the races observed in this dispatch code??
275 */
276
277 /* CPPI interrupts share the same IRQ line, but have their own
278 * mask, state, "vector", and EOI registers.
279 */
280 if (is_cppi_enabled()) {
281 u32 cppi_tx = musb_readl(tibase, DAVINCI_TXCPPI_MASKED_REG);
282 u32 cppi_rx = musb_readl(tibase, DAVINCI_RXCPPI_MASKED_REG);
283
284 if (cppi_tx || cppi_rx) {
285 DBG(4, "CPPI IRQ t%x r%x\n", cppi_tx, cppi_rx);
286 cppi_completion(musb, cppi_rx, cppi_tx);
287 retval = IRQ_HANDLED;
288 }
289 }
290
291 /* ack and handle non-CPPI interrupts */
292 tmp = musb_readl(tibase, DAVINCI_USB_INT_SRC_MASKED_REG);
293 musb_writel(tibase, DAVINCI_USB_INT_SRC_CLR_REG, tmp);
294 DBG(4, "IRQ %08x\n", tmp);
295
296 musb->int_rx = (tmp & DAVINCI_USB_RXINT_MASK)
297 >> DAVINCI_USB_RXINT_SHIFT;
298 musb->int_tx = (tmp & DAVINCI_USB_TXINT_MASK)
299 >> DAVINCI_USB_TXINT_SHIFT;
300 musb->int_usb = (tmp & DAVINCI_USB_USBINT_MASK)
301 >> DAVINCI_USB_USBINT_SHIFT;
302
303 /* DRVVBUS irqs are the only proxy we have (a very poor one!) for
304 * DaVinci's missing ID change IRQ. We need an ID change IRQ to
305 * switch appropriately between halves of the OTG state machine.
306 * Managing DEVCTL.SESSION per Mentor docs requires we know its
307 * value, but DEVCTL.BDEVICE is invalid without DEVCTL.SESSION set.
308 * Also, DRVVBUS pulses for SRP (but not at 5V) ...
309 */
310 if (tmp & (DAVINCI_INTR_DRVVBUS << DAVINCI_USB_USBINT_SHIFT)) {
311 int drvvbus = musb_readl(tibase, DAVINCI_USB_STAT_REG);
312 void __iomem *mregs = musb->mregs;
313 u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
314 int err = musb->int_usb & MUSB_INTR_VBUSERROR;
315
316 err = is_host_enabled(musb)
317 && (musb->int_usb & MUSB_INTR_VBUSERROR);
318 if (err) {
319 /* The Mentor core doesn't debounce VBUS as needed
320 * to cope with device connect current spikes. This
321 * means it's not uncommon for bus-powered devices
322 * to get VBUS errors during enumeration.
323 *
324 * This is a workaround, but newer RTL from Mentor
325 * seems to allow a better one: "re"starting sessions
326 * without waiting (on EVM, a **long** time) for VBUS
327 * to stop registering in devctl.
328 */
329 musb->int_usb &= ~MUSB_INTR_VBUSERROR;
330 musb->xceiv.state = OTG_STATE_A_WAIT_VFALL;
331 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
332 WARNING("VBUS error workaround (delay coming)\n");
333 } else if (is_host_enabled(musb) && drvvbus) {
334 musb->is_active = 1;
335 MUSB_HST_MODE(musb);
336 musb->xceiv.default_a = 1;
337 musb->xceiv.state = OTG_STATE_A_WAIT_VRISE;
338 portstate(musb->port1_status |= USB_PORT_STAT_POWER);
339 del_timer(&otg_workaround);
340 } else {
341 musb->is_active = 0;
342 MUSB_DEV_MODE(musb);
343 musb->xceiv.default_a = 0;
344 musb->xceiv.state = OTG_STATE_B_IDLE;
345 portstate(musb->port1_status &= ~USB_PORT_STAT_POWER);
346 }
347
348 /* NOTE: this must complete poweron within 100 msec */
349 davinci_source_power(musb, drvvbus, 0);
350 DBG(2, "VBUS %s (%s)%s, devctl %02x\n",
351 drvvbus ? "on" : "off",
352 otg_state_string(musb),
353 err ? " ERROR" : "",
354 devctl);
355 retval = IRQ_HANDLED;
356 }
357
358 if (musb->int_tx || musb->int_rx || musb->int_usb)
359 retval |= musb_interrupt(musb);
360
361 /* irq stays asserted until EOI is written */
362 musb_writel(tibase, DAVINCI_USB_EOI_REG, 0);
363
364 /* poll for ID change */
365 if (is_otg_enabled(musb)
366 && musb->xceiv.state == OTG_STATE_B_IDLE)
367 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
368
369 spin_unlock_irqrestore(&musb->lock, flags);
370
371 /* REVISIT we sometimes get unhandled IRQs
372 * (e.g. ep0). not clear why...
373 */
374 if (retval != IRQ_HANDLED)
375 DBG(5, "unhandled? %08x\n", tmp);
376 return IRQ_HANDLED;
377}
378
379int __init musb_platform_init(struct musb *musb)
380{
381 void __iomem *tibase = musb->ctrl_base;
382 u32 revision;
383
384 musb->mregs += DAVINCI_BASE_OFFSET;
385#if 0
386 /* REVISIT there's something odd about clocking, this
387 * didn't appear do the job ...
388 */
389 musb->clock = clk_get(pDevice, "usb");
390 if (IS_ERR(musb->clock))
391 return PTR_ERR(musb->clock);
392
393 status = clk_enable(musb->clock);
394 if (status < 0)
395 return -ENODEV;
396#endif
397
398 /* returns zero if e.g. not clocked */
399 revision = musb_readl(tibase, DAVINCI_USB_VERSION_REG);
400 if (revision == 0)
401 return -ENODEV;
402
403 if (is_host_enabled(musb))
404 setup_timer(&otg_workaround, otg_timer, (unsigned long) musb);
405
406 musb->board_set_vbus = davinci_set_vbus;
407 davinci_source_power(musb, 0, 1);
408
409 /* reset the controller */
410 musb_writel(tibase, DAVINCI_USB_CTRL_REG, 0x1);
411
412 /* start the on-chip PHY and its PLL */
413 phy_on();
414
415 msleep(5);
416
417 /* NOTE: irqs are in mixed mode, not bypass to pure-musb */
418 pr_debug("DaVinci OTG revision %08x phy %03x control %02x\n",
419 revision, __raw_readl((void __force __iomem *)
420 IO_ADDRESS(USBPHY_CTL_PADDR)),
421 musb_readb(tibase, DAVINCI_USB_CTRL_REG));
422
423 musb->isr = davinci_interrupt;
424 return 0;
425}
426
427int musb_platform_exit(struct musb *musb)
428{
429 if (is_host_enabled(musb))
430 del_timer_sync(&otg_workaround);
431
432 davinci_source_power(musb, 0 /*off*/, 1);
433
434 /* delay, to avoid problems with module reload */
435 if (is_host_enabled(musb) && musb->xceiv.default_a) {
436 int maxdelay = 30;
437 u8 devctl, warn = 0;
438
439 /* if there's no peripheral connected, this can take a
440 * long time to fall, especially on EVM with huge C133.
441 */
442 do {
443 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
444 if (!(devctl & MUSB_DEVCTL_VBUS))
445 break;
446 if ((devctl & MUSB_DEVCTL_VBUS) != warn) {
447 warn = devctl & MUSB_DEVCTL_VBUS;
448 DBG(1, "VBUS %d\n",
449 warn >> MUSB_DEVCTL_VBUS_SHIFT);
450 }
451 msleep(1000);
452 maxdelay--;
453 } while (maxdelay > 0);
454
455 /* in OTG mode, another host might be connected */
456 if (devctl & MUSB_DEVCTL_VBUS)
457 DBG(1, "VBUS off timeout (devctl %02x)\n", devctl);
458 }
459
460 phy_off();
461 return 0;
462}