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authorRussell King <rmk@dyn-67.arm.linux.org.uk>2008-10-15 18:16:07 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2008-10-15 18:16:07 -0400
commit2502991560dc8244dbe10e48473d85722c1e2ec1 (patch)
tree63b1f3be2ed56ff06f1e8db709e4ce85d69c3add /drivers/usb/host
parent7e69a8c4d06b7ecb874f571e82b715a9f79bc3c4 (diff)
parenta9ff8f6462635c8d9f8d64b7b10ddcea8404d77b (diff)
Merge branch 'fixes' into for-linus
Conflicts: arch/arm/mach-versatile/core.c
Diffstat (limited to 'drivers/usb/host')
-rw-r--r--drivers/usb/host/ehci-ixp4xx.c2
-rw-r--r--drivers/usb/host/ehci.h138
-rw-r--r--drivers/usb/host/sl811_cs.c133
3 files changed, 57 insertions, 216 deletions
diff --git a/drivers/usb/host/ehci-ixp4xx.c b/drivers/usb/host/ehci-ixp4xx.c
index f9575c409124..9c32063a0c2f 100644
--- a/drivers/usb/host/ehci-ixp4xx.c
+++ b/drivers/usb/host/ehci-ixp4xx.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * IXP4XX EHCI Host Controller Driver 2 * IXP4XX EHCI Host Controller Driver
3 * 3 *
4 * Author: Vladimir Barinov <vbarinov@ru.mvista.com> 4 * Author: Vladimir Barinov <vbarinov@embeddedalley.com>
5 * 5 *
6 * Based on "ehci-fsl.c" by Randy Vinson <rvinson@mvista.com> 6 * Based on "ehci-fsl.c" by Randy Vinson <rvinson@mvista.com>
7 * 7 *
diff --git a/drivers/usb/host/ehci.h b/drivers/usb/host/ehci.h
index 5799298364fb..b697a13364ec 100644
--- a/drivers/usb/host/ehci.h
+++ b/drivers/usb/host/ehci.h
@@ -210,143 +210,7 @@ timer_action (struct ehci_hcd *ehci, enum ehci_timer_action action)
210 210
211/*-------------------------------------------------------------------------*/ 211/*-------------------------------------------------------------------------*/
212 212
213/* EHCI register interface, corresponds to EHCI Revision 0.95 specification */ 213#include <linux/usb/ehci_def.h>
214
215/* Section 2.2 Host Controller Capability Registers */
216struct ehci_caps {
217 /* these fields are specified as 8 and 16 bit registers,
218 * but some hosts can't perform 8 or 16 bit PCI accesses.
219 */
220 u32 hc_capbase;
221#define HC_LENGTH(p) (((p)>>00)&0x00ff) /* bits 7:0 */
222#define HC_VERSION(p) (((p)>>16)&0xffff) /* bits 31:16 */
223 u32 hcs_params; /* HCSPARAMS - offset 0x4 */
224#define HCS_DEBUG_PORT(p) (((p)>>20)&0xf) /* bits 23:20, debug port? */
225#define HCS_INDICATOR(p) ((p)&(1 << 16)) /* true: has port indicators */
226#define HCS_N_CC(p) (((p)>>12)&0xf) /* bits 15:12, #companion HCs */
227#define HCS_N_PCC(p) (((p)>>8)&0xf) /* bits 11:8, ports per CC */
228#define HCS_PORTROUTED(p) ((p)&(1 << 7)) /* true: port routing */
229#define HCS_PPC(p) ((p)&(1 << 4)) /* true: port power control */
230#define HCS_N_PORTS(p) (((p)>>0)&0xf) /* bits 3:0, ports on HC */
231
232 u32 hcc_params; /* HCCPARAMS - offset 0x8 */
233#define HCC_EXT_CAPS(p) (((p)>>8)&0xff) /* for pci extended caps */
234#define HCC_ISOC_CACHE(p) ((p)&(1 << 7)) /* true: can cache isoc frame */
235#define HCC_ISOC_THRES(p) (((p)>>4)&0x7) /* bits 6:4, uframes cached */
236#define HCC_CANPARK(p) ((p)&(1 << 2)) /* true: can park on async qh */
237#define HCC_PGM_FRAMELISTLEN(p) ((p)&(1 << 1)) /* true: periodic_size changes*/
238#define HCC_64BIT_ADDR(p) ((p)&(1)) /* true: can use 64-bit addr */
239 u8 portroute [8]; /* nibbles for routing - offset 0xC */
240} __attribute__ ((packed));
241
242
243/* Section 2.3 Host Controller Operational Registers */
244struct ehci_regs {
245
246 /* USBCMD: offset 0x00 */
247 u32 command;
248/* 23:16 is r/w intr rate, in microframes; default "8" == 1/msec */
249#define CMD_PARK (1<<11) /* enable "park" on async qh */
250#define CMD_PARK_CNT(c) (((c)>>8)&3) /* how many transfers to park for */
251#define CMD_LRESET (1<<7) /* partial reset (no ports, etc) */
252#define CMD_IAAD (1<<6) /* "doorbell" interrupt async advance */
253#define CMD_ASE (1<<5) /* async schedule enable */
254#define CMD_PSE (1<<4) /* periodic schedule enable */
255/* 3:2 is periodic frame list size */
256#define CMD_RESET (1<<1) /* reset HC not bus */
257#define CMD_RUN (1<<0) /* start/stop HC */
258
259 /* USBSTS: offset 0x04 */
260 u32 status;
261#define STS_ASS (1<<15) /* Async Schedule Status */
262#define STS_PSS (1<<14) /* Periodic Schedule Status */
263#define STS_RECL (1<<13) /* Reclamation */
264#define STS_HALT (1<<12) /* Not running (any reason) */
265/* some bits reserved */
266 /* these STS_* flags are also intr_enable bits (USBINTR) */
267#define STS_IAA (1<<5) /* Interrupted on async advance */
268#define STS_FATAL (1<<4) /* such as some PCI access errors */
269#define STS_FLR (1<<3) /* frame list rolled over */
270#define STS_PCD (1<<2) /* port change detect */
271#define STS_ERR (1<<1) /* "error" completion (overflow, ...) */
272#define STS_INT (1<<0) /* "normal" completion (short, ...) */
273
274 /* USBINTR: offset 0x08 */
275 u32 intr_enable;
276
277 /* FRINDEX: offset 0x0C */
278 u32 frame_index; /* current microframe number */
279 /* CTRLDSSEGMENT: offset 0x10 */
280 u32 segment; /* address bits 63:32 if needed */
281 /* PERIODICLISTBASE: offset 0x14 */
282 u32 frame_list; /* points to periodic list */
283 /* ASYNCLISTADDR: offset 0x18 */
284 u32 async_next; /* address of next async queue head */
285
286 u32 reserved [9];
287
288 /* CONFIGFLAG: offset 0x40 */
289 u32 configured_flag;
290#define FLAG_CF (1<<0) /* true: we'll support "high speed" */
291
292 /* PORTSC: offset 0x44 */
293 u32 port_status [0]; /* up to N_PORTS */
294/* 31:23 reserved */
295#define PORT_WKOC_E (1<<22) /* wake on overcurrent (enable) */
296#define PORT_WKDISC_E (1<<21) /* wake on disconnect (enable) */
297#define PORT_WKCONN_E (1<<20) /* wake on connect (enable) */
298/* 19:16 for port testing */
299#define PORT_LED_OFF (0<<14)
300#define PORT_LED_AMBER (1<<14)
301#define PORT_LED_GREEN (2<<14)
302#define PORT_LED_MASK (3<<14)
303#define PORT_OWNER (1<<13) /* true: companion hc owns this port */
304#define PORT_POWER (1<<12) /* true: has power (see PPC) */
305#define PORT_USB11(x) (((x)&(3<<10))==(1<<10)) /* USB 1.1 device */
306/* 11:10 for detecting lowspeed devices (reset vs release ownership) */
307/* 9 reserved */
308#define PORT_RESET (1<<8) /* reset port */
309#define PORT_SUSPEND (1<<7) /* suspend port */
310#define PORT_RESUME (1<<6) /* resume it */
311#define PORT_OCC (1<<5) /* over current change */
312#define PORT_OC (1<<4) /* over current active */
313#define PORT_PEC (1<<3) /* port enable change */
314#define PORT_PE (1<<2) /* port enable */
315#define PORT_CSC (1<<1) /* connect status change */
316#define PORT_CONNECT (1<<0) /* device connected */
317#define PORT_RWC_BITS (PORT_CSC | PORT_PEC | PORT_OCC)
318} __attribute__ ((packed));
319
320#define USBMODE 0x68 /* USB Device mode */
321#define USBMODE_SDIS (1<<3) /* Stream disable */
322#define USBMODE_BE (1<<2) /* BE/LE endianness select */
323#define USBMODE_CM_HC (3<<0) /* host controller mode */
324#define USBMODE_CM_IDLE (0<<0) /* idle state */
325
326/* Appendix C, Debug port ... intended for use with special "debug devices"
327 * that can help if there's no serial console. (nonstandard enumeration.)
328 */
329struct ehci_dbg_port {
330 u32 control;
331#define DBGP_OWNER (1<<30)
332#define DBGP_ENABLED (1<<28)
333#define DBGP_DONE (1<<16)
334#define DBGP_INUSE (1<<10)
335#define DBGP_ERRCODE(x) (((x)>>7)&0x07)
336# define DBGP_ERR_BAD 1
337# define DBGP_ERR_SIGNAL 2
338#define DBGP_ERROR (1<<6)
339#define DBGP_GO (1<<5)
340#define DBGP_OUT (1<<4)
341#define DBGP_LEN(x) (((x)>>0)&0x0f)
342 u32 pids;
343#define DBGP_PID_GET(x) (((x)>>16)&0xff)
344#define DBGP_PID_SET(data,tok) (((data)<<8)|(tok))
345 u32 data03;
346 u32 data47;
347 u32 address;
348#define DBGP_EPADDR(dev,ep) (((dev)<<8)|(ep))
349} __attribute__ ((packed));
350 214
351/*-------------------------------------------------------------------------*/ 215/*-------------------------------------------------------------------------*/
352 216
diff --git a/drivers/usb/host/sl811_cs.c b/drivers/usb/host/sl811_cs.c
index 5da63f535005..516848dd9b48 100644
--- a/drivers/usb/host/sl811_cs.c
+++ b/drivers/usb/host/sl811_cs.c
@@ -112,7 +112,8 @@ static struct platform_device platform_dev = {
112 .num_resources = ARRAY_SIZE(resources), 112 .num_resources = ARRAY_SIZE(resources),
113}; 113};
114 114
115static int sl811_hc_init(struct device *parent, ioaddr_t base_addr, int irq) 115static int sl811_hc_init(struct device *parent, resource_size_t base_addr,
116 int irq)
116{ 117{
117 if (platform_dev.dev.parent) 118 if (platform_dev.dev.parent)
118 return -EBUSY; 119 return -EBUSY;
@@ -155,97 +156,72 @@ static void sl811_cs_release(struct pcmcia_device * link)
155 platform_device_unregister(&platform_dev); 156 platform_device_unregister(&platform_dev);
156} 157}
157 158
159static int sl811_cs_config_check(struct pcmcia_device *p_dev,
160 cistpl_cftable_entry_t *cfg,
161 cistpl_cftable_entry_t *dflt,
162 unsigned int vcc,
163 void *priv_data)
164{
165 if (cfg->index == 0)
166 return -ENODEV;
167
168 /* Use power settings for Vcc and Vpp if present */
169 /* Note that the CIS values need to be rescaled */
170 if (cfg->vcc.present & (1<<CISTPL_POWER_VNOM)) {
171 if (cfg->vcc.param[CISTPL_POWER_VNOM]/10000 != vcc)
172 return -ENODEV;
173 } else if (dflt->vcc.present & (1<<CISTPL_POWER_VNOM)) {
174 if (dflt->vcc.param[CISTPL_POWER_VNOM]/10000 != vcc)
175 return -ENODEV;
176 }
177
178 if (cfg->vpp1.present & (1<<CISTPL_POWER_VNOM))
179 p_dev->conf.Vpp =
180 cfg->vpp1.param[CISTPL_POWER_VNOM]/10000;
181 else if (dflt->vpp1.present & (1<<CISTPL_POWER_VNOM))
182 p_dev->conf.Vpp =
183 dflt->vpp1.param[CISTPL_POWER_VNOM]/10000;
184
185 /* we need an interrupt */
186 if (cfg->irq.IRQInfo1 || dflt->irq.IRQInfo1)
187 p_dev->conf.Attributes |= CONF_ENABLE_IRQ;
188
189 /* IO window settings */
190 p_dev->io.NumPorts1 = p_dev->io.NumPorts2 = 0;
191 if ((cfg->io.nwin > 0) || (dflt->io.nwin > 0)) {
192 cistpl_io_t *io = (cfg->io.nwin) ? &cfg->io : &dflt->io;
193
194 p_dev->io.Attributes1 = IO_DATA_PATH_WIDTH_8;
195 p_dev->io.IOAddrLines = io->flags & CISTPL_IO_LINES_MASK;
196 p_dev->io.BasePort1 = io->win[0].base;
197 p_dev->io.NumPorts1 = io->win[0].len;
198
199 return pcmcia_request_io(p_dev, &p_dev->io);
200 }
201 pcmcia_disable_device(p_dev);
202 return -ENODEV;
203}
204
205
158static int sl811_cs_config(struct pcmcia_device *link) 206static int sl811_cs_config(struct pcmcia_device *link)
159{ 207{
160 struct device *parent = &handle_to_dev(link); 208 struct device *parent = &handle_to_dev(link);
161 local_info_t *dev = link->priv; 209 local_info_t *dev = link->priv;
162 tuple_t tuple;
163 cisparse_t parse;
164 int last_fn, last_ret; 210 int last_fn, last_ret;
165 u_char buf[64];
166 config_info_t conf;
167 cistpl_cftable_entry_t dflt = { 0 };
168 211
169 DBG(0, "sl811_cs_config(0x%p)\n", link); 212 DBG(0, "sl811_cs_config(0x%p)\n", link);
170 213
171 /* Look up the current Vcc */ 214 if (pcmcia_loop_config(link, sl811_cs_config_check, NULL))
172 CS_CHECK(GetConfigurationInfo, 215 goto failed;
173 pcmcia_get_configuration_info(link, &conf));
174
175 tuple.Attributes = 0;
176 tuple.TupleData = buf;
177 tuple.TupleDataMax = sizeof(buf);
178 tuple.TupleOffset = 0;
179 tuple.DesiredTuple = CISTPL_CFTABLE_ENTRY;
180 CS_CHECK(GetFirstTuple, pcmcia_get_first_tuple(link, &tuple));
181 while (1) {
182 cistpl_cftable_entry_t *cfg = &(parse.cftable_entry);
183
184 if (pcmcia_get_tuple_data(link, &tuple) != 0
185 || pcmcia_parse_tuple(link, &tuple, &parse)
186 != 0)
187 goto next_entry;
188
189 if (cfg->flags & CISTPL_CFTABLE_DEFAULT) {
190 dflt = *cfg;
191 }
192
193 if (cfg->index == 0)
194 goto next_entry;
195
196 link->conf.ConfigIndex = cfg->index;
197
198 /* Use power settings for Vcc and Vpp if present */
199 /* Note that the CIS values need to be rescaled */
200 if (cfg->vcc.present & (1<<CISTPL_POWER_VNOM)) {
201 if (cfg->vcc.param[CISTPL_POWER_VNOM]/10000
202 != conf.Vcc)
203 goto next_entry;
204 } else if (dflt.vcc.present & (1<<CISTPL_POWER_VNOM)) {
205 if (dflt.vcc.param[CISTPL_POWER_VNOM]/10000
206 != conf.Vcc)
207 goto next_entry;
208 }
209
210 if (cfg->vpp1.present & (1<<CISTPL_POWER_VNOM))
211 link->conf.Vpp =
212 cfg->vpp1.param[CISTPL_POWER_VNOM]/10000;
213 else if (dflt.vpp1.present & (1<<CISTPL_POWER_VNOM))
214 link->conf.Vpp =
215 dflt.vpp1.param[CISTPL_POWER_VNOM]/10000;
216
217 /* we need an interrupt */
218 if (cfg->irq.IRQInfo1 || dflt.irq.IRQInfo1)
219 link->conf.Attributes |= CONF_ENABLE_IRQ;
220
221 /* IO window settings */
222 link->io.NumPorts1 = link->io.NumPorts2 = 0;
223 if ((cfg->io.nwin > 0) || (dflt.io.nwin > 0)) {
224 cistpl_io_t *io = (cfg->io.nwin) ? &cfg->io : &dflt.io;
225
226 link->io.Attributes1 = IO_DATA_PATH_WIDTH_8;
227 link->io.IOAddrLines = io->flags & CISTPL_IO_LINES_MASK;
228 link->io.BasePort1 = io->win[0].base;
229 link->io.NumPorts1 = io->win[0].len;
230
231 if (pcmcia_request_io(link, &link->io) != 0)
232 goto next_entry;
233 }
234 break;
235
236next_entry:
237 pcmcia_disable_device(link);
238 last_ret = pcmcia_get_next_tuple(link, &tuple);
239 }
240 216
241 /* require an IRQ and two registers */ 217 /* require an IRQ and two registers */
242 if (!link->io.NumPorts1 || link->io.NumPorts1 < 2) 218 if (!link->io.NumPorts1 || link->io.NumPorts1 < 2)
243 goto cs_failed; 219 goto failed;
244 if (link->conf.Attributes & CONF_ENABLE_IRQ) 220 if (link->conf.Attributes & CONF_ENABLE_IRQ)
245 CS_CHECK(RequestIRQ, 221 CS_CHECK(RequestIRQ,
246 pcmcia_request_irq(link, &link->irq)); 222 pcmcia_request_irq(link, &link->irq));
247 else 223 else
248 goto cs_failed; 224 goto failed;
249 225
250 CS_CHECK(RequestConfiguration, 226 CS_CHECK(RequestConfiguration,
251 pcmcia_request_configuration(link, &link->conf)); 227 pcmcia_request_configuration(link, &link->conf));
@@ -266,8 +242,9 @@ next_entry:
266 if (sl811_hc_init(parent, link->io.BasePort1, link->irq.AssignedIRQ) 242 if (sl811_hc_init(parent, link->io.BasePort1, link->irq.AssignedIRQ)
267 < 0) { 243 < 0) {
268cs_failed: 244cs_failed:
269 printk("sl811_cs_config failed\n");
270 cs_error(link, last_fn, last_ret); 245 cs_error(link, last_fn, last_ret);
246failed:
247 printk(KERN_WARNING "sl811_cs_config failed\n");
271 sl811_cs_release(link); 248 sl811_cs_release(link);
272 return -ENODEV; 249 return -ENODEV;
273 } 250 }