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authorLaurent Pinchart <laurent.pinchart@ideasonboard.com>2015-01-20 17:55:56 -0500
committerFelipe Balbi <balbi@ti.com>2015-01-27 10:39:12 -0500
commite19c99e7592e06b6fdf558aa8877b671f8cf0329 (patch)
tree8fd669c7412f3822fc4c7eb1baff55d75a79f969 /drivers/usb/host
parentea0b1fabc77420261c57c4ac4f0ea384f5a8c438 (diff)
usb: isp1760: Reorganize header files
The isp1760-rhcd.h header contains PTD constants and structures only useful for the HCD implementation. It also contains register definitions that will be needed by common code when implementing support for the ISP1761 device controller, but doesn't contain the isp1760_hcd structure definition that will also be used by common code. Move definitions to the right location and create an isp1760-regs.h to store register definitions. No change other than moving definitions and modifying indentation is performed. Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Reviewed-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
Diffstat (limited to 'drivers/usb/host')
-rw-r--r--drivers/usb/host/isp1760-hcd.c130
-rw-r--r--drivers/usb/host/isp1760-hcd.h230
-rw-r--r--drivers/usb/host/isp1760-if.c1
-rw-r--r--drivers/usb/host/isp1760-regs.h120
4 files changed, 256 insertions, 225 deletions
diff --git a/drivers/usb/host/isp1760-hcd.c b/drivers/usb/host/isp1760-hcd.c
index 99f56c6686e3..50434cc5335c 100644
--- a/drivers/usb/host/isp1760-hcd.c
+++ b/drivers/usb/host/isp1760-hcd.c
@@ -27,41 +27,12 @@
27#include <asm/cacheflush.h> 27#include <asm/cacheflush.h>
28 28
29#include "isp1760-hcd.h" 29#include "isp1760-hcd.h"
30#include "isp1760-regs.h"
30 31
31static struct kmem_cache *qtd_cachep; 32static struct kmem_cache *qtd_cachep;
32static struct kmem_cache *qh_cachep; 33static struct kmem_cache *qh_cachep;
33static struct kmem_cache *urb_listitem_cachep; 34static struct kmem_cache *urb_listitem_cachep;
34 35
35enum queue_head_types {
36 QH_CONTROL,
37 QH_BULK,
38 QH_INTERRUPT,
39 QH_END
40};
41
42struct isp1760_hcd {
43 struct usb_hcd *hcd;
44
45 u32 hcs_params;
46 spinlock_t lock;
47 struct isp1760_slotinfo atl_slots[32];
48 int atl_done_map;
49 struct isp1760_slotinfo int_slots[32];
50 int int_done_map;
51 struct isp1760_memory_chunk memory_pool[BLOCKS];
52 struct list_head qh_list[QH_END];
53
54 /* periodic schedule support */
55#define DEFAULT_I_TDPS 1024
56 unsigned periodic_size;
57 unsigned i_thresh;
58 unsigned long reset_done;
59 unsigned long next_statechange;
60 unsigned int devflags;
61
62 struct gpio_desc *rst_gpio;
63};
64
65typedef void (packet_enqueue)(struct usb_hcd *hcd, struct isp1760_qh *qh, 36typedef void (packet_enqueue)(struct usb_hcd *hcd, struct isp1760_qh *qh,
66 struct isp1760_qtd *qtd); 37 struct isp1760_qtd *qtd);
67 38
@@ -70,32 +41,79 @@ static inline struct isp1760_hcd *hcd_to_priv(struct usb_hcd *hcd)
70 return *(struct isp1760_hcd **)hcd->hcd_priv; 41 return *(struct isp1760_hcd **)hcd->hcd_priv;
71} 42}
72 43
73/* Section 2.2 Host Controller Capability Registers */ 44/* urb state*/
74#define HC_LENGTH(p) (((p)>>00)&0x00ff) /* bits 7:0 */ 45#define DELETE_URB (0x0008)
75#define HC_VERSION(p) (((p)>>16)&0xffff) /* bits 31:16 */ 46#define NO_TRANSFER_ACTIVE (0xffffffff)
76#define HCS_INDICATOR(p) ((p)&(1 << 16)) /* true: has port indicators */ 47
77#define HCS_PPC(p) ((p)&(1 << 4)) /* true: port power control */ 48/* Philips Proprietary Transfer Descriptor (PTD) */
78#define HCS_N_PORTS(p) (((p)>>0)&0xf) /* bits 3:0, ports on HC */ 49typedef __u32 __bitwise __dw;
79#define HCC_ISOC_CACHE(p) ((p)&(1 << 7)) /* true: can cache isoc frame */ 50struct ptd {
80#define HCC_ISOC_THRES(p) (((p)>>4)&0x7) /* bits 6:4, uframes cached */ 51 __dw dw0;
81 52 __dw dw1;
82/* Section 2.3 Host Controller Operational Registers */ 53 __dw dw2;
83#define CMD_LRESET (1<<7) /* partial reset (no ports, etc) */ 54 __dw dw3;
84#define CMD_RESET (1<<1) /* reset HC not bus */ 55 __dw dw4;
85#define CMD_RUN (1<<0) /* start/stop HC */ 56 __dw dw5;
86#define STS_PCD (1<<2) /* port change detect */ 57 __dw dw6;
87#define FLAG_CF (1<<0) /* true: we'll support "high speed" */ 58 __dw dw7;
88 59};
89#define PORT_OWNER (1<<13) /* true: companion hc owns this port */ 60#define PTD_OFFSET 0x0400
90#define PORT_POWER (1<<12) /* true: has power (see PPC) */ 61#define ISO_PTD_OFFSET 0x0400
91#define PORT_USB11(x) (((x) & (3 << 10)) == (1 << 10)) /* USB 1.1 device */ 62#define INT_PTD_OFFSET 0x0800
92#define PORT_RESET (1<<8) /* reset port */ 63#define ATL_PTD_OFFSET 0x0c00
93#define PORT_SUSPEND (1<<7) /* suspend port */ 64#define PAYLOAD_OFFSET 0x1000
94#define PORT_RESUME (1<<6) /* resume it */ 65
95#define PORT_PE (1<<2) /* port enable */ 66
96#define PORT_CSC (1<<1) /* connect status change */ 67/* ATL */
97#define PORT_CONNECT (1<<0) /* device connected */ 68/* DW0 */
98#define PORT_RWC_BITS (PORT_CSC) 69#define DW0_VALID_BIT 1
70#define FROM_DW0_VALID(x) ((x) & 0x01)
71#define TO_DW0_LENGTH(x) (((u32) x) << 3)
72#define TO_DW0_MAXPACKET(x) (((u32) x) << 18)
73#define TO_DW0_MULTI(x) (((u32) x) << 29)
74#define TO_DW0_ENDPOINT(x) (((u32) x) << 31)
75/* DW1 */
76#define TO_DW1_DEVICE_ADDR(x) (((u32) x) << 3)
77#define TO_DW1_PID_TOKEN(x) (((u32) x) << 10)
78#define DW1_TRANS_BULK ((u32) 2 << 12)
79#define DW1_TRANS_INT ((u32) 3 << 12)
80#define DW1_TRANS_SPLIT ((u32) 1 << 14)
81#define DW1_SE_USB_LOSPEED ((u32) 2 << 16)
82#define TO_DW1_PORT_NUM(x) (((u32) x) << 18)
83#define TO_DW1_HUB_NUM(x) (((u32) x) << 25)
84/* DW2 */
85#define TO_DW2_DATA_START_ADDR(x) (((u32) x) << 8)
86#define TO_DW2_RL(x) ((x) << 25)
87#define FROM_DW2_RL(x) (((x) >> 25) & 0xf)
88/* DW3 */
89#define FROM_DW3_NRBYTESTRANSFERRED(x) ((x) & 0x7fff)
90#define FROM_DW3_SCS_NRBYTESTRANSFERRED(x) ((x) & 0x07ff)
91#define TO_DW3_NAKCOUNT(x) ((x) << 19)
92#define FROM_DW3_NAKCOUNT(x) (((x) >> 19) & 0xf)
93#define TO_DW3_CERR(x) ((x) << 23)
94#define FROM_DW3_CERR(x) (((x) >> 23) & 0x3)
95#define TO_DW3_DATA_TOGGLE(x) ((x) << 25)
96#define FROM_DW3_DATA_TOGGLE(x) (((x) >> 25) & 0x1)
97#define TO_DW3_PING(x) ((x) << 26)
98#define FROM_DW3_PING(x) (((x) >> 26) & 0x1)
99#define DW3_ERROR_BIT (1 << 28)
100#define DW3_BABBLE_BIT (1 << 29)
101#define DW3_HALT_BIT (1 << 30)
102#define DW3_ACTIVE_BIT (1 << 31)
103#define FROM_DW3_ACTIVE(x) (((x) >> 31) & 0x01)
104
105#define INT_UNDERRUN (1 << 2)
106#define INT_BABBLE (1 << 1)
107#define INT_EXACT (1 << 0)
108
109#define SETUP_PID (2)
110#define IN_PID (1)
111#define OUT_PID (0)
112
113/* Errata 1 */
114#define RL_COUNTER (0)
115#define NAK_COUNTER (0)
116#define ERR_COUNTER (2)
99 117
100struct isp1760_qtd { 118struct isp1760_qtd {
101 u8 packet_type; 119 u8 packet_type;
diff --git a/drivers/usb/host/isp1760-hcd.h b/drivers/usb/host/isp1760-hcd.h
index 3056bcd8a393..44486c86f5f7 100644
--- a/drivers/usb/host/isp1760-hcd.h
+++ b/drivers/usb/host/isp1760-hcd.h
@@ -1,114 +1,31 @@
1#ifndef _ISP1760_HCD_H_ 1#ifndef _ISP1760_HCD_H_
2#define _ISP1760_HCD_H_ 2#define _ISP1760_HCD_H_
3 3
4/* exports for if */ 4#include <linux/spinlock.h>
5int isp1760_register(struct resource *mem, int irq, unsigned long irqflags,
6 struct device *dev, unsigned int devflags);
7void isp1760_unregister(struct device *dev);
8 5
9int isp1760_init_kmem_once(void); 6struct gpio_desc;
10void isp1760_deinit_kmem_cache(void); 7struct isp1760_qh;
8struct isp1760_qtd;
9struct resource;
10struct usb_hcd;
11 11
12/* EHCI capability registers */ 12/*
13#define HC_CAPLENGTH 0x00 13 * 60kb divided in:
14#define HC_HCSPARAMS 0x04 14 * - 32 blocks @ 256 bytes
15#define HC_HCCPARAMS 0x08 15 * - 20 blocks @ 1024 bytes
16 16 * - 4 blocks @ 8192 bytes
17/* EHCI operational registers */ 17 */
18#define HC_USBCMD 0x20
19#define HC_USBSTS 0x24
20#define HC_FRINDEX 0x2c
21#define HC_CONFIGFLAG 0x60
22#define HC_PORTSC1 0x64
23#define HC_ISO_PTD_DONEMAP_REG 0x130
24#define HC_ISO_PTD_SKIPMAP_REG 0x134
25#define HC_ISO_PTD_LASTPTD_REG 0x138
26#define HC_INT_PTD_DONEMAP_REG 0x140
27#define HC_INT_PTD_SKIPMAP_REG 0x144
28#define HC_INT_PTD_LASTPTD_REG 0x148
29#define HC_ATL_PTD_DONEMAP_REG 0x150
30#define HC_ATL_PTD_SKIPMAP_REG 0x154
31#define HC_ATL_PTD_LASTPTD_REG 0x158
32
33/* Configuration Register */
34#define HC_HW_MODE_CTRL 0x300
35#define ALL_ATX_RESET (1 << 31)
36#define HW_ANA_DIGI_OC (1 << 15)
37#define HW_DATA_BUS_32BIT (1 << 8)
38#define HW_DACK_POL_HIGH (1 << 6)
39#define HW_DREQ_POL_HIGH (1 << 5)
40#define HW_INTR_HIGH_ACT (1 << 2)
41#define HW_INTR_EDGE_TRIG (1 << 1)
42#define HW_GLOBAL_INTR_EN (1 << 0)
43
44#define HC_CHIP_ID_REG 0x304
45#define HC_SCRATCH_REG 0x308
46
47#define HC_RESET_REG 0x30c
48#define SW_RESET_RESET_HC (1 << 1)
49#define SW_RESET_RESET_ALL (1 << 0)
50
51#define HC_BUFFER_STATUS_REG 0x334
52#define ISO_BUF_FILL (1 << 2)
53#define INT_BUF_FILL (1 << 1)
54#define ATL_BUF_FILL (1 << 0)
55
56#define HC_MEMORY_REG 0x33c
57#define ISP_BANK(x) ((x) << 16)
58
59#define HC_PORT1_CTRL 0x374
60#define PORT1_POWER (3 << 3)
61#define PORT1_INIT1 (1 << 7)
62#define PORT1_INIT2 (1 << 23)
63#define HW_OTG_CTRL_SET 0x374
64#define HW_OTG_CTRL_CLR 0x376
65
66/* Interrupt Register */
67#define HC_INTERRUPT_REG 0x310
68
69#define HC_INTERRUPT_ENABLE 0x314
70#define HC_ISO_INT (1 << 9)
71#define HC_ATL_INT (1 << 8)
72#define HC_INTL_INT (1 << 7)
73#define HC_EOT_INT (1 << 3)
74#define HC_SOT_INT (1 << 1)
75#define INTERRUPT_ENABLE_MASK (HC_INTL_INT | HC_ATL_INT)
76
77#define HC_ISO_IRQ_MASK_OR_REG 0x318
78#define HC_INT_IRQ_MASK_OR_REG 0x31C
79#define HC_ATL_IRQ_MASK_OR_REG 0x320
80#define HC_ISO_IRQ_MASK_AND_REG 0x324
81#define HC_INT_IRQ_MASK_AND_REG 0x328
82#define HC_ATL_IRQ_MASK_AND_REG 0x32C
83
84/* urb state*/
85#define DELETE_URB (0x0008)
86#define NO_TRANSFER_ACTIVE (0xffffffff)
87
88/* Philips Proprietary Transfer Descriptor (PTD) */
89typedef __u32 __bitwise __dw;
90struct ptd {
91 __dw dw0;
92 __dw dw1;
93 __dw dw2;
94 __dw dw3;
95 __dw dw4;
96 __dw dw5;
97 __dw dw6;
98 __dw dw7;
99};
100#define PTD_OFFSET 0x0400
101#define ISO_PTD_OFFSET 0x0400
102#define INT_PTD_OFFSET 0x0800
103#define ATL_PTD_OFFSET 0x0c00
104#define PAYLOAD_OFFSET 0x1000
105 18
106struct isp1760_slotinfo { 19#define BLOCK_1_NUM 32
107 struct isp1760_qh *qh; 20#define BLOCK_2_NUM 20
108 struct isp1760_qtd *qtd; 21#define BLOCK_3_NUM 4
109 unsigned long timestamp;
110};
111 22
23#define BLOCK_1_SIZE 256
24#define BLOCK_2_SIZE 1024
25#define BLOCK_3_SIZE 8192
26#define BLOCKS (BLOCK_1_NUM + BLOCK_2_NUM + BLOCK_3_NUM)
27#define MAX_PAYLOAD_SIZE BLOCK_3_SIZE
28#define PAYLOAD_AREA_SIZE 0xf000
112 29
113/* 30/*
114 * Device flags that can vary from board to board. All of these 31 * Device flags that can vary from board to board. All of these
@@ -124,6 +41,12 @@ struct isp1760_slotinfo {
124#define ISP1760_FLAG_INTR_POL_HIGH 0x00000080 /* Interrupt polarity active high */ 41#define ISP1760_FLAG_INTR_POL_HIGH 0x00000080 /* Interrupt polarity active high */
125#define ISP1760_FLAG_INTR_EDGE_TRIG 0x00000100 /* Interrupt edge triggered */ 42#define ISP1760_FLAG_INTR_EDGE_TRIG 0x00000100 /* Interrupt edge triggered */
126 43
44struct isp1760_slotinfo {
45 struct isp1760_qh *qh;
46 struct isp1760_qtd *qtd;
47 unsigned long timestamp;
48};
49
127/* chip memory management */ 50/* chip memory management */
128struct isp1760_memory_chunk { 51struct isp1760_memory_chunk {
129 unsigned int start; 52 unsigned int start;
@@ -131,73 +54,42 @@ struct isp1760_memory_chunk {
131 unsigned int free; 54 unsigned int free;
132}; 55};
133 56
134/* 57enum isp1760_queue_head_types {
135 * 60kb divided in: 58 QH_CONTROL,
136 * - 32 blocks @ 256 bytes 59 QH_BULK,
137 * - 20 blocks @ 1024 bytes 60 QH_INTERRUPT,
138 * - 4 blocks @ 8192 bytes 61 QH_END
139 */ 62};
140 63
141#define BLOCK_1_NUM 32 64struct isp1760_hcd {
142#define BLOCK_2_NUM 20 65 struct usb_hcd *hcd;
143#define BLOCK_3_NUM 4 66
67 u32 hcs_params;
68 spinlock_t lock;
69 struct isp1760_slotinfo atl_slots[32];
70 int atl_done_map;
71 struct isp1760_slotinfo int_slots[32];
72 int int_done_map;
73 struct isp1760_memory_chunk memory_pool[BLOCKS];
74 struct list_head qh_list[QH_END];
75
76 /* periodic schedule support */
77#define DEFAULT_I_TDPS 1024
78 unsigned periodic_size;
79 unsigned i_thresh;
80 unsigned long reset_done;
81 unsigned long next_statechange;
82 unsigned int devflags;
83
84 struct gpio_desc *rst_gpio;
85};
144 86
145#define BLOCK_1_SIZE 256 87/* exports for if */
146#define BLOCK_2_SIZE 1024 88int isp1760_register(struct resource *mem, int irq, unsigned long irqflags,
147#define BLOCK_3_SIZE 8192 89 struct device *dev, unsigned int devflags);
148#define BLOCKS (BLOCK_1_NUM + BLOCK_2_NUM + BLOCK_3_NUM) 90void isp1760_unregister(struct device *dev);
149#define MAX_PAYLOAD_SIZE BLOCK_3_SIZE
150#define PAYLOAD_AREA_SIZE 0xf000
151 91
152/* ATL */ 92int isp1760_init_kmem_once(void);
153/* DW0 */ 93void isp1760_deinit_kmem_cache(void);
154#define DW0_VALID_BIT 1
155#define FROM_DW0_VALID(x) ((x) & 0x01)
156#define TO_DW0_LENGTH(x) (((u32) x) << 3)
157#define TO_DW0_MAXPACKET(x) (((u32) x) << 18)
158#define TO_DW0_MULTI(x) (((u32) x) << 29)
159#define TO_DW0_ENDPOINT(x) (((u32) x) << 31)
160/* DW1 */
161#define TO_DW1_DEVICE_ADDR(x) (((u32) x) << 3)
162#define TO_DW1_PID_TOKEN(x) (((u32) x) << 10)
163#define DW1_TRANS_BULK ((u32) 2 << 12)
164#define DW1_TRANS_INT ((u32) 3 << 12)
165#define DW1_TRANS_SPLIT ((u32) 1 << 14)
166#define DW1_SE_USB_LOSPEED ((u32) 2 << 16)
167#define TO_DW1_PORT_NUM(x) (((u32) x) << 18)
168#define TO_DW1_HUB_NUM(x) (((u32) x) << 25)
169/* DW2 */
170#define TO_DW2_DATA_START_ADDR(x) (((u32) x) << 8)
171#define TO_DW2_RL(x) ((x) << 25)
172#define FROM_DW2_RL(x) (((x) >> 25) & 0xf)
173/* DW3 */
174#define FROM_DW3_NRBYTESTRANSFERRED(x) ((x) & 0x7fff)
175#define FROM_DW3_SCS_NRBYTESTRANSFERRED(x) ((x) & 0x07ff)
176#define TO_DW3_NAKCOUNT(x) ((x) << 19)
177#define FROM_DW3_NAKCOUNT(x) (((x) >> 19) & 0xf)
178#define TO_DW3_CERR(x) ((x) << 23)
179#define FROM_DW3_CERR(x) (((x) >> 23) & 0x3)
180#define TO_DW3_DATA_TOGGLE(x) ((x) << 25)
181#define FROM_DW3_DATA_TOGGLE(x) (((x) >> 25) & 0x1)
182#define TO_DW3_PING(x) ((x) << 26)
183#define FROM_DW3_PING(x) (((x) >> 26) & 0x1)
184#define DW3_ERROR_BIT (1 << 28)
185#define DW3_BABBLE_BIT (1 << 29)
186#define DW3_HALT_BIT (1 << 30)
187#define DW3_ACTIVE_BIT (1 << 31)
188#define FROM_DW3_ACTIVE(x) (((x) >> 31) & 0x01)
189
190#define INT_UNDERRUN (1 << 2)
191#define INT_BABBLE (1 << 1)
192#define INT_EXACT (1 << 0)
193
194#define SETUP_PID (2)
195#define IN_PID (1)
196#define OUT_PID (0)
197
198/* Errata 1 */
199#define RL_COUNTER (0)
200#define NAK_COUNTER (0)
201#define ERR_COUNTER (2)
202 94
203#endif /* _ISP1760_HCD_H_ */ 95#endif /* _ISP1760_HCD_H_ */
diff --git a/drivers/usb/host/isp1760-if.c b/drivers/usb/host/isp1760-if.c
index 7c03320f7831..b1591c6cf54a 100644
--- a/drivers/usb/host/isp1760-if.c
+++ b/drivers/usb/host/isp1760-if.c
@@ -19,6 +19,7 @@
19#include <linux/usb/hcd.h> 19#include <linux/usb/hcd.h>
20 20
21#include "isp1760-hcd.h" 21#include "isp1760-hcd.h"
22#include "isp1760-regs.h"
22 23
23#ifdef CONFIG_PCI 24#ifdef CONFIG_PCI
24#include <linux/pci.h> 25#include <linux/pci.h>
diff --git a/drivers/usb/host/isp1760-regs.h b/drivers/usb/host/isp1760-regs.h
new file mode 100644
index 000000000000..c2a39009d11f
--- /dev/null
+++ b/drivers/usb/host/isp1760-regs.h
@@ -0,0 +1,120 @@
1/*
2 * Driver for the NXP ISP1760 chip
3 *
4 * Copyright 2014 Laurent Pinchart
5 * Copyright 2007 Sebastian Siewior
6 *
7 * Contacts:
8 * Sebastian Siewior <bigeasy@linutronix.de>
9 * Laurent Pinchart <laurent.pinchart@ideasonboard.com>
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * version 2 as published by the Free Software Foundation.
14 */
15
16#ifndef _ISP1760_REGS_H_
17#define _ISP1760_REGS_H_
18
19/* EHCI capability registers */
20#define HC_CAPLENGTH 0x000
21#define HC_LENGTH(p) (((p) >> 00) & 0x00ff) /* bits 7:0 */
22#define HC_VERSION(p) (((p) >> 16) & 0xffff) /* bits 31:16 */
23
24#define HC_HCSPARAMS 0x004
25#define HCS_INDICATOR(p) ((p) & (1 << 16)) /* true: has port indicators */
26#define HCS_PPC(p) ((p) & (1 << 4)) /* true: port power control */
27#define HCS_N_PORTS(p) (((p) >> 0) & 0xf) /* bits 3:0, ports on HC */
28
29#define HC_HCCPARAMS 0x008
30#define HCC_ISOC_CACHE(p) ((p) & (1 << 7)) /* true: can cache isoc frame */
31#define HCC_ISOC_THRES(p) (((p) >> 4) & 0x7) /* bits 6:4, uframes cached */
32
33/* EHCI operational registers */
34#define HC_USBCMD 0x020
35#define CMD_LRESET (1 << 7) /* partial reset (no ports, etc) */
36#define CMD_RESET (1 << 1) /* reset HC not bus */
37#define CMD_RUN (1 << 0) /* start/stop HC */
38
39#define HC_USBSTS 0x024
40#define STS_PCD (1 << 2) /* port change detect */
41
42#define HC_FRINDEX 0x02c
43
44#define HC_CONFIGFLAG 0x060
45#define FLAG_CF (1 << 0) /* true: we'll support "high speed" */
46
47#define HC_PORTSC1 0x064
48#define PORT_OWNER (1 << 13) /* true: companion hc owns this port */
49#define PORT_POWER (1 << 12) /* true: has power (see PPC) */
50#define PORT_USB11(x) (((x) & (3 << 10)) == (1 << 10)) /* USB 1.1 device */
51#define PORT_RESET (1 << 8) /* reset port */
52#define PORT_SUSPEND (1 << 7) /* suspend port */
53#define PORT_RESUME (1 << 6) /* resume it */
54#define PORT_PE (1 << 2) /* port enable */
55#define PORT_CSC (1 << 1) /* connect status change */
56#define PORT_CONNECT (1 << 0) /* device connected */
57#define PORT_RWC_BITS (PORT_CSC)
58
59#define HC_ISO_PTD_DONEMAP_REG 0x130
60#define HC_ISO_PTD_SKIPMAP_REG 0x134
61#define HC_ISO_PTD_LASTPTD_REG 0x138
62#define HC_INT_PTD_DONEMAP_REG 0x140
63#define HC_INT_PTD_SKIPMAP_REG 0x144
64#define HC_INT_PTD_LASTPTD_REG 0x148
65#define HC_ATL_PTD_DONEMAP_REG 0x150
66#define HC_ATL_PTD_SKIPMAP_REG 0x154
67#define HC_ATL_PTD_LASTPTD_REG 0x158
68
69/* Configuration Register */
70#define HC_HW_MODE_CTRL 0x300
71#define ALL_ATX_RESET (1 << 31)
72#define HW_ANA_DIGI_OC (1 << 15)
73#define HW_DATA_BUS_32BIT (1 << 8)
74#define HW_DACK_POL_HIGH (1 << 6)
75#define HW_DREQ_POL_HIGH (1 << 5)
76#define HW_INTR_HIGH_ACT (1 << 2)
77#define HW_INTR_EDGE_TRIG (1 << 1)
78#define HW_GLOBAL_INTR_EN (1 << 0)
79
80#define HC_CHIP_ID_REG 0x304
81#define HC_SCRATCH_REG 0x308
82
83#define HC_RESET_REG 0x30c
84#define SW_RESET_RESET_HC (1 << 1)
85#define SW_RESET_RESET_ALL (1 << 0)
86
87#define HC_BUFFER_STATUS_REG 0x334
88#define ISO_BUF_FILL (1 << 2)
89#define INT_BUF_FILL (1 << 1)
90#define ATL_BUF_FILL (1 << 0)
91
92#define HC_MEMORY_REG 0x33c
93#define ISP_BANK(x) ((x) << 16)
94
95#define HC_PORT1_CTRL 0x374
96#define PORT1_POWER (3 << 3)
97#define PORT1_INIT1 (1 << 7)
98#define PORT1_INIT2 (1 << 23)
99#define HW_OTG_CTRL_SET 0x374
100#define HW_OTG_CTRL_CLR 0x376
101
102/* Interrupt Register */
103#define HC_INTERRUPT_REG 0x310
104
105#define HC_INTERRUPT_ENABLE 0x314
106#define HC_ISO_INT (1 << 9)
107#define HC_ATL_INT (1 << 8)
108#define HC_INTL_INT (1 << 7)
109#define HC_EOT_INT (1 << 3)
110#define HC_SOT_INT (1 << 1)
111#define INTERRUPT_ENABLE_MASK (HC_INTL_INT | HC_ATL_INT)
112
113#define HC_ISO_IRQ_MASK_OR_REG 0x318
114#define HC_INT_IRQ_MASK_OR_REG 0x31c
115#define HC_ATL_IRQ_MASK_OR_REG 0x320
116#define HC_ISO_IRQ_MASK_AND_REG 0x324
117#define HC_INT_IRQ_MASK_AND_REG 0x328
118#define HC_ATL_IRQ_MASK_AND_REG 0x32c
119
120#endif
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