diff options
author | Alan Stern <stern@rowland.harvard.edu> | 2010-06-25 14:02:49 -0400 |
---|---|---|
committer | Greg Kroah-Hartman <gregkh@suse.de> | 2010-08-10 17:35:38 -0400 |
commit | 0d436b425e07f9e4b0fe571cec061f5d136f1d8b (patch) | |
tree | f1ebf7929aaf1b4b5e96e1182085e8924e2d0d50 /drivers/usb/host/uhci-hcd.h | |
parent | ff2f07874362d34684296f2bd5547a099f33c6d4 (diff) |
USB: UHCI: add support for Intel's wakeup flags
This patch (as1396) adds code to uhci-hcd to support the
vendor-specific wakeup settings found in Intel's ICHx hardware. A
couple of unnecessary memory barriers are removed. And the root hub
isn't put back into the "suspended" state if power was lost during a
system sleep -- there's not much point in doing so because the root hub
will be resumed shortly.
Signed-off-by: Alan Stern <stern@rowland.harvard.edu>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'drivers/usb/host/uhci-hcd.h')
-rw-r--r-- | drivers/usb/host/uhci-hcd.h | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/drivers/usb/host/uhci-hcd.h b/drivers/usb/host/uhci-hcd.h index 26bd1b2bcbfc..49bf2790f9c2 100644 --- a/drivers/usb/host/uhci-hcd.h +++ b/drivers/usb/host/uhci-hcd.h | |||
@@ -67,12 +67,17 @@ | |||
67 | #define USBPORTSC_RES3 0x4000 /* reserved, write zeroes */ | 67 | #define USBPORTSC_RES3 0x4000 /* reserved, write zeroes */ |
68 | #define USBPORTSC_RES4 0x8000 /* reserved, write zeroes */ | 68 | #define USBPORTSC_RES4 0x8000 /* reserved, write zeroes */ |
69 | 69 | ||
70 | /* Legacy support register */ | 70 | /* PCI legacy support register */ |
71 | #define USBLEGSUP 0xc0 | 71 | #define USBLEGSUP 0xc0 |
72 | #define USBLEGSUP_DEFAULT 0x2000 /* only PIRQ enable set */ | 72 | #define USBLEGSUP_DEFAULT 0x2000 /* only PIRQ enable set */ |
73 | #define USBLEGSUP_RWC 0x8f00 /* the R/WC bits */ | 73 | #define USBLEGSUP_RWC 0x8f00 /* the R/WC bits */ |
74 | #define USBLEGSUP_RO 0x5040 /* R/O and reserved bits */ | 74 | #define USBLEGSUP_RO 0x5040 /* R/O and reserved bits */ |
75 | 75 | ||
76 | /* PCI Intel-specific resume-enable register */ | ||
77 | #define USBRES_INTEL 0xc4 | ||
78 | #define USBPORT1EN 0x01 | ||
79 | #define USBPORT2EN 0x02 | ||
80 | |||
76 | #define UHCI_PTR_BITS cpu_to_le32(0x000F) | 81 | #define UHCI_PTR_BITS cpu_to_le32(0x000F) |
77 | #define UHCI_PTR_TERM cpu_to_le32(0x0001) | 82 | #define UHCI_PTR_TERM cpu_to_le32(0x0001) |
78 | #define UHCI_PTR_QH cpu_to_le32(0x0002) | 83 | #define UHCI_PTR_QH cpu_to_le32(0x0002) |