diff options
author | Jan Andersson <jan@gaisler.com> | 2011-05-06 06:00:16 -0400 |
---|---|---|
committer | Greg Kroah-Hartman <gregkh@suse.de> | 2011-05-06 21:24:01 -0400 |
commit | 9faa091a409851ac6b3812164d53644074bc89b1 (patch) | |
tree | c7d95c20e9b476261a1ccd7a5f02286be5b7502d /drivers/usb/host/uhci-hcd.c | |
parent | c31a65f869f7b8a7039007411c76d7b6f9a63323 (diff) |
USB: UHCI: Wrap I/O register accesses
This patch is part of a series that extend the UHCI HCD to support
non-PCI controllers.
This patch replaces in{b,w,l} and out{b,wl} with calls to local inline
functions. This is done so that the register access functions can be
extended to support register areas not mapped in PCI I/O space.
Signed-off-by: Jan Andersson <jan@gaisler.com>
Acked-by: Alan Stern <stern@rowland.harvard.edu>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'drivers/usb/host/uhci-hcd.c')
-rw-r--r-- | drivers/usb/host/uhci-hcd.c | 42 |
1 files changed, 21 insertions, 21 deletions
diff --git a/drivers/usb/host/uhci-hcd.c b/drivers/usb/host/uhci-hcd.c index 3d2a10563be8..5176c537b95a 100644 --- a/drivers/usb/host/uhci-hcd.c +++ b/drivers/usb/host/uhci-hcd.c | |||
@@ -133,7 +133,7 @@ static void finish_reset(struct uhci_hcd *uhci) | |||
133 | * We have to clear them by hand. | 133 | * We have to clear them by hand. |
134 | */ | 134 | */ |
135 | for (port = 0; port < uhci->rh_numports; ++port) | 135 | for (port = 0; port < uhci->rh_numports; ++port) |
136 | outw(0, uhci->io_addr + USBPORTSC1 + (port * 2)); | 136 | uhci_writew(uhci, 0, USBPORTSC1 + (port * 2)); |
137 | 137 | ||
138 | uhci->port_c_suspend = uhci->resuming_ports = 0; | 138 | uhci->port_c_suspend = uhci->resuming_ports = 0; |
139 | uhci->rh_state = UHCI_RH_RESET; | 139 | uhci->rh_state = UHCI_RH_RESET; |
@@ -173,14 +173,14 @@ static void check_and_reset_hc(struct uhci_hcd *uhci) | |||
173 | static void configure_hc(struct uhci_hcd *uhci) | 173 | static void configure_hc(struct uhci_hcd *uhci) |
174 | { | 174 | { |
175 | /* Set the frame length to the default: 1 ms exactly */ | 175 | /* Set the frame length to the default: 1 ms exactly */ |
176 | outb(USBSOF_DEFAULT, uhci->io_addr + USBSOF); | 176 | uhci_writeb(uhci, USBSOF_DEFAULT, USBSOF); |
177 | 177 | ||
178 | /* Store the frame list base address */ | 178 | /* Store the frame list base address */ |
179 | outl(uhci->frame_dma_handle, uhci->io_addr + USBFLBASEADD); | 179 | uhci_writel(uhci, uhci->frame_dma_handle, USBFLBASEADD); |
180 | 180 | ||
181 | /* Set the current frame number */ | 181 | /* Set the current frame number */ |
182 | outw(uhci->frame_number & UHCI_MAX_SOF_NUMBER, | 182 | uhci_writew(uhci, uhci->frame_number & UHCI_MAX_SOF_NUMBER, |
183 | uhci->io_addr + USBFRNUM); | 183 | USBFRNUM); |
184 | 184 | ||
185 | /* perform any arch/bus specific configuration */ | 185 | /* perform any arch/bus specific configuration */ |
186 | if (uhci->configure_hc) | 186 | if (uhci->configure_hc) |
@@ -264,8 +264,8 @@ __acquires(uhci->lock) | |||
264 | !int_enable) | 264 | !int_enable) |
265 | uhci->RD_enable = int_enable = 0; | 265 | uhci->RD_enable = int_enable = 0; |
266 | 266 | ||
267 | outw(int_enable, uhci->io_addr + USBINTR); | 267 | uhci_writew(uhci, int_enable, USBINTR); |
268 | outw(egsm_enable | USBCMD_CF, uhci->io_addr + USBCMD); | 268 | uhci_writew(uhci, egsm_enable | USBCMD_CF, USBCMD); |
269 | mb(); | 269 | mb(); |
270 | udelay(5); | 270 | udelay(5); |
271 | 271 | ||
@@ -274,7 +274,7 @@ __acquires(uhci->lock) | |||
274 | * controller should stop after a few microseconds. Otherwise | 274 | * controller should stop after a few microseconds. Otherwise |
275 | * we will give the controller one frame to stop. | 275 | * we will give the controller one frame to stop. |
276 | */ | 276 | */ |
277 | if (!auto_stop && !(inw(uhci->io_addr + USBSTS) & USBSTS_HCH)) { | 277 | if (!auto_stop && !(uhci_readw(uhci, USBSTS) & USBSTS_HCH)) { |
278 | uhci->rh_state = UHCI_RH_SUSPENDING; | 278 | uhci->rh_state = UHCI_RH_SUSPENDING; |
279 | spin_unlock_irq(&uhci->lock); | 279 | spin_unlock_irq(&uhci->lock); |
280 | msleep(1); | 280 | msleep(1); |
@@ -282,7 +282,7 @@ __acquires(uhci->lock) | |||
282 | if (uhci->dead) | 282 | if (uhci->dead) |
283 | return; | 283 | return; |
284 | } | 284 | } |
285 | if (!(inw(uhci->io_addr + USBSTS) & USBSTS_HCH)) | 285 | if (!(uhci_readw(uhci, USBSTS) & USBSTS_HCH)) |
286 | dev_warn(uhci_dev(uhci), "Controller not stopped yet!\n"); | 286 | dev_warn(uhci_dev(uhci), "Controller not stopped yet!\n"); |
287 | 287 | ||
288 | uhci_get_current_frame_number(uhci); | 288 | uhci_get_current_frame_number(uhci); |
@@ -309,9 +309,9 @@ static void start_rh(struct uhci_hcd *uhci) | |||
309 | /* Mark it configured and running with a 64-byte max packet. | 309 | /* Mark it configured and running with a 64-byte max packet. |
310 | * All interrupts are enabled, even though RESUME won't do anything. | 310 | * All interrupts are enabled, even though RESUME won't do anything. |
311 | */ | 311 | */ |
312 | outw(USBCMD_RS | USBCMD_CF | USBCMD_MAXP, uhci->io_addr + USBCMD); | 312 | uhci_writew(uhci, USBCMD_RS | USBCMD_CF | USBCMD_MAXP, USBCMD); |
313 | outw(USBINTR_TIMEOUT | USBINTR_RESUME | USBINTR_IOC | USBINTR_SP, | 313 | uhci_writew(uhci, USBINTR_TIMEOUT | USBINTR_RESUME | |
314 | uhci->io_addr + USBINTR); | 314 | USBINTR_IOC | USBINTR_SP, USBINTR); |
315 | mb(); | 315 | mb(); |
316 | uhci->rh_state = UHCI_RH_RUNNING; | 316 | uhci->rh_state = UHCI_RH_RUNNING; |
317 | set_bit(HCD_FLAG_POLL_RH, &uhci_to_hcd(uhci)->flags); | 317 | set_bit(HCD_FLAG_POLL_RH, &uhci_to_hcd(uhci)->flags); |
@@ -334,9 +334,9 @@ __acquires(uhci->lock) | |||
334 | unsigned egsm; | 334 | unsigned egsm; |
335 | 335 | ||
336 | /* Keep EGSM on if it was set before */ | 336 | /* Keep EGSM on if it was set before */ |
337 | egsm = inw(uhci->io_addr + USBCMD) & USBCMD_EGSM; | 337 | egsm = uhci_readw(uhci, USBCMD) & USBCMD_EGSM; |
338 | uhci->rh_state = UHCI_RH_RESUMING; | 338 | uhci->rh_state = UHCI_RH_RESUMING; |
339 | outw(USBCMD_FGR | USBCMD_CF | egsm, uhci->io_addr + USBCMD); | 339 | uhci_writew(uhci, USBCMD_FGR | USBCMD_CF | egsm, USBCMD); |
340 | spin_unlock_irq(&uhci->lock); | 340 | spin_unlock_irq(&uhci->lock); |
341 | msleep(20); | 341 | msleep(20); |
342 | spin_lock_irq(&uhci->lock); | 342 | spin_lock_irq(&uhci->lock); |
@@ -344,10 +344,10 @@ __acquires(uhci->lock) | |||
344 | return; | 344 | return; |
345 | 345 | ||
346 | /* End Global Resume and wait for EOP to be sent */ | 346 | /* End Global Resume and wait for EOP to be sent */ |
347 | outw(USBCMD_CF, uhci->io_addr + USBCMD); | 347 | uhci_writew(uhci, USBCMD_CF, USBCMD); |
348 | mb(); | 348 | mb(); |
349 | udelay(4); | 349 | udelay(4); |
350 | if (inw(uhci->io_addr + USBCMD) & USBCMD_FGR) | 350 | if (uhci_readw(uhci, USBCMD) & USBCMD_FGR) |
351 | dev_warn(uhci_dev(uhci), "FGR not stopped yet!\n"); | 351 | dev_warn(uhci_dev(uhci), "FGR not stopped yet!\n"); |
352 | } | 352 | } |
353 | 353 | ||
@@ -367,10 +367,10 @@ static irqreturn_t uhci_irq(struct usb_hcd *hcd) | |||
367 | * interrupt cause. Contrary to the UHCI specification, the | 367 | * interrupt cause. Contrary to the UHCI specification, the |
368 | * "HC Halted" status bit is persistent: it is RO, not R/WC. | 368 | * "HC Halted" status bit is persistent: it is RO, not R/WC. |
369 | */ | 369 | */ |
370 | status = inw(uhci->io_addr + USBSTS); | 370 | status = uhci_readw(uhci, USBSTS); |
371 | if (!(status & ~USBSTS_HCH)) /* shared interrupt, not mine */ | 371 | if (!(status & ~USBSTS_HCH)) /* shared interrupt, not mine */ |
372 | return IRQ_NONE; | 372 | return IRQ_NONE; |
373 | outw(status, uhci->io_addr + USBSTS); /* Clear it */ | 373 | uhci_writew(uhci, status, USBSTS); /* Clear it */ |
374 | 374 | ||
375 | if (status & ~(USBSTS_USBINT | USBSTS_ERROR | USBSTS_RD)) { | 375 | if (status & ~(USBSTS_USBINT | USBSTS_ERROR | USBSTS_RD)) { |
376 | if (status & USBSTS_HSE) | 376 | if (status & USBSTS_HSE) |
@@ -426,7 +426,7 @@ static void uhci_get_current_frame_number(struct uhci_hcd *uhci) | |||
426 | if (!uhci->is_stopped) { | 426 | if (!uhci->is_stopped) { |
427 | unsigned delta; | 427 | unsigned delta; |
428 | 428 | ||
429 | delta = (inw(uhci->io_addr + USBFRNUM) - uhci->frame_number) & | 429 | delta = (uhci_readw(uhci, USBFRNUM) - uhci->frame_number) & |
430 | (UHCI_NUMFRAMES - 1); | 430 | (UHCI_NUMFRAMES - 1); |
431 | uhci->frame_number += delta; | 431 | uhci->frame_number += delta; |
432 | } | 432 | } |
@@ -716,7 +716,7 @@ static int uhci_hcd_get_frame_number(struct usb_hcd *hcd) | |||
716 | /* Minimize latency by avoiding the spinlock */ | 716 | /* Minimize latency by avoiding the spinlock */ |
717 | frame_number = uhci->frame_number; | 717 | frame_number = uhci->frame_number; |
718 | barrier(); | 718 | barrier(); |
719 | delta = (inw(uhci->io_addr + USBFRNUM) - frame_number) & | 719 | delta = (uhci_readw(uhci, USBFRNUM) - frame_number) & |
720 | (UHCI_NUMFRAMES - 1); | 720 | (UHCI_NUMFRAMES - 1); |
721 | return frame_number + delta; | 721 | return frame_number + delta; |
722 | } | 722 | } |
@@ -739,7 +739,7 @@ static int uhci_count_ports(struct usb_hcd *hcd) | |||
739 | for (port = 0; port < (io_size - USBPORTSC1) / 2; port++) { | 739 | for (port = 0; port < (io_size - USBPORTSC1) / 2; port++) { |
740 | unsigned int portstatus; | 740 | unsigned int portstatus; |
741 | 741 | ||
742 | portstatus = inw(uhci->io_addr + USBPORTSC1 + (port * 2)); | 742 | portstatus = uhci_readw(uhci, USBPORTSC1 + (port * 2)); |
743 | if (!(portstatus & 0x0080) || portstatus == 0xffff) | 743 | if (!(portstatus & 0x0080) || portstatus == 0xffff) |
744 | break; | 744 | break; |
745 | } | 745 | } |