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authorYoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>2011-07-06 20:57:10 -0400
committerGreg Kroah-Hartman <gregkh@suse.de>2011-07-08 17:57:11 -0400
commitf2e9039a43b01f01cab9dfaea2cad5f304fb3343 (patch)
tree44ddb1f51f05b3cd51a8e08eea08d0d8d7c7362e /drivers/usb/host/r8a66597-hcd.c
parent81463c1d707186adbbe534016cd1249edeab0dac (diff)
usb: r8a66597-hcd: add function for external controller
R8A66597 has the pin of WR0 and WR1. So, if one write-pin of CPU connects to the pins, we have to change the setting of FIFOSEL register in the controller. If we don't change the setting, the controller cannot send the data of odd length. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'drivers/usb/host/r8a66597-hcd.c')
-rw-r--r--drivers/usb/host/r8a66597-hcd.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/usb/host/r8a66597-hcd.c b/drivers/usb/host/r8a66597-hcd.c
index db6f8b9c19b6..cc8ba3c220b5 100644
--- a/drivers/usb/host/r8a66597-hcd.c
+++ b/drivers/usb/host/r8a66597-hcd.c
@@ -1438,7 +1438,7 @@ static void packet_write(struct r8a66597 *r8a66597, u16 pipenum)
1438 if (pipenum > 0) 1438 if (pipenum > 0)
1439 r8a66597_write(r8a66597, ~(1 << pipenum), BEMPSTS); 1439 r8a66597_write(r8a66597, ~(1 << pipenum), BEMPSTS);
1440 if (urb->transfer_buffer) { 1440 if (urb->transfer_buffer) {
1441 r8a66597_write_fifo(r8a66597, td->pipe->fifoaddr, buf, size); 1441 r8a66597_write_fifo(r8a66597, td->pipe, buf, size);
1442 if (!usb_pipebulk(urb->pipe) || td->maxpacket != size) 1442 if (!usb_pipebulk(urb->pipe) || td->maxpacket != size)
1443 r8a66597_write(r8a66597, BVAL, td->pipe->fifoctr); 1443 r8a66597_write(r8a66597, BVAL, td->pipe->fifoctr);
1444 } 1444 }