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authorLothar Wassmann <LW@KARO-electronics.de>2009-07-16 20:51:21 -0400
committerGreg Kroah-Hartman <gregkh@suse.de>2009-09-23 09:46:30 -0400
commita9d43091c5be1e7a60d5abe84be4f3050236b26a (patch)
tree0fa131f785350d0119777611aabda4aca0c7e060 /drivers/usb/host/isp1362.h
parente9238221d3fef990e2fd01702ebe5af90dda52a2 (diff)
USB: NXP ISP1362 USB host driver
Signed-off-by: Lothar Wassmann <LW@KARO-electronics.de> Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> Signed-off-by: Bryan Wu <cooloney@kernel.org> Signed-off-by: Mike Frysinger <vapier@gentoo.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'drivers/usb/host/isp1362.h')
-rw-r--r--drivers/usb/host/isp1362.h1079
1 files changed, 1079 insertions, 0 deletions
diff --git a/drivers/usb/host/isp1362.h b/drivers/usb/host/isp1362.h
new file mode 100644
index 000000000000..26e44fc8776f
--- /dev/null
+++ b/drivers/usb/host/isp1362.h
@@ -0,0 +1,1079 @@
1/*
2 * ISP1362 HCD (Host Controller Driver) for USB.
3 *
4 * COPYRIGHT (C) by L. Wassmann <LW@KARO-electronics.de>
5 */
6
7/* ------------------------------------------------------------------------- */
8/*
9 * Platform specific compile time options
10 */
11#if defined(CONFIG_ARCH_KARO)
12#include <asm/arch/hardware.h>
13#include <asm/arch/pxa-regs.h>
14#include <asm/arch/karo.h>
15
16#define USE_32BIT 1
17
18
19/* These options are mutually eclusive */
20#define USE_PLATFORM_DELAY 1
21#define USE_NDELAY 0
22/*
23 * MAX_ROOT_PORTS: Number of downstream ports
24 *
25 * The chip has two USB ports, one of which can be configured as
26 * an USB device port, so the value of this constant is implementation
27 * specific.
28 */
29#define MAX_ROOT_PORTS 2
30#define DUMMY_DELAY_ACCESS do {} while (0)
31
32/* insert platform specific definitions for other machines here */
33#elif defined(CONFIG_BLACKFIN)
34
35#include <linux/io.h>
36#define USE_32BIT 0
37#define MAX_ROOT_PORTS 2
38#define USE_PLATFORM_DELAY 0
39#define USE_NDELAY 1
40
41#define DUMMY_DELAY_ACCESS \
42 do { \
43 bfin_read16(ASYNC_BANK0_BASE); \
44 bfin_read16(ASYNC_BANK0_BASE); \
45 bfin_read16(ASYNC_BANK0_BASE); \
46 } while (0)
47
48#undef insw
49#undef outsw
50
51#define insw delayed_insw
52#define outsw delayed_outsw
53
54static inline void delayed_outsw(unsigned int addr, void *buf, int len)
55{
56 unsigned short *bp = (unsigned short *)buf;
57 while (len--) {
58 DUMMY_DELAY_ACCESS;
59 outw(*bp++, addr);
60 }
61}
62
63static inline void delayed_insw(unsigned int addr, void *buf, int len)
64{
65 unsigned short *bp = (unsigned short *)buf;
66 while (len--) {
67 DUMMY_DELAY_ACCESS;
68 *bp++ = inw((void *)addr);
69 }
70}
71
72#else
73
74#define MAX_ROOT_PORTS 2
75
76#define USE_32BIT 0
77
78/* These options are mutually eclusive */
79#define USE_PLATFORM_DELAY 0
80#define USE_NDELAY 0
81
82#define DUMMY_DELAY_ACCESS do {} while (0)
83
84#endif
85
86
87/* ------------------------------------------------------------------------- */
88
89#define USB_RESET_WIDTH 50
90#define MAX_XFER_SIZE 1023
91
92/* Buffer sizes */
93#define ISP1362_BUF_SIZE 4096
94#define ISP1362_ISTL_BUFSIZE 512
95#define ISP1362_INTL_BLKSIZE 64
96#define ISP1362_INTL_BUFFERS 16
97#define ISP1362_ATL_BLKSIZE 64
98
99#define ISP1362_REG_WRITE_OFFSET 0x80
100
101#ifdef ISP1362_DEBUG
102typedef const unsigned int isp1362_reg_t;
103
104#define REG_WIDTH_16 0x000
105#define REG_WIDTH_32 0x100
106#define REG_WIDTH_MASK 0x100
107#define REG_NO_MASK 0x0ff
108
109#define REG_ACCESS_R 0x200
110#define REG_ACCESS_W 0x400
111#define REG_ACCESS_RW 0x600
112#define REG_ACCESS_MASK 0x600
113
114#define ISP1362_REG_NO(r) ((r) & REG_NO_MASK)
115
116#define _BUG_ON(x) BUG_ON(x)
117#define _WARN_ON(x) WARN_ON(x)
118
119#define ISP1362_REG(name, addr, width, rw) \
120static isp1362_reg_t ISP1362_REG_##name = ((addr) | (width) | (rw))
121
122#define REG_ACCESS_TEST(r) BUG_ON(((r) & ISP1362_REG_WRITE_OFFSET) && !((r) & REG_ACCESS_W))
123#define REG_WIDTH_TEST(r, w) BUG_ON(((r) & REG_WIDTH_MASK) != (w))
124#else
125typedef const unsigned char isp1362_reg_t;
126#define ISP1362_REG_NO(r) (r)
127#define _BUG_ON(x) do {} while (0)
128#define _WARN_ON(x) do {} while (0)
129
130#define ISP1362_REG(name, addr, width, rw) \
131static isp1362_reg_t ISP1362_REG_##name = addr
132
133#define REG_ACCESS_TEST(r) do {} while (0)
134#define REG_WIDTH_TEST(r, w) do {} while (0)
135#endif
136
137/* OHCI compatible registers */
138/*
139 * Note: Some of the ISP1362 'OHCI' registers implement only
140 * a subset of the bits defined in the OHCI spec.
141 *
142 * Bitmasks for the individual bits of these registers are defined in "ohci.h"
143 */
144ISP1362_REG(HCREVISION, 0x00, REG_WIDTH_32, REG_ACCESS_R);
145ISP1362_REG(HCCONTROL, 0x01, REG_WIDTH_32, REG_ACCESS_RW);
146ISP1362_REG(HCCMDSTAT, 0x02, REG_WIDTH_32, REG_ACCESS_RW);
147ISP1362_REG(HCINTSTAT, 0x03, REG_WIDTH_32, REG_ACCESS_RW);
148ISP1362_REG(HCINTENB, 0x04, REG_WIDTH_32, REG_ACCESS_RW);
149ISP1362_REG(HCINTDIS, 0x05, REG_WIDTH_32, REG_ACCESS_RW);
150ISP1362_REG(HCFMINTVL, 0x0d, REG_WIDTH_32, REG_ACCESS_RW);
151ISP1362_REG(HCFMREM, 0x0e, REG_WIDTH_32, REG_ACCESS_RW);
152ISP1362_REG(HCFMNUM, 0x0f, REG_WIDTH_32, REG_ACCESS_RW);
153ISP1362_REG(HCLSTHRESH, 0x11, REG_WIDTH_32, REG_ACCESS_RW);
154ISP1362_REG(HCRHDESCA, 0x12, REG_WIDTH_32, REG_ACCESS_RW);
155ISP1362_REG(HCRHDESCB, 0x13, REG_WIDTH_32, REG_ACCESS_RW);
156ISP1362_REG(HCRHSTATUS, 0x14, REG_WIDTH_32, REG_ACCESS_RW);
157ISP1362_REG(HCRHPORT1, 0x15, REG_WIDTH_32, REG_ACCESS_RW);
158ISP1362_REG(HCRHPORT2, 0x16, REG_WIDTH_32, REG_ACCESS_RW);
159
160/* Philips ISP1362 specific registers */
161ISP1362_REG(HCHWCFG, 0x20, REG_WIDTH_16, REG_ACCESS_RW);
162#define HCHWCFG_DISABLE_SUSPEND (1 << 15)
163#define HCHWCFG_GLOBAL_PWRDOWN (1 << 14)
164#define HCHWCFG_PULLDOWN_DS1 (1 << 13)
165#define HCHWCFG_PULLDOWN_DS2 (1 << 12)
166#define HCHWCFG_CLKNOTSTOP (1 << 11)
167#define HCHWCFG_ANALOG_OC (1 << 10)
168#define HCHWCFG_ONEINT (1 << 9)
169#define HCHWCFG_DACK_MODE (1 << 8)
170#define HCHWCFG_ONEDMA (1 << 7)
171#define HCHWCFG_DACK_POL (1 << 6)
172#define HCHWCFG_DREQ_POL (1 << 5)
173#define HCHWCFG_DBWIDTH_MASK (0x03 << 3)
174#define HCHWCFG_DBWIDTH(n) (((n) << 3) & HCHWCFG_DBWIDTH_MASK)
175#define HCHWCFG_INT_POL (1 << 2)
176#define HCHWCFG_INT_TRIGGER (1 << 1)
177#define HCHWCFG_INT_ENABLE (1 << 0)
178
179ISP1362_REG(HCDMACFG, 0x21, REG_WIDTH_16, REG_ACCESS_RW);
180#define HCDMACFG_CTR_ENABLE (1 << 7)
181#define HCDMACFG_BURST_LEN_MASK (0x03 << 5)
182#define HCDMACFG_BURST_LEN(n) (((n) << 5) & HCDMACFG_BURST_LEN_MASK)
183#define HCDMACFG_BURST_LEN_1 HCDMACFG_BURST_LEN(0)
184#define HCDMACFG_BURST_LEN_4 HCDMACFG_BURST_LEN(1)
185#define HCDMACFG_BURST_LEN_8 HCDMACFG_BURST_LEN(2)
186#define HCDMACFG_DMA_ENABLE (1 << 4)
187#define HCDMACFG_BUF_TYPE_MASK (0x07 << 1)
188#define HCDMACFG_BUF_TYPE(n) (((n) << 1) & HCDMACFG_BUF_TYPE_MASK)
189#define HCDMACFG_BUF_ISTL0 HCDMACFG_BUF_TYPE(0)
190#define HCDMACFG_BUF_ISTL1 HCDMACFG_BUF_TYPE(1)
191#define HCDMACFG_BUF_INTL HCDMACFG_BUF_TYPE(2)
192#define HCDMACFG_BUF_ATL HCDMACFG_BUF_TYPE(3)
193#define HCDMACFG_BUF_DIRECT HCDMACFG_BUF_TYPE(4)
194#define HCDMACFG_DMA_RW_SELECT (1 << 0)
195
196ISP1362_REG(HCXFERCTR, 0x22, REG_WIDTH_16, REG_ACCESS_RW);
197
198ISP1362_REG(HCuPINT, 0x24, REG_WIDTH_16, REG_ACCESS_RW);
199#define HCuPINT_SOF (1 << 0)
200#define HCuPINT_ISTL0 (1 << 1)
201#define HCuPINT_ISTL1 (1 << 2)
202#define HCuPINT_EOT (1 << 3)
203#define HCuPINT_OPR (1 << 4)
204#define HCuPINT_SUSP (1 << 5)
205#define HCuPINT_CLKRDY (1 << 6)
206#define HCuPINT_INTL (1 << 7)
207#define HCuPINT_ATL (1 << 8)
208#define HCuPINT_OTG (1 << 9)
209
210ISP1362_REG(HCuPINTENB, 0x25, REG_WIDTH_16, REG_ACCESS_RW);
211/* same bit definitions apply as for HCuPINT */
212
213ISP1362_REG(HCCHIPID, 0x27, REG_WIDTH_16, REG_ACCESS_R);
214#define HCCHIPID_MASK 0xff00
215#define HCCHIPID_MAGIC 0x3600
216
217ISP1362_REG(HCSCRATCH, 0x28, REG_WIDTH_16, REG_ACCESS_RW);
218
219ISP1362_REG(HCSWRES, 0x29, REG_WIDTH_16, REG_ACCESS_W);
220#define HCSWRES_MAGIC 0x00f6
221
222ISP1362_REG(HCBUFSTAT, 0x2c, REG_WIDTH_16, REG_ACCESS_RW);
223#define HCBUFSTAT_ISTL0_FULL (1 << 0)
224#define HCBUFSTAT_ISTL1_FULL (1 << 1)
225#define HCBUFSTAT_INTL_ACTIVE (1 << 2)
226#define HCBUFSTAT_ATL_ACTIVE (1 << 3)
227#define HCBUFSTAT_RESET_HWPP (1 << 4)
228#define HCBUFSTAT_ISTL0_ACTIVE (1 << 5)
229#define HCBUFSTAT_ISTL1_ACTIVE (1 << 6)
230#define HCBUFSTAT_ISTL0_DONE (1 << 8)
231#define HCBUFSTAT_ISTL1_DONE (1 << 9)
232#define HCBUFSTAT_PAIRED_PTDPP (1 << 10)
233
234ISP1362_REG(HCDIRADDR, 0x32, REG_WIDTH_32, REG_ACCESS_RW);
235#define HCDIRADDR_ADDR_MASK 0x0000ffff
236#define HCDIRADDR_ADDR(n) (((n) << 0) & HCDIRADDR_ADDR_MASK)
237#define HCDIRADDR_COUNT_MASK 0xffff0000
238#define HCDIRADDR_COUNT(n) (((n) << 16) & HCDIRADDR_COUNT_MASK)
239ISP1362_REG(HCDIRDATA, 0x45, REG_WIDTH_16, REG_ACCESS_RW);
240
241ISP1362_REG(HCISTLBUFSZ, 0x30, REG_WIDTH_16, REG_ACCESS_RW);
242ISP1362_REG(HCISTL0PORT, 0x40, REG_WIDTH_16, REG_ACCESS_RW);
243ISP1362_REG(HCISTL1PORT, 0x42, REG_WIDTH_16, REG_ACCESS_RW);
244ISP1362_REG(HCISTLRATE, 0x47, REG_WIDTH_16, REG_ACCESS_RW);
245
246ISP1362_REG(HCINTLBUFSZ, 0x33, REG_WIDTH_16, REG_ACCESS_RW);
247ISP1362_REG(HCINTLPORT, 0x43, REG_WIDTH_16, REG_ACCESS_RW);
248ISP1362_REG(HCINTLBLKSZ, 0x53, REG_WIDTH_16, REG_ACCESS_RW);
249ISP1362_REG(HCINTLDONE, 0x17, REG_WIDTH_32, REG_ACCESS_R);
250ISP1362_REG(HCINTLSKIP, 0x18, REG_WIDTH_32, REG_ACCESS_RW);
251ISP1362_REG(HCINTLLAST, 0x19, REG_WIDTH_32, REG_ACCESS_RW);
252ISP1362_REG(HCINTLCURR, 0x1a, REG_WIDTH_16, REG_ACCESS_R);
253
254ISP1362_REG(HCATLBUFSZ, 0x34, REG_WIDTH_16, REG_ACCESS_RW);
255ISP1362_REG(HCATLPORT, 0x44, REG_WIDTH_16, REG_ACCESS_RW);
256ISP1362_REG(HCATLBLKSZ, 0x54, REG_WIDTH_16, REG_ACCESS_RW);
257ISP1362_REG(HCATLDONE, 0x1b, REG_WIDTH_32, REG_ACCESS_R);
258ISP1362_REG(HCATLSKIP, 0x1c, REG_WIDTH_32, REG_ACCESS_RW);
259ISP1362_REG(HCATLLAST, 0x1d, REG_WIDTH_32, REG_ACCESS_RW);
260ISP1362_REG(HCATLCURR, 0x1e, REG_WIDTH_16, REG_ACCESS_R);
261
262ISP1362_REG(HCATLDTC, 0x51, REG_WIDTH_16, REG_ACCESS_RW);
263ISP1362_REG(HCATLDTCTO, 0x52, REG_WIDTH_16, REG_ACCESS_RW);
264
265
266ISP1362_REG(OTGCONTROL, 0x62, REG_WIDTH_16, REG_ACCESS_RW);
267ISP1362_REG(OTGSTATUS, 0x67, REG_WIDTH_16, REG_ACCESS_R);
268ISP1362_REG(OTGINT, 0x68, REG_WIDTH_16, REG_ACCESS_RW);
269ISP1362_REG(OTGINTENB, 0x69, REG_WIDTH_16, REG_ACCESS_RW);
270ISP1362_REG(OTGTIMER, 0x6A, REG_WIDTH_16, REG_ACCESS_RW);
271ISP1362_REG(OTGALTTMR, 0x6C, REG_WIDTH_16, REG_ACCESS_RW);
272
273/* Philips transfer descriptor, cpu-endian */
274struct ptd {
275 u16 count;
276#define PTD_COUNT_MSK (0x3ff << 0)
277#define PTD_TOGGLE_MSK (1 << 10)
278#define PTD_ACTIVE_MSK (1 << 11)
279#define PTD_CC_MSK (0xf << 12)
280 u16 mps;
281#define PTD_MPS_MSK (0x3ff << 0)
282#define PTD_SPD_MSK (1 << 10)
283#define PTD_LAST_MSK (1 << 11)
284#define PTD_EP_MSK (0xf << 12)
285 u16 len;
286#define PTD_LEN_MSK (0x3ff << 0)
287#define PTD_DIR_MSK (3 << 10)
288#define PTD_DIR_SETUP (0)
289#define PTD_DIR_OUT (1)
290#define PTD_DIR_IN (2)
291 u16 faddr;
292#define PTD_FA_MSK (0x7f << 0)
293/* PTD Byte 7: [StartingFrame (if ISO PTD) | StartingFrame[0..4], PollingRate[0..2] (if INT PTD)] */
294#define PTD_SF_ISO_MSK (0xff << 8)
295#define PTD_SF_INT_MSK (0x1f << 8)
296#define PTD_PR_MSK (0x07 << 13)
297} __attribute__ ((packed, aligned(2)));
298#define PTD_HEADER_SIZE sizeof(struct ptd)
299
300/* ------------------------------------------------------------------------- */
301/* Copied from ohci.h: */
302/*
303 * Hardware transfer status codes -- CC from PTD
304 */
305#define PTD_CC_NOERROR 0x00
306#define PTD_CC_CRC 0x01
307#define PTD_CC_BITSTUFFING 0x02
308#define PTD_CC_DATATOGGLEM 0x03
309#define PTD_CC_STALL 0x04
310#define PTD_DEVNOTRESP 0x05
311#define PTD_PIDCHECKFAIL 0x06
312#define PTD_UNEXPECTEDPID 0x07
313#define PTD_DATAOVERRUN 0x08
314#define PTD_DATAUNDERRUN 0x09
315 /* 0x0A, 0x0B reserved for hardware */
316#define PTD_BUFFEROVERRUN 0x0C
317#define PTD_BUFFERUNDERRUN 0x0D
318 /* 0x0E, 0x0F reserved for HCD */
319#define PTD_NOTACCESSED 0x0F
320
321
322/* map OHCI TD status codes (CC) to errno values */
323static const int cc_to_error[16] = {
324 /* No Error */ 0,
325 /* CRC Error */ -EILSEQ,
326 /* Bit Stuff */ -EPROTO,
327 /* Data Togg */ -EILSEQ,
328 /* Stall */ -EPIPE,
329 /* DevNotResp */ -ETIMEDOUT,
330 /* PIDCheck */ -EPROTO,
331 /* UnExpPID */ -EPROTO,
332 /* DataOver */ -EOVERFLOW,
333 /* DataUnder */ -EREMOTEIO,
334 /* (for hw) */ -EIO,
335 /* (for hw) */ -EIO,
336 /* BufferOver */ -ECOMM,
337 /* BuffUnder */ -ENOSR,
338 /* (for HCD) */ -EALREADY,
339 /* (for HCD) */ -EALREADY
340};
341
342
343/*
344 * HcControl (control) register masks
345 */
346#define OHCI_CTRL_HCFS (3 << 6) /* host controller functional state */
347#define OHCI_CTRL_RWC (1 << 9) /* remote wakeup connected */
348#define OHCI_CTRL_RWE (1 << 10) /* remote wakeup enable */
349
350/* pre-shifted values for HCFS */
351# define OHCI_USB_RESET (0 << 6)
352# define OHCI_USB_RESUME (1 << 6)
353# define OHCI_USB_OPER (2 << 6)
354# define OHCI_USB_SUSPEND (3 << 6)
355
356/*
357 * HcCommandStatus (cmdstatus) register masks
358 */
359#define OHCI_HCR (1 << 0) /* host controller reset */
360#define OHCI_SOC (3 << 16) /* scheduling overrun count */
361
362/*
363 * masks used with interrupt registers:
364 * HcInterruptStatus (intrstatus)
365 * HcInterruptEnable (intrenable)
366 * HcInterruptDisable (intrdisable)
367 */
368#define OHCI_INTR_SO (1 << 0) /* scheduling overrun */
369#define OHCI_INTR_WDH (1 << 1) /* writeback of done_head */
370#define OHCI_INTR_SF (1 << 2) /* start frame */
371#define OHCI_INTR_RD (1 << 3) /* resume detect */
372#define OHCI_INTR_UE (1 << 4) /* unrecoverable error */
373#define OHCI_INTR_FNO (1 << 5) /* frame number overflow */
374#define OHCI_INTR_RHSC (1 << 6) /* root hub status change */
375#define OHCI_INTR_OC (1 << 30) /* ownership change */
376#define OHCI_INTR_MIE (1 << 31) /* master interrupt enable */
377
378/* roothub.portstatus [i] bits */
379#define RH_PS_CCS 0x00000001 /* current connect status */
380#define RH_PS_PES 0x00000002 /* port enable status*/
381#define RH_PS_PSS 0x00000004 /* port suspend status */
382#define RH_PS_POCI 0x00000008 /* port over current indicator */
383#define RH_PS_PRS 0x00000010 /* port reset status */
384#define RH_PS_PPS 0x00000100 /* port power status */
385#define RH_PS_LSDA 0x00000200 /* low speed device attached */
386#define RH_PS_CSC 0x00010000 /* connect status change */
387#define RH_PS_PESC 0x00020000 /* port enable status change */
388#define RH_PS_PSSC 0x00040000 /* port suspend status change */
389#define RH_PS_OCIC 0x00080000 /* over current indicator change */
390#define RH_PS_PRSC 0x00100000 /* port reset status change */
391
392/* roothub.status bits */
393#define RH_HS_LPS 0x00000001 /* local power status */
394#define RH_HS_OCI 0x00000002 /* over current indicator */
395#define RH_HS_DRWE 0x00008000 /* device remote wakeup enable */
396#define RH_HS_LPSC 0x00010000 /* local power status change */
397#define RH_HS_OCIC 0x00020000 /* over current indicator change */
398#define RH_HS_CRWE 0x80000000 /* clear remote wakeup enable */
399
400/* roothub.b masks */
401#define RH_B_DR 0x0000ffff /* device removable flags */
402#define RH_B_PPCM 0xffff0000 /* port power control mask */
403
404/* roothub.a masks */
405#define RH_A_NDP (0xff << 0) /* number of downstream ports */
406#define RH_A_PSM (1 << 8) /* power switching mode */
407#define RH_A_NPS (1 << 9) /* no power switching */
408#define RH_A_DT (1 << 10) /* device type (mbz) */
409#define RH_A_OCPM (1 << 11) /* over current protection mode */
410#define RH_A_NOCP (1 << 12) /* no over current protection */
411#define RH_A_POTPGT (0xff << 24) /* power on to power good time */
412
413#define FI 0x2edf /* 12000 bits per frame (-1) */
414#define FSMP(fi) (0x7fff & ((6 * ((fi) - 210)) / 7))
415#define LSTHRESH 0x628 /* lowspeed bit threshold */
416
417/* ------------------------------------------------------------------------- */
418
419/* PTD accessor macros. */
420#define PTD_GET_COUNT(p) (((p)->count & PTD_COUNT_MSK) >> 0)
421#define PTD_COUNT(v) (((v) << 0) & PTD_COUNT_MSK)
422#define PTD_GET_TOGGLE(p) (((p)->count & PTD_TOGGLE_MSK) >> 10)
423#define PTD_TOGGLE(v) (((v) << 10) & PTD_TOGGLE_MSK)
424#define PTD_GET_ACTIVE(p) (((p)->count & PTD_ACTIVE_MSK) >> 11)
425#define PTD_ACTIVE(v) (((v) << 11) & PTD_ACTIVE_MSK)
426#define PTD_GET_CC(p) (((p)->count & PTD_CC_MSK) >> 12)
427#define PTD_CC(v) (((v) << 12) & PTD_CC_MSK)
428#define PTD_GET_MPS(p) (((p)->mps & PTD_MPS_MSK) >> 0)
429#define PTD_MPS(v) (((v) << 0) & PTD_MPS_MSK)
430#define PTD_GET_SPD(p) (((p)->mps & PTD_SPD_MSK) >> 10)
431#define PTD_SPD(v) (((v) << 10) & PTD_SPD_MSK)
432#define PTD_GET_LAST(p) (((p)->mps & PTD_LAST_MSK) >> 11)
433#define PTD_LAST(v) (((v) << 11) & PTD_LAST_MSK)
434#define PTD_GET_EP(p) (((p)->mps & PTD_EP_MSK) >> 12)
435#define PTD_EP(v) (((v) << 12) & PTD_EP_MSK)
436#define PTD_GET_LEN(p) (((p)->len & PTD_LEN_MSK) >> 0)
437#define PTD_LEN(v) (((v) << 0) & PTD_LEN_MSK)
438#define PTD_GET_DIR(p) (((p)->len & PTD_DIR_MSK) >> 10)
439#define PTD_DIR(v) (((v) << 10) & PTD_DIR_MSK)
440#define PTD_GET_FA(p) (((p)->faddr & PTD_FA_MSK) >> 0)
441#define PTD_FA(v) (((v) << 0) & PTD_FA_MSK)
442#define PTD_GET_SF_INT(p) (((p)->faddr & PTD_SF_INT_MSK) >> 8)
443#define PTD_SF_INT(v) (((v) << 8) & PTD_SF_INT_MSK)
444#define PTD_GET_SF_ISO(p) (((p)->faddr & PTD_SF_ISO_MSK) >> 8)
445#define PTD_SF_ISO(v) (((v) << 8) & PTD_SF_ISO_MSK)
446#define PTD_GET_PR(p) (((p)->faddr & PTD_PR_MSK) >> 13)
447#define PTD_PR(v) (((v) << 13) & PTD_PR_MSK)
448
449#define LOG2_PERIODIC_SIZE 5 /* arbitrary; this matches OHCI */
450#define PERIODIC_SIZE (1 << LOG2_PERIODIC_SIZE)
451
452struct isp1362_ep {
453 struct usb_host_endpoint *hep;
454 struct usb_device *udev;
455
456 /* philips transfer descriptor */
457 struct ptd ptd;
458
459 u8 maxpacket;
460 u8 epnum;
461 u8 nextpid;
462 u16 error_count;
463 u16 length; /* of current packet */
464 s16 ptd_offset; /* buffer offset in ISP1362 where
465 PTD has been stored
466 (for access thru HCDIRDATA) */
467 int ptd_index;
468 int num_ptds;
469 void *data; /* to databuf */
470 /* queue of active EPs (the ones transmitted to the chip) */
471 struct list_head active;
472
473 /* periodic schedule */
474 u8 branch;
475 u16 interval;
476 u16 load;
477 u16 last_iso;
478
479 /* async schedule */
480 struct list_head schedule; /* list of all EPs that need processing */
481 struct list_head remove_list;
482 int num_req;
483};
484
485struct isp1362_ep_queue {
486 struct list_head active; /* list of PTDs currently processed by HC */
487 atomic_t finishing;
488 unsigned long buf_map;
489 unsigned long skip_map;
490 int free_ptd;
491 u16 buf_start;
492 u16 buf_size;
493 u16 blk_size; /* PTD buffer block size for ATL and INTL */
494 u8 buf_count;
495 u8 buf_avail;
496 char name[16];
497
498 /* for statistical tracking */
499 u8 stat_maxptds; /* Max # of ptds seen simultaneously in fifo */
500 u8 ptd_count; /* number of ptds submitted to this queue */
501};
502
503struct isp1362_hcd {
504 spinlock_t lock;
505 void __iomem *addr_reg;
506 void __iomem *data_reg;
507
508 struct isp1362_platform_data *board;
509
510 struct proc_dir_entry *pde;
511 unsigned long stat1, stat2, stat4, stat8, stat16;
512
513 /* HC registers */
514 u32 intenb; /* "OHCI" interrupts */
515 u16 irqenb; /* uP interrupts */
516
517 /* Root hub registers */
518 u32 rhdesca;
519 u32 rhdescb;
520 u32 rhstatus;
521 u32 rhport[MAX_ROOT_PORTS];
522 unsigned long next_statechange;
523
524 /* HC control reg shadow copy */
525 u32 hc_control;
526
527 /* async schedule: control, bulk */
528 struct list_head async;
529
530 /* periodic schedule: int */
531 u16 load[PERIODIC_SIZE];
532 struct list_head periodic;
533 u16 fmindex;
534
535 /* periodic schedule: isochronous */
536 struct list_head isoc;
537 int istl_flip:1;
538 int irq_active:1;
539
540 /* Schedules for the current frame */
541 struct isp1362_ep_queue atl_queue;
542 struct isp1362_ep_queue intl_queue;
543 struct isp1362_ep_queue istl_queue[2];
544
545 /* list of PTDs retrieved from HC */
546 struct list_head remove_list;
547 enum {
548 ISP1362_INT_SOF,
549 ISP1362_INT_ISTL0,
550 ISP1362_INT_ISTL1,
551 ISP1362_INT_EOT,
552 ISP1362_INT_OPR,
553 ISP1362_INT_SUSP,
554 ISP1362_INT_CLKRDY,
555 ISP1362_INT_INTL,
556 ISP1362_INT_ATL,
557 ISP1362_INT_OTG,
558 NUM_ISP1362_IRQS
559 } IRQ_NAMES;
560 unsigned int irq_stat[NUM_ISP1362_IRQS];
561 int req_serial;
562};
563
564static inline const char *ISP1362_INT_NAME(int n)
565{
566 switch (n) {
567 case ISP1362_INT_SOF: return "SOF";
568 case ISP1362_INT_ISTL0: return "ISTL0";
569 case ISP1362_INT_ISTL1: return "ISTL1";
570 case ISP1362_INT_EOT: return "EOT";
571 case ISP1362_INT_OPR: return "OPR";
572 case ISP1362_INT_SUSP: return "SUSP";
573 case ISP1362_INT_CLKRDY: return "CLKRDY";
574 case ISP1362_INT_INTL: return "INTL";
575 case ISP1362_INT_ATL: return "ATL";
576 case ISP1362_INT_OTG: return "OTG";
577 default: return "unknown";
578 }
579}
580
581static inline void ALIGNSTAT(struct isp1362_hcd *isp1362_hcd, void *ptr)
582{
583 unsigned p = (unsigned)ptr;
584 if (!(p & 0xf))
585 isp1362_hcd->stat16++;
586 else if (!(p & 0x7))
587 isp1362_hcd->stat8++;
588 else if (!(p & 0x3))
589 isp1362_hcd->stat4++;
590 else if (!(p & 0x1))
591 isp1362_hcd->stat2++;
592 else
593 isp1362_hcd->stat1++;
594}
595
596static inline struct isp1362_hcd *hcd_to_isp1362_hcd(struct usb_hcd *hcd)
597{
598 return (struct isp1362_hcd *) (hcd->hcd_priv);
599}
600
601static inline struct usb_hcd *isp1362_hcd_to_hcd(struct isp1362_hcd *isp1362_hcd)
602{
603 return container_of((void *)isp1362_hcd, struct usb_hcd, hcd_priv);
604}
605
606#define frame_before(f1, f2) ((s16)((u16)f1 - (u16)f2) < 0)
607
608/*
609 * ISP1362 HW Interface
610 */
611
612#ifdef ISP1362_DEBUG
613#define DBG(level, fmt...) \
614 do { \
615 if (dbg_level > level) \
616 pr_debug(fmt); \
617 } while (0)
618#define _DBG(level, fmt...) \
619 do { \
620 if (dbg_level > level) \
621 printk(fmt); \
622 } while (0)
623#else
624#define DBG(fmt...) do {} while (0)
625#define _DBG DBG
626#endif
627
628#ifdef VERBOSE
629# define VDBG(fmt...) DBG(3, fmt)
630#else
631# define VDBG(fmt...) do {} while (0)
632#endif
633
634#ifdef REGISTERS
635# define RDBG(fmt...) DBG(1, fmt)
636#else
637# define RDBG(fmt...) do {} while (0)
638#endif
639
640#ifdef URB_TRACE
641#define URB_DBG(fmt...) DBG(0, fmt)
642#else
643#define URB_DBG(fmt...) do {} while (0)
644#endif
645
646
647#if USE_PLATFORM_DELAY
648#if USE_NDELAY
649#error USE_PLATFORM_DELAY and USE_NDELAY defined simultaneously.
650#endif
651#define isp1362_delay(h, d) (h)->board->delay(isp1362_hcd_to_hcd(h)->self.controller, d)
652#elif USE_NDELAY
653#define isp1362_delay(h, d) ndelay(d)
654#else
655#define isp1362_delay(h, d) do {} while (0)
656#endif
657
658#define get_urb(ep) ({ \
659 BUG_ON(list_empty(&ep->hep->urb_list)); \
660 container_of(ep->hep->urb_list.next, struct urb, urb_list); \
661})
662
663/* basic access functions for ISP1362 chip registers */
664/* NOTE: The contents of the address pointer register cannot be read back! The driver must ensure,
665 * that all register accesses are performed with interrupts disabled, since the interrupt
666 * handler has no way of restoring the previous state.
667 */
668static void isp1362_write_addr(struct isp1362_hcd *isp1362_hcd, isp1362_reg_t reg)
669{
670 /*_BUG_ON((reg & ISP1362_REG_WRITE_OFFSET) && !(reg & REG_ACCESS_W));*/
671 REG_ACCESS_TEST(reg);
672 _BUG_ON(!irqs_disabled());
673 DUMMY_DELAY_ACCESS;
674 writew(ISP1362_REG_NO(reg), isp1362_hcd->addr_reg);
675 DUMMY_DELAY_ACCESS;
676 isp1362_delay(isp1362_hcd, 1);
677}
678
679static void isp1362_write_data16(struct isp1362_hcd *isp1362_hcd, u16 val)
680{
681 _BUG_ON(!irqs_disabled());
682 DUMMY_DELAY_ACCESS;
683 writew(val, isp1362_hcd->data_reg);
684}
685
686static u16 isp1362_read_data16(struct isp1362_hcd *isp1362_hcd)
687{
688 u16 val;
689
690 _BUG_ON(!irqs_disabled());
691 DUMMY_DELAY_ACCESS;
692 val = readw(isp1362_hcd->data_reg);
693
694 return val;
695}
696
697static void isp1362_write_data32(struct isp1362_hcd *isp1362_hcd, u32 val)
698{
699 _BUG_ON(!irqs_disabled());
700#if USE_32BIT
701 DUMMY_DELAY_ACCESS;
702 writel(val, isp1362_hcd->data_reg);
703#else
704 DUMMY_DELAY_ACCESS;
705 writew((u16)val, isp1362_hcd->data_reg);
706 DUMMY_DELAY_ACCESS;
707 writew(val >> 16, isp1362_hcd->data_reg);
708#endif
709}
710
711static u32 isp1362_read_data32(struct isp1362_hcd *isp1362_hcd)
712{
713 u32 val;
714
715 _BUG_ON(!irqs_disabled());
716#if USE_32BIT
717 DUMMY_DELAY_ACCESS;
718 val = readl(isp1362_hcd->data_reg);
719#else
720 DUMMY_DELAY_ACCESS;
721 val = (u32)readw(isp1362_hcd->data_reg);
722 DUMMY_DELAY_ACCESS;
723 val |= (u32)readw(isp1362_hcd->data_reg) << 16;
724#endif
725 return val;
726}
727
728/* use readsw/writesw to access the fifo whenever possible */
729/* assume HCDIRDATA or XFERCTR & addr_reg have been set up */
730static void isp1362_read_fifo(struct isp1362_hcd *isp1362_hcd, void *buf, u16 len)
731{
732 u8 *dp = buf;
733 u16 data;
734
735 if (!len)
736 return;
737
738 _BUG_ON(!irqs_disabled());
739
740 RDBG("%s: Reading %d byte from fifo to mem @ %p\n", __func__, len, buf);
741#if USE_32BIT
742 if (len >= 4) {
743 RDBG("%s: Using readsl for %d dwords\n", __func__, len >> 2);
744 readsl(isp1362_hcd->data_reg, dp, len >> 2);
745 dp += len & ~3;
746 len &= 3;
747 }
748#endif
749 if (len >= 2) {
750 RDBG("%s: Using readsw for %d words\n", __func__, len >> 1);
751 insw((unsigned long)isp1362_hcd->data_reg, dp, len >> 1);
752 dp += len & ~1;
753 len &= 1;
754 }
755
756 BUG_ON(len & ~1);
757 if (len > 0) {
758 data = isp1362_read_data16(isp1362_hcd);
759 RDBG("%s: Reading trailing byte %02x to mem @ %08x\n", __func__,
760 (u8)data, (u32)dp);
761 *dp = (u8)data;
762 }
763}
764
765static void isp1362_write_fifo(struct isp1362_hcd *isp1362_hcd, void *buf, u16 len)
766{
767 u8 *dp = buf;
768 u16 data;
769
770 if (!len)
771 return;
772
773 if ((unsigned)dp & 0x1) {
774 /* not aligned */
775 for (; len > 1; len -= 2) {
776 data = *dp++;
777 data |= *dp++ << 8;
778 isp1362_write_data16(isp1362_hcd, data);
779 }
780 if (len)
781 isp1362_write_data16(isp1362_hcd, *dp);
782 return;
783 }
784
785 _BUG_ON(!irqs_disabled());
786
787 RDBG("%s: Writing %d byte to fifo from memory @%p\n", __func__, len, buf);
788#if USE_32BIT
789 if (len >= 4) {
790 RDBG("%s: Using writesl for %d dwords\n", __func__, len >> 2);
791 writesl(isp1362_hcd->data_reg, dp, len >> 2);
792 dp += len & ~3;
793 len &= 3;
794 }
795#endif
796 if (len >= 2) {
797 RDBG("%s: Using writesw for %d words\n", __func__, len >> 1);
798 outsw((unsigned long)isp1362_hcd->data_reg, dp, len >> 1);
799 dp += len & ~1;
800 len &= 1;
801 }
802
803 BUG_ON(len & ~1);
804 if (len > 0) {
805 /* finally write any trailing byte; we don't need to care
806 * about the high byte of the last word written
807 */
808 data = (u16)*dp;
809 RDBG("%s: Sending trailing byte %02x from mem @ %08x\n", __func__,
810 data, (u32)dp);
811 isp1362_write_data16(isp1362_hcd, data);
812 }
813}
814
815#define isp1362_read_reg16(d, r) ({ \
816 u16 __v; \
817 REG_WIDTH_TEST(ISP1362_REG_##r, REG_WIDTH_16); \
818 isp1362_write_addr(d, ISP1362_REG_##r); \
819 __v = isp1362_read_data16(d); \
820 RDBG("%s: Read %04x from %s[%02x]\n", __func__, __v, #r, \
821 ISP1362_REG_NO(ISP1362_REG_##r)); \
822 __v; \
823})
824
825#define isp1362_read_reg32(d, r) ({ \
826 u32 __v; \
827 REG_WIDTH_TEST(ISP1362_REG_##r, REG_WIDTH_32); \
828 isp1362_write_addr(d, ISP1362_REG_##r); \
829 __v = isp1362_read_data32(d); \
830 RDBG("%s: Read %08x from %s[%02x]\n", __func__, __v, #r, \
831 ISP1362_REG_NO(ISP1362_REG_##r)); \
832 __v; \
833})
834
835#define isp1362_write_reg16(d, r, v) { \
836 REG_WIDTH_TEST(ISP1362_REG_##r, REG_WIDTH_16); \
837 isp1362_write_addr(d, (ISP1362_REG_##r) | ISP1362_REG_WRITE_OFFSET); \
838 isp1362_write_data16(d, (u16)(v)); \
839 RDBG("%s: Wrote %04x to %s[%02x]\n", __func__, (u16)(v), #r, \
840 ISP1362_REG_NO(ISP1362_REG_##r)); \
841}
842
843#define isp1362_write_reg32(d, r, v) { \
844 REG_WIDTH_TEST(ISP1362_REG_##r, REG_WIDTH_32); \
845 isp1362_write_addr(d, (ISP1362_REG_##r) | ISP1362_REG_WRITE_OFFSET); \
846 isp1362_write_data32(d, (u32)(v)); \
847 RDBG("%s: Wrote %08x to %s[%02x]\n", __func__, (u32)(v), #r, \
848 ISP1362_REG_NO(ISP1362_REG_##r)); \
849}
850
851#define isp1362_set_mask16(d, r, m) { \
852 u16 __v; \
853 __v = isp1362_read_reg16(d, r); \
854 if ((__v | m) != __v) \
855 isp1362_write_reg16(d, r, __v | m); \
856}
857
858#define isp1362_clr_mask16(d, r, m) { \
859 u16 __v; \
860 __v = isp1362_read_reg16(d, r); \
861 if ((__v & ~m) != __v) \
862 isp1362_write_reg16(d, r, __v & ~m); \
863}
864
865#define isp1362_set_mask32(d, r, m) { \
866 u32 __v; \
867 __v = isp1362_read_reg32(d, r); \
868 if ((__v | m) != __v) \
869 isp1362_write_reg32(d, r, __v | m); \
870}
871
872#define isp1362_clr_mask32(d, r, m) { \
873 u32 __v; \
874 __v = isp1362_read_reg32(d, r); \
875 if ((__v & ~m) != __v) \
876 isp1362_write_reg32(d, r, __v & ~m); \
877}
878
879#ifdef ISP1362_DEBUG
880#define isp1362_show_reg(d, r) { \
881 if ((ISP1362_REG_##r & REG_WIDTH_MASK) == REG_WIDTH_32) \
882 DBG(0, "%-12s[%02x]: %08x\n", #r, \
883 ISP1362_REG_NO(ISP1362_REG_##r), isp1362_read_reg32(d, r)); \
884 else \
885 DBG(0, "%-12s[%02x]: %04x\n", #r, \
886 ISP1362_REG_NO(ISP1362_REG_##r), isp1362_read_reg16(d, r)); \
887}
888#else
889#define isp1362_show_reg(d, r) do {} while (0)
890#endif
891
892static void __attribute__((__unused__)) isp1362_show_regs(struct isp1362_hcd *isp1362_hcd)
893{
894 isp1362_show_reg(isp1362_hcd, HCREVISION);
895 isp1362_show_reg(isp1362_hcd, HCCONTROL);
896 isp1362_show_reg(isp1362_hcd, HCCMDSTAT);
897 isp1362_show_reg(isp1362_hcd, HCINTSTAT);
898 isp1362_show_reg(isp1362_hcd, HCINTENB);
899 isp1362_show_reg(isp1362_hcd, HCFMINTVL);
900 isp1362_show_reg(isp1362_hcd, HCFMREM);
901 isp1362_show_reg(isp1362_hcd, HCFMNUM);
902 isp1362_show_reg(isp1362_hcd, HCLSTHRESH);
903 isp1362_show_reg(isp1362_hcd, HCRHDESCA);
904 isp1362_show_reg(isp1362_hcd, HCRHDESCB);
905 isp1362_show_reg(isp1362_hcd, HCRHSTATUS);
906 isp1362_show_reg(isp1362_hcd, HCRHPORT1);
907 isp1362_show_reg(isp1362_hcd, HCRHPORT2);
908
909 isp1362_show_reg(isp1362_hcd, HCHWCFG);
910 isp1362_show_reg(isp1362_hcd, HCDMACFG);
911 isp1362_show_reg(isp1362_hcd, HCXFERCTR);
912 isp1362_show_reg(isp1362_hcd, HCuPINT);
913
914 if (in_interrupt())
915 DBG(0, "%-12s[%02x]: %04x\n", "HCuPINTENB",
916 ISP1362_REG_NO(ISP1362_REG_HCuPINTENB), isp1362_hcd->irqenb);
917 else
918 isp1362_show_reg(isp1362_hcd, HCuPINTENB);
919 isp1362_show_reg(isp1362_hcd, HCCHIPID);
920 isp1362_show_reg(isp1362_hcd, HCSCRATCH);
921 isp1362_show_reg(isp1362_hcd, HCBUFSTAT);
922 isp1362_show_reg(isp1362_hcd, HCDIRADDR);
923 /* Access would advance fifo
924 * isp1362_show_reg(isp1362_hcd, HCDIRDATA);
925 */
926 isp1362_show_reg(isp1362_hcd, HCISTLBUFSZ);
927 isp1362_show_reg(isp1362_hcd, HCISTLRATE);
928 isp1362_show_reg(isp1362_hcd, HCINTLBUFSZ);
929 isp1362_show_reg(isp1362_hcd, HCINTLBLKSZ);
930 isp1362_show_reg(isp1362_hcd, HCINTLDONE);
931 isp1362_show_reg(isp1362_hcd, HCINTLSKIP);
932 isp1362_show_reg(isp1362_hcd, HCINTLLAST);
933 isp1362_show_reg(isp1362_hcd, HCINTLCURR);
934 isp1362_show_reg(isp1362_hcd, HCATLBUFSZ);
935 isp1362_show_reg(isp1362_hcd, HCATLBLKSZ);
936 /* only valid after ATL_DONE interrupt
937 * isp1362_show_reg(isp1362_hcd, HCATLDONE);
938 */
939 isp1362_show_reg(isp1362_hcd, HCATLSKIP);
940 isp1362_show_reg(isp1362_hcd, HCATLLAST);
941 isp1362_show_reg(isp1362_hcd, HCATLCURR);
942 isp1362_show_reg(isp1362_hcd, HCATLDTC);
943 isp1362_show_reg(isp1362_hcd, HCATLDTCTO);
944}
945
946static void isp1362_write_diraddr(struct isp1362_hcd *isp1362_hcd, u16 offset, u16 len)
947{
948 _BUG_ON(offset & 1);
949 _BUG_ON(offset >= ISP1362_BUF_SIZE);
950 _BUG_ON(len > ISP1362_BUF_SIZE);
951 _BUG_ON(offset + len > ISP1362_BUF_SIZE);
952 len = (len + 1) & ~1;
953
954 isp1362_clr_mask16(isp1362_hcd, HCDMACFG, HCDMACFG_CTR_ENABLE);
955 isp1362_write_reg32(isp1362_hcd, HCDIRADDR,
956 HCDIRADDR_ADDR(offset) | HCDIRADDR_COUNT(len));
957}
958
959static void isp1362_read_buffer(struct isp1362_hcd *isp1362_hcd, void *buf, u16 offset, int len)
960{
961 _BUG_ON(offset & 1);
962
963 isp1362_write_diraddr(isp1362_hcd, offset, len);
964
965 DBG(3, "%s: Reading %d byte from buffer @%04x to memory @ %08x\n", __func__,
966 len, offset, (u32)buf);
967
968 isp1362_write_reg16(isp1362_hcd, HCuPINT, HCuPINT_EOT);
969 _WARN_ON((isp1362_read_reg16(isp1362_hcd, HCuPINT) & HCuPINT_EOT));
970
971 isp1362_write_addr(isp1362_hcd, ISP1362_REG_HCDIRDATA);
972
973 isp1362_read_fifo(isp1362_hcd, buf, len);
974 _WARN_ON(!(isp1362_read_reg16(isp1362_hcd, HCuPINT) & HCuPINT_EOT));
975 isp1362_write_reg16(isp1362_hcd, HCuPINT, HCuPINT_EOT);
976 _WARN_ON((isp1362_read_reg16(isp1362_hcd, HCuPINT) & HCuPINT_EOT));
977}
978
979static void isp1362_write_buffer(struct isp1362_hcd *isp1362_hcd, void *buf, u16 offset, int len)
980{
981 _BUG_ON(offset & 1);
982
983 isp1362_write_diraddr(isp1362_hcd, offset, len);
984
985 DBG(3, "%s: Writing %d byte to buffer @%04x from memory @ %08x\n", __func__,
986 len, offset, (u32)buf);
987
988 isp1362_write_reg16(isp1362_hcd, HCuPINT, HCuPINT_EOT);
989 _WARN_ON((isp1362_read_reg16(isp1362_hcd, HCuPINT) & HCuPINT_EOT));
990
991 isp1362_write_addr(isp1362_hcd, ISP1362_REG_HCDIRDATA | ISP1362_REG_WRITE_OFFSET);
992 isp1362_write_fifo(isp1362_hcd, buf, len);
993
994 _WARN_ON(!(isp1362_read_reg16(isp1362_hcd, HCuPINT) & HCuPINT_EOT));
995 isp1362_write_reg16(isp1362_hcd, HCuPINT, HCuPINT_EOT);
996 _WARN_ON((isp1362_read_reg16(isp1362_hcd, HCuPINT) & HCuPINT_EOT));
997}
998
999static void __attribute__((unused)) dump_data(char *buf, int len)
1000{
1001 if (dbg_level > 0) {
1002 int k;
1003 int lf = 0;
1004
1005 for (k = 0; k < len; ++k) {
1006 if (!lf)
1007 DBG(0, "%04x:", k);
1008 printk(" %02x", ((u8 *) buf)[k]);
1009 lf = 1;
1010 if (!k)
1011 continue;
1012 if (k % 16 == 15) {
1013 printk("\n");
1014 lf = 0;
1015 continue;
1016 }
1017 if (k % 8 == 7)
1018 printk(" ");
1019 if (k % 4 == 3)
1020 printk(" ");
1021 }
1022 if (lf)
1023 printk("\n");
1024 }
1025}
1026
1027#if defined(ISP1362_DEBUG) && defined(PTD_TRACE)
1028
1029static void dump_ptd(struct ptd *ptd)
1030{
1031 DBG(0, "EP %p: CC=%x EP=%d DIR=%x CNT=%d LEN=%d MPS=%d TGL=%x ACT=%x FA=%d SPD=%x SF=%x PR=%x LST=%x\n",
1032 container_of(ptd, struct isp1362_ep, ptd),
1033 PTD_GET_CC(ptd), PTD_GET_EP(ptd), PTD_GET_DIR(ptd),
1034 PTD_GET_COUNT(ptd), PTD_GET_LEN(ptd), PTD_GET_MPS(ptd),
1035 PTD_GET_TOGGLE(ptd), PTD_GET_ACTIVE(ptd), PTD_GET_FA(ptd),
1036 PTD_GET_SPD(ptd), PTD_GET_SF_INT(ptd), PTD_GET_PR(ptd), PTD_GET_LAST(ptd));
1037 DBG(0, " %04x %04x %04x %04x\n", ptd->count, ptd->mps, ptd->len, ptd->faddr);
1038}
1039
1040static void dump_ptd_out_data(struct ptd *ptd, u8 *buf)
1041{
1042 if (dbg_level > 0) {
1043 if (PTD_GET_DIR(ptd) != PTD_DIR_IN && PTD_GET_LEN(ptd)) {
1044 DBG(0, "--out->\n");
1045 dump_data(buf, PTD_GET_LEN(ptd));
1046 }
1047 }
1048}
1049
1050static void dump_ptd_in_data(struct ptd *ptd, u8 *buf)
1051{
1052 if (dbg_level > 0) {
1053 if (PTD_GET_DIR(ptd) == PTD_DIR_IN && PTD_GET_COUNT(ptd)) {
1054 DBG(0, "<--in--\n");
1055 dump_data(buf, PTD_GET_COUNT(ptd));
1056 }
1057 DBG(0, "-----\n");
1058 }
1059}
1060
1061static void dump_ptd_queue(struct isp1362_ep_queue *epq)
1062{
1063 struct isp1362_ep *ep;
1064 int dbg = dbg_level;
1065
1066 dbg_level = 1;
1067 list_for_each_entry(ep, &epq->active, active) {
1068 dump_ptd(&ep->ptd);
1069 dump_data(ep->data, ep->length);
1070 }
1071 dbg_level = dbg;
1072}
1073#else
1074#define dump_ptd(ptd) do {} while (0)
1075#define dump_ptd_in_data(ptd, buf) do {} while (0)
1076#define dump_ptd_out_data(ptd, buf) do {} while (0)
1077#define dump_ptd_data(ptd, buf) do {} while (0)
1078#define dump_ptd_queue(epq) do {} while (0)
1079#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-06 15:29:42 -0500