USB: EHCI: Support controllers with big endian capability regs

The two first HC capability registers (CAPLENGTH and HCIVERSION)
are defined as one 8-bit and one 16-bit register. Most HC
implementations have selected to treat these registers as part
of a 32-bit register, giving the same layout for both big and
small endian systems.

This patch adds a new quirk, big_endian_capbase, to support
controllers with big endian register interfaces that treat
HCIVERSION and CAPLENGTH as individual registers.

Signed-off-by: Jan Andersson <jan@gaisler.com>
Acked-by: Alan Stern <stern@rowland.harvard.edu>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>

1 files changed, 1 insertions, 1 deletions

diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c
index 83b7d5f02a15..8164ffafd10a 100644
--- a/drivers/usb/host/ehci-hcd.c
+++ b/drivers/usb/host/ehci-hcd.c
@@ -739,7 +739,7 @@ static int ehci_run (struct usb_hcd *hcd)
         up_write(&ehci_cf_port_reset_rwsem);
         ehci->last_periodic_enable = ktime_get_real();
 
-        temp = HC_VERSION(ehci_readl(ehci, &ehci->caps->hc_capbase));
+        temp = HC_VERSION(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase));
         ehci_info (ehci,
                 "USB %x.%x started, EHCI %x.%02x%s\n",
                 ((ehci->sbrn & 0xf0)>>4), (ehci->sbrn & 0x0f),