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authorVladimir Barinov <vbarinov@ru.mvista.com>2007-05-23 12:07:48 -0400
committerGreg Kroah-Hartman <gregkh@suse.de>2007-07-12 19:34:29 -0400
commitd23a13779f14808b54181d31222e6c44532abd80 (patch)
tree1520b79dc32638884162aa5933f9adefb01f5fd8 /drivers/usb/host/ehci-hcd.c
parent5fea2a4dabdfa1ad59845c42ea770ee8cb41ecad (diff)
USB: EHCI: Safe endianness for transfer buffers after reset in case of HUB with TT
This patch fixes the endianness select for transfer buffers in EHCI controllers that have Transaction Translator built in the hub. Also I cleaned it up to make rid of magic numbers. Signed-off-by: Vladimir Barinov <vbarinov@ru.mvista.com> Cc: <david-b@pacbell.net> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'drivers/usb/host/ehci-hcd.c')
-rw-r--r--drivers/usb/host/ehci-hcd.c10
1 files changed, 8 insertions, 2 deletions
diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c
index 889c2027e7f7..a205a53c61ff 100644
--- a/drivers/usb/host/ehci-hcd.c
+++ b/drivers/usb/host/ehci-hcd.c
@@ -201,9 +201,15 @@ static void tdi_reset (struct ehci_hcd *ehci)
201 u32 __iomem *reg_ptr; 201 u32 __iomem *reg_ptr;
202 u32 tmp; 202 u32 tmp;
203 203
204 reg_ptr = (u32 __iomem *)(((u8 __iomem *)ehci->regs) + 0x68); 204 reg_ptr = (u32 __iomem *)(((u8 __iomem *)ehci->regs) + USBMODE);
205 tmp = ehci_readl(ehci, reg_ptr); 205 tmp = ehci_readl(ehci, reg_ptr);
206 tmp |= 0x3; 206 tmp |= USBMODE_CM_HC;
207 /* The default byte access to MMR space is LE after
208 * controller reset. Set the required endian mode
209 * for transfer buffers to match the host microprocessor
210 */
211 if (ehci_big_endian_mmio(ehci))
212 tmp |= USBMODE_BE;
207 ehci_writel(ehci, tmp, reg_ptr); 213 ehci_writel(ehci, tmp, reg_ptr);
208} 214}
209 215