USB: Implement support for EHCI with big endian MMIO

This patch implements supports for EHCI controllers whose MMIO
registers are big endian and enables that functionality for
the Toshiba SCC chip. It does _not_ add support for big endian
in-memory data structures as this is not needed for that chip
and I hope it will never be.

The guts of the patch are to convert readl(...) to
ehci_readl(ehci, ...) and similarly for register writes.

Signed-off-by: Kou Ishizaki <kou.ishizaki@toshiba.co.jp>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Acked-by: Geoff Levand <geoffrey.levand@am.sony.com>
Acked-by: David Brownell <dbrownell@users.sourceforge.net>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>

1 files changed, 4 insertions, 4 deletions

diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
index 1a915e982c1c..a52480505f78 100644
--- a/drivers/usb/host/ehci-fsl.c
+++ b/drivers/usb/host/ehci-fsl.c
@@ -177,7 +177,7 @@ static void mpc83xx_setup_phy(struct ehci_hcd *ehci,
         case FSL_USB2_PHY_NONE:
                 break;
         }
-        writel(portsc, &ehci->regs->port_status[port_offset]);
+        ehci_writel(ehci, portsc, &ehci->regs->port_status[port_offset]);
 }
 
 static void mpc83xx_usb_setup(struct usb_hcd *hcd)
@@ -214,7 +214,7 @@ static void mpc83xx_usb_setup(struct usb_hcd *hcd)
         }
 
         /* put controller in host mode. */
-        writel(0x00000003, non_ehci + FSL_SOC_USB_USBMODE);
+        ehci_writel(ehci, 0x00000003, non_ehci + FSL_SOC_USB_USBMODE);
         out_be32(non_ehci + FSL_SOC_USB_PRICTRL, 0x0000000c);
         out_be32(non_ehci + FSL_SOC_USB_AGECNTTHRSH, 0x00000040);
         out_be32(non_ehci + FSL_SOC_USB_SICTRL, 0x00000001);
@@ -238,12 +238,12 @@ static int ehci_fsl_setup(struct usb_hcd *hcd)
         /* EHCI registers start at offset 0x100 */
         ehci->caps = hcd->regs + 0x100;
         ehci->regs = hcd->regs + 0x100 +
-            HC_LENGTH(readl(&ehci->caps->hc_capbase));
+            HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase));
         dbg_hcs_params(ehci, "reset");
         dbg_hcc_params(ehci, "reset");
 
         /* cache this readonly data; minimize chip reads */
-        ehci->hcs_params = readl(&ehci->caps->hcs_params);
+        ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params);
 
         retval = ehci_halt(ehci);
         if (retval)