USB: cns3xxx: Add EHCI and OHCI bus glue for cns3xxx SOCs

The CNS3XXX SOC has include USB EHCI and OHCI compatible controllers.
This patch adds the necessary glue logic to allow ehci-hcd and ohci-hcd
drivers to work on CNS3XXX

The EHCI and OHCI controllers share a common clock control and reset
bit, therefore additional check for the timming of enabling and disabling
is required. The USB bit of PLL Power Down Control is also shared by OTG,
24MHzUART clock, Crypto clock, PCIe reference clock, and Clock Scale
Generator. Therefore we only ensure it is enabled, while not disabling it.

Signed-off-by: Mac Lin <mkl0301@gmail.com>
Acked-by: Alan Stern <stern@rowland.harvard.edu>
Acked-by: Greg Kroah-Hartman <gregkh@suse.de>
Signed-off-by: Anton Vorontsov <cbouatmailru@gmail.com>

1 files changed, 15 insertions, 0 deletions

diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index 6f4f8e6a40c7..f8970d151d2a 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -147,6 +147,14 @@ config USB_W90X900_EHCI
         ---help---
                 Enables support for the W90X900 USB controller
 
+config USB_CNS3XXX_EHCI
+        bool "Cavium CNS3XXX EHCI Module"
+        depends on USB_EHCI_HCD && ARCH_CNS3XXX
+        ---help---
+          Enable support for the CNS3XXX SOC's on-chip EHCI controller.
+          It is needed for high-speed (480Mbit/sec) USB 2.0 device
+          support.
+
 config USB_OXU210HP_HCD
         tristate "OXU210HP HCD support"
         depends on USB
@@ -286,6 +294,13 @@ config USB_OHCI_HCD_SSB
 
           If unsure, say N.
 
+config USB_CNS3XXX_OHCI
+        bool "Cavium CNS3XXX OHCI Module"
+        depends on USB_OHCI_HCD && ARCH_CNS3XXX
+        ---help---
+          Enable support for the CNS3XXX SOC's on-chip OHCI controller.
+          It is needed for low-speed USB 1.0 device support.
+
 config USB_OHCI_BIG_ENDIAN_DESC
         bool
         depends on USB_OHCI_HCD