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authorLinus Torvalds <torvalds@linux-foundation.org>2009-06-16 16:06:10 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2009-06-16 16:06:10 -0400
commite1f5b94fd0c93c3e27ede88b7ab652d086dc960f (patch)
treee8de7a132eb88521dd1c19e128eba2d5349bdf4f /drivers/usb/gadget
parent6fd03301d76bc439382710e449f58efbb233df1b (diff)
parent1b6ed69f974f6f32c8be0d9a7fc952822eb83b6f (diff)
Merge git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb-2.6
* git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb-2.6: (143 commits) USB: xhci depends on PCI. USB: xhci: Add Makefile, MAINTAINERS, and Kconfig entries. USB: xhci: Respect critical sections. USB: xHCI: Fix interrupt moderation. USB: xhci: Remove packed attribute from structures. usb; xhci: Fix TRB offset calculations. USB: xhci: replace if-elseif-else with switch-case USB: xhci: Make xhci-mem.c include linux/dmapool.h USB: xhci: drop spinlock in xhci_urb_enqueue() error path. USB: Change names of SuperSpeed ep companion descriptor structs. USB: xhci: Avoid compiler reordering in Link TRB giveback. USB: xhci: Clean up xhci_irq() function. USB: xhci: Avoid global namespace pollution. USB: xhci: Fix Link TRB handoff bit twiddling. USB: xhci: Fix register write order. USB: xhci: fix some compiler warnings in xhci.h USB: xhci: fix lots of compiler warnings. USB: xhci: use xhci_handle_event instead of handle_event USB: xhci: URB cancellation support. USB: xhci: Scatter gather list support for bulk transfers. ...
Diffstat (limited to 'drivers/usb/gadget')
-rw-r--r--drivers/usb/gadget/Kconfig53
-rw-r--r--drivers/usb/gadget/Makefile8
-rw-r--r--drivers/usb/gadget/at91_udc.c4
-rw-r--r--drivers/usb/gadget/atmel_usba_udc.c20
-rw-r--r--drivers/usb/gadget/audio.c302
-rw-r--r--drivers/usb/gadget/ci13xxx_udc.c6
-rw-r--r--drivers/usb/gadget/f_audio.c707
-rw-r--r--drivers/usb/gadget/f_rndis.c4
-rw-r--r--drivers/usb/gadget/file_storage.c93
-rw-r--r--drivers/usb/gadget/fsl_mx3_udc.c95
-rw-r--r--drivers/usb/gadget/fsl_udc_core.c (renamed from drivers/usb/gadget/fsl_usb2_udc.c)69
-rw-r--r--drivers/usb/gadget/fsl_usb2_udc.h18
-rw-r--r--drivers/usb/gadget/gadget_chips.h8
-rw-r--r--drivers/usb/gadget/goku_udc.c6
-rw-r--r--drivers/usb/gadget/imx_udc.c14
-rw-r--r--drivers/usb/gadget/inode.c14
-rw-r--r--drivers/usb/gadget/langwell_udc.c3373
-rw-r--r--drivers/usb/gadget/langwell_udc.h228
-rw-r--r--drivers/usb/gadget/pxa27x_udc.c71
-rw-r--r--drivers/usb/gadget/pxa27x_udc.h2
-rw-r--r--drivers/usb/gadget/s3c-hsotg.c3269
-rw-r--r--drivers/usb/gadget/u_audio.c319
-rw-r--r--drivers/usb/gadget/u_audio.h56
-rw-r--r--drivers/usb/gadget/u_serial.c1
24 files changed, 8617 insertions, 123 deletions
diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig
index 080bb1e4b847..5d1ddf485d1e 100644
--- a/drivers/usb/gadget/Kconfig
+++ b/drivers/usb/gadget/Kconfig
@@ -156,7 +156,7 @@ config USB_ATMEL_USBA
156 156
157config USB_GADGET_FSL_USB2 157config USB_GADGET_FSL_USB2
158 boolean "Freescale Highspeed USB DR Peripheral Controller" 158 boolean "Freescale Highspeed USB DR Peripheral Controller"
159 depends on FSL_SOC 159 depends on FSL_SOC || ARCH_MXC
160 select USB_GADGET_DUALSPEED 160 select USB_GADGET_DUALSPEED
161 help 161 help
162 Some of Freescale PowerPC processors have a High Speed 162 Some of Freescale PowerPC processors have a High Speed
@@ -253,7 +253,7 @@ config USB_PXA25X_SMALL
253 253
254config USB_GADGET_PXA27X 254config USB_GADGET_PXA27X
255 boolean "PXA 27x" 255 boolean "PXA 27x"
256 depends on ARCH_PXA && PXA27x 256 depends on ARCH_PXA && (PXA27x || PXA3xx)
257 select USB_OTG_UTILS 257 select USB_OTG_UTILS
258 help 258 help
259 Intel's PXA 27x series XScale ARM v5TE processors include 259 Intel's PXA 27x series XScale ARM v5TE processors include
@@ -272,6 +272,20 @@ config USB_PXA27X
272 default USB_GADGET 272 default USB_GADGET
273 select USB_GADGET_SELECTED 273 select USB_GADGET_SELECTED
274 274
275config USB_GADGET_S3C_HSOTG
276 boolean "S3C HS/OtG USB Device controller"
277 depends on S3C_DEV_USB_HSOTG
278 select USB_GADGET_S3C_HSOTG_PIO
279 help
280 The Samsung S3C64XX USB2.0 high-speed gadget controller
281 integrated into the S3C64XX series SoC.
282
283config USB_S3C_HSOTG
284 tristate
285 depends on USB_GADGET_S3C_HSOTG
286 default USB_GADGET
287 select USB_GADGET_SELECTED
288
275config USB_GADGET_S3C2410 289config USB_GADGET_S3C2410
276 boolean "S3C2410 USB Device Controller" 290 boolean "S3C2410 USB Device Controller"
277 depends on ARCH_S3C2410 291 depends on ARCH_S3C2410
@@ -460,6 +474,27 @@ config USB_GOKU
460 default USB_GADGET 474 default USB_GADGET
461 select USB_GADGET_SELECTED 475 select USB_GADGET_SELECTED
462 476
477config USB_GADGET_LANGWELL
478 boolean "Intel Langwell USB Device Controller"
479 depends on PCI
480 select USB_GADGET_DUALSPEED
481 help
482 Intel Langwell USB Device Controller is a High-Speed USB
483 On-The-Go device controller.
484
485 The number of programmable endpoints is different through
486 controller revision.
487
488 Say "y" to link the driver statically, or "m" to build a
489 dynamically linked module called "langwell_udc" and force all
490 gadget drivers to also be dynamically linked.
491
492config USB_LANGWELL
493 tristate
494 depends on USB_GADGET_LANGWELL
495 default USB_GADGET
496 select USB_GADGET_SELECTED
497
463 498
464# 499#
465# LAST -- dummy/emulated controller 500# LAST -- dummy/emulated controller
@@ -566,6 +601,20 @@ config USB_ZERO_HNPTEST
566 the "B-Peripheral" role, that device will use HNP to let this 601 the "B-Peripheral" role, that device will use HNP to let this
567 one serve as the USB host instead (in the "B-Host" role). 602 one serve as the USB host instead (in the "B-Host" role).
568 603
604config USB_AUDIO
605 tristate "Audio Gadget (EXPERIMENTAL)"
606 depends on SND
607 help
608 Gadget Audio is compatible with USB Audio Class specification 1.0.
609 It will include at least one AudioControl interface, zero or more
610 AudioStream interface and zero or more MIDIStream interface.
611
612 Gadget Audio will use on-board ALSA (CONFIG_SND) audio card to
613 playback or capture audio stream.
614
615 Say "y" to link the driver statically, or "m" to build a
616 dynamically linked module called "g_audio".
617
569config USB_ETH 618config USB_ETH
570 tristate "Ethernet Gadget (with CDC Ethernet support)" 619 tristate "Ethernet Gadget (with CDC Ethernet support)"
571 depends on NET 620 depends on NET
diff --git a/drivers/usb/gadget/Makefile b/drivers/usb/gadget/Makefile
index 39a51d746cb7..e6017e6bf6da 100644
--- a/drivers/usb/gadget/Makefile
+++ b/drivers/usb/gadget/Makefile
@@ -18,14 +18,21 @@ obj-$(CONFIG_USB_S3C2410) += s3c2410_udc.o
18obj-$(CONFIG_USB_AT91) += at91_udc.o 18obj-$(CONFIG_USB_AT91) += at91_udc.o
19obj-$(CONFIG_USB_ATMEL_USBA) += atmel_usba_udc.o 19obj-$(CONFIG_USB_ATMEL_USBA) += atmel_usba_udc.o
20obj-$(CONFIG_USB_FSL_USB2) += fsl_usb2_udc.o 20obj-$(CONFIG_USB_FSL_USB2) += fsl_usb2_udc.o
21fsl_usb2_udc-objs := fsl_udc_core.o
22ifeq ($(CONFIG_ARCH_MXC),y)
23fsl_usb2_udc-objs += fsl_mx3_udc.o
24endif
21obj-$(CONFIG_USB_M66592) += m66592-udc.o 25obj-$(CONFIG_USB_M66592) += m66592-udc.o
22obj-$(CONFIG_USB_FSL_QE) += fsl_qe_udc.o 26obj-$(CONFIG_USB_FSL_QE) += fsl_qe_udc.o
23obj-$(CONFIG_USB_CI13XXX) += ci13xxx_udc.o 27obj-$(CONFIG_USB_CI13XXX) += ci13xxx_udc.o
28obj-$(CONFIG_USB_S3C_HSOTG) += s3c-hsotg.o
29obj-$(CONFIG_USB_LANGWELL) += langwell_udc.o
24 30
25# 31#
26# USB gadget drivers 32# USB gadget drivers
27# 33#
28g_zero-objs := zero.o 34g_zero-objs := zero.o
35g_audio-objs := audio.o
29g_ether-objs := ether.o 36g_ether-objs := ether.o
30g_serial-objs := serial.o 37g_serial-objs := serial.o
31g_midi-objs := gmidi.o 38g_midi-objs := gmidi.o
@@ -35,6 +42,7 @@ g_printer-objs := printer.o
35g_cdc-objs := cdc2.o 42g_cdc-objs := cdc2.o
36 43
37obj-$(CONFIG_USB_ZERO) += g_zero.o 44obj-$(CONFIG_USB_ZERO) += g_zero.o
45obj-$(CONFIG_USB_AUDIO) += g_audio.o
38obj-$(CONFIG_USB_ETH) += g_ether.o 46obj-$(CONFIG_USB_ETH) += g_ether.o
39obj-$(CONFIG_USB_GADGETFS) += gadgetfs.o 47obj-$(CONFIG_USB_GADGETFS) += gadgetfs.o
40obj-$(CONFIG_USB_FILE_STORAGE) += g_file_storage.o 48obj-$(CONFIG_USB_FILE_STORAGE) += g_file_storage.o
diff --git a/drivers/usb/gadget/at91_udc.c b/drivers/usb/gadget/at91_udc.c
index 53bcdd2f8282..72bae8f39d81 100644
--- a/drivers/usb/gadget/at91_udc.c
+++ b/drivers/usb/gadget/at91_udc.c
@@ -485,7 +485,7 @@ static int at91_ep_enable(struct usb_ep *_ep,
485 return -ESHUTDOWN; 485 return -ESHUTDOWN;
486 } 486 }
487 487
488 tmp = desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK; 488 tmp = usb_endpoint_type(desc);
489 switch (tmp) { 489 switch (tmp) {
490 case USB_ENDPOINT_XFER_CONTROL: 490 case USB_ENDPOINT_XFER_CONTROL:
491 DBG("only one control endpoint\n"); 491 DBG("only one control endpoint\n");
@@ -517,7 +517,7 @@ ok:
517 local_irq_save(flags); 517 local_irq_save(flags);
518 518
519 /* initialize endpoint to match this descriptor */ 519 /* initialize endpoint to match this descriptor */
520 ep->is_in = (desc->bEndpointAddress & USB_DIR_IN) != 0; 520 ep->is_in = usb_endpoint_dir_in(desc);
521 ep->is_iso = (tmp == USB_ENDPOINT_XFER_ISOC); 521 ep->is_iso = (tmp == USB_ENDPOINT_XFER_ISOC);
522 ep->stopped = 0; 522 ep->stopped = 0;
523 if (ep->is_in) 523 if (ep->is_in)
diff --git a/drivers/usb/gadget/atmel_usba_udc.c b/drivers/usb/gadget/atmel_usba_udc.c
index 05c913cc3658..4e970cf0e29a 100644
--- a/drivers/usb/gadget/atmel_usba_udc.c
+++ b/drivers/usb/gadget/atmel_usba_udc.c
@@ -326,13 +326,7 @@ static int vbus_is_present(struct usba_udc *udc)
326 return 1; 326 return 1;
327} 327}
328 328
329#if defined(CONFIG_AVR32) 329#if defined(CONFIG_ARCH_AT91SAM9RL)
330
331static void toggle_bias(int is_on)
332{
333}
334
335#elif defined(CONFIG_ARCH_AT91)
336 330
337#include <mach/at91_pmc.h> 331#include <mach/at91_pmc.h>
338 332
@@ -346,7 +340,13 @@ static void toggle_bias(int is_on)
346 at91_sys_write(AT91_CKGR_UCKR, uckr & ~(AT91_PMC_BIASEN)); 340 at91_sys_write(AT91_CKGR_UCKR, uckr & ~(AT91_PMC_BIASEN));
347} 341}
348 342
349#endif /* CONFIG_ARCH_AT91 */ 343#else
344
345static void toggle_bias(int is_on)
346{
347}
348
349#endif /* CONFIG_ARCH_AT91SAM9RL */
350 350
351static void next_fifo_transaction(struct usba_ep *ep, struct usba_request *req) 351static void next_fifo_transaction(struct usba_ep *ep, struct usba_request *req)
352{ 352{
@@ -550,12 +550,12 @@ usba_ep_enable(struct usb_ep *_ep, const struct usb_endpoint_descriptor *desc)
550 DBG(DBG_HW, "%s: EPT_SIZE = %lu (maxpacket = %lu)\n", 550 DBG(DBG_HW, "%s: EPT_SIZE = %lu (maxpacket = %lu)\n",
551 ep->ep.name, ept_cfg, maxpacket); 551 ep->ep.name, ept_cfg, maxpacket);
552 552
553 if ((desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN) { 553 if (usb_endpoint_dir_in(desc)) {
554 ep->is_in = 1; 554 ep->is_in = 1;
555 ept_cfg |= USBA_EPT_DIR_IN; 555 ept_cfg |= USBA_EPT_DIR_IN;
556 } 556 }
557 557
558 switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) { 558 switch (usb_endpoint_type(desc)) {
559 case USB_ENDPOINT_XFER_CONTROL: 559 case USB_ENDPOINT_XFER_CONTROL:
560 ept_cfg |= USBA_BF(EPT_TYPE, USBA_EPT_TYPE_CONTROL); 560 ept_cfg |= USBA_BF(EPT_TYPE, USBA_EPT_TYPE_CONTROL);
561 ept_cfg |= USBA_BF(BK_NUMBER, USBA_BK_NUMBER_ONE); 561 ept_cfg |= USBA_BF(BK_NUMBER, USBA_BK_NUMBER_ONE);
diff --git a/drivers/usb/gadget/audio.c b/drivers/usb/gadget/audio.c
new file mode 100644
index 000000000000..94de7e864614
--- /dev/null
+++ b/drivers/usb/gadget/audio.c
@@ -0,0 +1,302 @@
1/*
2 * audio.c -- Audio gadget driver
3 *
4 * Copyright (C) 2008 Bryan Wu <cooloney@kernel.org>
5 * Copyright (C) 2008 Analog Devices, Inc
6 *
7 * Enter bugs at http://blackfin.uclinux.org/
8 *
9 * Licensed under the GPL-2 or later.
10 */
11
12/* #define VERBOSE_DEBUG */
13
14#include <linux/kernel.h>
15#include <linux/utsname.h>
16
17#include "u_audio.h"
18
19#define DRIVER_DESC "Linux USB Audio Gadget"
20#define DRIVER_VERSION "Dec 18, 2008"
21
22/*-------------------------------------------------------------------------*/
23
24/*
25 * Kbuild is not very cooperative with respect to linking separately
26 * compiled library objects into one module. So for now we won't use
27 * separate compilation ... ensuring init/exit sections work to shrink
28 * the runtime footprint, and giving us at least some parts of what
29 * a "gcc --combine ... part1.c part2.c part3.c ... " build would.
30 */
31#include "composite.c"
32#include "usbstring.c"
33#include "config.c"
34#include "epautoconf.c"
35
36#include "u_audio.c"
37#include "f_audio.c"
38
39/*-------------------------------------------------------------------------*/
40
41/* DO NOT REUSE THESE IDs with a protocol-incompatible driver!! Ever!!
42 * Instead: allocate your own, using normal USB-IF procedures.
43 */
44
45/* Thanks to NetChip Technologies for donating this product ID. */
46#define AUDIO_VENDOR_NUM 0x0525 /* NetChip */
47#define AUDIO_PRODUCT_NUM 0xa4a1 /* Linux-USB Audio Gadget */
48
49/*-------------------------------------------------------------------------*/
50
51static struct usb_device_descriptor device_desc = {
52 .bLength = sizeof device_desc,
53 .bDescriptorType = USB_DT_DEVICE,
54
55 .bcdUSB = __constant_cpu_to_le16(0x200),
56
57 .bDeviceClass = USB_CLASS_PER_INTERFACE,
58 .bDeviceSubClass = 0,
59 .bDeviceProtocol = 0,
60 /* .bMaxPacketSize0 = f(hardware) */
61
62 /* Vendor and product id defaults change according to what configs
63 * we support. (As does bNumConfigurations.) These values can
64 * also be overridden by module parameters.
65 */
66 .idVendor = __constant_cpu_to_le16(AUDIO_VENDOR_NUM),
67 .idProduct = __constant_cpu_to_le16(AUDIO_PRODUCT_NUM),
68 /* .bcdDevice = f(hardware) */
69 /* .iManufacturer = DYNAMIC */
70 /* .iProduct = DYNAMIC */
71 /* NO SERIAL NUMBER */
72 .bNumConfigurations = 1,
73};
74
75static struct usb_otg_descriptor otg_descriptor = {
76 .bLength = sizeof otg_descriptor,
77 .bDescriptorType = USB_DT_OTG,
78
79 /* REVISIT SRP-only hardware is possible, although
80 * it would not be called "OTG" ...
81 */
82 .bmAttributes = USB_OTG_SRP | USB_OTG_HNP,
83};
84
85static const struct usb_descriptor_header *otg_desc[] = {
86 (struct usb_descriptor_header *) &otg_descriptor,
87 NULL,
88};
89
90/*-------------------------------------------------------------------------*/
91
92/**
93 * Handle USB audio endpoint set/get command in setup class request
94 */
95
96static int audio_set_endpoint_req(struct usb_configuration *c,
97 const struct usb_ctrlrequest *ctrl)
98{
99 struct usb_composite_dev *cdev = c->cdev;
100 int value = -EOPNOTSUPP;
101 u16 ep = le16_to_cpu(ctrl->wIndex);
102 u16 len = le16_to_cpu(ctrl->wLength);
103 u16 w_value = le16_to_cpu(ctrl->wValue);
104
105 DBG(cdev, "bRequest 0x%x, w_value 0x%04x, len %d, endpoint %d\n",
106 ctrl->bRequest, w_value, len, ep);
107
108 switch (ctrl->bRequest) {
109 case SET_CUR:
110 value = 0;
111 break;
112
113 case SET_MIN:
114 break;
115
116 case SET_MAX:
117 break;
118
119 case SET_RES:
120 break;
121
122 case SET_MEM:
123 break;
124
125 default:
126 break;
127 }
128
129 return value;
130}
131
132static int audio_get_endpoint_req(struct usb_configuration *c,
133 const struct usb_ctrlrequest *ctrl)
134{
135 struct usb_composite_dev *cdev = c->cdev;
136 int value = -EOPNOTSUPP;
137 u8 ep = ((le16_to_cpu(ctrl->wIndex) >> 8) & 0xFF);
138 u16 len = le16_to_cpu(ctrl->wLength);
139 u16 w_value = le16_to_cpu(ctrl->wValue);
140
141 DBG(cdev, "bRequest 0x%x, w_value 0x%04x, len %d, endpoint %d\n",
142 ctrl->bRequest, w_value, len, ep);
143
144 switch (ctrl->bRequest) {
145 case GET_CUR:
146 case GET_MIN:
147 case GET_MAX:
148 case GET_RES:
149 value = 3;
150 break;
151 case GET_MEM:
152 break;
153 default:
154 break;
155 }
156
157 return value;
158}
159
160static int
161audio_setup(struct usb_configuration *c, const struct usb_ctrlrequest *ctrl)
162{
163 struct usb_composite_dev *cdev = c->cdev;
164 struct usb_request *req = cdev->req;
165 int value = -EOPNOTSUPP;
166 u16 w_index = le16_to_cpu(ctrl->wIndex);
167 u16 w_value = le16_to_cpu(ctrl->wValue);
168 u16 w_length = le16_to_cpu(ctrl->wLength);
169
170 /* composite driver infrastructure handles everything except
171 * Audio class messages; interface activation uses set_alt().
172 */
173 switch (ctrl->bRequestType) {
174 case USB_AUDIO_SET_ENDPOINT:
175 value = audio_set_endpoint_req(c, ctrl);
176 break;
177
178 case USB_AUDIO_GET_ENDPOINT:
179 value = audio_get_endpoint_req(c, ctrl);
180 break;
181
182 default:
183 ERROR(cdev, "Invalid control req%02x.%02x v%04x i%04x l%d\n",
184 ctrl->bRequestType, ctrl->bRequest,
185 w_value, w_index, w_length);
186 }
187
188 /* respond with data transfer or status phase? */
189 if (value >= 0) {
190 DBG(cdev, "Audio req%02x.%02x v%04x i%04x l%d\n",
191 ctrl->bRequestType, ctrl->bRequest,
192 w_value, w_index, w_length);
193 req->zero = 0;
194 req->length = value;
195 value = usb_ep_queue(cdev->gadget->ep0, req, GFP_ATOMIC);
196 if (value < 0)
197 ERROR(cdev, "Audio response on err %d\n", value);
198 }
199
200 /* device either stalls (value < 0) or reports success */
201 return value;
202}
203
204/*-------------------------------------------------------------------------*/
205
206static int __init audio_do_config(struct usb_configuration *c)
207{
208 /* FIXME alloc iConfiguration string, set it in c->strings */
209
210 if (gadget_is_otg(c->cdev->gadget)) {
211 c->descriptors = otg_desc;
212 c->bmAttributes |= USB_CONFIG_ATT_WAKEUP;
213 }
214
215 audio_bind_config(c);
216
217 return 0;
218}
219
220static struct usb_configuration audio_config_driver = {
221 .label = DRIVER_DESC,
222 .bind = audio_do_config,
223 .setup = audio_setup,
224 .bConfigurationValue = 1,
225 /* .iConfiguration = DYNAMIC */
226 .bmAttributes = USB_CONFIG_ATT_SELFPOWER,
227};
228
229/*-------------------------------------------------------------------------*/
230
231static int __init audio_bind(struct usb_composite_dev *cdev)
232{
233 int gcnum;
234 int status;
235
236 gcnum = usb_gadget_controller_number(cdev->gadget);
237 if (gcnum >= 0)
238 device_desc.bcdDevice = cpu_to_le16(0x0300 | gcnum);
239 else {
240 ERROR(cdev, "controller '%s' not recognized; trying %s\n",
241 cdev->gadget->name,
242 audio_config_driver.label);
243 device_desc.bcdDevice =
244 __constant_cpu_to_le16(0x0300 | 0x0099);
245 }
246
247 /* device descriptor strings: manufacturer, product */
248 snprintf(manufacturer, sizeof manufacturer, "%s %s with %s",
249 init_utsname()->sysname, init_utsname()->release,
250 cdev->gadget->name);
251 status = usb_string_id(cdev);
252 if (status < 0)
253 goto fail;
254 strings_dev[STRING_MANUFACTURER_IDX].id = status;
255 device_desc.iManufacturer = status;
256
257 status = usb_string_id(cdev);
258 if (status < 0)
259 goto fail;
260 strings_dev[STRING_PRODUCT_IDX].id = status;
261 device_desc.iProduct = status;
262
263 status = usb_add_config(cdev, &audio_config_driver);
264 if (status < 0)
265 goto fail;
266
267 INFO(cdev, "%s, version: %s\n", DRIVER_DESC, DRIVER_VERSION);
268 return 0;
269
270fail:
271 return status;
272}
273
274static int __exit audio_unbind(struct usb_composite_dev *cdev)
275{
276 return 0;
277}
278
279static struct usb_composite_driver audio_driver = {
280 .name = "g_audio",
281 .dev = &device_desc,
282 .strings = audio_strings,
283 .bind = audio_bind,
284 .unbind = __exit_p(audio_unbind),
285};
286
287static int __init init(void)
288{
289 return usb_composite_register(&audio_driver);
290}
291module_init(init);
292
293static void __exit cleanup(void)
294{
295 usb_composite_unregister(&audio_driver);
296}
297module_exit(cleanup);
298
299MODULE_DESCRIPTION(DRIVER_DESC);
300MODULE_AUTHOR("Bryan Wu <cooloney@kernel.org>");
301MODULE_LICENSE("GPL");
302
diff --git a/drivers/usb/gadget/ci13xxx_udc.c b/drivers/usb/gadget/ci13xxx_udc.c
index 38e531ecae4d..c7cb87a6fee2 100644
--- a/drivers/usb/gadget/ci13xxx_udc.c
+++ b/drivers/usb/gadget/ci13xxx_udc.c
@@ -1977,9 +1977,9 @@ static int ep_enable(struct usb_ep *ep,
1977 if (!list_empty(&mEp->qh[mEp->dir].queue)) 1977 if (!list_empty(&mEp->qh[mEp->dir].queue))
1978 warn("enabling a non-empty endpoint!"); 1978 warn("enabling a non-empty endpoint!");
1979 1979
1980 mEp->dir = (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK) ? TX : RX; 1980 mEp->dir = usb_endpoint_dir_in(desc) ? TX : RX;
1981 mEp->num = desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK; 1981 mEp->num = usb_endpoint_num(desc);
1982 mEp->type = desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK; 1982 mEp->type = usb_endpoint_type(desc);
1983 1983
1984 mEp->ep.maxpacket = __constant_le16_to_cpu(desc->wMaxPacketSize); 1984 mEp->ep.maxpacket = __constant_le16_to_cpu(desc->wMaxPacketSize);
1985 1985
diff --git a/drivers/usb/gadget/f_audio.c b/drivers/usb/gadget/f_audio.c
new file mode 100644
index 000000000000..66527ba2d2ea
--- /dev/null
+++ b/drivers/usb/gadget/f_audio.c
@@ -0,0 +1,707 @@
1/*
2 * f_audio.c -- USB Audio class function driver
3 *
4 * Copyright (C) 2008 Bryan Wu <cooloney@kernel.org>
5 * Copyright (C) 2008 Analog Devices, Inc
6 *
7 * Enter bugs at http://blackfin.uclinux.org/
8 *
9 * Licensed under the GPL-2 or later.
10 */
11
12#include <linux/kernel.h>
13#include <linux/device.h>
14#include <asm/atomic.h>
15
16#include "u_audio.h"
17
18#define OUT_EP_MAX_PACKET_SIZE 200
19static int req_buf_size = OUT_EP_MAX_PACKET_SIZE;
20module_param(req_buf_size, int, S_IRUGO);
21MODULE_PARM_DESC(req_buf_size, "ISO OUT endpoint request buffer size");
22
23static int req_count = 256;
24module_param(req_count, int, S_IRUGO);
25MODULE_PARM_DESC(req_count, "ISO OUT endpoint request count");
26
27static int audio_buf_size = 48000;
28module_param(audio_buf_size, int, S_IRUGO);
29MODULE_PARM_DESC(audio_buf_size, "Audio buffer size");
30
31/*
32 * DESCRIPTORS ... most are static, but strings and full
33 * configuration descriptors are built on demand.
34 */
35
36/*
37 * We have two interfaces- AudioControl and AudioStreaming
38 * TODO: only supcard playback currently
39 */
40#define F_AUDIO_AC_INTERFACE 0
41#define F_AUDIO_AS_INTERFACE 1
42#define F_AUDIO_NUM_INTERFACES 2
43
44/* B.3.1 Standard AC Interface Descriptor */
45static struct usb_interface_descriptor ac_interface_desc __initdata = {
46 .bLength = USB_DT_INTERFACE_SIZE,
47 .bDescriptorType = USB_DT_INTERFACE,
48 .bNumEndpoints = 0,
49 .bInterfaceClass = USB_CLASS_AUDIO,
50 .bInterfaceSubClass = USB_SUBCLASS_AUDIOCONTROL,
51};
52
53DECLARE_USB_AC_HEADER_DESCRIPTOR(2);
54
55#define USB_DT_AC_HEADER_LENGH USB_DT_AC_HEADER_SIZE(F_AUDIO_NUM_INTERFACES)
56/* B.3.2 Class-Specific AC Interface Descriptor */
57static struct usb_ac_header_descriptor_2 ac_header_desc = {
58 .bLength = USB_DT_AC_HEADER_LENGH,
59 .bDescriptorType = USB_DT_CS_INTERFACE,
60 .bDescriptorSubtype = HEADER,
61 .bcdADC = __constant_cpu_to_le16(0x0100),
62 .wTotalLength = __constant_cpu_to_le16(USB_DT_AC_HEADER_LENGH),
63 .bInCollection = F_AUDIO_NUM_INTERFACES,
64 .baInterfaceNr = {
65 [0] = F_AUDIO_AC_INTERFACE,
66 [1] = F_AUDIO_AS_INTERFACE,
67 }
68};
69
70#define INPUT_TERMINAL_ID 1
71static struct usb_input_terminal_descriptor input_terminal_desc = {
72 .bLength = USB_DT_AC_INPUT_TERMINAL_SIZE,
73 .bDescriptorType = USB_DT_CS_INTERFACE,
74 .bDescriptorSubtype = INPUT_TERMINAL,
75 .bTerminalID = INPUT_TERMINAL_ID,
76 .wTerminalType = USB_AC_TERMINAL_STREAMING,
77 .bAssocTerminal = 0,
78 .wChannelConfig = 0x3,
79};
80
81DECLARE_USB_AC_FEATURE_UNIT_DESCRIPTOR(0);
82
83#define FEATURE_UNIT_ID 2
84static struct usb_ac_feature_unit_descriptor_0 feature_unit_desc = {
85 .bLength = USB_DT_AC_FEATURE_UNIT_SIZE(0),
86 .bDescriptorType = USB_DT_CS_INTERFACE,
87 .bDescriptorSubtype = FEATURE_UNIT,
88 .bUnitID = FEATURE_UNIT_ID,
89 .bSourceID = INPUT_TERMINAL_ID,
90 .bControlSize = 2,
91 .bmaControls[0] = (FU_MUTE | FU_VOLUME),
92};
93
94static struct usb_audio_control mute_control = {
95 .list = LIST_HEAD_INIT(mute_control.list),
96 .name = "Mute Control",
97 .type = MUTE_CONTROL,
98 /* Todo: add real Mute control code */
99 .set = generic_set_cmd,
100 .get = generic_get_cmd,
101};
102
103static struct usb_audio_control volume_control = {
104 .list = LIST_HEAD_INIT(volume_control.list),
105 .name = "Volume Control",
106 .type = VOLUME_CONTROL,
107 /* Todo: add real Volume control code */
108 .set = generic_set_cmd,
109 .get = generic_get_cmd,
110};
111
112static struct usb_audio_control_selector feature_unit = {
113 .list = LIST_HEAD_INIT(feature_unit.list),
114 .id = FEATURE_UNIT_ID,
115 .name = "Mute & Volume Control",
116 .type = FEATURE_UNIT,
117 .desc = (struct usb_descriptor_header *)&feature_unit_desc,
118};
119
120#define OUTPUT_TERMINAL_ID 3
121static struct usb_output_terminal_descriptor output_terminal_desc = {
122 .bLength = USB_DT_AC_OUTPUT_TERMINAL_SIZE,
123 .bDescriptorType = USB_DT_CS_INTERFACE,
124 .bDescriptorSubtype = OUTPUT_TERMINAL,
125 .bTerminalID = OUTPUT_TERMINAL_ID,
126 .wTerminalType = USB_AC_OUTPUT_TERMINAL_SPEAKER,
127 .bAssocTerminal = FEATURE_UNIT_ID,
128 .bSourceID = FEATURE_UNIT_ID,
129};
130
131/* B.4.1 Standard AS Interface Descriptor */
132static struct usb_interface_descriptor as_interface_alt_0_desc = {
133 .bLength = USB_DT_INTERFACE_SIZE,
134 .bDescriptorType = USB_DT_INTERFACE,
135 .bAlternateSetting = 0,
136 .bNumEndpoints = 0,
137 .bInterfaceClass = USB_CLASS_AUDIO,
138 .bInterfaceSubClass = USB_SUBCLASS_AUDIOSTREAMING,
139};
140
141static struct usb_interface_descriptor as_interface_alt_1_desc = {
142 .bLength = USB_DT_INTERFACE_SIZE,
143 .bDescriptorType = USB_DT_INTERFACE,
144 .bAlternateSetting = 1,
145 .bNumEndpoints = 1,
146 .bInterfaceClass = USB_CLASS_AUDIO,
147 .bInterfaceSubClass = USB_SUBCLASS_AUDIOSTREAMING,
148};
149
150/* B.4.2 Class-Specific AS Interface Descriptor */
151static struct usb_as_header_descriptor as_header_desc = {
152 .bLength = USB_DT_AS_HEADER_SIZE,
153 .bDescriptorType = USB_DT_CS_INTERFACE,
154 .bDescriptorSubtype = AS_GENERAL,
155 .bTerminalLink = INPUT_TERMINAL_ID,
156 .bDelay = 1,
157 .wFormatTag = USB_AS_AUDIO_FORMAT_TYPE_I_PCM,
158};
159
160DECLARE_USB_AS_FORMAT_TYPE_I_DISCRETE_DESC(1);
161
162static struct usb_as_formate_type_i_discrete_descriptor_1 as_type_i_desc = {
163 .bLength = USB_AS_FORMAT_TYPE_I_DISCRETE_DESC_SIZE(1),
164 .bDescriptorType = USB_DT_CS_INTERFACE,
165 .bDescriptorSubtype = FORMAT_TYPE,
166 .bFormatType = USB_AS_FORMAT_TYPE_I,
167 .bSubframeSize = 2,
168 .bBitResolution = 16,
169 .bSamFreqType = 1,
170};
171
172/* Standard ISO OUT Endpoint Descriptor */
173static struct usb_endpoint_descriptor as_out_ep_desc __initdata = {
174 .bLength = USB_DT_ENDPOINT_AUDIO_SIZE,
175 .bDescriptorType = USB_DT_ENDPOINT,
176 .bEndpointAddress = USB_DIR_OUT,
177 .bmAttributes = USB_AS_ENDPOINT_ADAPTIVE
178 | USB_ENDPOINT_XFER_ISOC,
179 .wMaxPacketSize = __constant_cpu_to_le16(OUT_EP_MAX_PACKET_SIZE),
180 .bInterval = 4,
181};
182
183/* Class-specific AS ISO OUT Endpoint Descriptor */
184static struct usb_as_iso_endpoint_descriptor as_iso_out_desc __initdata = {
185 .bLength = USB_AS_ISO_ENDPOINT_DESC_SIZE,
186 .bDescriptorType = USB_DT_CS_ENDPOINT,
187 .bDescriptorSubtype = EP_GENERAL,
188 .bmAttributes = 1,
189 .bLockDelayUnits = 1,
190 .wLockDelay = __constant_cpu_to_le16(1),
191};
192
193static struct usb_descriptor_header *f_audio_desc[] __initdata = {
194 (struct usb_descriptor_header *)&ac_interface_desc,
195 (struct usb_descriptor_header *)&ac_header_desc,
196
197 (struct usb_descriptor_header *)&input_terminal_desc,
198 (struct usb_descriptor_header *)&output_terminal_desc,
199 (struct usb_descriptor_header *)&feature_unit_desc,
200
201 (struct usb_descriptor_header *)&as_interface_alt_0_desc,
202 (struct usb_descriptor_header *)&as_interface_alt_1_desc,
203 (struct usb_descriptor_header *)&as_header_desc,
204
205 (struct usb_descriptor_header *)&as_type_i_desc,
206
207 (struct usb_descriptor_header *)&as_out_ep_desc,
208 (struct usb_descriptor_header *)&as_iso_out_desc,
209 NULL,
210};
211
212/* string IDs are assigned dynamically */
213
214#define STRING_MANUFACTURER_IDX 0
215#define STRING_PRODUCT_IDX 1
216
217static char manufacturer[50];
218
219static struct usb_string strings_dev[] = {
220 [STRING_MANUFACTURER_IDX].s = manufacturer,
221 [STRING_PRODUCT_IDX].s = DRIVER_DESC,
222 { } /* end of list */
223};
224
225static struct usb_gadget_strings stringtab_dev = {
226 .language = 0x0409, /* en-us */
227 .strings = strings_dev,
228};
229
230static struct usb_gadget_strings *audio_strings[] = {
231 &stringtab_dev,
232 NULL,
233};
234
235/*
236 * This function is an ALSA sound card following USB Audio Class Spec 1.0.
237 */
238
239/*-------------------------------------------------------------------------*/
240struct f_audio_buf {
241 u8 *buf;
242 int actual;
243 struct list_head list;
244};
245
246static struct f_audio_buf *f_audio_buffer_alloc(int buf_size)
247{
248 struct f_audio_buf *copy_buf;
249
250 copy_buf = kzalloc(sizeof *copy_buf, GFP_ATOMIC);
251 if (!copy_buf)
252 return (struct f_audio_buf *)-ENOMEM;
253
254 copy_buf->buf = kzalloc(buf_size, GFP_ATOMIC);
255 if (!copy_buf->buf) {
256 kfree(copy_buf);
257 return (struct f_audio_buf *)-ENOMEM;
258 }
259
260 return copy_buf;
261}
262
263static void f_audio_buffer_free(struct f_audio_buf *audio_buf)
264{
265 kfree(audio_buf->buf);
266 kfree(audio_buf);
267}
268/*-------------------------------------------------------------------------*/
269
270struct f_audio {
271 struct gaudio card;
272
273 /* endpoints handle full and/or high speeds */
274 struct usb_ep *out_ep;
275 struct usb_endpoint_descriptor *out_desc;
276
277 spinlock_t lock;
278 struct f_audio_buf *copy_buf;
279 struct work_struct playback_work;
280 struct list_head play_queue;
281
282 /* Control Set command */
283 struct list_head cs;
284 u8 set_cmd;
285 struct usb_audio_control *set_con;
286};
287
288static inline struct f_audio *func_to_audio(struct usb_function *f)
289{
290 return container_of(f, struct f_audio, card.func);
291}
292
293/*-------------------------------------------------------------------------*/
294
295static void f_audio_playback_work(struct work_struct *data)
296{
297 struct f_audio *audio = container_of(data, struct f_audio,
298 playback_work);
299 struct f_audio_buf *play_buf;
300
301 spin_lock_irq(&audio->lock);
302 if (list_empty(&audio->play_queue)) {
303 spin_unlock_irq(&audio->lock);
304 return;
305 }
306 play_buf = list_first_entry(&audio->play_queue,
307 struct f_audio_buf, list);
308 list_del(&play_buf->list);
309 spin_unlock_irq(&audio->lock);
310
311 u_audio_playback(&audio->card, play_buf->buf, play_buf->actual);
312 f_audio_buffer_free(play_buf);
313
314 return;
315}
316
317static int f_audio_out_ep_complete(struct usb_ep *ep, struct usb_request *req)
318{
319 struct f_audio *audio = req->context;
320 struct usb_composite_dev *cdev = audio->card.func.config->cdev;
321 struct f_audio_buf *copy_buf = audio->copy_buf;
322 int err;
323
324 if (!copy_buf)
325 return -EINVAL;
326
327 /* Copy buffer is full, add it to the play_queue */
328 if (audio_buf_size - copy_buf->actual < req->actual) {
329 list_add_tail(&copy_buf->list, &audio->play_queue);
330 schedule_work(&audio->playback_work);
331 copy_buf = f_audio_buffer_alloc(audio_buf_size);
332 if (copy_buf < 0)
333 return -ENOMEM;
334 }
335
336 memcpy(copy_buf->buf + copy_buf->actual, req->buf, req->actual);
337 copy_buf->actual += req->actual;
338 audio->copy_buf = copy_buf;
339
340 err = usb_ep_queue(ep, req, GFP_ATOMIC);
341 if (err)
342 ERROR(cdev, "%s queue req: %d\n", ep->name, err);
343
344 return 0;
345
346}
347
348static void f_audio_complete(struct usb_ep *ep, struct usb_request *req)
349{
350 struct f_audio *audio = req->context;
351 int status = req->status;
352 u32 data = 0;
353 struct usb_ep *out_ep = audio->out_ep;
354
355 switch (status) {
356
357 case 0: /* normal completion? */
358 if (ep == out_ep)
359 f_audio_out_ep_complete(ep, req);
360 else if (audio->set_con) {
361 memcpy(&data, req->buf, req->length);
362 audio->set_con->set(audio->set_con, audio->set_cmd,
363 le16_to_cpu(data));
364 audio->set_con = NULL;
365 }
366 break;
367 default:
368 break;
369 }
370}
371
372static int audio_set_intf_req(struct usb_function *f,
373 const struct usb_ctrlrequest *ctrl)
374{
375 struct f_audio *audio = func_to_audio(f);
376 struct usb_composite_dev *cdev = f->config->cdev;
377 struct usb_request *req = cdev->req;
378 u8 id = ((le16_to_cpu(ctrl->wIndex) >> 8) & 0xFF);
379 u16 len = le16_to_cpu(ctrl->wLength);
380 u16 w_value = le16_to_cpu(ctrl->wValue);
381 u8 con_sel = (w_value >> 8) & 0xFF;
382 u8 cmd = (ctrl->bRequest & 0x0F);
383 struct usb_audio_control_selector *cs;
384 struct usb_audio_control *con;
385
386 DBG(cdev, "bRequest 0x%x, w_value 0x%04x, len %d, entity %d\n",
387 ctrl->bRequest, w_value, len, id);
388
389 list_for_each_entry(cs, &audio->cs, list) {
390 if (cs->id == id) {
391 list_for_each_entry(con, &cs->control, list) {
392 if (con->type == con_sel) {
393 audio->set_con = con;
394 break;
395 }
396 }
397 break;
398 }
399 }
400
401 audio->set_cmd = cmd;
402 req->context = audio;
403 req->complete = f_audio_complete;
404
405 return len;
406}
407
408static int audio_get_intf_req(struct usb_function *f,
409 const struct usb_ctrlrequest *ctrl)
410{
411 struct f_audio *audio = func_to_audio(f);
412 struct usb_composite_dev *cdev = f->config->cdev;
413 struct usb_request *req = cdev->req;
414 int value = -EOPNOTSUPP;
415 u8 id = ((le16_to_cpu(ctrl->wIndex) >> 8) & 0xFF);
416 u16 len = le16_to_cpu(ctrl->wLength);
417 u16 w_value = le16_to_cpu(ctrl->wValue);
418 u8 con_sel = (w_value >> 8) & 0xFF;
419 u8 cmd = (ctrl->bRequest & 0x0F);
420 struct usb_audio_control_selector *cs;
421 struct usb_audio_control *con;
422
423 DBG(cdev, "bRequest 0x%x, w_value 0x%04x, len %d, entity %d\n",
424 ctrl->bRequest, w_value, len, id);
425
426 list_for_each_entry(cs, &audio->cs, list) {
427 if (cs->id == id) {
428 list_for_each_entry(con, &cs->control, list) {
429 if (con->type == con_sel && con->get) {
430 value = con->get(con, cmd);
431 break;
432 }
433 }
434 break;
435 }
436 }
437
438 req->context = audio;
439 req->complete = f_audio_complete;
440 memcpy(req->buf, &value, len);
441
442 return len;
443}
444
445static int
446f_audio_setup(struct usb_function *f, const struct usb_ctrlrequest *ctrl)
447{
448 struct usb_composite_dev *cdev = f->config->cdev;
449 struct usb_request *req = cdev->req;
450 int value = -EOPNOTSUPP;
451 u16 w_index = le16_to_cpu(ctrl->wIndex);
452 u16 w_value = le16_to_cpu(ctrl->wValue);
453 u16 w_length = le16_to_cpu(ctrl->wLength);
454
455 /* composite driver infrastructure handles everything except
456 * Audio class messages; interface activation uses set_alt().
457 */
458 switch (ctrl->bRequestType) {
459 case USB_AUDIO_SET_INTF:
460 value = audio_set_intf_req(f, ctrl);
461 break;
462
463 case USB_AUDIO_GET_INTF:
464 value = audio_get_intf_req(f, ctrl);
465 break;
466
467 default:
468 ERROR(cdev, "invalid control req%02x.%02x v%04x i%04x l%d\n",
469 ctrl->bRequestType, ctrl->bRequest,
470 w_value, w_index, w_length);
471 }
472
473 /* respond with data transfer or status phase? */
474 if (value >= 0) {
475 DBG(cdev, "audio req%02x.%02x v%04x i%04x l%d\n",
476 ctrl->bRequestType, ctrl->bRequest,
477 w_value, w_index, w_length);
478 req->zero = 0;
479 req->length = value;
480 value = usb_ep_queue(cdev->gadget->ep0, req, GFP_ATOMIC);
481 if (value < 0)
482 ERROR(cdev, "audio response on err %d\n", value);
483 }
484
485 /* device either stalls (value < 0) or reports success */
486 return value;
487}
488
489static int f_audio_set_alt(struct usb_function *f, unsigned intf, unsigned alt)
490{
491 struct f_audio *audio = func_to_audio(f);
492 struct usb_composite_dev *cdev = f->config->cdev;
493 struct usb_ep *out_ep = audio->out_ep;
494 struct usb_request *req;
495 int i = 0, err = 0;
496
497 DBG(cdev, "intf %d, alt %d\n", intf, alt);
498
499 if (intf == 1) {
500 if (alt == 1) {
501 usb_ep_enable(out_ep, audio->out_desc);
502 out_ep->driver_data = audio;
503 audio->copy_buf = f_audio_buffer_alloc(audio_buf_size);
504
505 /*
506 * allocate a bunch of read buffers
507 * and queue them all at once.
508 */
509 for (i = 0; i < req_count && err == 0; i++) {
510 req = usb_ep_alloc_request(out_ep, GFP_ATOMIC);
511 if (req) {
512 req->buf = kzalloc(req_buf_size,
513 GFP_ATOMIC);
514 if (req->buf) {
515 req->length = req_buf_size;
516 req->context = audio;
517 req->complete =
518 f_audio_complete;
519 err = usb_ep_queue(out_ep,
520 req, GFP_ATOMIC);
521 if (err)
522 ERROR(cdev,
523 "%s queue req: %d\n",
524 out_ep->name, err);
525 } else
526 err = -ENOMEM;
527 } else
528 err = -ENOMEM;
529 }
530
531 } else {
532 struct f_audio_buf *copy_buf = audio->copy_buf;
533 if (copy_buf) {
534 list_add_tail(&copy_buf->list,
535 &audio->play_queue);
536 schedule_work(&audio->playback_work);
537 }
538 }
539 }
540
541 return err;
542}
543
544static void f_audio_disable(struct usb_function *f)
545{
546 return;
547}
548
549/*-------------------------------------------------------------------------*/
550
551static void f_audio_build_desc(struct f_audio *audio)
552{
553 struct gaudio *card = &audio->card;
554 u8 *sam_freq;
555 int rate;
556
557 /* Set channel numbers */
558 input_terminal_desc.bNrChannels = u_audio_get_playback_channels(card);
559 as_type_i_desc.bNrChannels = u_audio_get_playback_channels(card);
560
561 /* Set sample rates */
562 rate = u_audio_get_playback_rate(card);
563 sam_freq = as_type_i_desc.tSamFreq[0];
564 memcpy(sam_freq, &rate, 3);
565
566 /* Todo: Set Sample bits and other parameters */
567
568 return;
569}
570
571/* audio function driver setup/binding */
572static int __init
573f_audio_bind(struct usb_configuration *c, struct usb_function *f)
574{
575 struct usb_composite_dev *cdev = c->cdev;
576 struct f_audio *audio = func_to_audio(f);
577 int status;
578 struct usb_ep *ep;
579
580 f_audio_build_desc(audio);
581
582 /* allocate instance-specific interface IDs, and patch descriptors */
583 status = usb_interface_id(c, f);
584 if (status < 0)
585 goto fail;
586 ac_interface_desc.bInterfaceNumber = status;
587
588 status = usb_interface_id(c, f);
589 if (status < 0)
590 goto fail;
591 as_interface_alt_0_desc.bInterfaceNumber = status;
592 as_interface_alt_1_desc.bInterfaceNumber = status;
593
594 status = -ENODEV;
595
596 /* allocate instance-specific endpoints */
597 ep = usb_ep_autoconfig(cdev->gadget, &as_out_ep_desc);
598 if (!ep)
599 goto fail;
600 audio->out_ep = ep;
601 ep->driver_data = cdev; /* claim */
602
603 status = -ENOMEM;
604
605 /* supcard all relevant hardware speeds... we expect that when
606 * hardware is dual speed, all bulk-capable endpoints work at
607 * both speeds
608 */
609
610 /* copy descriptors, and track endpoint copies */
611 if (gadget_is_dualspeed(c->cdev->gadget)) {
612 c->highspeed = true;
613 f->hs_descriptors = usb_copy_descriptors(f_audio_desc);
614 } else
615 f->descriptors = usb_copy_descriptors(f_audio_desc);
616
617 return 0;
618
619fail:
620
621 return status;
622}
623
624static void
625f_audio_unbind(struct usb_configuration *c, struct usb_function *f)
626{
627 struct f_audio *audio = func_to_audio(f);
628
629 usb_free_descriptors(f->descriptors);
630 kfree(audio);
631}
632
633/*-------------------------------------------------------------------------*/
634
635/* Todo: add more control selecotor dynamically */
636int __init control_selector_init(struct f_audio *audio)
637{
638 INIT_LIST_HEAD(&audio->cs);
639 list_add(&feature_unit.list, &audio->cs);
640
641 INIT_LIST_HEAD(&feature_unit.control);
642 list_add(&mute_control.list, &feature_unit.control);
643 list_add(&volume_control.list, &feature_unit.control);
644
645 volume_control.data[_CUR] = 0xffc0;
646 volume_control.data[_MIN] = 0xe3a0;
647 volume_control.data[_MAX] = 0xfff0;
648 volume_control.data[_RES] = 0x0030;
649
650 return 0;
651}
652
653/**
654 * audio_bind_config - add USB audio fucntion to a configuration
655 * @c: the configuration to supcard the USB audio function
656 * Context: single threaded during gadget setup
657 *
658 * Returns zero on success, else negative errno.
659 */
660int __init audio_bind_config(struct usb_configuration *c)
661{
662 struct f_audio *audio;
663 int status;
664
665 /* allocate and initialize one new instance */
666 audio = kzalloc(sizeof *audio, GFP_KERNEL);
667 if (!audio)
668 return -ENOMEM;
669
670 audio->card.func.name = "g_audio";
671 audio->card.gadget = c->cdev->gadget;
672
673 INIT_LIST_HEAD(&audio->play_queue);
674 spin_lock_init(&audio->lock);
675
676 /* set up ASLA audio devices */
677 status = gaudio_setup(&audio->card);
678 if (status < 0)
679 goto setup_fail;
680
681 audio->card.func.strings = audio_strings;
682 audio->card.func.bind = f_audio_bind;
683 audio->card.func.unbind = f_audio_unbind;
684 audio->card.func.set_alt = f_audio_set_alt;
685 audio->card.func.setup = f_audio_setup;
686 audio->card.func.disable = f_audio_disable;
687 audio->out_desc = &as_out_ep_desc;
688
689 control_selector_init(audio);
690
691 INIT_WORK(&audio->playback_work, f_audio_playback_work);
692
693 status = usb_add_function(c, &audio->card.func);
694 if (status)
695 goto add_fail;
696
697 INFO(c->cdev, "audio_buf_size %d, req_buf_size %d, req_count %d\n",
698 audio_buf_size, req_buf_size, req_count);
699
700 return status;
701
702add_fail:
703 gaudio_cleanup(&audio->card);
704setup_fail:
705 kfree(audio);
706 return status;
707}
diff --git a/drivers/usb/gadget/f_rndis.c b/drivers/usb/gadget/f_rndis.c
index 3279a4726042..424a37c5773f 100644
--- a/drivers/usb/gadget/f_rndis.c
+++ b/drivers/usb/gadget/f_rndis.c
@@ -475,7 +475,9 @@ static int rndis_set_alt(struct usb_function *f, unsigned intf, unsigned alt)
475 if (rndis->port.in_ep->driver_data) { 475 if (rndis->port.in_ep->driver_data) {
476 DBG(cdev, "reset rndis\n"); 476 DBG(cdev, "reset rndis\n");
477 gether_disconnect(&rndis->port); 477 gether_disconnect(&rndis->port);
478 } else { 478 }
479
480 if (!rndis->port.in) {
479 DBG(cdev, "init rndis\n"); 481 DBG(cdev, "init rndis\n");
480 rndis->port.in = ep_choose(cdev->gadget, 482 rndis->port.in = ep_choose(cdev->gadget,
481 rndis->hs.in, rndis->fs.in); 483 rndis->hs.in, rndis->fs.in);
diff --git a/drivers/usb/gadget/file_storage.c b/drivers/usb/gadget/file_storage.c
index 381a53b3e11c..1e6aa504d58a 100644
--- a/drivers/usb/gadget/file_storage.c
+++ b/drivers/usb/gadget/file_storage.c
@@ -248,6 +248,8 @@
248#include <linux/freezer.h> 248#include <linux/freezer.h>
249#include <linux/utsname.h> 249#include <linux/utsname.h>
250 250
251#include <asm/unaligned.h>
252
251#include <linux/usb/ch9.h> 253#include <linux/usb/ch9.h>
252#include <linux/usb/gadget.h> 254#include <linux/usb/gadget.h>
253 255
@@ -799,29 +801,9 @@ static int fsg_set_halt(struct fsg_dev *fsg, struct usb_ep *ep)
799 801
800/* Routines for unaligned data access */ 802/* Routines for unaligned data access */
801 803
802static u16 get_be16(u8 *buf) 804static u32 get_unaligned_be24(u8 *buf)
803{
804 return ((u16) buf[0] << 8) | ((u16) buf[1]);
805}
806
807static u32 get_be32(u8 *buf)
808{
809 return ((u32) buf[0] << 24) | ((u32) buf[1] << 16) |
810 ((u32) buf[2] << 8) | ((u32) buf[3]);
811}
812
813static void put_be16(u8 *buf, u16 val)
814{
815 buf[0] = val >> 8;
816 buf[1] = val;
817}
818
819static void put_be32(u8 *buf, u32 val)
820{ 805{
821 buf[0] = val >> 24; 806 return 0xffffff & (u32) get_unaligned_be32(buf - 1);
822 buf[1] = val >> 16;
823 buf[2] = val >> 8;
824 buf[3] = val & 0xff;
825} 807}
826 808
827 809
@@ -1582,9 +1564,9 @@ static int do_read(struct fsg_dev *fsg)
1582 /* Get the starting Logical Block Address and check that it's 1564 /* Get the starting Logical Block Address and check that it's
1583 * not too big */ 1565 * not too big */
1584 if (fsg->cmnd[0] == SC_READ_6) 1566 if (fsg->cmnd[0] == SC_READ_6)
1585 lba = (fsg->cmnd[1] << 16) | get_be16(&fsg->cmnd[2]); 1567 lba = get_unaligned_be24(&fsg->cmnd[1]);
1586 else { 1568 else {
1587 lba = get_be32(&fsg->cmnd[2]); 1569 lba = get_unaligned_be32(&fsg->cmnd[2]);
1588 1570
1589 /* We allow DPO (Disable Page Out = don't save data in the 1571 /* We allow DPO (Disable Page Out = don't save data in the
1590 * cache) and FUA (Force Unit Access = don't read from the 1572 * cache) and FUA (Force Unit Access = don't read from the
@@ -1717,9 +1699,9 @@ static int do_write(struct fsg_dev *fsg)
1717 /* Get the starting Logical Block Address and check that it's 1699 /* Get the starting Logical Block Address and check that it's
1718 * not too big */ 1700 * not too big */
1719 if (fsg->cmnd[0] == SC_WRITE_6) 1701 if (fsg->cmnd[0] == SC_WRITE_6)
1720 lba = (fsg->cmnd[1] << 16) | get_be16(&fsg->cmnd[2]); 1702 lba = get_unaligned_be24(&fsg->cmnd[1]);
1721 else { 1703 else {
1722 lba = get_be32(&fsg->cmnd[2]); 1704 lba = get_unaligned_be32(&fsg->cmnd[2]);
1723 1705
1724 /* We allow DPO (Disable Page Out = don't save data in the 1706 /* We allow DPO (Disable Page Out = don't save data in the
1725 * cache) and FUA (Force Unit Access = write directly to the 1707 * cache) and FUA (Force Unit Access = write directly to the
@@ -1940,7 +1922,7 @@ static int do_verify(struct fsg_dev *fsg)
1940 1922
1941 /* Get the starting Logical Block Address and check that it's 1923 /* Get the starting Logical Block Address and check that it's
1942 * not too big */ 1924 * not too big */
1943 lba = get_be32(&fsg->cmnd[2]); 1925 lba = get_unaligned_be32(&fsg->cmnd[2]);
1944 if (lba >= curlun->num_sectors) { 1926 if (lba >= curlun->num_sectors) {
1945 curlun->sense_data = SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE; 1927 curlun->sense_data = SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE;
1946 return -EINVAL; 1928 return -EINVAL;
@@ -1953,7 +1935,7 @@ static int do_verify(struct fsg_dev *fsg)
1953 return -EINVAL; 1935 return -EINVAL;
1954 } 1936 }
1955 1937
1956 verification_length = get_be16(&fsg->cmnd[7]); 1938 verification_length = get_unaligned_be16(&fsg->cmnd[7]);
1957 if (unlikely(verification_length == 0)) 1939 if (unlikely(verification_length == 0))
1958 return -EIO; // No default reply 1940 return -EIO; // No default reply
1959 1941
@@ -2103,7 +2085,7 @@ static int do_request_sense(struct fsg_dev *fsg, struct fsg_buffhd *bh)
2103 memset(buf, 0, 18); 2085 memset(buf, 0, 18);
2104 buf[0] = valid | 0x70; // Valid, current error 2086 buf[0] = valid | 0x70; // Valid, current error
2105 buf[2] = SK(sd); 2087 buf[2] = SK(sd);
2106 put_be32(&buf[3], sdinfo); // Sense information 2088 put_unaligned_be32(sdinfo, &buf[3]); /* Sense information */
2107 buf[7] = 18 - 8; // Additional sense length 2089 buf[7] = 18 - 8; // Additional sense length
2108 buf[12] = ASC(sd); 2090 buf[12] = ASC(sd);
2109 buf[13] = ASCQ(sd); 2091 buf[13] = ASCQ(sd);
@@ -2114,7 +2096,7 @@ static int do_request_sense(struct fsg_dev *fsg, struct fsg_buffhd *bh)
2114static int do_read_capacity(struct fsg_dev *fsg, struct fsg_buffhd *bh) 2096static int do_read_capacity(struct fsg_dev *fsg, struct fsg_buffhd *bh)
2115{ 2097{
2116 struct lun *curlun = fsg->curlun; 2098 struct lun *curlun = fsg->curlun;
2117 u32 lba = get_be32(&fsg->cmnd[2]); 2099 u32 lba = get_unaligned_be32(&fsg->cmnd[2]);
2118 int pmi = fsg->cmnd[8]; 2100 int pmi = fsg->cmnd[8];
2119 u8 *buf = (u8 *) bh->buf; 2101 u8 *buf = (u8 *) bh->buf;
2120 2102
@@ -2124,8 +2106,9 @@ static int do_read_capacity(struct fsg_dev *fsg, struct fsg_buffhd *bh)
2124 return -EINVAL; 2106 return -EINVAL;
2125 } 2107 }
2126 2108
2127 put_be32(&buf[0], curlun->num_sectors - 1); // Max logical block 2109 put_unaligned_be32(curlun->num_sectors - 1, &buf[0]);
2128 put_be32(&buf[4], 512); // Block length 2110 /* Max logical block */
2111 put_unaligned_be32(512, &buf[4]); /* Block length */
2129 return 8; 2112 return 8;
2130} 2113}
2131 2114
@@ -2144,7 +2127,7 @@ static void store_cdrom_address(u8 *dest, int msf, u32 addr)
2144 dest[0] = 0; /* Reserved */ 2127 dest[0] = 0; /* Reserved */
2145 } else { 2128 } else {
2146 /* Absolute sector */ 2129 /* Absolute sector */
2147 put_be32(dest, addr); 2130 put_unaligned_be32(addr, dest);
2148 } 2131 }
2149} 2132}
2150 2133
@@ -2152,7 +2135,7 @@ static int do_read_header(struct fsg_dev *fsg, struct fsg_buffhd *bh)
2152{ 2135{
2153 struct lun *curlun = fsg->curlun; 2136 struct lun *curlun = fsg->curlun;
2154 int msf = fsg->cmnd[1] & 0x02; 2137 int msf = fsg->cmnd[1] & 0x02;
2155 u32 lba = get_be32(&fsg->cmnd[2]); 2138 u32 lba = get_unaligned_be32(&fsg->cmnd[2]);
2156 u8 *buf = (u8 *) bh->buf; 2139 u8 *buf = (u8 *) bh->buf;
2157 2140
2158 if ((fsg->cmnd[1] & ~0x02) != 0) { /* Mask away MSF */ 2141 if ((fsg->cmnd[1] & ~0x02) != 0) { /* Mask away MSF */
@@ -2252,10 +2235,13 @@ static int do_mode_sense(struct fsg_dev *fsg, struct fsg_buffhd *bh)
2252 buf[2] = 0x04; // Write cache enable, 2235 buf[2] = 0x04; // Write cache enable,
2253 // Read cache not disabled 2236 // Read cache not disabled
2254 // No cache retention priorities 2237 // No cache retention priorities
2255 put_be16(&buf[4], 0xffff); // Don't disable prefetch 2238 put_unaligned_be16(0xffff, &buf[4]);
2256 // Minimum prefetch = 0 2239 /* Don't disable prefetch */
2257 put_be16(&buf[8], 0xffff); // Maximum prefetch 2240 /* Minimum prefetch = 0 */
2258 put_be16(&buf[10], 0xffff); // Maximum prefetch ceiling 2241 put_unaligned_be16(0xffff, &buf[8]);
2242 /* Maximum prefetch */
2243 put_unaligned_be16(0xffff, &buf[10]);
2244 /* Maximum prefetch ceiling */
2259 } 2245 }
2260 buf += 12; 2246 buf += 12;
2261 } 2247 }
@@ -2272,7 +2258,7 @@ static int do_mode_sense(struct fsg_dev *fsg, struct fsg_buffhd *bh)
2272 if (mscmnd == SC_MODE_SENSE_6) 2258 if (mscmnd == SC_MODE_SENSE_6)
2273 buf0[0] = len - 1; 2259 buf0[0] = len - 1;
2274 else 2260 else
2275 put_be16(buf0, len - 2); 2261 put_unaligned_be16(len - 2, buf0);
2276 return len; 2262 return len;
2277} 2263}
2278 2264
@@ -2360,9 +2346,10 @@ static int do_read_format_capacities(struct fsg_dev *fsg,
2360 buf[3] = 8; // Only the Current/Maximum Capacity Descriptor 2346 buf[3] = 8; // Only the Current/Maximum Capacity Descriptor
2361 buf += 4; 2347 buf += 4;
2362 2348
2363 put_be32(&buf[0], curlun->num_sectors); // Number of blocks 2349 put_unaligned_be32(curlun->num_sectors, &buf[0]);
2364 put_be32(&buf[4], 512); // Block length 2350 /* Number of blocks */
2365 buf[4] = 0x02; // Current capacity 2351 put_unaligned_be32(512, &buf[4]); /* Block length */
2352 buf[4] = 0x02; /* Current capacity */
2366 return 12; 2353 return 12;
2367} 2354}
2368 2355
@@ -2882,7 +2869,7 @@ static int do_scsi_command(struct fsg_dev *fsg)
2882 break; 2869 break;
2883 2870
2884 case SC_MODE_SELECT_10: 2871 case SC_MODE_SELECT_10:
2885 fsg->data_size_from_cmnd = get_be16(&fsg->cmnd[7]); 2872 fsg->data_size_from_cmnd = get_unaligned_be16(&fsg->cmnd[7]);
2886 if ((reply = check_command(fsg, 10, DATA_DIR_FROM_HOST, 2873 if ((reply = check_command(fsg, 10, DATA_DIR_FROM_HOST,
2887 (1<<1) | (3<<7), 0, 2874 (1<<1) | (3<<7), 0,
2888 "MODE SELECT(10)")) == 0) 2875 "MODE SELECT(10)")) == 0)
@@ -2898,7 +2885,7 @@ static int do_scsi_command(struct fsg_dev *fsg)
2898 break; 2885 break;
2899 2886
2900 case SC_MODE_SENSE_10: 2887 case SC_MODE_SENSE_10:
2901 fsg->data_size_from_cmnd = get_be16(&fsg->cmnd[7]); 2888 fsg->data_size_from_cmnd = get_unaligned_be16(&fsg->cmnd[7]);
2902 if ((reply = check_command(fsg, 10, DATA_DIR_TO_HOST, 2889 if ((reply = check_command(fsg, 10, DATA_DIR_TO_HOST,
2903 (1<<1) | (1<<2) | (3<<7), 0, 2890 (1<<1) | (1<<2) | (3<<7), 0,
2904 "MODE SENSE(10)")) == 0) 2891 "MODE SENSE(10)")) == 0)
@@ -2923,7 +2910,8 @@ static int do_scsi_command(struct fsg_dev *fsg)
2923 break; 2910 break;
2924 2911
2925 case SC_READ_10: 2912 case SC_READ_10:
2926 fsg->data_size_from_cmnd = get_be16(&fsg->cmnd[7]) << 9; 2913 fsg->data_size_from_cmnd =
2914 get_unaligned_be16(&fsg->cmnd[7]) << 9;
2927 if ((reply = check_command(fsg, 10, DATA_DIR_TO_HOST, 2915 if ((reply = check_command(fsg, 10, DATA_DIR_TO_HOST,
2928 (1<<1) | (0xf<<2) | (3<<7), 1, 2916 (1<<1) | (0xf<<2) | (3<<7), 1,
2929 "READ(10)")) == 0) 2917 "READ(10)")) == 0)
@@ -2931,7 +2919,8 @@ static int do_scsi_command(struct fsg_dev *fsg)
2931 break; 2919 break;
2932 2920
2933 case SC_READ_12: 2921 case SC_READ_12:
2934 fsg->data_size_from_cmnd = get_be32(&fsg->cmnd[6]) << 9; 2922 fsg->data_size_from_cmnd =
2923 get_unaligned_be32(&fsg->cmnd[6]) << 9;
2935 if ((reply = check_command(fsg, 12, DATA_DIR_TO_HOST, 2924 if ((reply = check_command(fsg, 12, DATA_DIR_TO_HOST,
2936 (1<<1) | (0xf<<2) | (0xf<<6), 1, 2925 (1<<1) | (0xf<<2) | (0xf<<6), 1,
2937 "READ(12)")) == 0) 2926 "READ(12)")) == 0)
@@ -2949,7 +2938,7 @@ static int do_scsi_command(struct fsg_dev *fsg)
2949 case SC_READ_HEADER: 2938 case SC_READ_HEADER:
2950 if (!mod_data.cdrom) 2939 if (!mod_data.cdrom)
2951 goto unknown_cmnd; 2940 goto unknown_cmnd;
2952 fsg->data_size_from_cmnd = get_be16(&fsg->cmnd[7]); 2941 fsg->data_size_from_cmnd = get_unaligned_be16(&fsg->cmnd[7]);
2953 if ((reply = check_command(fsg, 10, DATA_DIR_TO_HOST, 2942 if ((reply = check_command(fsg, 10, DATA_DIR_TO_HOST,
2954 (3<<7) | (0x1f<<1), 1, 2943 (3<<7) | (0x1f<<1), 1,
2955 "READ HEADER")) == 0) 2944 "READ HEADER")) == 0)
@@ -2959,7 +2948,7 @@ static int do_scsi_command(struct fsg_dev *fsg)
2959 case SC_READ_TOC: 2948 case SC_READ_TOC:
2960 if (!mod_data.cdrom) 2949 if (!mod_data.cdrom)
2961 goto unknown_cmnd; 2950 goto unknown_cmnd;
2962 fsg->data_size_from_cmnd = get_be16(&fsg->cmnd[7]); 2951 fsg->data_size_from_cmnd = get_unaligned_be16(&fsg->cmnd[7]);
2963 if ((reply = check_command(fsg, 10, DATA_DIR_TO_HOST, 2952 if ((reply = check_command(fsg, 10, DATA_DIR_TO_HOST,
2964 (7<<6) | (1<<1), 1, 2953 (7<<6) | (1<<1), 1,
2965 "READ TOC")) == 0) 2954 "READ TOC")) == 0)
@@ -2967,7 +2956,7 @@ static int do_scsi_command(struct fsg_dev *fsg)
2967 break; 2956 break;
2968 2957
2969 case SC_READ_FORMAT_CAPACITIES: 2958 case SC_READ_FORMAT_CAPACITIES:
2970 fsg->data_size_from_cmnd = get_be16(&fsg->cmnd[7]); 2959 fsg->data_size_from_cmnd = get_unaligned_be16(&fsg->cmnd[7]);
2971 if ((reply = check_command(fsg, 10, DATA_DIR_TO_HOST, 2960 if ((reply = check_command(fsg, 10, DATA_DIR_TO_HOST,
2972 (3<<7), 1, 2961 (3<<7), 1,
2973 "READ FORMAT CAPACITIES")) == 0) 2962 "READ FORMAT CAPACITIES")) == 0)
@@ -3025,7 +3014,8 @@ static int do_scsi_command(struct fsg_dev *fsg)
3025 break; 3014 break;
3026 3015
3027 case SC_WRITE_10: 3016 case SC_WRITE_10:
3028 fsg->data_size_from_cmnd = get_be16(&fsg->cmnd[7]) << 9; 3017 fsg->data_size_from_cmnd =
3018 get_unaligned_be16(&fsg->cmnd[7]) << 9;
3029 if ((reply = check_command(fsg, 10, DATA_DIR_FROM_HOST, 3019 if ((reply = check_command(fsg, 10, DATA_DIR_FROM_HOST,
3030 (1<<1) | (0xf<<2) | (3<<7), 1, 3020 (1<<1) | (0xf<<2) | (3<<7), 1,
3031 "WRITE(10)")) == 0) 3021 "WRITE(10)")) == 0)
@@ -3033,7 +3023,8 @@ static int do_scsi_command(struct fsg_dev *fsg)
3033 break; 3023 break;
3034 3024
3035 case SC_WRITE_12: 3025 case SC_WRITE_12:
3036 fsg->data_size_from_cmnd = get_be32(&fsg->cmnd[6]) << 9; 3026 fsg->data_size_from_cmnd =
3027 get_unaligned_be32(&fsg->cmnd[6]) << 9;
3037 if ((reply = check_command(fsg, 12, DATA_DIR_FROM_HOST, 3028 if ((reply = check_command(fsg, 12, DATA_DIR_FROM_HOST,
3038 (1<<1) | (0xf<<2) | (0xf<<6), 1, 3029 (1<<1) | (0xf<<2) | (0xf<<6), 1,
3039 "WRITE(12)")) == 0) 3030 "WRITE(12)")) == 0)
diff --git a/drivers/usb/gadget/fsl_mx3_udc.c b/drivers/usb/gadget/fsl_mx3_udc.c
new file mode 100644
index 000000000000..4bc2bf3d602e
--- /dev/null
+++ b/drivers/usb/gadget/fsl_mx3_udc.c
@@ -0,0 +1,95 @@
1/*
2 * Copyright (C) 2009
3 * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de>
4 *
5 * Description:
6 * Helper routines for i.MX3x SoCs from Freescale, needed by the fsl_usb2_udc.c
7 * driver to function correctly on these systems.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 */
14#include <linux/clk.h>
15#include <linux/delay.h>
16#include <linux/err.h>
17#include <linux/fsl_devices.h>
18#include <linux/platform_device.h>
19
20static struct clk *mxc_ahb_clk;
21static struct clk *mxc_usb_clk;
22
23int fsl_udc_clk_init(struct platform_device *pdev)
24{
25 struct fsl_usb2_platform_data *pdata;
26 unsigned long freq;
27 int ret;
28
29 pdata = pdev->dev.platform_data;
30
31 mxc_ahb_clk = clk_get(&pdev->dev, "usb_ahb");
32 if (IS_ERR(mxc_ahb_clk))
33 return PTR_ERR(mxc_ahb_clk);
34
35 ret = clk_enable(mxc_ahb_clk);
36 if (ret < 0) {
37 dev_err(&pdev->dev, "clk_enable(\"usb_ahb\") failed\n");
38 goto eenahb;
39 }
40
41 /* make sure USB_CLK is running at 60 MHz +/- 1000 Hz */
42 mxc_usb_clk = clk_get(&pdev->dev, "usb");
43 if (IS_ERR(mxc_usb_clk)) {
44 dev_err(&pdev->dev, "clk_get(\"usb\") failed\n");
45 ret = PTR_ERR(mxc_usb_clk);
46 goto egusb;
47 }
48
49 freq = clk_get_rate(mxc_usb_clk);
50 if (pdata->phy_mode != FSL_USB2_PHY_ULPI &&
51 (freq < 59999000 || freq > 60001000)) {
52 dev_err(&pdev->dev, "USB_CLK=%lu, should be 60MHz\n", freq);
53 goto eclkrate;
54 }
55
56 ret = clk_enable(mxc_usb_clk);
57 if (ret < 0) {
58 dev_err(&pdev->dev, "clk_enable(\"usb_clk\") failed\n");
59 goto eenusb;
60 }
61
62 return 0;
63
64eenusb:
65eclkrate:
66 clk_put(mxc_usb_clk);
67 mxc_usb_clk = NULL;
68egusb:
69 clk_disable(mxc_ahb_clk);
70eenahb:
71 clk_put(mxc_ahb_clk);
72 return ret;
73}
74
75void fsl_udc_clk_finalize(struct platform_device *pdev)
76{
77 struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data;
78
79 /* ULPI transceivers don't need usbpll */
80 if (pdata->phy_mode == FSL_USB2_PHY_ULPI) {
81 clk_disable(mxc_usb_clk);
82 clk_put(mxc_usb_clk);
83 mxc_usb_clk = NULL;
84 }
85}
86
87void fsl_udc_clk_release(void)
88{
89 if (mxc_usb_clk) {
90 clk_disable(mxc_usb_clk);
91 clk_put(mxc_usb_clk);
92 }
93 clk_disable(mxc_ahb_clk);
94 clk_put(mxc_ahb_clk);
95}
diff --git a/drivers/usb/gadget/fsl_usb2_udc.c b/drivers/usb/gadget/fsl_udc_core.c
index 9d7b95d4e3d2..42a74b8a0bb8 100644
--- a/drivers/usb/gadget/fsl_usb2_udc.c
+++ b/drivers/usb/gadget/fsl_udc_core.c
@@ -38,6 +38,7 @@
38#include <linux/platform_device.h> 38#include <linux/platform_device.h>
39#include <linux/fsl_devices.h> 39#include <linux/fsl_devices.h>
40#include <linux/dmapool.h> 40#include <linux/dmapool.h>
41#include <linux/delay.h>
41 42
42#include <asm/byteorder.h> 43#include <asm/byteorder.h>
43#include <asm/io.h> 44#include <asm/io.h>
@@ -57,7 +58,9 @@ static const char driver_name[] = "fsl-usb2-udc";
57static const char driver_desc[] = DRIVER_DESC; 58static const char driver_desc[] = DRIVER_DESC;
58 59
59static struct usb_dr_device *dr_regs; 60static struct usb_dr_device *dr_regs;
61#ifndef CONFIG_ARCH_MXC
60static struct usb_sys_interface *usb_sys_regs; 62static struct usb_sys_interface *usb_sys_regs;
63#endif
61 64
62/* it is initialized in probe() */ 65/* it is initialized in probe() */
63static struct fsl_udc *udc_controller = NULL; 66static struct fsl_udc *udc_controller = NULL;
@@ -174,10 +177,34 @@ static void nuke(struct fsl_ep *ep, int status)
174 177
175static int dr_controller_setup(struct fsl_udc *udc) 178static int dr_controller_setup(struct fsl_udc *udc)
176{ 179{
177 unsigned int tmp = 0, portctrl = 0, ctrl = 0; 180 unsigned int tmp, portctrl;
181#ifndef CONFIG_ARCH_MXC
182 unsigned int ctrl;
183#endif
178 unsigned long timeout; 184 unsigned long timeout;
179#define FSL_UDC_RESET_TIMEOUT 1000 185#define FSL_UDC_RESET_TIMEOUT 1000
180 186
187 /* Config PHY interface */
188 portctrl = fsl_readl(&dr_regs->portsc1);
189 portctrl &= ~(PORTSCX_PHY_TYPE_SEL | PORTSCX_PORT_WIDTH);
190 switch (udc->phy_mode) {
191 case FSL_USB2_PHY_ULPI:
192 portctrl |= PORTSCX_PTS_ULPI;
193 break;
194 case FSL_USB2_PHY_UTMI_WIDE:
195 portctrl |= PORTSCX_PTW_16BIT;
196 /* fall through */
197 case FSL_USB2_PHY_UTMI:
198 portctrl |= PORTSCX_PTS_UTMI;
199 break;
200 case FSL_USB2_PHY_SERIAL:
201 portctrl |= PORTSCX_PTS_FSLS;
202 break;
203 default:
204 return -EINVAL;
205 }
206 fsl_writel(portctrl, &dr_regs->portsc1);
207
181 /* Stop and reset the usb controller */ 208 /* Stop and reset the usb controller */
182 tmp = fsl_readl(&dr_regs->usbcmd); 209 tmp = fsl_readl(&dr_regs->usbcmd);
183 tmp &= ~USB_CMD_RUN_STOP; 210 tmp &= ~USB_CMD_RUN_STOP;
@@ -215,31 +242,12 @@ static int dr_controller_setup(struct fsl_udc *udc)
215 udc->ep_qh, (int)tmp, 242 udc->ep_qh, (int)tmp,
216 fsl_readl(&dr_regs->endpointlistaddr)); 243 fsl_readl(&dr_regs->endpointlistaddr));
217 244
218 /* Config PHY interface */
219 portctrl = fsl_readl(&dr_regs->portsc1);
220 portctrl &= ~(PORTSCX_PHY_TYPE_SEL | PORTSCX_PORT_WIDTH);
221 switch (udc->phy_mode) {
222 case FSL_USB2_PHY_ULPI:
223 portctrl |= PORTSCX_PTS_ULPI;
224 break;
225 case FSL_USB2_PHY_UTMI_WIDE:
226 portctrl |= PORTSCX_PTW_16BIT;
227 /* fall through */
228 case FSL_USB2_PHY_UTMI:
229 portctrl |= PORTSCX_PTS_UTMI;
230 break;
231 case FSL_USB2_PHY_SERIAL:
232 portctrl |= PORTSCX_PTS_FSLS;
233 break;
234 default:
235 return -EINVAL;
236 }
237 fsl_writel(portctrl, &dr_regs->portsc1);
238
239 /* Config control enable i/o output, cpu endian register */ 245 /* Config control enable i/o output, cpu endian register */
246#ifndef CONFIG_ARCH_MXC
240 ctrl = __raw_readl(&usb_sys_regs->control); 247 ctrl = __raw_readl(&usb_sys_regs->control);
241 ctrl |= USB_CTRL_IOENB; 248 ctrl |= USB_CTRL_IOENB;
242 __raw_writel(ctrl, &usb_sys_regs->control); 249 __raw_writel(ctrl, &usb_sys_regs->control);
250#endif
243 251
244#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE) 252#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
245 /* Turn on cache snooping hardware, since some PowerPC platforms 253 /* Turn on cache snooping hardware, since some PowerPC platforms
@@ -2043,6 +2051,7 @@ static int fsl_proc_read(char *page, char **start, off_t off, int count,
2043 size -= t; 2051 size -= t;
2044 next += t; 2052 next += t;
2045 2053
2054#ifndef CONFIG_ARCH_MXC
2046 tmp_reg = usb_sys_regs->snoop1; 2055 tmp_reg = usb_sys_regs->snoop1;
2047 t = scnprintf(next, size, "Snoop1 Reg : = [0x%x]\n\n", tmp_reg); 2056 t = scnprintf(next, size, "Snoop1 Reg : = [0x%x]\n\n", tmp_reg);
2048 size -= t; 2057 size -= t;
@@ -2053,6 +2062,7 @@ static int fsl_proc_read(char *page, char **start, off_t off, int count,
2053 tmp_reg); 2062 tmp_reg);
2054 size -= t; 2063 size -= t;
2055 next += t; 2064 next += t;
2065#endif
2056 2066
2057 /* ------fsl_udc, fsl_ep, fsl_request structure information ----- */ 2067 /* ------fsl_udc, fsl_ep, fsl_request structure information ----- */
2058 ep = &udc->eps[0]; 2068 ep = &udc->eps[0];
@@ -2263,14 +2273,21 @@ static int __init fsl_udc_probe(struct platform_device *pdev)
2263 goto err_kfree; 2273 goto err_kfree;
2264 } 2274 }
2265 2275
2266 dr_regs = ioremap(res->start, res->end - res->start + 1); 2276 dr_regs = ioremap(res->start, resource_size(res));
2267 if (!dr_regs) { 2277 if (!dr_regs) {
2268 ret = -ENOMEM; 2278 ret = -ENOMEM;
2269 goto err_release_mem_region; 2279 goto err_release_mem_region;
2270 } 2280 }
2271 2281
2282#ifndef CONFIG_ARCH_MXC
2272 usb_sys_regs = (struct usb_sys_interface *) 2283 usb_sys_regs = (struct usb_sys_interface *)
2273 ((u32)dr_regs + USB_DR_SYS_OFFSET); 2284 ((u32)dr_regs + USB_DR_SYS_OFFSET);
2285#endif
2286
2287 /* Initialize USB clocks */
2288 ret = fsl_udc_clk_init(pdev);
2289 if (ret < 0)
2290 goto err_iounmap_noclk;
2274 2291
2275 /* Read Device Controller Capability Parameters register */ 2292 /* Read Device Controller Capability Parameters register */
2276 dccparams = fsl_readl(&dr_regs->dccparams); 2293 dccparams = fsl_readl(&dr_regs->dccparams);
@@ -2308,6 +2325,8 @@ static int __init fsl_udc_probe(struct platform_device *pdev)
2308 * leave usbintr reg untouched */ 2325 * leave usbintr reg untouched */
2309 dr_controller_setup(udc_controller); 2326 dr_controller_setup(udc_controller);
2310 2327
2328 fsl_udc_clk_finalize(pdev);
2329
2311 /* Setup gadget structure */ 2330 /* Setup gadget structure */
2312 udc_controller->gadget.ops = &fsl_gadget_ops; 2331 udc_controller->gadget.ops = &fsl_gadget_ops;
2313 udc_controller->gadget.is_dualspeed = 1; 2332 udc_controller->gadget.is_dualspeed = 1;
@@ -2362,6 +2381,8 @@ err_unregister:
2362err_free_irq: 2381err_free_irq:
2363 free_irq(udc_controller->irq, udc_controller); 2382 free_irq(udc_controller->irq, udc_controller);
2364err_iounmap: 2383err_iounmap:
2384 fsl_udc_clk_release();
2385err_iounmap_noclk:
2365 iounmap(dr_regs); 2386 iounmap(dr_regs);
2366err_release_mem_region: 2387err_release_mem_region:
2367 release_mem_region(res->start, res->end - res->start + 1); 2388 release_mem_region(res->start, res->end - res->start + 1);
@@ -2384,6 +2405,8 @@ static int __exit fsl_udc_remove(struct platform_device *pdev)
2384 return -ENODEV; 2405 return -ENODEV;
2385 udc_controller->done = &done; 2406 udc_controller->done = &done;
2386 2407
2408 fsl_udc_clk_release();
2409
2387 /* DR has been stopped in usb_gadget_unregister_driver() */ 2410 /* DR has been stopped in usb_gadget_unregister_driver() */
2388 remove_proc_file(); 2411 remove_proc_file();
2389 2412
diff --git a/drivers/usb/gadget/fsl_usb2_udc.h b/drivers/usb/gadget/fsl_usb2_udc.h
index e63ef12645f5..20aeceed48c7 100644
--- a/drivers/usb/gadget/fsl_usb2_udc.h
+++ b/drivers/usb/gadget/fsl_usb2_udc.h
@@ -563,4 +563,22 @@ static void dump_msg(const char *label, const u8 * buf, unsigned int length)
563 * 2 + ((windex & USB_DIR_IN) ? 1 : 0)) 563 * 2 + ((windex & USB_DIR_IN) ? 1 : 0))
564#define get_pipe_by_ep(EP) (ep_index(EP) * 2 + ep_is_in(EP)) 564#define get_pipe_by_ep(EP) (ep_index(EP) * 2 + ep_is_in(EP))
565 565
566struct platform_device;
567#ifdef CONFIG_ARCH_MXC
568int fsl_udc_clk_init(struct platform_device *pdev);
569void fsl_udc_clk_finalize(struct platform_device *pdev);
570void fsl_udc_clk_release(void);
571#else
572static inline int fsl_udc_clk_init(struct platform_device *pdev)
573{
574 return 0;
575}
576static inline void fsl_udc_clk_finalize(struct platform_device *pdev)
577{
578}
579static inline void fsl_udc_clk_release(void)
580{
581}
582#endif
583
566#endif 584#endif
diff --git a/drivers/usb/gadget/gadget_chips.h b/drivers/usb/gadget/gadget_chips.h
index ec6d439a2aa5..8e0e9a0b7364 100644
--- a/drivers/usb/gadget/gadget_chips.h
+++ b/drivers/usb/gadget/gadget_chips.h
@@ -137,6 +137,12 @@
137#define gadget_is_musbhdrc(g) 0 137#define gadget_is_musbhdrc(g) 0
138#endif 138#endif
139 139
140#ifdef CONFIG_USB_GADGET_LANGWELL
141#define gadget_is_langwell(g) (!strcmp("langwell_udc", (g)->name))
142#else
143#define gadget_is_langwell(g) 0
144#endif
145
140/* from Montavista kernel (?) */ 146/* from Montavista kernel (?) */
141#ifdef CONFIG_USB_GADGET_MPC8272 147#ifdef CONFIG_USB_GADGET_MPC8272
142#define gadget_is_mpc8272(g) !strcmp("mpc8272_udc", (g)->name) 148#define gadget_is_mpc8272(g) !strcmp("mpc8272_udc", (g)->name)
@@ -231,6 +237,8 @@ static inline int usb_gadget_controller_number(struct usb_gadget *gadget)
231 return 0x22; 237 return 0x22;
232 else if (gadget_is_ci13xxx(gadget)) 238 else if (gadget_is_ci13xxx(gadget))
233 return 0x23; 239 return 0x23;
240 else if (gadget_is_langwell(gadget))
241 return 0x24;
234 return -ENOENT; 242 return -ENOENT;
235} 243}
236 244
diff --git a/drivers/usb/gadget/goku_udc.c b/drivers/usb/gadget/goku_udc.c
index de010c939dbb..112bb40a427c 100644
--- a/drivers/usb/gadget/goku_udc.c
+++ b/drivers/usb/gadget/goku_udc.c
@@ -110,10 +110,10 @@ goku_ep_enable(struct usb_ep *_ep, const struct usb_endpoint_descriptor *desc)
110 return -EINVAL; 110 return -EINVAL;
111 if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN) 111 if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)
112 return -ESHUTDOWN; 112 return -ESHUTDOWN;
113 if (ep->num != (desc->bEndpointAddress & 0x0f)) 113 if (ep->num != usb_endpoint_num(desc))
114 return -EINVAL; 114 return -EINVAL;
115 115
116 switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) { 116 switch (usb_endpoint_type(desc)) {
117 case USB_ENDPOINT_XFER_BULK: 117 case USB_ENDPOINT_XFER_BULK:
118 case USB_ENDPOINT_XFER_INT: 118 case USB_ENDPOINT_XFER_INT:
119 break; 119 break;
@@ -142,7 +142,7 @@ goku_ep_enable(struct usb_ep *_ep, const struct usb_endpoint_descriptor *desc)
142 /* ep1/ep2 dma direction is chosen early; it works in the other 142 /* ep1/ep2 dma direction is chosen early; it works in the other
143 * direction, with pio. be cautious with out-dma. 143 * direction, with pio. be cautious with out-dma.
144 */ 144 */
145 ep->is_in = (USB_DIR_IN & desc->bEndpointAddress) != 0; 145 ep->is_in = usb_endpoint_dir_in(desc);
146 if (ep->is_in) { 146 if (ep->is_in) {
147 mode |= 1; 147 mode |= 1;
148 ep->dma = (use_dma != 0) && (ep->num == UDC_MSTRD_ENDPOINT); 148 ep->dma = (use_dma != 0) && (ep->num == UDC_MSTRD_ENDPOINT);
diff --git a/drivers/usb/gadget/imx_udc.c b/drivers/usb/gadget/imx_udc.c
index 168658b4b4e2..c52a681f376c 100644
--- a/drivers/usb/gadget/imx_udc.c
+++ b/drivers/usb/gadget/imx_udc.c
@@ -415,6 +415,13 @@ static int write_packet(struct imx_ep_struct *imx_ep, struct imx_request *req)
415 u8 *buf; 415 u8 *buf;
416 int length, count, temp; 416 int length, count, temp;
417 417
418 if (unlikely(__raw_readl(imx_ep->imx_usb->base +
419 USB_EP_STAT(EP_NO(imx_ep))) & EPSTAT_ZLPS)) {
420 D_TRX(imx_ep->imx_usb->dev, "<%s> zlp still queued in EP %s\n",
421 __func__, imx_ep->ep.name);
422 return -1;
423 }
424
418 buf = req->req.buf + req->req.actual; 425 buf = req->req.buf + req->req.actual;
419 prefetch(buf); 426 prefetch(buf);
420 427
@@ -734,9 +741,12 @@ static struct usb_request *imx_ep_alloc_request
734{ 741{
735 struct imx_request *req; 742 struct imx_request *req;
736 743
744 if (!usb_ep)
745 return NULL;
746
737 req = kzalloc(sizeof *req, gfp_flags); 747 req = kzalloc(sizeof *req, gfp_flags);
738 if (!req || !usb_ep) 748 if (!req)
739 return 0; 749 return NULL;
740 750
741 INIT_LIST_HEAD(&req->queue); 751 INIT_LIST_HEAD(&req->queue);
742 req->in_use = 0; 752 req->in_use = 0;
diff --git a/drivers/usb/gadget/inode.c b/drivers/usb/gadget/inode.c
index d20937f28a19..7d33f50b5874 100644
--- a/drivers/usb/gadget/inode.c
+++ b/drivers/usb/gadget/inode.c
@@ -384,9 +384,8 @@ ep_read (struct file *fd, char __user *buf, size_t len, loff_t *ptr)
384 return value; 384 return value;
385 385
386 /* halt any endpoint by doing a "wrong direction" i/o call */ 386 /* halt any endpoint by doing a "wrong direction" i/o call */
387 if (data->desc.bEndpointAddress & USB_DIR_IN) { 387 if (usb_endpoint_dir_in(&data->desc)) {
388 if ((data->desc.bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) 388 if (usb_endpoint_xfer_isoc(&data->desc))
389 == USB_ENDPOINT_XFER_ISOC)
390 return -EINVAL; 389 return -EINVAL;
391 DBG (data->dev, "%s halt\n", data->name); 390 DBG (data->dev, "%s halt\n", data->name);
392 spin_lock_irq (&data->dev->lock); 391 spin_lock_irq (&data->dev->lock);
@@ -428,9 +427,8 @@ ep_write (struct file *fd, const char __user *buf, size_t len, loff_t *ptr)
428 return value; 427 return value;
429 428
430 /* halt any endpoint by doing a "wrong direction" i/o call */ 429 /* halt any endpoint by doing a "wrong direction" i/o call */
431 if (!(data->desc.bEndpointAddress & USB_DIR_IN)) { 430 if (!usb_endpoint_dir_in(&data->desc)) {
432 if ((data->desc.bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) 431 if (usb_endpoint_xfer_isoc(&data->desc))
433 == USB_ENDPOINT_XFER_ISOC)
434 return -EINVAL; 432 return -EINVAL;
435 DBG (data->dev, "%s halt\n", data->name); 433 DBG (data->dev, "%s halt\n", data->name);
436 spin_lock_irq (&data->dev->lock); 434 spin_lock_irq (&data->dev->lock);
@@ -691,7 +689,7 @@ ep_aio_read(struct kiocb *iocb, const struct iovec *iov,
691 struct ep_data *epdata = iocb->ki_filp->private_data; 689 struct ep_data *epdata = iocb->ki_filp->private_data;
692 char *buf; 690 char *buf;
693 691
694 if (unlikely(epdata->desc.bEndpointAddress & USB_DIR_IN)) 692 if (unlikely(usb_endpoint_dir_in(&epdata->desc)))
695 return -EINVAL; 693 return -EINVAL;
696 694
697 buf = kmalloc(iocb->ki_left, GFP_KERNEL); 695 buf = kmalloc(iocb->ki_left, GFP_KERNEL);
@@ -711,7 +709,7 @@ ep_aio_write(struct kiocb *iocb, const struct iovec *iov,
711 size_t len = 0; 709 size_t len = 0;
712 int i = 0; 710 int i = 0;
713 711
714 if (unlikely(!(epdata->desc.bEndpointAddress & USB_DIR_IN))) 712 if (unlikely(!usb_endpoint_dir_in(&epdata->desc)))
715 return -EINVAL; 713 return -EINVAL;
716 714
717 buf = kmalloc(iocb->ki_left, GFP_KERNEL); 715 buf = kmalloc(iocb->ki_left, GFP_KERNEL);
diff --git a/drivers/usb/gadget/langwell_udc.c b/drivers/usb/gadget/langwell_udc.c
new file mode 100644
index 000000000000..6829d5961359
--- /dev/null
+++ b/drivers/usb/gadget/langwell_udc.c
@@ -0,0 +1,3373 @@
1/*
2 * Intel Langwell USB Device Controller driver
3 * Copyright (C) 2008-2009, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
17 *
18 */
19
20
21/* #undef DEBUG */
22/* #undef VERBOSE */
23
24#if defined(CONFIG_USB_LANGWELL_OTG)
25#define OTG_TRANSCEIVER
26#endif
27
28
29#include <linux/module.h>
30#include <linux/pci.h>
31#include <linux/dma-mapping.h>
32#include <linux/kernel.h>
33#include <linux/delay.h>
34#include <linux/ioport.h>
35#include <linux/sched.h>
36#include <linux/slab.h>
37#include <linux/smp_lock.h>
38#include <linux/errno.h>
39#include <linux/init.h>
40#include <linux/timer.h>
41#include <linux/list.h>
42#include <linux/interrupt.h>
43#include <linux/moduleparam.h>
44#include <linux/device.h>
45#include <linux/usb/ch9.h>
46#include <linux/usb/gadget.h>
47#include <linux/usb/otg.h>
48#include <linux/pm.h>
49#include <linux/io.h>
50#include <linux/irq.h>
51#include <asm/system.h>
52#include <asm/unaligned.h>
53
54#include "langwell_udc.h"
55
56
57#define DRIVER_DESC "Intel Langwell USB Device Controller driver"
58#define DRIVER_VERSION "16 May 2009"
59
60static const char driver_name[] = "langwell_udc";
61static const char driver_desc[] = DRIVER_DESC;
62
63
64/* controller device global variable */
65static struct langwell_udc *the_controller;
66
67/* for endpoint 0 operations */
68static const struct usb_endpoint_descriptor
69langwell_ep0_desc = {
70 .bLength = USB_DT_ENDPOINT_SIZE,
71 .bDescriptorType = USB_DT_ENDPOINT,
72 .bEndpointAddress = 0,
73 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
74 .wMaxPacketSize = EP0_MAX_PKT_SIZE,
75};
76
77
78/*-------------------------------------------------------------------------*/
79/* debugging */
80
81#ifdef DEBUG
82#define DBG(dev, fmt, args...) \
83 pr_debug("%s %s: " fmt , driver_name, \
84 pci_name(dev->pdev), ## args)
85#else
86#define DBG(dev, fmt, args...) \
87 do { } while (0)
88#endif /* DEBUG */
89
90
91#ifdef VERBOSE
92#define VDBG DBG
93#else
94#define VDBG(dev, fmt, args...) \
95 do { } while (0)
96#endif /* VERBOSE */
97
98
99#define ERROR(dev, fmt, args...) \
100 pr_err("%s %s: " fmt , driver_name, \
101 pci_name(dev->pdev), ## args)
102
103#define WARNING(dev, fmt, args...) \
104 pr_warning("%s %s: " fmt , driver_name, \
105 pci_name(dev->pdev), ## args)
106
107#define INFO(dev, fmt, args...) \
108 pr_info("%s %s: " fmt , driver_name, \
109 pci_name(dev->pdev), ## args)
110
111
112#ifdef VERBOSE
113static inline void print_all_registers(struct langwell_udc *dev)
114{
115 int i;
116
117 /* Capability Registers */
118 printk(KERN_DEBUG "Capability Registers (offset: "
119 "0x%04x, length: 0x%08x)\n",
120 CAP_REG_OFFSET,
121 (u32)sizeof(struct langwell_cap_regs));
122 printk(KERN_DEBUG "caplength=0x%02x\n",
123 readb(&dev->cap_regs->caplength));
124 printk(KERN_DEBUG "hciversion=0x%04x\n",
125 readw(&dev->cap_regs->hciversion));
126 printk(KERN_DEBUG "hcsparams=0x%08x\n",
127 readl(&dev->cap_regs->hcsparams));
128 printk(KERN_DEBUG "hccparams=0x%08x\n",
129 readl(&dev->cap_regs->hccparams));
130 printk(KERN_DEBUG "dciversion=0x%04x\n",
131 readw(&dev->cap_regs->dciversion));
132 printk(KERN_DEBUG "dccparams=0x%08x\n",
133 readl(&dev->cap_regs->dccparams));
134
135 /* Operational Registers */
136 printk(KERN_DEBUG "Operational Registers (offset: "
137 "0x%04x, length: 0x%08x)\n",
138 OP_REG_OFFSET,
139 (u32)sizeof(struct langwell_op_regs));
140 printk(KERN_DEBUG "extsts=0x%08x\n",
141 readl(&dev->op_regs->extsts));
142 printk(KERN_DEBUG "extintr=0x%08x\n",
143 readl(&dev->op_regs->extintr));
144 printk(KERN_DEBUG "usbcmd=0x%08x\n",
145 readl(&dev->op_regs->usbcmd));
146 printk(KERN_DEBUG "usbsts=0x%08x\n",
147 readl(&dev->op_regs->usbsts));
148 printk(KERN_DEBUG "usbintr=0x%08x\n",
149 readl(&dev->op_regs->usbintr));
150 printk(KERN_DEBUG "frindex=0x%08x\n",
151 readl(&dev->op_regs->frindex));
152 printk(KERN_DEBUG "ctrldssegment=0x%08x\n",
153 readl(&dev->op_regs->ctrldssegment));
154 printk(KERN_DEBUG "deviceaddr=0x%08x\n",
155 readl(&dev->op_regs->deviceaddr));
156 printk(KERN_DEBUG "endpointlistaddr=0x%08x\n",
157 readl(&dev->op_regs->endpointlistaddr));
158 printk(KERN_DEBUG "ttctrl=0x%08x\n",
159 readl(&dev->op_regs->ttctrl));
160 printk(KERN_DEBUG "burstsize=0x%08x\n",
161 readl(&dev->op_regs->burstsize));
162 printk(KERN_DEBUG "txfilltuning=0x%08x\n",
163 readl(&dev->op_regs->txfilltuning));
164 printk(KERN_DEBUG "txttfilltuning=0x%08x\n",
165 readl(&dev->op_regs->txttfilltuning));
166 printk(KERN_DEBUG "ic_usb=0x%08x\n",
167 readl(&dev->op_regs->ic_usb));
168 printk(KERN_DEBUG "ulpi_viewport=0x%08x\n",
169 readl(&dev->op_regs->ulpi_viewport));
170 printk(KERN_DEBUG "configflag=0x%08x\n",
171 readl(&dev->op_regs->configflag));
172 printk(KERN_DEBUG "portsc1=0x%08x\n",
173 readl(&dev->op_regs->portsc1));
174 printk(KERN_DEBUG "devlc=0x%08x\n",
175 readl(&dev->op_regs->devlc));
176 printk(KERN_DEBUG "otgsc=0x%08x\n",
177 readl(&dev->op_regs->otgsc));
178 printk(KERN_DEBUG "usbmode=0x%08x\n",
179 readl(&dev->op_regs->usbmode));
180 printk(KERN_DEBUG "endptnak=0x%08x\n",
181 readl(&dev->op_regs->endptnak));
182 printk(KERN_DEBUG "endptnaken=0x%08x\n",
183 readl(&dev->op_regs->endptnaken));
184 printk(KERN_DEBUG "endptsetupstat=0x%08x\n",
185 readl(&dev->op_regs->endptsetupstat));
186 printk(KERN_DEBUG "endptprime=0x%08x\n",
187 readl(&dev->op_regs->endptprime));
188 printk(KERN_DEBUG "endptflush=0x%08x\n",
189 readl(&dev->op_regs->endptflush));
190 printk(KERN_DEBUG "endptstat=0x%08x\n",
191 readl(&dev->op_regs->endptstat));
192 printk(KERN_DEBUG "endptcomplete=0x%08x\n",
193 readl(&dev->op_regs->endptcomplete));
194
195 for (i = 0; i < dev->ep_max / 2; i++) {
196 printk(KERN_DEBUG "endptctrl[%d]=0x%08x\n",
197 i, readl(&dev->op_regs->endptctrl[i]));
198 }
199}
200#endif /* VERBOSE */
201
202
203/*-------------------------------------------------------------------------*/
204
205#define DIR_STRING(bAddress) (((bAddress) & USB_DIR_IN) ? "in" : "out")
206
207#define is_in(ep) (((ep)->ep_num == 0) ? ((ep)->dev->ep0_dir == \
208 USB_DIR_IN) : ((ep)->desc->bEndpointAddress \
209 & USB_DIR_IN) == USB_DIR_IN)
210
211
212#ifdef DEBUG
213static char *type_string(u8 bmAttributes)
214{
215 switch ((bmAttributes) & USB_ENDPOINT_XFERTYPE_MASK) {
216 case USB_ENDPOINT_XFER_BULK:
217 return "bulk";
218 case USB_ENDPOINT_XFER_ISOC:
219 return "iso";
220 case USB_ENDPOINT_XFER_INT:
221 return "int";
222 };
223
224 return "control";
225}
226#endif
227
228
229/* configure endpoint control registers */
230static void ep_reset(struct langwell_ep *ep, unsigned char ep_num,
231 unsigned char is_in, unsigned char ep_type)
232{
233 struct langwell_udc *dev;
234 u32 endptctrl;
235
236 dev = ep->dev;
237 VDBG(dev, "---> %s()\n", __func__);
238
239 endptctrl = readl(&dev->op_regs->endptctrl[ep_num]);
240 if (is_in) { /* TX */
241 if (ep_num)
242 endptctrl |= EPCTRL_TXR;
243 endptctrl |= EPCTRL_TXE;
244 endptctrl |= ep_type << EPCTRL_TXT_SHIFT;
245 } else { /* RX */
246 if (ep_num)
247 endptctrl |= EPCTRL_RXR;
248 endptctrl |= EPCTRL_RXE;
249 endptctrl |= ep_type << EPCTRL_RXT_SHIFT;
250 }
251
252 writel(endptctrl, &dev->op_regs->endptctrl[ep_num]);
253
254 VDBG(dev, "<--- %s()\n", __func__);
255}
256
257
258/* reset ep0 dQH and endptctrl */
259static void ep0_reset(struct langwell_udc *dev)
260{
261 struct langwell_ep *ep;
262 int i;
263
264 VDBG(dev, "---> %s()\n", __func__);
265
266 /* ep0 in and out */
267 for (i = 0; i < 2; i++) {
268 ep = &dev->ep[i];
269 ep->dev = dev;
270
271 /* ep0 dQH */
272 ep->dqh = &dev->ep_dqh[i];
273
274 /* configure ep0 endpoint capabilities in dQH */
275 ep->dqh->dqh_ios = 1;
276 ep->dqh->dqh_mpl = EP0_MAX_PKT_SIZE;
277
278 /* FIXME: enable ep0-in HW zero length termination select */
279 if (is_in(ep))
280 ep->dqh->dqh_zlt = 0;
281 ep->dqh->dqh_mult = 0;
282
283 /* configure ep0 control registers */
284 ep_reset(&dev->ep[0], 0, i, USB_ENDPOINT_XFER_CONTROL);
285 }
286
287 VDBG(dev, "<--- %s()\n", __func__);
288 return;
289}
290
291
292/*-------------------------------------------------------------------------*/
293
294/* endpoints operations */
295
296/* configure endpoint, making it usable */
297static int langwell_ep_enable(struct usb_ep *_ep,
298 const struct usb_endpoint_descriptor *desc)
299{
300 struct langwell_udc *dev;
301 struct langwell_ep *ep;
302 u16 max = 0;
303 unsigned long flags;
304 int retval = 0;
305 unsigned char zlt, ios = 0, mult = 0;
306
307 ep = container_of(_ep, struct langwell_ep, ep);
308 dev = ep->dev;
309 VDBG(dev, "---> %s()\n", __func__);
310
311 if (!_ep || !desc || ep->desc
312 || desc->bDescriptorType != USB_DT_ENDPOINT)
313 return -EINVAL;
314
315 if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)
316 return -ESHUTDOWN;
317
318 max = le16_to_cpu(desc->wMaxPacketSize);
319
320 /*
321 * disable HW zero length termination select
322 * driver handles zero length packet through req->req.zero
323 */
324 zlt = 1;
325
326 /*
327 * sanity check type, direction, address, and then
328 * initialize the endpoint capabilities fields in dQH
329 */
330 switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
331 case USB_ENDPOINT_XFER_CONTROL:
332 ios = 1;
333 break;
334 case USB_ENDPOINT_XFER_BULK:
335 if ((dev->gadget.speed == USB_SPEED_HIGH
336 && max != 512)
337 || (dev->gadget.speed == USB_SPEED_FULL
338 && max > 64)) {
339 goto done;
340 }
341 break;
342 case USB_ENDPOINT_XFER_INT:
343 if (strstr(ep->ep.name, "-iso")) /* bulk is ok */
344 goto done;
345
346 switch (dev->gadget.speed) {
347 case USB_SPEED_HIGH:
348 if (max <= 1024)
349 break;
350 case USB_SPEED_FULL:
351 if (max <= 64)
352 break;
353 default:
354 if (max <= 8)
355 break;
356 goto done;
357 }
358 break;
359 case USB_ENDPOINT_XFER_ISOC:
360 if (strstr(ep->ep.name, "-bulk")
361 || strstr(ep->ep.name, "-int"))
362 goto done;
363
364 switch (dev->gadget.speed) {
365 case USB_SPEED_HIGH:
366 if (max <= 1024)
367 break;
368 case USB_SPEED_FULL:
369 if (max <= 1023)
370 break;
371 default:
372 goto done;
373 }
374 /*
375 * FIXME:
376 * calculate transactions needed for high bandwidth iso
377 */
378 mult = (unsigned char)(1 + ((max >> 11) & 0x03));
379 max = max & 0x8ff; /* bit 0~10 */
380 /* 3 transactions at most */
381 if (mult > 3)
382 goto done;
383 break;
384 default:
385 goto done;
386 }
387
388 spin_lock_irqsave(&dev->lock, flags);
389
390 /* configure endpoint capabilities in dQH */
391 ep->dqh->dqh_ios = ios;
392 ep->dqh->dqh_mpl = cpu_to_le16(max);
393 ep->dqh->dqh_zlt = zlt;
394 ep->dqh->dqh_mult = mult;
395
396 ep->ep.maxpacket = max;
397 ep->desc = desc;
398 ep->stopped = 0;
399 ep->ep_num = desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
400
401 /* ep_type */
402 ep->ep_type = desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK;
403
404 /* configure endpoint control registers */
405 ep_reset(ep, ep->ep_num, is_in(ep), ep->ep_type);
406
407 DBG(dev, "enabled %s (ep%d%s-%s), max %04x\n",
408 _ep->name,
409 ep->ep_num,
410 DIR_STRING(desc->bEndpointAddress),
411 type_string(desc->bmAttributes),
412 max);
413
414 spin_unlock_irqrestore(&dev->lock, flags);
415done:
416 VDBG(dev, "<--- %s()\n", __func__);
417 return retval;
418}
419
420
421/*-------------------------------------------------------------------------*/
422
423/* retire a request */
424static void done(struct langwell_ep *ep, struct langwell_request *req,
425 int status)
426{
427 struct langwell_udc *dev = ep->dev;
428 unsigned stopped = ep->stopped;
429 struct langwell_dtd *curr_dtd, *next_dtd;
430 int i;
431
432 VDBG(dev, "---> %s()\n", __func__);
433
434 /* remove the req from ep->queue */
435 list_del_init(&req->queue);
436
437 if (req->req.status == -EINPROGRESS)
438 req->req.status = status;
439 else
440 status = req->req.status;
441
442 /* free dTD for the request */
443 next_dtd = req->head;
444 for (i = 0; i < req->dtd_count; i++) {
445 curr_dtd = next_dtd;
446 if (i != req->dtd_count - 1)
447 next_dtd = curr_dtd->next_dtd_virt;
448 dma_pool_free(dev->dtd_pool, curr_dtd, curr_dtd->dtd_dma);
449 }
450
451 if (req->mapped) {
452 dma_unmap_single(&dev->pdev->dev, req->req.dma, req->req.length,
453 is_in(ep) ? PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
454 req->req.dma = DMA_ADDR_INVALID;
455 req->mapped = 0;
456 } else
457 dma_sync_single_for_cpu(&dev->pdev->dev, req->req.dma,
458 req->req.length,
459 is_in(ep) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
460
461 if (status != -ESHUTDOWN)
462 DBG(dev, "complete %s, req %p, stat %d, len %u/%u\n",
463 ep->ep.name, &req->req, status,
464 req->req.actual, req->req.length);
465
466 /* don't modify queue heads during completion callback */
467 ep->stopped = 1;
468
469 spin_unlock(&dev->lock);
470 /* complete routine from gadget driver */
471 if (req->req.complete)
472 req->req.complete(&ep->ep, &req->req);
473
474 spin_lock(&dev->lock);
475 ep->stopped = stopped;
476
477 VDBG(dev, "<--- %s()\n", __func__);
478}
479
480
481static void langwell_ep_fifo_flush(struct usb_ep *_ep);
482
483/* delete all endpoint requests, called with spinlock held */
484static void nuke(struct langwell_ep *ep, int status)
485{
486 /* called with spinlock held */
487 ep->stopped = 1;
488
489 /* endpoint fifo flush */
490 if (&ep->ep && ep->desc)
491 langwell_ep_fifo_flush(&ep->ep);
492
493 while (!list_empty(&ep->queue)) {
494 struct langwell_request *req = NULL;
495 req = list_entry(ep->queue.next, struct langwell_request,
496 queue);
497 done(ep, req, status);
498 }
499}
500
501
502/*-------------------------------------------------------------------------*/
503
504/* endpoint is no longer usable */
505static int langwell_ep_disable(struct usb_ep *_ep)
506{
507 struct langwell_ep *ep;
508 unsigned long flags;
509 struct langwell_udc *dev;
510 int ep_num;
511 u32 endptctrl;
512
513 ep = container_of(_ep, struct langwell_ep, ep);
514 dev = ep->dev;
515 VDBG(dev, "---> %s()\n", __func__);
516
517 if (!_ep || !ep->desc)
518 return -EINVAL;
519
520 spin_lock_irqsave(&dev->lock, flags);
521
522 /* disable endpoint control register */
523 ep_num = ep->ep_num;
524 endptctrl = readl(&dev->op_regs->endptctrl[ep_num]);
525 if (is_in(ep))
526 endptctrl &= ~EPCTRL_TXE;
527 else
528 endptctrl &= ~EPCTRL_RXE;
529 writel(endptctrl, &dev->op_regs->endptctrl[ep_num]);
530
531 /* nuke all pending requests (does flush) */
532 nuke(ep, -ESHUTDOWN);
533
534 ep->desc = NULL;
535 ep->stopped = 1;
536
537 spin_unlock_irqrestore(&dev->lock, flags);
538
539 DBG(dev, "disabled %s\n", _ep->name);
540 VDBG(dev, "<--- %s()\n", __func__);
541
542 return 0;
543}
544
545
546/* allocate a request object to use with this endpoint */
547static struct usb_request *langwell_alloc_request(struct usb_ep *_ep,
548 gfp_t gfp_flags)
549{
550 struct langwell_ep *ep;
551 struct langwell_udc *dev;
552 struct langwell_request *req = NULL;
553
554 if (!_ep)
555 return NULL;
556
557 ep = container_of(_ep, struct langwell_ep, ep);
558 dev = ep->dev;
559 VDBG(dev, "---> %s()\n", __func__);
560
561 req = kzalloc(sizeof(*req), gfp_flags);
562 if (!req)
563 return NULL;
564
565 req->req.dma = DMA_ADDR_INVALID;
566 INIT_LIST_HEAD(&req->queue);
567
568 VDBG(dev, "alloc request for %s\n", _ep->name);
569 VDBG(dev, "<--- %s()\n", __func__);
570 return &req->req;
571}
572
573
574/* free a request object */
575static void langwell_free_request(struct usb_ep *_ep,
576 struct usb_request *_req)
577{
578 struct langwell_ep *ep;
579 struct langwell_udc *dev;
580 struct langwell_request *req = NULL;
581
582 ep = container_of(_ep, struct langwell_ep, ep);
583 dev = ep->dev;
584 VDBG(dev, "---> %s()\n", __func__);
585
586 if (!_ep || !_req)
587 return;
588
589 req = container_of(_req, struct langwell_request, req);
590 WARN_ON(!list_empty(&req->queue));
591
592 if (_req)
593 kfree(req);
594
595 VDBG(dev, "free request for %s\n", _ep->name);
596 VDBG(dev, "<--- %s()\n", __func__);
597}
598
599
600/*-------------------------------------------------------------------------*/
601
602/* queue dTD and PRIME endpoint */
603static int queue_dtd(struct langwell_ep *ep, struct langwell_request *req)
604{
605 u32 bit_mask, usbcmd, endptstat, dtd_dma;
606 u8 dtd_status;
607 int i;
608 struct langwell_dqh *dqh;
609 struct langwell_udc *dev;
610
611 dev = ep->dev;
612 VDBG(dev, "---> %s()\n", __func__);
613
614 i = ep->ep_num * 2 + is_in(ep);
615 dqh = &dev->ep_dqh[i];
616
617 if (ep->ep_num)
618 VDBG(dev, "%s\n", ep->name);
619 else
620 /* ep0 */
621 VDBG(dev, "%s-%s\n", ep->name, is_in(ep) ? "in" : "out");
622
623 VDBG(dev, "ep_dqh[%d] addr: 0x%08x\n", i, (u32)&(dev->ep_dqh[i]));
624
625 bit_mask = is_in(ep) ?
626 (1 << (ep->ep_num + 16)) : (1 << (ep->ep_num));
627
628 VDBG(dev, "bit_mask = 0x%08x\n", bit_mask);
629
630 /* check if the pipe is empty */
631 if (!(list_empty(&ep->queue))) {
632 /* add dTD to the end of linked list */
633 struct langwell_request *lastreq;
634 lastreq = list_entry(ep->queue.prev,
635 struct langwell_request, queue);
636
637 lastreq->tail->dtd_next =
638 cpu_to_le32(req->head->dtd_dma & DTD_NEXT_MASK);
639
640 /* read prime bit, if 1 goto out */
641 if (readl(&dev->op_regs->endptprime) & bit_mask)
642 goto out;
643
644 do {
645 /* set ATDTW bit in USBCMD */
646 usbcmd = readl(&dev->op_regs->usbcmd);
647 writel(usbcmd | CMD_ATDTW, &dev->op_regs->usbcmd);
648
649 /* read correct status bit */
650 endptstat = readl(&dev->op_regs->endptstat) & bit_mask;
651
652 } while (!(readl(&dev->op_regs->usbcmd) & CMD_ATDTW));
653
654 /* write ATDTW bit to 0 */
655 usbcmd = readl(&dev->op_regs->usbcmd);
656 writel(usbcmd & ~CMD_ATDTW, &dev->op_regs->usbcmd);
657
658 if (endptstat)
659 goto out;
660 }
661
662 /* write dQH next pointer and terminate bit to 0 */
663 dtd_dma = req->head->dtd_dma & DTD_NEXT_MASK;
664 dqh->dtd_next = cpu_to_le32(dtd_dma);
665
666 /* clear active and halt bit */
667 dtd_status = (u8) ~(DTD_STS_ACTIVE | DTD_STS_HALTED);
668 dqh->dtd_status &= dtd_status;
669 VDBG(dev, "dqh->dtd_status = 0x%x\n", dqh->dtd_status);
670
671 /* write 1 to endptprime register to PRIME endpoint */
672 bit_mask = is_in(ep) ? (1 << (ep->ep_num + 16)) : (1 << ep->ep_num);
673 VDBG(dev, "endprime bit_mask = 0x%08x\n", bit_mask);
674 writel(bit_mask, &dev->op_regs->endptprime);
675out:
676 VDBG(dev, "<--- %s()\n", __func__);
677 return 0;
678}
679
680
681/* fill in the dTD structure to build a transfer descriptor */
682static struct langwell_dtd *build_dtd(struct langwell_request *req,
683 unsigned *length, dma_addr_t *dma, int *is_last)
684{
685 u32 buf_ptr;
686 struct langwell_dtd *dtd;
687 struct langwell_udc *dev;
688 int i;
689
690 dev = req->ep->dev;
691 VDBG(dev, "---> %s()\n", __func__);
692
693 /* the maximum transfer length, up to 16k bytes */
694 *length = min(req->req.length - req->req.actual,
695 (unsigned)DTD_MAX_TRANSFER_LENGTH);
696
697 /* create dTD dma_pool resource */
698 dtd = dma_pool_alloc(dev->dtd_pool, GFP_KERNEL, dma);
699 if (dtd == NULL)
700 return dtd;
701 dtd->dtd_dma = *dma;
702
703 /* initialize buffer page pointers */
704 buf_ptr = (u32)(req->req.dma + req->req.actual);
705 for (i = 0; i < 5; i++)
706 dtd->dtd_buf[i] = cpu_to_le32(buf_ptr + i * PAGE_SIZE);
707
708 req->req.actual += *length;
709
710 /* fill in total bytes with transfer size */
711 dtd->dtd_total = cpu_to_le16(*length);
712 VDBG(dev, "dtd->dtd_total = %d\n", dtd->dtd_total);
713
714 /* set is_last flag if req->req.zero is set or not */
715 if (req->req.zero) {
716 if (*length == 0 || (*length % req->ep->ep.maxpacket) != 0)
717 *is_last = 1;
718 else
719 *is_last = 0;
720 } else if (req->req.length == req->req.actual) {
721 *is_last = 1;
722 } else
723 *is_last = 0;
724
725 if (*is_last == 0)
726 VDBG(dev, "multi-dtd request!\n");
727
728 /* set interrupt on complete bit for the last dTD */
729 if (*is_last && !req->req.no_interrupt)
730 dtd->dtd_ioc = 1;
731
732 /* set multiplier override 0 for non-ISO and non-TX endpoint */
733 dtd->dtd_multo = 0;
734
735 /* set the active bit of status field to 1 */
736 dtd->dtd_status = DTD_STS_ACTIVE;
737 VDBG(dev, "dtd->dtd_status = 0x%02x\n", dtd->dtd_status);
738
739 VDBG(dev, "length = %d, dma addr= 0x%08x\n", *length, (int)*dma);
740 VDBG(dev, "<--- %s()\n", __func__);
741 return dtd;
742}
743
744
745/* generate dTD linked list for a request */
746static int req_to_dtd(struct langwell_request *req)
747{
748 unsigned count;
749 int is_last, is_first = 1;
750 struct langwell_dtd *dtd, *last_dtd = NULL;
751 struct langwell_udc *dev;
752 dma_addr_t dma;
753
754 dev = req->ep->dev;
755 VDBG(dev, "---> %s()\n", __func__);
756 do {
757 dtd = build_dtd(req, &count, &dma, &is_last);
758 if (dtd == NULL)
759 return -ENOMEM;
760
761 if (is_first) {
762 is_first = 0;
763 req->head = dtd;
764 } else {
765 last_dtd->dtd_next = cpu_to_le32(dma);
766 last_dtd->next_dtd_virt = dtd;
767 }
768 last_dtd = dtd;
769 req->dtd_count++;
770 } while (!is_last);
771
772 /* set terminate bit to 1 for the last dTD */
773 dtd->dtd_next = DTD_TERM;
774
775 req->tail = dtd;
776
777 VDBG(dev, "<--- %s()\n", __func__);
778 return 0;
779}
780
781/*-------------------------------------------------------------------------*/
782
783/* queue (submits) an I/O requests to an endpoint */
784static int langwell_ep_queue(struct usb_ep *_ep, struct usb_request *_req,
785 gfp_t gfp_flags)
786{
787 struct langwell_request *req;
788 struct langwell_ep *ep;
789 struct langwell_udc *dev;
790 unsigned long flags;
791 int is_iso = 0, zlflag = 0;
792
793 /* always require a cpu-view buffer */
794 req = container_of(_req, struct langwell_request, req);
795 ep = container_of(_ep, struct langwell_ep, ep);
796
797 if (!_req || !_req->complete || !_req->buf
798 || !list_empty(&req->queue)) {
799 return -EINVAL;
800 }
801
802 if (unlikely(!_ep || !ep->desc))
803 return -EINVAL;
804
805 dev = ep->dev;
806 req->ep = ep;
807 VDBG(dev, "---> %s()\n", __func__);
808
809 if (ep->desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
810 if (req->req.length > ep->ep.maxpacket)
811 return -EMSGSIZE;
812 is_iso = 1;
813 }
814
815 if (unlikely(!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN))
816 return -ESHUTDOWN;
817
818 /* set up dma mapping in case the caller didn't */
819 if (_req->dma == DMA_ADDR_INVALID) {
820 /* WORKAROUND: WARN_ON(size == 0) */
821 if (_req->length == 0) {
822 VDBG(dev, "req->length: 0->1\n");
823 zlflag = 1;
824 _req->length++;
825 }
826
827 _req->dma = dma_map_single(&dev->pdev->dev,
828 _req->buf, _req->length,
829 is_in(ep) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
830 if (zlflag && (_req->length == 1)) {
831 VDBG(dev, "req->length: 1->0\n");
832 zlflag = 0;
833 _req->length = 0;
834 }
835
836 req->mapped = 1;
837 VDBG(dev, "req->mapped = 1\n");
838 } else {
839 dma_sync_single_for_device(&dev->pdev->dev,
840 _req->dma, _req->length,
841 is_in(ep) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
842 req->mapped = 0;
843 VDBG(dev, "req->mapped = 0\n");
844 }
845
846 DBG(dev, "%s queue req %p, len %u, buf %p, dma 0x%08x\n",
847 _ep->name,
848 _req, _req->length, _req->buf, _req->dma);
849
850 _req->status = -EINPROGRESS;
851 _req->actual = 0;
852 req->dtd_count = 0;
853
854 spin_lock_irqsave(&dev->lock, flags);
855
856 /* build and put dTDs to endpoint queue */
857 if (!req_to_dtd(req)) {
858 queue_dtd(ep, req);
859 } else {
860 spin_unlock_irqrestore(&dev->lock, flags);
861 return -ENOMEM;
862 }
863
864 /* update ep0 state */
865 if (ep->ep_num == 0)
866 dev->ep0_state = DATA_STATE_XMIT;
867
868 if (likely(req != NULL)) {
869 list_add_tail(&req->queue, &ep->queue);
870 VDBG(dev, "list_add_tail() \n");
871 }
872
873 spin_unlock_irqrestore(&dev->lock, flags);
874
875 VDBG(dev, "<--- %s()\n", __func__);
876 return 0;
877}
878
879
880/* dequeue (cancels, unlinks) an I/O request from an endpoint */
881static int langwell_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
882{
883 struct langwell_ep *ep;
884 struct langwell_udc *dev;
885 struct langwell_request *req;
886 unsigned long flags;
887 int stopped, ep_num, retval = 0;
888 u32 endptctrl;
889
890 ep = container_of(_ep, struct langwell_ep, ep);
891 dev = ep->dev;
892 VDBG(dev, "---> %s()\n", __func__);
893
894 if (!_ep || !ep->desc || !_req)
895 return -EINVAL;
896
897 if (!dev->driver)
898 return -ESHUTDOWN;
899
900 spin_lock_irqsave(&dev->lock, flags);
901 stopped = ep->stopped;
902
903 /* quiesce dma while we patch the queue */
904 ep->stopped = 1;
905 ep_num = ep->ep_num;
906
907 /* disable endpoint control register */
908 endptctrl = readl(&dev->op_regs->endptctrl[ep_num]);
909 if (is_in(ep))
910 endptctrl &= ~EPCTRL_TXE;
911 else
912 endptctrl &= ~EPCTRL_RXE;
913 writel(endptctrl, &dev->op_regs->endptctrl[ep_num]);
914
915 /* make sure it's still queued on this endpoint */
916 list_for_each_entry(req, &ep->queue, queue) {
917 if (&req->req == _req)
918 break;
919 }
920
921 if (&req->req != _req) {
922 retval = -EINVAL;
923 goto done;
924 }
925
926 /* queue head may be partially complete. */
927 if (ep->queue.next == &req->queue) {
928 DBG(dev, "unlink (%s) dma\n", _ep->name);
929 _req->status = -ECONNRESET;
930 langwell_ep_fifo_flush(&ep->ep);
931
932 /* not the last request in endpoint queue */
933 if (likely(ep->queue.next == &req->queue)) {
934 struct langwell_dqh *dqh;
935 struct langwell_request *next_req;
936
937 dqh = ep->dqh;
938 next_req = list_entry(req->queue.next,
939 struct langwell_request, queue);
940
941 /* point the dQH to the first dTD of next request */
942 writel((u32) next_req->head, &dqh->dqh_current);
943 }
944 } else {
945 struct langwell_request *prev_req;
946
947 prev_req = list_entry(req->queue.prev,
948 struct langwell_request, queue);
949 writel(readl(&req->tail->dtd_next),
950 &prev_req->tail->dtd_next);
951 }
952
953 done(ep, req, -ECONNRESET);
954
955done:
956 /* enable endpoint again */
957 endptctrl = readl(&dev->op_regs->endptctrl[ep_num]);
958 if (is_in(ep))
959 endptctrl |= EPCTRL_TXE;
960 else
961 endptctrl |= EPCTRL_RXE;
962 writel(endptctrl, &dev->op_regs->endptctrl[ep_num]);
963
964 ep->stopped = stopped;
965 spin_unlock_irqrestore(&dev->lock, flags);
966
967 VDBG(dev, "<--- %s()\n", __func__);
968 return retval;
969}
970
971
972/*-------------------------------------------------------------------------*/
973
974/* endpoint set/clear halt */
975static void ep_set_halt(struct langwell_ep *ep, int value)
976{
977 u32 endptctrl = 0;
978 int ep_num;
979 struct langwell_udc *dev = ep->dev;
980 VDBG(dev, "---> %s()\n", __func__);
981
982 ep_num = ep->ep_num;
983 endptctrl = readl(&dev->op_regs->endptctrl[ep_num]);
984
985 /* value: 1 - set halt, 0 - clear halt */
986 if (value) {
987 /* set the stall bit */
988 if (is_in(ep))
989 endptctrl |= EPCTRL_TXS;
990 else
991 endptctrl |= EPCTRL_RXS;
992 } else {
993 /* clear the stall bit and reset data toggle */
994 if (is_in(ep)) {
995 endptctrl &= ~EPCTRL_TXS;
996 endptctrl |= EPCTRL_TXR;
997 } else {
998 endptctrl &= ~EPCTRL_RXS;
999 endptctrl |= EPCTRL_RXR;
1000 }
1001 }
1002
1003 writel(endptctrl, &dev->op_regs->endptctrl[ep_num]);
1004
1005 VDBG(dev, "<--- %s()\n", __func__);
1006}
1007
1008
1009/* set the endpoint halt feature */
1010static int langwell_ep_set_halt(struct usb_ep *_ep, int value)
1011{
1012 struct langwell_ep *ep;
1013 struct langwell_udc *dev;
1014 unsigned long flags;
1015 int retval = 0;
1016
1017 ep = container_of(_ep, struct langwell_ep, ep);
1018 dev = ep->dev;
1019
1020 VDBG(dev, "---> %s()\n", __func__);
1021
1022 if (!_ep || !ep->desc)
1023 return -EINVAL;
1024
1025 if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)
1026 return -ESHUTDOWN;
1027
1028 if (ep->desc && (ep->desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK)
1029 == USB_ENDPOINT_XFER_ISOC)
1030 return -EOPNOTSUPP;
1031
1032 spin_lock_irqsave(&dev->lock, flags);
1033
1034 /*
1035 * attempt to halt IN ep will fail if any transfer requests
1036 * are still queue
1037 */
1038 if (!list_empty(&ep->queue) && is_in(ep) && value) {
1039 /* IN endpoint FIFO holds bytes */
1040 DBG(dev, "%s FIFO holds bytes\n", _ep->name);
1041 retval = -EAGAIN;
1042 goto done;
1043 }
1044
1045 /* endpoint set/clear halt */
1046 if (ep->ep_num) {
1047 ep_set_halt(ep, value);
1048 } else { /* endpoint 0 */
1049 dev->ep0_state = WAIT_FOR_SETUP;
1050 dev->ep0_dir = USB_DIR_OUT;
1051 }
1052done:
1053 spin_unlock_irqrestore(&dev->lock, flags);
1054 DBG(dev, "%s %s halt\n", _ep->name, value ? "set" : "clear");
1055 VDBG(dev, "<--- %s()\n", __func__);
1056 return retval;
1057}
1058
1059
1060/* set the halt feature and ignores clear requests */
1061static int langwell_ep_set_wedge(struct usb_ep *_ep)
1062{
1063 struct langwell_ep *ep;
1064 struct langwell_udc *dev;
1065
1066 ep = container_of(_ep, struct langwell_ep, ep);
1067 dev = ep->dev;
1068
1069 VDBG(dev, "---> %s()\n", __func__);
1070
1071 if (!_ep || !ep->desc)
1072 return -EINVAL;
1073
1074 VDBG(dev, "<--- %s()\n", __func__);
1075 return usb_ep_set_halt(_ep);
1076}
1077
1078
1079/* flush contents of a fifo */
1080static void langwell_ep_fifo_flush(struct usb_ep *_ep)
1081{
1082 struct langwell_ep *ep;
1083 struct langwell_udc *dev;
1084 u32 flush_bit;
1085 unsigned long timeout;
1086
1087 ep = container_of(_ep, struct langwell_ep, ep);
1088 dev = ep->dev;
1089
1090 VDBG(dev, "---> %s()\n", __func__);
1091
1092 if (!_ep || !ep->desc) {
1093 VDBG(dev, "ep or ep->desc is NULL\n");
1094 VDBG(dev, "<--- %s()\n", __func__);
1095 return;
1096 }
1097
1098 VDBG(dev, "%s-%s fifo flush\n", _ep->name, is_in(ep) ? "in" : "out");
1099
1100 /* flush endpoint buffer */
1101 if (ep->ep_num == 0)
1102 flush_bit = (1 << 16) | 1;
1103 else if (is_in(ep))
1104 flush_bit = 1 << (ep->ep_num + 16); /* TX */
1105 else
1106 flush_bit = 1 << ep->ep_num; /* RX */
1107
1108 /* wait until flush complete */
1109 timeout = jiffies + FLUSH_TIMEOUT;
1110 do {
1111 writel(flush_bit, &dev->op_regs->endptflush);
1112 while (readl(&dev->op_regs->endptflush)) {
1113 if (time_after(jiffies, timeout)) {
1114 ERROR(dev, "ep flush timeout\n");
1115 goto done;
1116 }
1117 cpu_relax();
1118 }
1119 } while (readl(&dev->op_regs->endptstat) & flush_bit);
1120done:
1121 VDBG(dev, "<--- %s()\n", __func__);
1122}
1123
1124
1125/* endpoints operations structure */
1126static const struct usb_ep_ops langwell_ep_ops = {
1127
1128 /* configure endpoint, making it usable */
1129 .enable = langwell_ep_enable,
1130
1131 /* endpoint is no longer usable */
1132 .disable = langwell_ep_disable,
1133
1134 /* allocate a request object to use with this endpoint */
1135 .alloc_request = langwell_alloc_request,
1136
1137 /* free a request object */
1138 .free_request = langwell_free_request,
1139
1140 /* queue (submits) an I/O requests to an endpoint */
1141 .queue = langwell_ep_queue,
1142
1143 /* dequeue (cancels, unlinks) an I/O request from an endpoint */
1144 .dequeue = langwell_ep_dequeue,
1145
1146 /* set the endpoint halt feature */
1147 .set_halt = langwell_ep_set_halt,
1148
1149 /* set the halt feature and ignores clear requests */
1150 .set_wedge = langwell_ep_set_wedge,
1151
1152 /* flush contents of a fifo */
1153 .fifo_flush = langwell_ep_fifo_flush,
1154};
1155
1156
1157/*-------------------------------------------------------------------------*/
1158
1159/* device controller usb_gadget_ops structure */
1160
1161/* returns the current frame number */
1162static int langwell_get_frame(struct usb_gadget *_gadget)
1163{
1164 struct langwell_udc *dev;
1165 u16 retval;
1166
1167 if (!_gadget)
1168 return -ENODEV;
1169
1170 dev = container_of(_gadget, struct langwell_udc, gadget);
1171 VDBG(dev, "---> %s()\n", __func__);
1172
1173 retval = readl(&dev->op_regs->frindex) & FRINDEX_MASK;
1174
1175 VDBG(dev, "<--- %s()\n", __func__);
1176 return retval;
1177}
1178
1179
1180/* tries to wake up the host connected to this gadget */
1181static int langwell_wakeup(struct usb_gadget *_gadget)
1182{
1183 struct langwell_udc *dev;
1184 u32 portsc1, devlc;
1185 unsigned long flags;
1186
1187 if (!_gadget)
1188 return 0;
1189
1190 dev = container_of(_gadget, struct langwell_udc, gadget);
1191 VDBG(dev, "---> %s()\n", __func__);
1192
1193 /* Remote Wakeup feature not enabled by host */
1194 if (!dev->remote_wakeup)
1195 return -ENOTSUPP;
1196
1197 spin_lock_irqsave(&dev->lock, flags);
1198
1199 portsc1 = readl(&dev->op_regs->portsc1);
1200 if (!(portsc1 & PORTS_SUSP)) {
1201 spin_unlock_irqrestore(&dev->lock, flags);
1202 return 0;
1203 }
1204
1205 /* LPM L1 to L0, remote wakeup */
1206 if (dev->lpm && dev->lpm_state == LPM_L1) {
1207 portsc1 |= PORTS_SLP;
1208 writel(portsc1, &dev->op_regs->portsc1);
1209 }
1210
1211 /* force port resume */
1212 if (dev->usb_state == USB_STATE_SUSPENDED) {
1213 portsc1 |= PORTS_FPR;
1214 writel(portsc1, &dev->op_regs->portsc1);
1215 }
1216
1217 /* exit PHY low power suspend */
1218 devlc = readl(&dev->op_regs->devlc);
1219 VDBG(dev, "devlc = 0x%08x\n", devlc);
1220 devlc &= ~LPM_PHCD;
1221 writel(devlc, &dev->op_regs->devlc);
1222
1223 spin_unlock_irqrestore(&dev->lock, flags);
1224
1225 VDBG(dev, "<--- %s()\n", __func__);
1226 return 0;
1227}
1228
1229
1230/* notify controller that VBUS is powered or not */
1231static int langwell_vbus_session(struct usb_gadget *_gadget, int is_active)
1232{
1233 struct langwell_udc *dev;
1234 unsigned long flags;
1235 u32 usbcmd;
1236
1237 if (!_gadget)
1238 return -ENODEV;
1239
1240 dev = container_of(_gadget, struct langwell_udc, gadget);
1241 VDBG(dev, "---> %s()\n", __func__);
1242
1243 spin_lock_irqsave(&dev->lock, flags);
1244 VDBG(dev, "VBUS status: %s\n", is_active ? "on" : "off");
1245
1246 dev->vbus_active = (is_active != 0);
1247 if (dev->driver && dev->softconnected && dev->vbus_active) {
1248 usbcmd = readl(&dev->op_regs->usbcmd);
1249 usbcmd |= CMD_RUNSTOP;
1250 writel(usbcmd, &dev->op_regs->usbcmd);
1251 } else {
1252 usbcmd = readl(&dev->op_regs->usbcmd);
1253 usbcmd &= ~CMD_RUNSTOP;
1254 writel(usbcmd, &dev->op_regs->usbcmd);
1255 }
1256
1257 spin_unlock_irqrestore(&dev->lock, flags);
1258
1259 VDBG(dev, "<--- %s()\n", __func__);
1260 return 0;
1261}
1262
1263
1264/* constrain controller's VBUS power usage */
1265static int langwell_vbus_draw(struct usb_gadget *_gadget, unsigned mA)
1266{
1267 struct langwell_udc *dev;
1268
1269 if (!_gadget)
1270 return -ENODEV;
1271
1272 dev = container_of(_gadget, struct langwell_udc, gadget);
1273 VDBG(dev, "---> %s()\n", __func__);
1274
1275 if (dev->transceiver) {
1276 VDBG(dev, "otg_set_power\n");
1277 VDBG(dev, "<--- %s()\n", __func__);
1278 return otg_set_power(dev->transceiver, mA);
1279 }
1280
1281 VDBG(dev, "<--- %s()\n", __func__);
1282 return -ENOTSUPP;
1283}
1284
1285
1286/* D+ pullup, software-controlled connect/disconnect to USB host */
1287static int langwell_pullup(struct usb_gadget *_gadget, int is_on)
1288{
1289 struct langwell_udc *dev;
1290 u32 usbcmd;
1291 unsigned long flags;
1292
1293 if (!_gadget)
1294 return -ENODEV;
1295
1296 dev = container_of(_gadget, struct langwell_udc, gadget);
1297
1298 VDBG(dev, "---> %s()\n", __func__);
1299
1300 spin_lock_irqsave(&dev->lock, flags);
1301 dev->softconnected = (is_on != 0);
1302
1303 if (dev->driver && dev->softconnected && dev->vbus_active) {
1304 usbcmd = readl(&dev->op_regs->usbcmd);
1305 usbcmd |= CMD_RUNSTOP;
1306 writel(usbcmd, &dev->op_regs->usbcmd);
1307 } else {
1308 usbcmd = readl(&dev->op_regs->usbcmd);
1309 usbcmd &= ~CMD_RUNSTOP;
1310 writel(usbcmd, &dev->op_regs->usbcmd);
1311 }
1312 spin_unlock_irqrestore(&dev->lock, flags);
1313
1314 VDBG(dev, "<--- %s()\n", __func__);
1315 return 0;
1316}
1317
1318
1319/* device controller usb_gadget_ops structure */
1320static const struct usb_gadget_ops langwell_ops = {
1321
1322 /* returns the current frame number */
1323 .get_frame = langwell_get_frame,
1324
1325 /* tries to wake up the host connected to this gadget */
1326 .wakeup = langwell_wakeup,
1327
1328 /* set the device selfpowered feature, always selfpowered */
1329 /* .set_selfpowered = langwell_set_selfpowered, */
1330
1331 /* notify controller that VBUS is powered or not */
1332 .vbus_session = langwell_vbus_session,
1333
1334 /* constrain controller's VBUS power usage */
1335 .vbus_draw = langwell_vbus_draw,
1336
1337 /* D+ pullup, software-controlled connect/disconnect to USB host */
1338 .pullup = langwell_pullup,
1339};
1340
1341
1342/*-------------------------------------------------------------------------*/
1343
1344/* device controller operations */
1345
1346/* reset device controller */
1347static int langwell_udc_reset(struct langwell_udc *dev)
1348{
1349 u32 usbcmd, usbmode, devlc, endpointlistaddr;
1350 unsigned long timeout;
1351
1352 if (!dev)
1353 return -EINVAL;
1354
1355 DBG(dev, "---> %s()\n", __func__);
1356
1357 /* set controller to stop state */
1358 usbcmd = readl(&dev->op_regs->usbcmd);
1359 usbcmd &= ~CMD_RUNSTOP;
1360 writel(usbcmd, &dev->op_regs->usbcmd);
1361
1362 /* reset device controller */
1363 usbcmd = readl(&dev->op_regs->usbcmd);
1364 usbcmd |= CMD_RST;
1365 writel(usbcmd, &dev->op_regs->usbcmd);
1366
1367 /* wait for reset to complete */
1368 timeout = jiffies + RESET_TIMEOUT;
1369 while (readl(&dev->op_regs->usbcmd) & CMD_RST) {
1370 if (time_after(jiffies, timeout)) {
1371 ERROR(dev, "device reset timeout\n");
1372 return -ETIMEDOUT;
1373 }
1374 cpu_relax();
1375 }
1376
1377 /* set controller to device mode */
1378 usbmode = readl(&dev->op_regs->usbmode);
1379 usbmode |= MODE_DEVICE;
1380
1381 /* turn setup lockout off, require setup tripwire in usbcmd */
1382 usbmode |= MODE_SLOM;
1383
1384 writel(usbmode, &dev->op_regs->usbmode);
1385 usbmode = readl(&dev->op_regs->usbmode);
1386 VDBG(dev, "usbmode=0x%08x\n", usbmode);
1387
1388 /* Write-Clear setup status */
1389 writel(0, &dev->op_regs->usbsts);
1390
1391 /* if support USB LPM, ACK all LPM token */
1392 if (dev->lpm) {
1393 devlc = readl(&dev->op_regs->devlc);
1394 devlc &= ~LPM_STL; /* don't STALL LPM token */
1395 devlc &= ~LPM_NYT_ACK; /* ACK LPM token */
1396 writel(devlc, &dev->op_regs->devlc);
1397 }
1398
1399 /* fill endpointlistaddr register */
1400 endpointlistaddr = dev->ep_dqh_dma;
1401 endpointlistaddr &= ENDPOINTLISTADDR_MASK;
1402 writel(endpointlistaddr, &dev->op_regs->endpointlistaddr);
1403
1404 VDBG(dev, "dQH base (vir: %p, phy: 0x%08x), endpointlistaddr=0x%08x\n",
1405 dev->ep_dqh, endpointlistaddr,
1406 readl(&dev->op_regs->endpointlistaddr));
1407 DBG(dev, "<--- %s()\n", __func__);
1408 return 0;
1409}
1410
1411
1412/* reinitialize device controller endpoints */
1413static int eps_reinit(struct langwell_udc *dev)
1414{
1415 struct langwell_ep *ep;
1416 char name[14];
1417 int i;
1418
1419 VDBG(dev, "---> %s()\n", __func__);
1420
1421 /* initialize ep0 */
1422 ep = &dev->ep[0];
1423 ep->dev = dev;
1424 strncpy(ep->name, "ep0", sizeof(ep->name));
1425 ep->ep.name = ep->name;
1426 ep->ep.ops = &langwell_ep_ops;
1427 ep->stopped = 0;
1428 ep->ep.maxpacket = EP0_MAX_PKT_SIZE;
1429 ep->ep_num = 0;
1430 ep->desc = &langwell_ep0_desc;
1431 INIT_LIST_HEAD(&ep->queue);
1432
1433 ep->ep_type = USB_ENDPOINT_XFER_CONTROL;
1434
1435 /* initialize other endpoints */
1436 for (i = 2; i < dev->ep_max; i++) {
1437 ep = &dev->ep[i];
1438 if (i % 2)
1439 snprintf(name, sizeof(name), "ep%din", i / 2);
1440 else
1441 snprintf(name, sizeof(name), "ep%dout", i / 2);
1442 ep->dev = dev;
1443 strncpy(ep->name, name, sizeof(ep->name));
1444 ep->ep.name = ep->name;
1445
1446 ep->ep.ops = &langwell_ep_ops;
1447 ep->stopped = 0;
1448 ep->ep.maxpacket = (unsigned short) ~0;
1449 ep->ep_num = i / 2;
1450
1451 INIT_LIST_HEAD(&ep->queue);
1452 list_add_tail(&ep->ep.ep_list, &dev->gadget.ep_list);
1453
1454 ep->dqh = &dev->ep_dqh[i];
1455 }
1456
1457 VDBG(dev, "<--- %s()\n", __func__);
1458 return 0;
1459}
1460
1461
1462/* enable interrupt and set controller to run state */
1463static void langwell_udc_start(struct langwell_udc *dev)
1464{
1465 u32 usbintr, usbcmd;
1466 DBG(dev, "---> %s()\n", __func__);
1467
1468 /* enable interrupts */
1469 usbintr = INTR_ULPIE /* ULPI */
1470 | INTR_SLE /* suspend */
1471 /* | INTR_SRE SOF received */
1472 | INTR_URE /* USB reset */
1473 | INTR_AAE /* async advance */
1474 | INTR_SEE /* system error */
1475 | INTR_FRE /* frame list rollover */
1476 | INTR_PCE /* port change detect */
1477 | INTR_UEE /* USB error interrupt */
1478 | INTR_UE; /* USB interrupt */
1479 writel(usbintr, &dev->op_regs->usbintr);
1480
1481 /* clear stopped bit */
1482 dev->stopped = 0;
1483
1484 /* set controller to run */
1485 usbcmd = readl(&dev->op_regs->usbcmd);
1486 usbcmd |= CMD_RUNSTOP;
1487 writel(usbcmd, &dev->op_regs->usbcmd);
1488
1489 DBG(dev, "<--- %s()\n", __func__);
1490 return;
1491}
1492
1493
1494/* disable interrupt and set controller to stop state */
1495static void langwell_udc_stop(struct langwell_udc *dev)
1496{
1497 u32 usbcmd;
1498
1499 DBG(dev, "---> %s()\n", __func__);
1500
1501 /* disable all interrupts */
1502 writel(0, &dev->op_regs->usbintr);
1503
1504 /* set stopped bit */
1505 dev->stopped = 1;
1506
1507 /* set controller to stop state */
1508 usbcmd = readl(&dev->op_regs->usbcmd);
1509 usbcmd &= ~CMD_RUNSTOP;
1510 writel(usbcmd, &dev->op_regs->usbcmd);
1511
1512 DBG(dev, "<--- %s()\n", __func__);
1513 return;
1514}
1515
1516
1517/* stop all USB activities */
1518static void stop_activity(struct langwell_udc *dev,
1519 struct usb_gadget_driver *driver)
1520{
1521 struct langwell_ep *ep;
1522 DBG(dev, "---> %s()\n", __func__);
1523
1524 nuke(&dev->ep[0], -ESHUTDOWN);
1525
1526 list_for_each_entry(ep, &dev->gadget.ep_list, ep.ep_list) {
1527 nuke(ep, -ESHUTDOWN);
1528 }
1529
1530 /* report disconnect; the driver is already quiesced */
1531 if (driver) {
1532 spin_unlock(&dev->lock);
1533 driver->disconnect(&dev->gadget);
1534 spin_lock(&dev->lock);
1535 }
1536
1537 DBG(dev, "<--- %s()\n", __func__);
1538}
1539
1540
1541/*-------------------------------------------------------------------------*/
1542
1543/* device "function" sysfs attribute file */
1544static ssize_t show_function(struct device *_dev,
1545 struct device_attribute *attr, char *buf)
1546{
1547 struct langwell_udc *dev = the_controller;
1548
1549 if (!dev->driver || !dev->driver->function
1550 || strlen(dev->driver->function) > PAGE_SIZE)
1551 return 0;
1552
1553 return scnprintf(buf, PAGE_SIZE, "%s\n", dev->driver->function);
1554}
1555static DEVICE_ATTR(function, S_IRUGO, show_function, NULL);
1556
1557
1558/* device "langwell_udc" sysfs attribute file */
1559static ssize_t show_langwell_udc(struct device *_dev,
1560 struct device_attribute *attr, char *buf)
1561{
1562 struct langwell_udc *dev = the_controller;
1563 struct langwell_request *req;
1564 struct langwell_ep *ep = NULL;
1565 char *next;
1566 unsigned size;
1567 unsigned t;
1568 unsigned i;
1569 unsigned long flags;
1570 u32 tmp_reg;
1571
1572 next = buf;
1573 size = PAGE_SIZE;
1574 spin_lock_irqsave(&dev->lock, flags);
1575
1576 /* driver basic information */
1577 t = scnprintf(next, size,
1578 DRIVER_DESC "\n"
1579 "%s version: %s\n"
1580 "Gadget driver: %s\n\n",
1581 driver_name, DRIVER_VERSION,
1582 dev->driver ? dev->driver->driver.name : "(none)");
1583 size -= t;
1584 next += t;
1585
1586 /* device registers */
1587 tmp_reg = readl(&dev->op_regs->usbcmd);
1588 t = scnprintf(next, size,
1589 "USBCMD reg:\n"
1590 "SetupTW: %d\n"
1591 "Run/Stop: %s\n\n",
1592 (tmp_reg & CMD_SUTW) ? 1 : 0,
1593 (tmp_reg & CMD_RUNSTOP) ? "Run" : "Stop");
1594 size -= t;
1595 next += t;
1596
1597 tmp_reg = readl(&dev->op_regs->usbsts);
1598 t = scnprintf(next, size,
1599 "USB Status Reg:\n"
1600 "Device Suspend: %d\n"
1601 "Reset Received: %d\n"
1602 "System Error: %s\n"
1603 "USB Error Interrupt: %s\n\n",
1604 (tmp_reg & STS_SLI) ? 1 : 0,
1605 (tmp_reg & STS_URI) ? 1 : 0,
1606 (tmp_reg & STS_SEI) ? "Error" : "No error",
1607 (tmp_reg & STS_UEI) ? "Error detected" : "No error");
1608 size -= t;
1609 next += t;
1610
1611 tmp_reg = readl(&dev->op_regs->usbintr);
1612 t = scnprintf(next, size,
1613 "USB Intrrupt Enable Reg:\n"
1614 "Sleep Enable: %d\n"
1615 "SOF Received Enable: %d\n"
1616 "Reset Enable: %d\n"
1617 "System Error Enable: %d\n"
1618 "Port Change Dectected Enable: %d\n"
1619 "USB Error Intr Enable: %d\n"
1620 "USB Intr Enable: %d\n\n",
1621 (tmp_reg & INTR_SLE) ? 1 : 0,
1622 (tmp_reg & INTR_SRE) ? 1 : 0,
1623 (tmp_reg & INTR_URE) ? 1 : 0,
1624 (tmp_reg & INTR_SEE) ? 1 : 0,
1625 (tmp_reg & INTR_PCE) ? 1 : 0,
1626 (tmp_reg & INTR_UEE) ? 1 : 0,
1627 (tmp_reg & INTR_UE) ? 1 : 0);
1628 size -= t;
1629 next += t;
1630
1631 tmp_reg = readl(&dev->op_regs->frindex);
1632 t = scnprintf(next, size,
1633 "USB Frame Index Reg:\n"
1634 "Frame Number is 0x%08x\n\n",
1635 (tmp_reg & FRINDEX_MASK));
1636 size -= t;
1637 next += t;
1638
1639 tmp_reg = readl(&dev->op_regs->deviceaddr);
1640 t = scnprintf(next, size,
1641 "USB Device Address Reg:\n"
1642 "Device Addr is 0x%x\n\n",
1643 USBADR(tmp_reg));
1644 size -= t;
1645 next += t;
1646
1647 tmp_reg = readl(&dev->op_regs->endpointlistaddr);
1648 t = scnprintf(next, size,
1649 "USB Endpoint List Address Reg:\n"
1650 "Endpoint List Pointer is 0x%x\n\n",
1651 EPBASE(tmp_reg));
1652 size -= t;
1653 next += t;
1654
1655 tmp_reg = readl(&dev->op_regs->portsc1);
1656 t = scnprintf(next, size,
1657 "USB Port Status & Control Reg:\n"
1658 "Port Reset: %s\n"
1659 "Port Suspend Mode: %s\n"
1660 "Over-current Change: %s\n"
1661 "Port Enable/Disable Change: %s\n"
1662 "Port Enabled/Disabled: %s\n"
1663 "Current Connect Status: %s\n\n",
1664 (tmp_reg & PORTS_PR) ? "Reset" : "Not Reset",
1665 (tmp_reg & PORTS_SUSP) ? "Suspend " : "Not Suspend",
1666 (tmp_reg & PORTS_OCC) ? "Detected" : "No",
1667 (tmp_reg & PORTS_PEC) ? "Changed" : "Not Changed",
1668 (tmp_reg & PORTS_PE) ? "Enable" : "Not Correct",
1669 (tmp_reg & PORTS_CCS) ? "Attached" : "Not Attached");
1670 size -= t;
1671 next += t;
1672
1673 tmp_reg = readl(&dev->op_regs->devlc);
1674 t = scnprintf(next, size,
1675 "Device LPM Control Reg:\n"
1676 "Parallel Transceiver : %d\n"
1677 "Serial Transceiver : %d\n"
1678 "Port Speed: %s\n"
1679 "Port Force Full Speed Connenct: %s\n"
1680 "PHY Low Power Suspend Clock Disable: %s\n"
1681 "BmAttributes: %d\n\n",
1682 LPM_PTS(tmp_reg),
1683 (tmp_reg & LPM_STS) ? 1 : 0,
1684 ({
1685 char *s;
1686 switch (LPM_PSPD(tmp_reg)) {
1687 case LPM_SPEED_FULL:
1688 s = "Full Speed"; break;
1689 case LPM_SPEED_LOW:
1690 s = "Low Speed"; break;
1691 case LPM_SPEED_HIGH:
1692 s = "High Speed"; break;
1693 default:
1694 s = "Unknown Speed"; break;
1695 }
1696 s;
1697 }),
1698 (tmp_reg & LPM_PFSC) ? "Force Full Speed" : "Not Force",
1699 (tmp_reg & LPM_PHCD) ? "Disabled" : "Enabled",
1700 LPM_BA(tmp_reg));
1701 size -= t;
1702 next += t;
1703
1704 tmp_reg = readl(&dev->op_regs->usbmode);
1705 t = scnprintf(next, size,
1706 "USB Mode Reg:\n"
1707 "Controller Mode is : %s\n\n", ({
1708 char *s;
1709 switch (MODE_CM(tmp_reg)) {
1710 case MODE_IDLE:
1711 s = "Idle"; break;
1712 case MODE_DEVICE:
1713 s = "Device Controller"; break;
1714 case MODE_HOST:
1715 s = "Host Controller"; break;
1716 default:
1717 s = "None"; break;
1718 }
1719 s;
1720 }));
1721 size -= t;
1722 next += t;
1723
1724 tmp_reg = readl(&dev->op_regs->endptsetupstat);
1725 t = scnprintf(next, size,
1726 "Endpoint Setup Status Reg:\n"
1727 "SETUP on ep 0x%04x\n\n",
1728 tmp_reg & SETUPSTAT_MASK);
1729 size -= t;
1730 next += t;
1731
1732 for (i = 0; i < dev->ep_max / 2; i++) {
1733 tmp_reg = readl(&dev->op_regs->endptctrl[i]);
1734 t = scnprintf(next, size, "EP Ctrl Reg [%d]: 0x%08x\n",
1735 i, tmp_reg);
1736 size -= t;
1737 next += t;
1738 }
1739 tmp_reg = readl(&dev->op_regs->endptprime);
1740 t = scnprintf(next, size, "EP Prime Reg: 0x%08x\n\n", tmp_reg);
1741 size -= t;
1742 next += t;
1743
1744 /* langwell_udc, langwell_ep, langwell_request structure information */
1745 ep = &dev->ep[0];
1746 t = scnprintf(next, size, "%s MaxPacketSize: 0x%x, ep_num: %d\n",
1747 ep->ep.name, ep->ep.maxpacket, ep->ep_num);
1748 size -= t;
1749 next += t;
1750
1751 if (list_empty(&ep->queue)) {
1752 t = scnprintf(next, size, "its req queue is empty\n\n");
1753 size -= t;
1754 next += t;
1755 } else {
1756 list_for_each_entry(req, &ep->queue, queue) {
1757 t = scnprintf(next, size,
1758 "req %p actual 0x%x length 0x%x buf %p\n",
1759 &req->req, req->req.actual,
1760 req->req.length, req->req.buf);
1761 size -= t;
1762 next += t;
1763 }
1764 }
1765 /* other gadget->eplist ep */
1766 list_for_each_entry(ep, &dev->gadget.ep_list, ep.ep_list) {
1767 if (ep->desc) {
1768 t = scnprintf(next, size,
1769 "\n%s MaxPacketSize: 0x%x, "
1770 "ep_num: %d\n",
1771 ep->ep.name, ep->ep.maxpacket,
1772 ep->ep_num);
1773 size -= t;
1774 next += t;
1775
1776 if (list_empty(&ep->queue)) {
1777 t = scnprintf(next, size,
1778 "its req queue is empty\n\n");
1779 size -= t;
1780 next += t;
1781 } else {
1782 list_for_each_entry(req, &ep->queue, queue) {
1783 t = scnprintf(next, size,
1784 "req %p actual 0x%x length "
1785 "0x%x buf %p\n",
1786 &req->req, req->req.actual,
1787 req->req.length, req->req.buf);
1788 size -= t;
1789 next += t;
1790 }
1791 }
1792 }
1793 }
1794
1795 spin_unlock_irqrestore(&dev->lock, flags);
1796 return PAGE_SIZE - size;
1797}
1798static DEVICE_ATTR(langwell_udc, S_IRUGO, show_langwell_udc, NULL);
1799
1800
1801/*-------------------------------------------------------------------------*/
1802
1803/*
1804 * when a driver is successfully registered, it will receive
1805 * control requests including set_configuration(), which enables
1806 * non-control requests. then usb traffic follows until a
1807 * disconnect is reported. then a host may connect again, or
1808 * the driver might get unbound.
1809 */
1810
1811int usb_gadget_register_driver(struct usb_gadget_driver *driver)
1812{
1813 struct langwell_udc *dev = the_controller;
1814 unsigned long flags;
1815 int retval;
1816
1817 if (!dev)
1818 return -ENODEV;
1819
1820 DBG(dev, "---> %s()\n", __func__);
1821
1822 if (dev->driver)
1823 return -EBUSY;
1824
1825 spin_lock_irqsave(&dev->lock, flags);
1826
1827 /* hook up the driver ... */
1828 driver->driver.bus = NULL;
1829 dev->driver = driver;
1830 dev->gadget.dev.driver = &driver->driver;
1831
1832 spin_unlock_irqrestore(&dev->lock, flags);
1833
1834 retval = driver->bind(&dev->gadget);
1835 if (retval) {
1836 DBG(dev, "bind to driver %s --> %d\n",
1837 driver->driver.name, retval);
1838 dev->driver = NULL;
1839 dev->gadget.dev.driver = NULL;
1840 return retval;
1841 }
1842
1843 retval = device_create_file(&dev->pdev->dev, &dev_attr_function);
1844 if (retval)
1845 goto err_unbind;
1846
1847 dev->usb_state = USB_STATE_ATTACHED;
1848 dev->ep0_state = WAIT_FOR_SETUP;
1849 dev->ep0_dir = USB_DIR_OUT;
1850
1851 /* enable interrupt and set controller to run state */
1852 if (dev->got_irq)
1853 langwell_udc_start(dev);
1854
1855 VDBG(dev, "After langwell_udc_start(), print all registers:\n");
1856#ifdef VERBOSE
1857 print_all_registers(dev);
1858#endif
1859
1860 INFO(dev, "register driver: %s\n", driver->driver.name);
1861 VDBG(dev, "<--- %s()\n", __func__);
1862 return 0;
1863
1864err_unbind:
1865 driver->unbind(&dev->gadget);
1866 dev->gadget.dev.driver = NULL;
1867 dev->driver = NULL;
1868
1869 DBG(dev, "<--- %s()\n", __func__);
1870 return retval;
1871}
1872EXPORT_SYMBOL(usb_gadget_register_driver);
1873
1874
1875/* unregister gadget driver */
1876int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
1877{
1878 struct langwell_udc *dev = the_controller;
1879 unsigned long flags;
1880
1881 if (!dev)
1882 return -ENODEV;
1883
1884 DBG(dev, "---> %s()\n", __func__);
1885
1886 if (unlikely(!driver || !driver->bind || !driver->unbind))
1887 return -EINVAL;
1888
1889 /* unbind OTG transceiver */
1890 if (dev->transceiver)
1891 (void)otg_set_peripheral(dev->transceiver, 0);
1892
1893 /* disable interrupt and set controller to stop state */
1894 langwell_udc_stop(dev);
1895
1896 dev->usb_state = USB_STATE_ATTACHED;
1897 dev->ep0_state = WAIT_FOR_SETUP;
1898 dev->ep0_dir = USB_DIR_OUT;
1899
1900 spin_lock_irqsave(&dev->lock, flags);
1901
1902 /* stop all usb activities */
1903 dev->gadget.speed = USB_SPEED_UNKNOWN;
1904 stop_activity(dev, driver);
1905 spin_unlock_irqrestore(&dev->lock, flags);
1906
1907 /* unbind gadget driver */
1908 driver->unbind(&dev->gadget);
1909 dev->gadget.dev.driver = NULL;
1910 dev->driver = NULL;
1911
1912 device_remove_file(&dev->pdev->dev, &dev_attr_function);
1913
1914 INFO(dev, "unregistered driver '%s'\n", driver->driver.name);
1915 DBG(dev, "<--- %s()\n", __func__);
1916 return 0;
1917}
1918EXPORT_SYMBOL(usb_gadget_unregister_driver);
1919
1920
1921/*-------------------------------------------------------------------------*/
1922
1923/*
1924 * setup tripwire is used as a semaphore to ensure that the setup data
1925 * payload is extracted from a dQH without being corrupted
1926 */
1927static void setup_tripwire(struct langwell_udc *dev)
1928{
1929 u32 usbcmd,
1930 endptsetupstat;
1931 unsigned long timeout;
1932 struct langwell_dqh *dqh;
1933
1934 VDBG(dev, "---> %s()\n", __func__);
1935
1936 /* ep0 OUT dQH */
1937 dqh = &dev->ep_dqh[EP_DIR_OUT];
1938
1939 /* Write-Clear endptsetupstat */
1940 endptsetupstat = readl(&dev->op_regs->endptsetupstat);
1941 writel(endptsetupstat, &dev->op_regs->endptsetupstat);
1942
1943 /* wait until endptsetupstat is cleared */
1944 timeout = jiffies + SETUPSTAT_TIMEOUT;
1945 while (readl(&dev->op_regs->endptsetupstat)) {
1946 if (time_after(jiffies, timeout)) {
1947 ERROR(dev, "setup_tripwire timeout\n");
1948 break;
1949 }
1950 cpu_relax();
1951 }
1952
1953 /* while a hazard exists when setup packet arrives */
1954 do {
1955 /* set setup tripwire bit */
1956 usbcmd = readl(&dev->op_regs->usbcmd);
1957 writel(usbcmd | CMD_SUTW, &dev->op_regs->usbcmd);
1958
1959 /* copy the setup packet to local buffer */
1960 memcpy(&dev->local_setup_buff, &dqh->dqh_setup, 8);
1961 } while (!(readl(&dev->op_regs->usbcmd) & CMD_SUTW));
1962
1963 /* Write-Clear setup tripwire bit */
1964 usbcmd = readl(&dev->op_regs->usbcmd);
1965 writel(usbcmd & ~CMD_SUTW, &dev->op_regs->usbcmd);
1966
1967 VDBG(dev, "<--- %s()\n", __func__);
1968}
1969
1970
1971/* protocol ep0 stall, will automatically be cleared on new transaction */
1972static void ep0_stall(struct langwell_udc *dev)
1973{
1974 u32 endptctrl;
1975
1976 VDBG(dev, "---> %s()\n", __func__);
1977
1978 /* set TX and RX to stall */
1979 endptctrl = readl(&dev->op_regs->endptctrl[0]);
1980 endptctrl |= EPCTRL_TXS | EPCTRL_RXS;
1981 writel(endptctrl, &dev->op_regs->endptctrl[0]);
1982
1983 /* update ep0 state */
1984 dev->ep0_state = WAIT_FOR_SETUP;
1985 dev->ep0_dir = USB_DIR_OUT;
1986
1987 VDBG(dev, "<--- %s()\n", __func__);
1988}
1989
1990
1991/* PRIME a status phase for ep0 */
1992static int prime_status_phase(struct langwell_udc *dev, int dir)
1993{
1994 struct langwell_request *req;
1995 struct langwell_ep *ep;
1996 int status = 0;
1997
1998 VDBG(dev, "---> %s()\n", __func__);
1999
2000 if (dir == EP_DIR_IN)
2001 dev->ep0_dir = USB_DIR_IN;
2002 else
2003 dev->ep0_dir = USB_DIR_OUT;
2004
2005 ep = &dev->ep[0];
2006 dev->ep0_state = WAIT_FOR_OUT_STATUS;
2007
2008 req = dev->status_req;
2009
2010 req->ep = ep;
2011 req->req.length = 0;
2012 req->req.status = -EINPROGRESS;
2013 req->req.actual = 0;
2014 req->req.complete = NULL;
2015 req->dtd_count = 0;
2016
2017 if (!req_to_dtd(req))
2018 status = queue_dtd(ep, req);
2019 else
2020 return -ENOMEM;
2021
2022 if (status)
2023 ERROR(dev, "can't queue ep0 status request\n");
2024
2025 list_add_tail(&req->queue, &ep->queue);
2026
2027 VDBG(dev, "<--- %s()\n", __func__);
2028 return status;
2029}
2030
2031
2032/* SET_ADDRESS request routine */
2033static void set_address(struct langwell_udc *dev, u16 value,
2034 u16 index, u16 length)
2035{
2036 VDBG(dev, "---> %s()\n", __func__);
2037
2038 /* save the new address to device struct */
2039 dev->dev_addr = (u8) value;
2040 VDBG(dev, "dev->dev_addr = %d\n", dev->dev_addr);
2041
2042 /* update usb state */
2043 dev->usb_state = USB_STATE_ADDRESS;
2044
2045 /* STATUS phase */
2046 if (prime_status_phase(dev, EP_DIR_IN))
2047 ep0_stall(dev);
2048
2049 VDBG(dev, "<--- %s()\n", __func__);
2050}
2051
2052
2053/* return endpoint by windex */
2054static struct langwell_ep *get_ep_by_windex(struct langwell_udc *dev,
2055 u16 wIndex)
2056{
2057 struct langwell_ep *ep;
2058 VDBG(dev, "---> %s()\n", __func__);
2059
2060 if ((wIndex & USB_ENDPOINT_NUMBER_MASK) == 0)
2061 return &dev->ep[0];
2062
2063 list_for_each_entry(ep, &dev->gadget.ep_list, ep.ep_list) {
2064 u8 bEndpointAddress;
2065 if (!ep->desc)
2066 continue;
2067
2068 bEndpointAddress = ep->desc->bEndpointAddress;
2069 if ((wIndex ^ bEndpointAddress) & USB_DIR_IN)
2070 continue;
2071
2072 if ((wIndex & USB_ENDPOINT_NUMBER_MASK)
2073 == (bEndpointAddress & USB_ENDPOINT_NUMBER_MASK))
2074 return ep;
2075 }
2076
2077 VDBG(dev, "<--- %s()\n", __func__);
2078 return NULL;
2079}
2080
2081
2082/* return whether endpoint is stalled, 0: not stalled; 1: stalled */
2083static int ep_is_stall(struct langwell_ep *ep)
2084{
2085 struct langwell_udc *dev = ep->dev;
2086 u32 endptctrl;
2087 int retval;
2088
2089 VDBG(dev, "---> %s()\n", __func__);
2090
2091 endptctrl = readl(&dev->op_regs->endptctrl[ep->ep_num]);
2092 if (is_in(ep))
2093 retval = endptctrl & EPCTRL_TXS ? 1 : 0;
2094 else
2095 retval = endptctrl & EPCTRL_RXS ? 1 : 0;
2096
2097 VDBG(dev, "<--- %s()\n", __func__);
2098 return retval;
2099}
2100
2101
2102/* GET_STATUS request routine */
2103static void get_status(struct langwell_udc *dev, u8 request_type, u16 value,
2104 u16 index, u16 length)
2105{
2106 struct langwell_request *req;
2107 struct langwell_ep *ep;
2108 u16 status_data = 0; /* 16 bits cpu view status data */
2109 int status = 0;
2110
2111 VDBG(dev, "---> %s()\n", __func__);
2112
2113 ep = &dev->ep[0];
2114
2115 if ((request_type & USB_RECIP_MASK) == USB_RECIP_DEVICE) {
2116 /* get device status */
2117 status_data = 1 << USB_DEVICE_SELF_POWERED;
2118 status_data |= dev->remote_wakeup << USB_DEVICE_REMOTE_WAKEUP;
2119 } else if ((request_type & USB_RECIP_MASK) == USB_RECIP_INTERFACE) {
2120 /* get interface status */
2121 status_data = 0;
2122 } else if ((request_type & USB_RECIP_MASK) == USB_RECIP_ENDPOINT) {
2123 /* get endpoint status */
2124 struct langwell_ep *epn;
2125 epn = get_ep_by_windex(dev, index);
2126 /* stall if endpoint doesn't exist */
2127 if (!epn)
2128 goto stall;
2129
2130 status_data = ep_is_stall(epn) << USB_ENDPOINT_HALT;
2131 }
2132
2133 dev->ep0_dir = USB_DIR_IN;
2134
2135 /* borrow the per device status_req */
2136 req = dev->status_req;
2137
2138 /* fill in the reqest structure */
2139 *((u16 *) req->req.buf) = cpu_to_le16(status_data);
2140 req->ep = ep;
2141 req->req.length = 2;
2142 req->req.status = -EINPROGRESS;
2143 req->req.actual = 0;
2144 req->req.complete = NULL;
2145 req->dtd_count = 0;
2146
2147 /* prime the data phase */
2148 if (!req_to_dtd(req))
2149 status = queue_dtd(ep, req);
2150 else /* no mem */
2151 goto stall;
2152
2153 if (status) {
2154 ERROR(dev, "response error on GET_STATUS request\n");
2155 goto stall;
2156 }
2157
2158 list_add_tail(&req->queue, &ep->queue);
2159 dev->ep0_state = DATA_STATE_XMIT;
2160
2161 VDBG(dev, "<--- %s()\n", __func__);
2162 return;
2163stall:
2164 ep0_stall(dev);
2165 VDBG(dev, "<--- %s()\n", __func__);
2166}
2167
2168
2169/* setup packet interrupt handler */
2170static void handle_setup_packet(struct langwell_udc *dev,
2171 struct usb_ctrlrequest *setup)
2172{
2173 u16 wValue = le16_to_cpu(setup->wValue);
2174 u16 wIndex = le16_to_cpu(setup->wIndex);
2175 u16 wLength = le16_to_cpu(setup->wLength);
2176
2177 VDBG(dev, "---> %s()\n", __func__);
2178
2179 /* ep0 fifo flush */
2180 nuke(&dev->ep[0], -ESHUTDOWN);
2181
2182 DBG(dev, "SETUP %02x.%02x v%04x i%04x l%04x\n",
2183 setup->bRequestType, setup->bRequest,
2184 wValue, wIndex, wLength);
2185
2186 /* RNDIS gadget delegate */
2187 if ((setup->bRequestType == 0x21) && (setup->bRequest == 0x00)) {
2188 /* USB_CDC_SEND_ENCAPSULATED_COMMAND */
2189 goto delegate;
2190 }
2191
2192 /* USB_CDC_GET_ENCAPSULATED_RESPONSE */
2193 if ((setup->bRequestType == 0xa1) && (setup->bRequest == 0x01)) {
2194 /* USB_CDC_GET_ENCAPSULATED_RESPONSE */
2195 goto delegate;
2196 }
2197
2198 /* We process some stardard setup requests here */
2199 switch (setup->bRequest) {
2200 case USB_REQ_GET_STATUS:
2201 DBG(dev, "SETUP: USB_REQ_GET_STATUS\n");
2202 /* get status, DATA and STATUS phase */
2203 if ((setup->bRequestType & (USB_DIR_IN | USB_TYPE_MASK))
2204 != (USB_DIR_IN | USB_TYPE_STANDARD))
2205 break;
2206 get_status(dev, setup->bRequestType, wValue, wIndex, wLength);
2207 goto end;
2208
2209 case USB_REQ_SET_ADDRESS:
2210 DBG(dev, "SETUP: USB_REQ_SET_ADDRESS\n");
2211 /* STATUS phase */
2212 if (setup->bRequestType != (USB_DIR_OUT | USB_TYPE_STANDARD
2213 | USB_RECIP_DEVICE))
2214 break;
2215 set_address(dev, wValue, wIndex, wLength);
2216 goto end;
2217
2218 case USB_REQ_CLEAR_FEATURE:
2219 case USB_REQ_SET_FEATURE:
2220 /* STATUS phase */
2221 {
2222 int rc = -EOPNOTSUPP;
2223 if (setup->bRequest == USB_REQ_SET_FEATURE)
2224 DBG(dev, "SETUP: USB_REQ_SET_FEATURE\n");
2225 else if (setup->bRequest == USB_REQ_CLEAR_FEATURE)
2226 DBG(dev, "SETUP: USB_REQ_CLEAR_FEATURE\n");
2227
2228 if ((setup->bRequestType & (USB_RECIP_MASK | USB_TYPE_MASK))
2229 == (USB_RECIP_ENDPOINT | USB_TYPE_STANDARD)) {
2230 struct langwell_ep *epn;
2231 epn = get_ep_by_windex(dev, wIndex);
2232 /* stall if endpoint doesn't exist */
2233 if (!epn) {
2234 ep0_stall(dev);
2235 goto end;
2236 }
2237
2238 if (wValue != 0 || wLength != 0
2239 || epn->ep_num > dev->ep_max)
2240 break;
2241
2242 spin_unlock(&dev->lock);
2243 rc = langwell_ep_set_halt(&epn->ep,
2244 (setup->bRequest == USB_REQ_SET_FEATURE)
2245 ? 1 : 0);
2246 spin_lock(&dev->lock);
2247
2248 } else if ((setup->bRequestType & (USB_RECIP_MASK
2249 | USB_TYPE_MASK)) == (USB_RECIP_DEVICE
2250 | USB_TYPE_STANDARD)) {
2251 if (!gadget_is_otg(&dev->gadget))
2252 break;
2253 else if (setup->bRequest == USB_DEVICE_B_HNP_ENABLE) {
2254 dev->gadget.b_hnp_enable = 1;
2255#ifdef OTG_TRANSCEIVER
2256 if (!dev->lotg->otg.default_a)
2257 dev->lotg->hsm.b_hnp_enable = 1;
2258#endif
2259 } else if (setup->bRequest == USB_DEVICE_A_HNP_SUPPORT)
2260 dev->gadget.a_hnp_support = 1;
2261 else if (setup->bRequest ==
2262 USB_DEVICE_A_ALT_HNP_SUPPORT)
2263 dev->gadget.a_alt_hnp_support = 1;
2264 else
2265 break;
2266 rc = 0;
2267 } else
2268 break;
2269
2270 if (rc == 0) {
2271 if (prime_status_phase(dev, EP_DIR_IN))
2272 ep0_stall(dev);
2273 }
2274 goto end;
2275 }
2276
2277 case USB_REQ_GET_DESCRIPTOR:
2278 DBG(dev, "SETUP: USB_REQ_GET_DESCRIPTOR\n");
2279 goto delegate;
2280
2281 case USB_REQ_SET_DESCRIPTOR:
2282 DBG(dev, "SETUP: USB_REQ_SET_DESCRIPTOR unsupported\n");
2283 goto delegate;
2284
2285 case USB_REQ_GET_CONFIGURATION:
2286 DBG(dev, "SETUP: USB_REQ_GET_CONFIGURATION\n");
2287 goto delegate;
2288
2289 case USB_REQ_SET_CONFIGURATION:
2290 DBG(dev, "SETUP: USB_REQ_SET_CONFIGURATION\n");
2291 goto delegate;
2292
2293 case USB_REQ_GET_INTERFACE:
2294 DBG(dev, "SETUP: USB_REQ_GET_INTERFACE\n");
2295 goto delegate;
2296
2297 case USB_REQ_SET_INTERFACE:
2298 DBG(dev, "SETUP: USB_REQ_SET_INTERFACE\n");
2299 goto delegate;
2300
2301 case USB_REQ_SYNCH_FRAME:
2302 DBG(dev, "SETUP: USB_REQ_SYNCH_FRAME unsupported\n");
2303 goto delegate;
2304
2305 default:
2306 /* delegate USB standard requests to the gadget driver */
2307 goto delegate;
2308delegate:
2309 /* USB requests handled by gadget */
2310 if (wLength) {
2311 /* DATA phase from gadget, STATUS phase from udc */
2312 dev->ep0_dir = (setup->bRequestType & USB_DIR_IN)
2313 ? USB_DIR_IN : USB_DIR_OUT;
2314 VDBG(dev, "dev->ep0_dir = 0x%x, wLength = %d\n",
2315 dev->ep0_dir, wLength);
2316 spin_unlock(&dev->lock);
2317 if (dev->driver->setup(&dev->gadget,
2318 &dev->local_setup_buff) < 0)
2319 ep0_stall(dev);
2320 spin_lock(&dev->lock);
2321 dev->ep0_state = (setup->bRequestType & USB_DIR_IN)
2322 ? DATA_STATE_XMIT : DATA_STATE_RECV;
2323 } else {
2324 /* no DATA phase, IN STATUS phase from gadget */
2325 dev->ep0_dir = USB_DIR_IN;
2326 VDBG(dev, "dev->ep0_dir = 0x%x, wLength = %d\n",
2327 dev->ep0_dir, wLength);
2328 spin_unlock(&dev->lock);
2329 if (dev->driver->setup(&dev->gadget,
2330 &dev->local_setup_buff) < 0)
2331 ep0_stall(dev);
2332 spin_lock(&dev->lock);
2333 dev->ep0_state = WAIT_FOR_OUT_STATUS;
2334 }
2335 break;
2336 }
2337end:
2338 VDBG(dev, "<--- %s()\n", __func__);
2339 return;
2340}
2341
2342
2343/* transfer completion, process endpoint request and free the completed dTDs
2344 * for this request
2345 */
2346static int process_ep_req(struct langwell_udc *dev, int index,
2347 struct langwell_request *curr_req)
2348{
2349 struct langwell_dtd *curr_dtd;
2350 struct langwell_dqh *curr_dqh;
2351 int td_complete, actual, remaining_length;
2352 int i, dir;
2353 u8 dtd_status = 0;
2354 int retval = 0;
2355
2356 curr_dqh = &dev->ep_dqh[index];
2357 dir = index % 2;
2358
2359 curr_dtd = curr_req->head;
2360 td_complete = 0;
2361 actual = curr_req->req.length;
2362
2363 VDBG(dev, "---> %s()\n", __func__);
2364
2365 for (i = 0; i < curr_req->dtd_count; i++) {
2366 remaining_length = le16_to_cpu(curr_dtd->dtd_total);
2367 actual -= remaining_length;
2368
2369 /* command execution states by dTD */
2370 dtd_status = curr_dtd->dtd_status;
2371
2372 if (!dtd_status) {
2373 /* transfers completed successfully */
2374 if (!remaining_length) {
2375 td_complete++;
2376 VDBG(dev, "dTD transmitted successfully\n");
2377 } else {
2378 if (dir) {
2379 VDBG(dev, "TX dTD remains data\n");
2380 retval = -EPROTO;
2381 break;
2382
2383 } else {
2384 td_complete++;
2385 break;
2386 }
2387 }
2388 } else {
2389 /* transfers completed with errors */
2390 if (dtd_status & DTD_STS_ACTIVE) {
2391 DBG(dev, "request not completed\n");
2392 retval = 1;
2393 return retval;
2394 } else if (dtd_status & DTD_STS_HALTED) {
2395 ERROR(dev, "dTD error %08x dQH[%d]\n",
2396 dtd_status, index);
2397 /* clear the errors and halt condition */
2398 curr_dqh->dtd_status = 0;
2399 retval = -EPIPE;
2400 break;
2401 } else if (dtd_status & DTD_STS_DBE) {
2402 DBG(dev, "data buffer (overflow) error\n");
2403 retval = -EPROTO;
2404 break;
2405 } else if (dtd_status & DTD_STS_TRE) {
2406 DBG(dev, "transaction(ISO) error\n");
2407 retval = -EILSEQ;
2408 break;
2409 } else
2410 ERROR(dev, "unknown error (0x%x)!\n",
2411 dtd_status);
2412 }
2413
2414 if (i != curr_req->dtd_count - 1)
2415 curr_dtd = (struct langwell_dtd *)
2416 curr_dtd->next_dtd_virt;
2417 }
2418
2419 if (retval)
2420 return retval;
2421
2422 curr_req->req.actual = actual;
2423
2424 VDBG(dev, "<--- %s()\n", __func__);
2425 return 0;
2426}
2427
2428
2429/* complete DATA or STATUS phase of ep0 prime status phase if needed */
2430static void ep0_req_complete(struct langwell_udc *dev,
2431 struct langwell_ep *ep0, struct langwell_request *req)
2432{
2433 u32 new_addr;
2434 VDBG(dev, "---> %s()\n", __func__);
2435
2436 if (dev->usb_state == USB_STATE_ADDRESS) {
2437 /* set the new address */
2438 new_addr = (u32)dev->dev_addr;
2439 writel(new_addr << USBADR_SHIFT, &dev->op_regs->deviceaddr);
2440
2441 new_addr = USBADR(readl(&dev->op_regs->deviceaddr));
2442 VDBG(dev, "new_addr = %d\n", new_addr);
2443 }
2444
2445 done(ep0, req, 0);
2446
2447 switch (dev->ep0_state) {
2448 case DATA_STATE_XMIT:
2449 /* receive status phase */
2450 if (prime_status_phase(dev, EP_DIR_OUT))
2451 ep0_stall(dev);
2452 break;
2453 case DATA_STATE_RECV:
2454 /* send status phase */
2455 if (prime_status_phase(dev, EP_DIR_IN))
2456 ep0_stall(dev);
2457 break;
2458 case WAIT_FOR_OUT_STATUS:
2459 dev->ep0_state = WAIT_FOR_SETUP;
2460 break;
2461 case WAIT_FOR_SETUP:
2462 ERROR(dev, "unexpect ep0 packets\n");
2463 break;
2464 default:
2465 ep0_stall(dev);
2466 break;
2467 }
2468
2469 VDBG(dev, "<--- %s()\n", __func__);
2470}
2471
2472
2473/* USB transfer completion interrupt */
2474static void handle_trans_complete(struct langwell_udc *dev)
2475{
2476 u32 complete_bits;
2477 int i, ep_num, dir, bit_mask, status;
2478 struct langwell_ep *epn;
2479 struct langwell_request *curr_req, *temp_req;
2480
2481 VDBG(dev, "---> %s()\n", __func__);
2482
2483 complete_bits = readl(&dev->op_regs->endptcomplete);
2484 VDBG(dev, "endptcomplete register: 0x%08x\n", complete_bits);
2485
2486 /* Write-Clear the bits in endptcomplete register */
2487 writel(complete_bits, &dev->op_regs->endptcomplete);
2488
2489 if (!complete_bits) {
2490 DBG(dev, "complete_bits = 0\n");
2491 goto done;
2492 }
2493
2494 for (i = 0; i < dev->ep_max; i++) {
2495 ep_num = i / 2;
2496 dir = i % 2;
2497
2498 bit_mask = 1 << (ep_num + 16 * dir);
2499
2500 if (!(complete_bits & bit_mask))
2501 continue;
2502
2503 /* ep0 */
2504 if (i == 1)
2505 epn = &dev->ep[0];
2506 else
2507 epn = &dev->ep[i];
2508
2509 if (epn->name == NULL) {
2510 WARNING(dev, "invalid endpoint\n");
2511 continue;
2512 }
2513
2514 if (i < 2)
2515 /* ep0 in and out */
2516 DBG(dev, "%s-%s transfer completed\n",
2517 epn->name,
2518 is_in(epn) ? "in" : "out");
2519 else
2520 DBG(dev, "%s transfer completed\n", epn->name);
2521
2522 /* process the req queue until an uncomplete request */
2523 list_for_each_entry_safe(curr_req, temp_req,
2524 &epn->queue, queue) {
2525 status = process_ep_req(dev, i, curr_req);
2526 VDBG(dev, "%s req status: %d\n", epn->name, status);
2527
2528 if (status)
2529 break;
2530
2531 /* write back status to req */
2532 curr_req->req.status = status;
2533
2534 /* ep0 request completion */
2535 if (ep_num == 0) {
2536 ep0_req_complete(dev, epn, curr_req);
2537 break;
2538 } else {
2539 done(epn, curr_req, status);
2540 }
2541 }
2542 }
2543done:
2544 VDBG(dev, "<--- %s()\n", __func__);
2545 return;
2546}
2547
2548
2549/* port change detect interrupt handler */
2550static void handle_port_change(struct langwell_udc *dev)
2551{
2552 u32 portsc1, devlc;
2553 u32 speed;
2554
2555 VDBG(dev, "---> %s()\n", __func__);
2556
2557 if (dev->bus_reset)
2558 dev->bus_reset = 0;
2559
2560 portsc1 = readl(&dev->op_regs->portsc1);
2561 devlc = readl(&dev->op_regs->devlc);
2562 VDBG(dev, "portsc1 = 0x%08x, devlc = 0x%08x\n",
2563 portsc1, devlc);
2564
2565 /* bus reset is finished */
2566 if (!(portsc1 & PORTS_PR)) {
2567 /* get the speed */
2568 speed = LPM_PSPD(devlc);
2569 switch (speed) {
2570 case LPM_SPEED_HIGH:
2571 dev->gadget.speed = USB_SPEED_HIGH;
2572 break;
2573 case LPM_SPEED_FULL:
2574 dev->gadget.speed = USB_SPEED_FULL;
2575 break;
2576 case LPM_SPEED_LOW:
2577 dev->gadget.speed = USB_SPEED_LOW;
2578 break;
2579 default:
2580 dev->gadget.speed = USB_SPEED_UNKNOWN;
2581 break;
2582 }
2583 VDBG(dev, "speed = %d, dev->gadget.speed = %d\n",
2584 speed, dev->gadget.speed);
2585 }
2586
2587 /* LPM L0 to L1 */
2588 if (dev->lpm && dev->lpm_state == LPM_L0)
2589 if (portsc1 & PORTS_SUSP && portsc1 & PORTS_SLP) {
2590 INFO(dev, "LPM L0 to L1\n");
2591 dev->lpm_state = LPM_L1;
2592 }
2593
2594 /* LPM L1 to L0, force resume or remote wakeup finished */
2595 if (dev->lpm && dev->lpm_state == LPM_L1)
2596 if (!(portsc1 & PORTS_SUSP)) {
2597 if (portsc1 & PORTS_SLP)
2598 INFO(dev, "LPM L1 to L0, force resume\n");
2599 else
2600 INFO(dev, "LPM L1 to L0, remote wakeup\n");
2601
2602 dev->lpm_state = LPM_L0;
2603 }
2604
2605 /* update USB state */
2606 if (!dev->resume_state)
2607 dev->usb_state = USB_STATE_DEFAULT;
2608
2609 VDBG(dev, "<--- %s()\n", __func__);
2610}
2611
2612
2613/* USB reset interrupt handler */
2614static void handle_usb_reset(struct langwell_udc *dev)
2615{
2616 u32 deviceaddr,
2617 endptsetupstat,
2618 endptcomplete;
2619 unsigned long timeout;
2620
2621 VDBG(dev, "---> %s()\n", __func__);
2622
2623 /* Write-Clear the device address */
2624 deviceaddr = readl(&dev->op_regs->deviceaddr);
2625 writel(deviceaddr & ~USBADR_MASK, &dev->op_regs->deviceaddr);
2626
2627 dev->dev_addr = 0;
2628
2629 /* clear usb state */
2630 dev->resume_state = 0;
2631
2632 /* LPM L1 to L0, reset */
2633 if (dev->lpm)
2634 dev->lpm_state = LPM_L0;
2635
2636 dev->ep0_dir = USB_DIR_OUT;
2637 dev->ep0_state = WAIT_FOR_SETUP;
2638 dev->remote_wakeup = 0; /* default to 0 on reset */
2639 dev->gadget.b_hnp_enable = 0;
2640 dev->gadget.a_hnp_support = 0;
2641 dev->gadget.a_alt_hnp_support = 0;
2642
2643 /* Write-Clear all the setup token semaphores */
2644 endptsetupstat = readl(&dev->op_regs->endptsetupstat);
2645 writel(endptsetupstat, &dev->op_regs->endptsetupstat);
2646
2647 /* Write-Clear all the endpoint complete status bits */
2648 endptcomplete = readl(&dev->op_regs->endptcomplete);
2649 writel(endptcomplete, &dev->op_regs->endptcomplete);
2650
2651 /* wait until all endptprime bits cleared */
2652 timeout = jiffies + PRIME_TIMEOUT;
2653 while (readl(&dev->op_regs->endptprime)) {
2654 if (time_after(jiffies, timeout)) {
2655 ERROR(dev, "USB reset timeout\n");
2656 break;
2657 }
2658 cpu_relax();
2659 }
2660
2661 /* write 1s to endptflush register to clear any primed buffers */
2662 writel((u32) ~0, &dev->op_regs->endptflush);
2663
2664 if (readl(&dev->op_regs->portsc1) & PORTS_PR) {
2665 VDBG(dev, "USB bus reset\n");
2666 /* bus is reseting */
2667 dev->bus_reset = 1;
2668
2669 /* reset all the queues, stop all USB activities */
2670 stop_activity(dev, dev->driver);
2671 dev->usb_state = USB_STATE_DEFAULT;
2672 } else {
2673 VDBG(dev, "device controller reset\n");
2674 /* controller reset */
2675 langwell_udc_reset(dev);
2676
2677 /* reset all the queues, stop all USB activities */
2678 stop_activity(dev, dev->driver);
2679
2680 /* reset ep0 dQH and endptctrl */
2681 ep0_reset(dev);
2682
2683 /* enable interrupt and set controller to run state */
2684 langwell_udc_start(dev);
2685
2686 dev->usb_state = USB_STATE_ATTACHED;
2687 }
2688
2689#ifdef OTG_TRANSCEIVER
2690 /* refer to USB OTG 6.6.2.3 b_hnp_en is cleared */
2691 if (!dev->lotg->otg.default_a)
2692 dev->lotg->hsm.b_hnp_enable = 0;
2693#endif
2694
2695 VDBG(dev, "<--- %s()\n", __func__);
2696}
2697
2698
2699/* USB bus suspend/resume interrupt */
2700static void handle_bus_suspend(struct langwell_udc *dev)
2701{
2702 u32 devlc;
2703 DBG(dev, "---> %s()\n", __func__);
2704
2705 dev->resume_state = dev->usb_state;
2706 dev->usb_state = USB_STATE_SUSPENDED;
2707
2708#ifdef OTG_TRANSCEIVER
2709 if (dev->lotg->otg.default_a) {
2710 if (dev->lotg->hsm.b_bus_suspend_vld == 1) {
2711 dev->lotg->hsm.b_bus_suspend = 1;
2712 /* notify transceiver the state changes */
2713 if (spin_trylock(&dev->lotg->wq_lock)) {
2714 langwell_update_transceiver();
2715 spin_unlock(&dev->lotg->wq_lock);
2716 }
2717 }
2718 dev->lotg->hsm.b_bus_suspend_vld++;
2719 } else {
2720 if (!dev->lotg->hsm.a_bus_suspend) {
2721 dev->lotg->hsm.a_bus_suspend = 1;
2722 /* notify transceiver the state changes */
2723 if (spin_trylock(&dev->lotg->wq_lock)) {
2724 langwell_update_transceiver();
2725 spin_unlock(&dev->lotg->wq_lock);
2726 }
2727 }
2728 }
2729#endif
2730
2731 /* report suspend to the driver */
2732 if (dev->driver) {
2733 if (dev->driver->suspend) {
2734 spin_unlock(&dev->lock);
2735 dev->driver->suspend(&dev->gadget);
2736 spin_lock(&dev->lock);
2737 DBG(dev, "suspend %s\n", dev->driver->driver.name);
2738 }
2739 }
2740
2741 /* enter PHY low power suspend */
2742 devlc = readl(&dev->op_regs->devlc);
2743 VDBG(dev, "devlc = 0x%08x\n", devlc);
2744 devlc |= LPM_PHCD;
2745 writel(devlc, &dev->op_regs->devlc);
2746
2747 DBG(dev, "<--- %s()\n", __func__);
2748}
2749
2750
2751static void handle_bus_resume(struct langwell_udc *dev)
2752{
2753 u32 devlc;
2754 DBG(dev, "---> %s()\n", __func__);
2755
2756 dev->usb_state = dev->resume_state;
2757 dev->resume_state = 0;
2758
2759 /* exit PHY low power suspend */
2760 devlc = readl(&dev->op_regs->devlc);
2761 VDBG(dev, "devlc = 0x%08x\n", devlc);
2762 devlc &= ~LPM_PHCD;
2763 writel(devlc, &dev->op_regs->devlc);
2764
2765#ifdef OTG_TRANSCEIVER
2766 if (dev->lotg->otg.default_a == 0)
2767 dev->lotg->hsm.a_bus_suspend = 0;
2768#endif
2769
2770 /* report resume to the driver */
2771 if (dev->driver) {
2772 if (dev->driver->resume) {
2773 spin_unlock(&dev->lock);
2774 dev->driver->resume(&dev->gadget);
2775 spin_lock(&dev->lock);
2776 DBG(dev, "resume %s\n", dev->driver->driver.name);
2777 }
2778 }
2779
2780 DBG(dev, "<--- %s()\n", __func__);
2781}
2782
2783
2784/* USB device controller interrupt handler */
2785static irqreturn_t langwell_irq(int irq, void *_dev)
2786{
2787 struct langwell_udc *dev = _dev;
2788 u32 usbsts,
2789 usbintr,
2790 irq_sts,
2791 portsc1;
2792
2793 VDBG(dev, "---> %s()\n", __func__);
2794
2795 if (dev->stopped) {
2796 VDBG(dev, "handle IRQ_NONE\n");
2797 VDBG(dev, "<--- %s()\n", __func__);
2798 return IRQ_NONE;
2799 }
2800
2801 spin_lock(&dev->lock);
2802
2803 /* USB status */
2804 usbsts = readl(&dev->op_regs->usbsts);
2805
2806 /* USB interrupt enable */
2807 usbintr = readl(&dev->op_regs->usbintr);
2808
2809 irq_sts = usbsts & usbintr;
2810 VDBG(dev, "usbsts = 0x%08x, usbintr = 0x%08x, irq_sts = 0x%08x\n",
2811 usbsts, usbintr, irq_sts);
2812
2813 if (!irq_sts) {
2814 VDBG(dev, "handle IRQ_NONE\n");
2815 VDBG(dev, "<--- %s()\n", __func__);
2816 spin_unlock(&dev->lock);
2817 return IRQ_NONE;
2818 }
2819
2820 /* Write-Clear interrupt status bits */
2821 writel(irq_sts, &dev->op_regs->usbsts);
2822
2823 /* resume from suspend */
2824 portsc1 = readl(&dev->op_regs->portsc1);
2825 if (dev->usb_state == USB_STATE_SUSPENDED)
2826 if (!(portsc1 & PORTS_SUSP))
2827 handle_bus_resume(dev);
2828
2829 /* USB interrupt */
2830 if (irq_sts & STS_UI) {
2831 VDBG(dev, "USB interrupt\n");
2832
2833 /* setup packet received from ep0 */
2834 if (readl(&dev->op_regs->endptsetupstat)
2835 & EP0SETUPSTAT_MASK) {
2836 VDBG(dev, "USB SETUP packet received interrupt\n");
2837 /* setup tripwire semaphone */
2838 setup_tripwire(dev);
2839 handle_setup_packet(dev, &dev->local_setup_buff);
2840 }
2841
2842 /* USB transfer completion */
2843 if (readl(&dev->op_regs->endptcomplete)) {
2844 VDBG(dev, "USB transfer completion interrupt\n");
2845 handle_trans_complete(dev);
2846 }
2847 }
2848
2849 /* SOF received interrupt (for ISO transfer) */
2850 if (irq_sts & STS_SRI) {
2851 /* FIXME */
2852 /* VDBG(dev, "SOF received interrupt\n"); */
2853 }
2854
2855 /* port change detect interrupt */
2856 if (irq_sts & STS_PCI) {
2857 VDBG(dev, "port change detect interrupt\n");
2858 handle_port_change(dev);
2859 }
2860
2861 /* suspend interrrupt */
2862 if (irq_sts & STS_SLI) {
2863 VDBG(dev, "suspend interrupt\n");
2864 handle_bus_suspend(dev);
2865 }
2866
2867 /* USB reset interrupt */
2868 if (irq_sts & STS_URI) {
2869 VDBG(dev, "USB reset interrupt\n");
2870 handle_usb_reset(dev);
2871 }
2872
2873 /* USB error or system error interrupt */
2874 if (irq_sts & (STS_UEI | STS_SEI)) {
2875 /* FIXME */
2876 WARNING(dev, "error IRQ, irq_sts: %x\n", irq_sts);
2877 }
2878
2879 spin_unlock(&dev->lock);
2880
2881 VDBG(dev, "<--- %s()\n", __func__);
2882 return IRQ_HANDLED;
2883}
2884
2885
2886/*-------------------------------------------------------------------------*/
2887
2888/* release device structure */
2889static void gadget_release(struct device *_dev)
2890{
2891 struct langwell_udc *dev = the_controller;
2892
2893 DBG(dev, "---> %s()\n", __func__);
2894
2895 complete(dev->done);
2896
2897 DBG(dev, "<--- %s()\n", __func__);
2898 kfree(dev);
2899}
2900
2901
2902/* tear down the binding between this driver and the pci device */
2903static void langwell_udc_remove(struct pci_dev *pdev)
2904{
2905 struct langwell_udc *dev = the_controller;
2906
2907 DECLARE_COMPLETION(done);
2908
2909 BUG_ON(dev->driver);
2910 DBG(dev, "---> %s()\n", __func__);
2911
2912 dev->done = &done;
2913
2914 /* free memory allocated in probe */
2915 if (dev->dtd_pool)
2916 dma_pool_destroy(dev->dtd_pool);
2917
2918 if (dev->status_req) {
2919 kfree(dev->status_req->req.buf);
2920 kfree(dev->status_req);
2921 }
2922
2923 if (dev->ep_dqh)
2924 dma_free_coherent(&pdev->dev, dev->ep_dqh_size,
2925 dev->ep_dqh, dev->ep_dqh_dma);
2926
2927 kfree(dev->ep);
2928
2929 /* diable IRQ handler */
2930 if (dev->got_irq)
2931 free_irq(pdev->irq, dev);
2932
2933#ifndef OTG_TRANSCEIVER
2934 if (dev->cap_regs)
2935 iounmap(dev->cap_regs);
2936
2937 if (dev->region)
2938 release_mem_region(pci_resource_start(pdev, 0),
2939 pci_resource_len(pdev, 0));
2940
2941 if (dev->enabled)
2942 pci_disable_device(pdev);
2943#else
2944 if (dev->transceiver) {
2945 otg_put_transceiver(dev->transceiver);
2946 dev->transceiver = NULL;
2947 dev->lotg = NULL;
2948 }
2949#endif
2950
2951 dev->cap_regs = NULL;
2952
2953 INFO(dev, "unbind\n");
2954 DBG(dev, "<--- %s()\n", __func__);
2955
2956 device_unregister(&dev->gadget.dev);
2957 device_remove_file(&pdev->dev, &dev_attr_langwell_udc);
2958
2959#ifndef OTG_TRANSCEIVER
2960 pci_set_drvdata(pdev, NULL);
2961#endif
2962
2963 /* free dev, wait for the release() finished */
2964 wait_for_completion(&done);
2965
2966 the_controller = NULL;
2967}
2968
2969
2970/*
2971 * wrap this driver around the specified device, but
2972 * don't respond over USB until a gadget driver binds to us.
2973 */
2974static int langwell_udc_probe(struct pci_dev *pdev,
2975 const struct pci_device_id *id)
2976{
2977 struct langwell_udc *dev;
2978#ifndef OTG_TRANSCEIVER
2979 unsigned long resource, len;
2980#endif
2981 void __iomem *base = NULL;
2982 size_t size;
2983 int retval;
2984
2985 if (the_controller) {
2986 dev_warn(&pdev->dev, "ignoring\n");
2987 return -EBUSY;
2988 }
2989
2990 /* alloc, and start init */
2991 dev = kzalloc(sizeof *dev, GFP_KERNEL);
2992 if (dev == NULL) {
2993 retval = -ENOMEM;
2994 goto error;
2995 }
2996
2997 /* initialize device spinlock */
2998 spin_lock_init(&dev->lock);
2999
3000 dev->pdev = pdev;
3001 DBG(dev, "---> %s()\n", __func__);
3002
3003#ifdef OTG_TRANSCEIVER
3004 /* PCI device is already enabled by otg_transceiver driver */
3005 dev->enabled = 1;
3006
3007 /* mem region and register base */
3008 dev->region = 1;
3009 dev->transceiver = otg_get_transceiver();
3010 dev->lotg = otg_to_langwell(dev->transceiver);
3011 base = dev->lotg->regs;
3012#else
3013 pci_set_drvdata(pdev, dev);
3014
3015 /* now all the pci goodies ... */
3016 if (pci_enable_device(pdev) < 0) {
3017 retval = -ENODEV;
3018 goto error;
3019 }
3020 dev->enabled = 1;
3021
3022 /* control register: BAR 0 */
3023 resource = pci_resource_start(pdev, 0);
3024 len = pci_resource_len(pdev, 0);
3025 if (!request_mem_region(resource, len, driver_name)) {
3026 ERROR(dev, "controller already in use\n");
3027 retval = -EBUSY;
3028 goto error;
3029 }
3030 dev->region = 1;
3031
3032 base = ioremap_nocache(resource, len);
3033#endif
3034 if (base == NULL) {
3035 ERROR(dev, "can't map memory\n");
3036 retval = -EFAULT;
3037 goto error;
3038 }
3039
3040 dev->cap_regs = (struct langwell_cap_regs __iomem *) base;
3041 VDBG(dev, "dev->cap_regs: %p\n", dev->cap_regs);
3042 dev->op_regs = (struct langwell_op_regs __iomem *)
3043 (base + OP_REG_OFFSET);
3044 VDBG(dev, "dev->op_regs: %p\n", dev->op_regs);
3045
3046 /* irq setup after old hardware is cleaned up */
3047 if (!pdev->irq) {
3048 ERROR(dev, "No IRQ. Check PCI setup!\n");
3049 retval = -ENODEV;
3050 goto error;
3051 }
3052
3053#ifndef OTG_TRANSCEIVER
3054 INFO(dev, "irq %d, io mem: 0x%08lx, len: 0x%08lx, pci mem 0x%p\n",
3055 pdev->irq, resource, len, base);
3056 /* enables bus-mastering for device dev */
3057 pci_set_master(pdev);
3058
3059 if (request_irq(pdev->irq, langwell_irq, IRQF_SHARED,
3060 driver_name, dev) != 0) {
3061 ERROR(dev, "request interrupt %d failed\n", pdev->irq);
3062 retval = -EBUSY;
3063 goto error;
3064 }
3065 dev->got_irq = 1;
3066#endif
3067
3068 /* set stopped bit */
3069 dev->stopped = 1;
3070
3071 /* capabilities and endpoint number */
3072 dev->lpm = (readl(&dev->cap_regs->hccparams) & HCC_LEN) ? 1 : 0;
3073 dev->dciversion = readw(&dev->cap_regs->dciversion);
3074 dev->devcap = (readl(&dev->cap_regs->dccparams) & DEVCAP) ? 1 : 0;
3075 VDBG(dev, "dev->lpm: %d\n", dev->lpm);
3076 VDBG(dev, "dev->dciversion: 0x%04x\n", dev->dciversion);
3077 VDBG(dev, "dccparams: 0x%08x\n", readl(&dev->cap_regs->dccparams));
3078 VDBG(dev, "dev->devcap: %d\n", dev->devcap);
3079 if (!dev->devcap) {
3080 ERROR(dev, "can't support device mode\n");
3081 retval = -ENODEV;
3082 goto error;
3083 }
3084
3085 /* a pair of endpoints (out/in) for each address */
3086 dev->ep_max = DEN(readl(&dev->cap_regs->dccparams)) * 2;
3087 VDBG(dev, "dev->ep_max: %d\n", dev->ep_max);
3088
3089 /* allocate endpoints memory */
3090 dev->ep = kzalloc(sizeof(struct langwell_ep) * dev->ep_max,
3091 GFP_KERNEL);
3092 if (!dev->ep) {
3093 ERROR(dev, "allocate endpoints memory failed\n");
3094 retval = -ENOMEM;
3095 goto error;
3096 }
3097
3098 /* allocate device dQH memory */
3099 size = dev->ep_max * sizeof(struct langwell_dqh);
3100 VDBG(dev, "orig size = %d\n", size);
3101 if (size < DQH_ALIGNMENT)
3102 size = DQH_ALIGNMENT;
3103 else if ((size % DQH_ALIGNMENT) != 0) {
3104 size += DQH_ALIGNMENT + 1;
3105 size &= ~(DQH_ALIGNMENT - 1);
3106 }
3107 dev->ep_dqh = dma_alloc_coherent(&pdev->dev, size,
3108 &dev->ep_dqh_dma, GFP_KERNEL);
3109 if (!dev->ep_dqh) {
3110 ERROR(dev, "allocate dQH memory failed\n");
3111 retval = -ENOMEM;
3112 goto error;
3113 }
3114 dev->ep_dqh_size = size;
3115 VDBG(dev, "ep_dqh_size = %d\n", dev->ep_dqh_size);
3116
3117 /* initialize ep0 status request structure */
3118 dev->status_req = kzalloc(sizeof(struct langwell_request), GFP_KERNEL);
3119 if (!dev->status_req) {
3120 ERROR(dev, "allocate status_req memory failed\n");
3121 retval = -ENOMEM;
3122 goto error;
3123 }
3124 INIT_LIST_HEAD(&dev->status_req->queue);
3125
3126 /* allocate a small amount of memory to get valid address */
3127 dev->status_req->req.buf = kmalloc(8, GFP_KERNEL);
3128 dev->status_req->req.dma = virt_to_phys(dev->status_req->req.buf);
3129
3130 dev->resume_state = USB_STATE_NOTATTACHED;
3131 dev->usb_state = USB_STATE_POWERED;
3132 dev->ep0_dir = USB_DIR_OUT;
3133 dev->remote_wakeup = 0; /* default to 0 on reset */
3134
3135#ifndef OTG_TRANSCEIVER
3136 /* reset device controller */
3137 langwell_udc_reset(dev);
3138#endif
3139
3140 /* initialize gadget structure */
3141 dev->gadget.ops = &langwell_ops; /* usb_gadget_ops */
3142 dev->gadget.ep0 = &dev->ep[0].ep; /* gadget ep0 */
3143 INIT_LIST_HEAD(&dev->gadget.ep_list); /* ep_list */
3144 dev->gadget.speed = USB_SPEED_UNKNOWN; /* speed */
3145 dev->gadget.is_dualspeed = 1; /* support dual speed */
3146#ifdef OTG_TRANSCEIVER
3147 dev->gadget.is_otg = 1; /* support otg mode */
3148#endif
3149
3150 /* the "gadget" abstracts/virtualizes the controller */
3151 dev_set_name(&dev->gadget.dev, "gadget");
3152 dev->gadget.dev.parent = &pdev->dev;
3153 dev->gadget.dev.dma_mask = pdev->dev.dma_mask;
3154 dev->gadget.dev.release = gadget_release;
3155 dev->gadget.name = driver_name; /* gadget name */
3156
3157 /* controller endpoints reinit */
3158 eps_reinit(dev);
3159
3160#ifndef OTG_TRANSCEIVER
3161 /* reset ep0 dQH and endptctrl */
3162 ep0_reset(dev);
3163#endif
3164
3165 /* create dTD dma_pool resource */
3166 dev->dtd_pool = dma_pool_create("langwell_dtd",
3167 &dev->pdev->dev,
3168 sizeof(struct langwell_dtd),
3169 DTD_ALIGNMENT,
3170 DMA_BOUNDARY);
3171
3172 if (!dev->dtd_pool) {
3173 retval = -ENOMEM;
3174 goto error;
3175 }
3176
3177 /* done */
3178 INFO(dev, "%s\n", driver_desc);
3179 INFO(dev, "irq %d, pci mem %p\n", pdev->irq, base);
3180 INFO(dev, "Driver version: " DRIVER_VERSION "\n");
3181 INFO(dev, "Support (max) %d endpoints\n", dev->ep_max);
3182 INFO(dev, "Device interface version: 0x%04x\n", dev->dciversion);
3183 INFO(dev, "Controller mode: %s\n", dev->devcap ? "Device" : "Host");
3184 INFO(dev, "Support USB LPM: %s\n", dev->lpm ? "Yes" : "No");
3185
3186 VDBG(dev, "After langwell_udc_probe(), print all registers:\n");
3187#ifdef VERBOSE
3188 print_all_registers(dev);
3189#endif
3190
3191 the_controller = dev;
3192
3193 retval = device_register(&dev->gadget.dev);
3194 if (retval)
3195 goto error;
3196
3197 retval = device_create_file(&pdev->dev, &dev_attr_langwell_udc);
3198 if (retval)
3199 goto error;
3200
3201 VDBG(dev, "<--- %s()\n", __func__);
3202 return 0;
3203
3204error:
3205 if (dev) {
3206 DBG(dev, "<--- %s()\n", __func__);
3207 langwell_udc_remove(pdev);
3208 }
3209
3210 return retval;
3211}
3212
3213
3214/* device controller suspend */
3215static int langwell_udc_suspend(struct pci_dev *pdev, pm_message_t state)
3216{
3217 struct langwell_udc *dev = the_controller;
3218 u32 devlc;
3219
3220 DBG(dev, "---> %s()\n", __func__);
3221
3222 /* disable interrupt and set controller to stop state */
3223 langwell_udc_stop(dev);
3224
3225 /* diable IRQ handler */
3226 if (dev->got_irq)
3227 free_irq(pdev->irq, dev);
3228 dev->got_irq = 0;
3229
3230
3231 /* save PCI state */
3232 pci_save_state(pdev);
3233
3234 /* set device power state */
3235 pci_set_power_state(pdev, PCI_D3hot);
3236
3237 /* enter PHY low power suspend */
3238 devlc = readl(&dev->op_regs->devlc);
3239 VDBG(dev, "devlc = 0x%08x\n", devlc);
3240 devlc |= LPM_PHCD;
3241 writel(devlc, &dev->op_regs->devlc);
3242
3243 DBG(dev, "<--- %s()\n", __func__);
3244 return 0;
3245}
3246
3247
3248/* device controller resume */
3249static int langwell_udc_resume(struct pci_dev *pdev)
3250{
3251 struct langwell_udc *dev = the_controller;
3252 u32 devlc;
3253
3254 DBG(dev, "---> %s()\n", __func__);
3255
3256 /* exit PHY low power suspend */
3257 devlc = readl(&dev->op_regs->devlc);
3258 VDBG(dev, "devlc = 0x%08x\n", devlc);
3259 devlc &= ~LPM_PHCD;
3260 writel(devlc, &dev->op_regs->devlc);
3261
3262 /* set device D0 power state */
3263 pci_set_power_state(pdev, PCI_D0);
3264
3265 /* restore PCI state */
3266 pci_restore_state(pdev);
3267
3268 /* enable IRQ handler */
3269 if (request_irq(pdev->irq, langwell_irq, IRQF_SHARED, driver_name, dev)
3270 != 0) {
3271 ERROR(dev, "request interrupt %d failed\n", pdev->irq);
3272 return -1;
3273 }
3274 dev->got_irq = 1;
3275
3276 /* reset and start controller to run state */
3277 if (dev->stopped) {
3278 /* reset device controller */
3279 langwell_udc_reset(dev);
3280
3281 /* reset ep0 dQH and endptctrl */
3282 ep0_reset(dev);
3283
3284 /* start device if gadget is loaded */
3285 if (dev->driver)
3286 langwell_udc_start(dev);
3287 }
3288
3289 /* reset USB status */
3290 dev->usb_state = USB_STATE_ATTACHED;
3291 dev->ep0_state = WAIT_FOR_SETUP;
3292 dev->ep0_dir = USB_DIR_OUT;
3293
3294 DBG(dev, "<--- %s()\n", __func__);
3295 return 0;
3296}
3297
3298
3299/* pci driver shutdown */
3300static void langwell_udc_shutdown(struct pci_dev *pdev)
3301{
3302 struct langwell_udc *dev = the_controller;
3303 u32 usbmode;
3304
3305 DBG(dev, "---> %s()\n", __func__);
3306
3307 /* reset controller mode to IDLE */
3308 usbmode = readl(&dev->op_regs->usbmode);
3309 DBG(dev, "usbmode = 0x%08x\n", usbmode);
3310 usbmode &= (~3 | MODE_IDLE);
3311 writel(usbmode, &dev->op_regs->usbmode);
3312
3313 DBG(dev, "<--- %s()\n", __func__);
3314}
3315
3316/*-------------------------------------------------------------------------*/
3317
3318static const struct pci_device_id pci_ids[] = { {
3319 .class = ((PCI_CLASS_SERIAL_USB << 8) | 0xfe),
3320 .class_mask = ~0,
3321 .vendor = 0x8086,
3322 .device = 0x0811,
3323 .subvendor = PCI_ANY_ID,
3324 .subdevice = PCI_ANY_ID,
3325}, { /* end: all zeroes */ }
3326};
3327
3328
3329MODULE_DEVICE_TABLE(pci, pci_ids);
3330
3331
3332static struct pci_driver langwell_pci_driver = {
3333 .name = (char *) driver_name,
3334 .id_table = pci_ids,
3335
3336 .probe = langwell_udc_probe,
3337 .remove = langwell_udc_remove,
3338
3339 /* device controller suspend/resume */
3340 .suspend = langwell_udc_suspend,
3341 .resume = langwell_udc_resume,
3342
3343 .shutdown = langwell_udc_shutdown,
3344};
3345
3346
3347MODULE_DESCRIPTION(DRIVER_DESC);
3348MODULE_AUTHOR("Xiaochen Shen <xiaochen.shen@intel.com>");
3349MODULE_VERSION(DRIVER_VERSION);
3350MODULE_LICENSE("GPL");
3351
3352
3353static int __init init(void)
3354{
3355#ifdef OTG_TRANSCEIVER
3356 return langwell_register_peripheral(&langwell_pci_driver);
3357#else
3358 return pci_register_driver(&langwell_pci_driver);
3359#endif
3360}
3361module_init(init);
3362
3363
3364static void __exit cleanup(void)
3365{
3366#ifdef OTG_TRANSCEIVER
3367 return langwell_unregister_peripheral(&langwell_pci_driver);
3368#else
3369 pci_unregister_driver(&langwell_pci_driver);
3370#endif
3371}
3372module_exit(cleanup);
3373
diff --git a/drivers/usb/gadget/langwell_udc.h b/drivers/usb/gadget/langwell_udc.h
new file mode 100644
index 000000000000..9719934e1c08
--- /dev/null
+++ b/drivers/usb/gadget/langwell_udc.h
@@ -0,0 +1,228 @@
1/*
2 * Intel Langwell USB Device Controller driver
3 * Copyright (C) 2008-2009, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
17 *
18 */
19
20#include <linux/usb/langwell_udc.h>
21
22#if defined(CONFIG_USB_LANGWELL_OTG)
23#include <linux/usb/langwell_otg.h>
24#endif
25
26
27/*-------------------------------------------------------------------------*/
28
29/* driver data structures and utilities */
30
31/*
32 * dTD: Device Endpoint Transfer Descriptor
33 * describe to the device controller the location and quantity of
34 * data to be send/received for given transfer
35 */
36struct langwell_dtd {
37 u32 dtd_next;
38/* bits 31:5, next transfer element pointer */
39#define DTD_NEXT(d) (((d)>>5)&0x7ffffff)
40#define DTD_NEXT_MASK (0x7ffffff << 5)
41/* terminate */
42#define DTD_TERM BIT(0)
43 /* bits 7:0, execution back states */
44 u32 dtd_status:8;
45#define DTD_STATUS(d) (((d)>>0)&0xff)
46#define DTD_STS_ACTIVE BIT(7) /* active */
47#define DTD_STS_HALTED BIT(6) /* halted */
48#define DTD_STS_DBE BIT(5) /* data buffer error */
49#define DTD_STS_TRE BIT(3) /* transaction error */
50 /* bits 9:8 */
51 u32 dtd_res0:2;
52 /* bits 11:10, multipier override */
53 u32 dtd_multo:2;
54#define DTD_MULTO (BIT(11) | BIT(10))
55 /* bits 14:12 */
56 u32 dtd_res1:3;
57 /* bit 15, interrupt on complete */
58 u32 dtd_ioc:1;
59#define DTD_IOC BIT(15)
60 /* bits 30:16, total bytes */
61 u32 dtd_total:15;
62#define DTD_TOTAL(d) (((d)>>16)&0x7fff)
63#define DTD_MAX_TRANSFER_LENGTH 0x4000
64 /* bit 31 */
65 u32 dtd_res2:1;
66 /* dTD buffer pointer page 0 to 4 */
67 u32 dtd_buf[5];
68#define DTD_OFFSET_MASK 0xfff
69/* bits 31:12, buffer pointer */
70#define DTD_BUFFER(d) (((d)>>12)&0x3ff)
71/* bits 11:0, current offset */
72#define DTD_C_OFFSET(d) (((d)>>0)&0xfff)
73/* bits 10:0, frame number */
74#define DTD_FRAME(d) (((d)>>0)&0x7ff)
75
76 /* driver-private parts */
77
78 /* dtd dma address */
79 dma_addr_t dtd_dma;
80 /* next dtd virtual address */
81 struct langwell_dtd *next_dtd_virt;
82};
83
84
85/*
86 * dQH: Device Endpoint Queue Head
87 * describe where all transfers are managed
88 * 48-byte data structure, aligned on 64-byte boundary
89 *
90 * These are associated with dTD structure
91 */
92struct langwell_dqh {
93 /* endpoint capabilities and characteristics */
94 u32 dqh_res0:15; /* bits 14:0 */
95 u32 dqh_ios:1; /* bit 15, interrupt on setup */
96#define DQH_IOS BIT(15)
97 u32 dqh_mpl:11; /* bits 26:16, maximum packet length */
98#define DQH_MPL (0x7ff << 16)
99 u32 dqh_res1:2; /* bits 28:27 */
100 u32 dqh_zlt:1; /* bit 29, zero length termination */
101#define DQH_ZLT BIT(29)
102 u32 dqh_mult:2; /* bits 31:30 */
103#define DQH_MULT (BIT(30) | BIT(31))
104
105 /* current dTD pointer */
106 u32 dqh_current; /* locate the transfer in progress */
107#define DQH_C_DTD(e) \
108 (((e)>>5)&0x7ffffff) /* bits 31:5, current dTD pointer */
109
110 /* transfer overlay, hardware parts of a struct langwell_dtd */
111 u32 dtd_next;
112 u32 dtd_status:8; /* bits 7:0, execution back states */
113 u32 dtd_res0:2; /* bits 9:8 */
114 u32 dtd_multo:2; /* bits 11:10, multipier override */
115 u32 dtd_res1:3; /* bits 14:12 */
116 u32 dtd_ioc:1; /* bit 15, interrupt on complete */
117 u32 dtd_total:15; /* bits 30:16, total bytes */
118 u32 dtd_res2:1; /* bit 31 */
119 u32 dtd_buf[5]; /* dTD buffer pointer page 0 to 4 */
120
121 u32 dqh_res2;
122 struct usb_ctrlrequest dqh_setup; /* setup packet buffer */
123} __attribute__ ((aligned(64)));
124
125
126/* endpoint data structure */
127struct langwell_ep {
128 struct usb_ep ep;
129 dma_addr_t dma;
130 struct langwell_udc *dev;
131 unsigned long irqs;
132 struct list_head queue;
133 struct langwell_dqh *dqh;
134 const struct usb_endpoint_descriptor *desc;
135 char name[14];
136 unsigned stopped:1,
137 ep_type:2,
138 ep_num:8;
139};
140
141
142/* request data structure */
143struct langwell_request {
144 struct usb_request req;
145 struct langwell_dtd *dtd, *head, *tail;
146 struct langwell_ep *ep;
147 dma_addr_t dtd_dma;
148 struct list_head queue;
149 unsigned dtd_count;
150 unsigned mapped:1;
151};
152
153
154/* ep0 transfer state */
155enum ep0_state {
156 WAIT_FOR_SETUP,
157 DATA_STATE_XMIT,
158 DATA_STATE_NEED_ZLP,
159 WAIT_FOR_OUT_STATUS,
160 DATA_STATE_RECV,
161};
162
163
164/* device suspend state */
165enum lpm_state {
166 LPM_L0, /* on */
167 LPM_L1, /* LPM L1 sleep */
168 LPM_L2, /* suspend */
169 LPM_L3, /* off */
170};
171
172
173/* device data structure */
174struct langwell_udc {
175 /* each pci device provides one gadget, several endpoints */
176 struct usb_gadget gadget;
177 spinlock_t lock; /* device lock */
178 struct langwell_ep *ep;
179 struct usb_gadget_driver *driver;
180 struct otg_transceiver *transceiver;
181 u8 dev_addr;
182 u32 usb_state;
183 u32 resume_state;
184 u32 bus_reset;
185 enum lpm_state lpm_state;
186 enum ep0_state ep0_state;
187 u32 ep0_dir;
188 u16 dciversion;
189 unsigned ep_max;
190 unsigned devcap:1,
191 enabled:1,
192 region:1,
193 got_irq:1,
194 powered:1,
195 remote_wakeup:1,
196 rate:1,
197 is_reset:1,
198 softconnected:1,
199 vbus_active:1,
200 suspended:1,
201 stopped:1,
202 lpm:1; /* LPM capability */
203
204 /* pci state used to access those endpoints */
205 struct pci_dev *pdev;
206
207 /* Langwell otg transceiver */
208 struct langwell_otg *lotg;
209
210 /* control registers */
211 struct langwell_cap_regs __iomem *cap_regs;
212 struct langwell_op_regs __iomem *op_regs;
213
214 struct usb_ctrlrequest local_setup_buff;
215 struct langwell_dqh *ep_dqh;
216 size_t ep_dqh_size;
217 dma_addr_t ep_dqh_dma;
218
219 /* ep0 status request */
220 struct langwell_request *status_req;
221
222 /* dma pool */
223 struct dma_pool *dtd_pool;
224
225 /* make sure release() is done */
226 struct completion *done;
227};
228
diff --git a/drivers/usb/gadget/pxa27x_udc.c b/drivers/usb/gadget/pxa27x_udc.c
index 8cc676ecbb23..1937d8c7b433 100644
--- a/drivers/usb/gadget/pxa27x_udc.c
+++ b/drivers/usb/gadget/pxa27x_udc.c
@@ -38,7 +38,6 @@
38#include <linux/usb.h> 38#include <linux/usb.h>
39#include <linux/usb/ch9.h> 39#include <linux/usb/ch9.h>
40#include <linux/usb/gadget.h> 40#include <linux/usb/gadget.h>
41#include <mach/pxa2xx-regs.h> /* FIXME: for PSSR */
42#include <mach/udc.h> 41#include <mach/udc.h>
43 42
44#include "pxa27x_udc.h" 43#include "pxa27x_udc.h"
@@ -474,6 +473,23 @@ static inline void udc_clear_mask_UDCCR(struct pxa_udc *udc, int mask)
474} 473}
475 474
476/** 475/**
476 * ep_write_UDCCSR - set bits in UDCCSR
477 * @udc: udc device
478 * @mask: bits to set in UDCCR
479 *
480 * Sets bits in UDCCSR (UDCCSR0 and UDCCSR*).
481 *
482 * A specific case is applied to ep0 : the ACM bit is always set to 1, for
483 * SET_INTERFACE and SET_CONFIGURATION.
484 */
485static inline void ep_write_UDCCSR(struct pxa_ep *ep, int mask)
486{
487 if (is_ep0(ep))
488 mask |= UDCCSR0_ACM;
489 udc_ep_writel(ep, UDCCSR, mask);
490}
491
492/**
477 * ep_count_bytes_remain - get how many bytes in udc endpoint 493 * ep_count_bytes_remain - get how many bytes in udc endpoint
478 * @ep: udc endpoint 494 * @ep: udc endpoint
479 * 495 *
@@ -861,7 +877,7 @@ static int read_packet(struct pxa_ep *ep, struct pxa27x_request *req)
861 *buf++ = udc_ep_readl(ep, UDCDR); 877 *buf++ = udc_ep_readl(ep, UDCDR);
862 req->req.actual += count; 878 req->req.actual += count;
863 879
864 udc_ep_writel(ep, UDCCSR, UDCCSR_PC); 880 ep_write_UDCCSR(ep, UDCCSR_PC);
865 881
866 return count; 882 return count;
867} 883}
@@ -969,12 +985,12 @@ static int write_fifo(struct pxa_ep *ep, struct pxa27x_request *req)
969 if (udccsr & UDCCSR_PC) { 985 if (udccsr & UDCCSR_PC) {
970 ep_vdbg(ep, "Clearing Transmit Complete, udccsr=%x\n", 986 ep_vdbg(ep, "Clearing Transmit Complete, udccsr=%x\n",
971 udccsr); 987 udccsr);
972 udc_ep_writel(ep, UDCCSR, UDCCSR_PC); 988 ep_write_UDCCSR(ep, UDCCSR_PC);
973 } 989 }
974 if (udccsr & UDCCSR_TRN) { 990 if (udccsr & UDCCSR_TRN) {
975 ep_vdbg(ep, "Clearing Underrun on, udccsr=%x\n", 991 ep_vdbg(ep, "Clearing Underrun on, udccsr=%x\n",
976 udccsr); 992 udccsr);
977 udc_ep_writel(ep, UDCCSR, UDCCSR_TRN); 993 ep_write_UDCCSR(ep, UDCCSR_TRN);
978 } 994 }
979 995
980 count = write_packet(ep, req, max); 996 count = write_packet(ep, req, max);
@@ -996,7 +1012,7 @@ static int write_fifo(struct pxa_ep *ep, struct pxa27x_request *req)
996 } 1012 }
997 1013
998 if (is_short) 1014 if (is_short)
999 udc_ep_writel(ep, UDCCSR, UDCCSR_SP); 1015 ep_write_UDCCSR(ep, UDCCSR_SP);
1000 1016
1001 /* requests complete when all IN data is in the FIFO */ 1017 /* requests complete when all IN data is in the FIFO */
1002 if (is_last) { 1018 if (is_last) {
@@ -1029,7 +1045,7 @@ static int read_ep0_fifo(struct pxa_ep *ep, struct pxa27x_request *req)
1029 1045
1030 while (epout_has_pkt(ep)) { 1046 while (epout_has_pkt(ep)) {
1031 count = read_packet(ep, req); 1047 count = read_packet(ep, req);
1032 udc_ep_writel(ep, UDCCSR, UDCCSR0_OPC); 1048 ep_write_UDCCSR(ep, UDCCSR0_OPC);
1033 inc_ep_stats_bytes(ep, count, !USB_DIR_IN); 1049 inc_ep_stats_bytes(ep, count, !USB_DIR_IN);
1034 1050
1035 is_short = (count < ep->fifo_size); 1051 is_short = (count < ep->fifo_size);
@@ -1074,7 +1090,7 @@ static int write_ep0_fifo(struct pxa_ep *ep, struct pxa27x_request *req)
1074 1090
1075 /* Sends either a short packet or a 0 length packet */ 1091 /* Sends either a short packet or a 0 length packet */
1076 if (unlikely(is_short)) 1092 if (unlikely(is_short))
1077 udc_ep_writel(ep, UDCCSR, UDCCSR0_IPR); 1093 ep_write_UDCCSR(ep, UDCCSR0_IPR);
1078 1094
1079 ep_dbg(ep, "in %d bytes%s%s, %d left, req=%p, udccsr0=0x%03x\n", 1095 ep_dbg(ep, "in %d bytes%s%s, %d left, req=%p, udccsr0=0x%03x\n",
1080 count, is_short ? "/S" : "", is_last ? "/L" : "", 1096 count, is_short ? "/S" : "", is_last ? "/L" : "",
@@ -1277,7 +1293,7 @@ static int pxa_ep_set_halt(struct usb_ep *_ep, int value)
1277 1293
1278 /* FST, FEF bits are the same for control and non control endpoints */ 1294 /* FST, FEF bits are the same for control and non control endpoints */
1279 rc = 0; 1295 rc = 0;
1280 udc_ep_writel(ep, UDCCSR, UDCCSR_FST | UDCCSR_FEF); 1296 ep_write_UDCCSR(ep, UDCCSR_FST | UDCCSR_FEF);
1281 if (is_ep0(ep)) 1297 if (is_ep0(ep))
1282 set_ep0state(ep->dev, STALL); 1298 set_ep0state(ep->dev, STALL);
1283 1299
@@ -1343,7 +1359,7 @@ static void pxa_ep_fifo_flush(struct usb_ep *_ep)
1343 udc_ep_readl(ep, UDCDR); 1359 udc_ep_readl(ep, UDCDR);
1344 } else { 1360 } else {
1345 /* most IN status is the same, but ISO can't stall */ 1361 /* most IN status is the same, but ISO can't stall */
1346 udc_ep_writel(ep, UDCCSR, 1362 ep_write_UDCCSR(ep,
1347 UDCCSR_PC | UDCCSR_FEF | UDCCSR_TRN 1363 UDCCSR_PC | UDCCSR_FEF | UDCCSR_TRN
1348 | (EPXFERTYPE_is_ISO(ep) ? 0 : UDCCSR_SST)); 1364 | (EPXFERTYPE_is_ISO(ep) ? 0 : UDCCSR_SST));
1349 } 1365 }
@@ -1728,6 +1744,7 @@ static void udc_enable(struct pxa_udc *udc)
1728 memset(&udc->stats, 0, sizeof(udc->stats)); 1744 memset(&udc->stats, 0, sizeof(udc->stats));
1729 1745
1730 udc_set_mask_UDCCR(udc, UDCCR_UDE); 1746 udc_set_mask_UDCCR(udc, UDCCR_UDE);
1747 ep_write_UDCCSR(&udc->pxa_ep[0], UDCCSR0_ACM);
1731 udelay(2); 1748 udelay(2);
1732 if (udc_readl(udc, UDCCR) & UDCCR_EMCE) 1749 if (udc_readl(udc, UDCCR) & UDCCR_EMCE)
1733 dev_err(udc->dev, "Configuration errors, udc disabled\n"); 1750 dev_err(udc->dev, "Configuration errors, udc disabled\n");
@@ -1893,6 +1910,15 @@ static void handle_ep0_ctrl_req(struct pxa_udc *udc,
1893 1910
1894 nuke(ep, -EPROTO); 1911 nuke(ep, -EPROTO);
1895 1912
1913 /*
1914 * In the PXA320 manual, in the section about Back-to-Back setup
1915 * packets, it describes this situation. The solution is to set OPC to
1916 * get rid of the status packet, and then continue with the setup
1917 * packet. Generalize to pxa27x CPUs.
1918 */
1919 if (epout_has_pkt(ep) && (ep_count_bytes_remain(ep) == 0))
1920 ep_write_UDCCSR(ep, UDCCSR0_OPC);
1921
1896 /* read SETUP packet */ 1922 /* read SETUP packet */
1897 for (i = 0; i < 2; i++) { 1923 for (i = 0; i < 2; i++) {
1898 if (unlikely(ep_is_empty(ep))) 1924 if (unlikely(ep_is_empty(ep)))
@@ -1919,7 +1945,7 @@ static void handle_ep0_ctrl_req(struct pxa_udc *udc,
1919 set_ep0state(udc, OUT_DATA_STAGE); 1945 set_ep0state(udc, OUT_DATA_STAGE);
1920 1946
1921 /* Tell UDC to enter Data Stage */ 1947 /* Tell UDC to enter Data Stage */
1922 udc_ep_writel(ep, UDCCSR, UDCCSR0_SA | UDCCSR0_OPC); 1948 ep_write_UDCCSR(ep, UDCCSR0_SA | UDCCSR0_OPC);
1923 1949
1924 i = udc->driver->setup(&udc->gadget, &u.r); 1950 i = udc->driver->setup(&udc->gadget, &u.r);
1925 if (i < 0) 1951 if (i < 0)
@@ -1929,7 +1955,7 @@ out:
1929stall: 1955stall:
1930 ep_dbg(ep, "protocol STALL, udccsr0=%03x err %d\n", 1956 ep_dbg(ep, "protocol STALL, udccsr0=%03x err %d\n",
1931 udc_ep_readl(ep, UDCCSR), i); 1957 udc_ep_readl(ep, UDCCSR), i);
1932 udc_ep_writel(ep, UDCCSR, UDCCSR0_FST | UDCCSR0_FTF); 1958 ep_write_UDCCSR(ep, UDCCSR0_FST | UDCCSR0_FTF);
1933 set_ep0state(udc, STALL); 1959 set_ep0state(udc, STALL);
1934 goto out; 1960 goto out;
1935} 1961}
@@ -1966,6 +1992,8 @@ stall:
1966 * cleared by software. 1992 * cleared by software.
1967 * - clearing UDCCSR0_OPC always flushes ep0. If in setup stage, never do it 1993 * - clearing UDCCSR0_OPC always flushes ep0. If in setup stage, never do it
1968 * before reading ep0. 1994 * before reading ep0.
1995 * This is true only for PXA27x. This is not true anymore for PXA3xx family
1996 * (check Back-to-Back setup packet in developers guide).
1969 * - irq can be called on a "packet complete" event (opc_irq=1), while 1997 * - irq can be called on a "packet complete" event (opc_irq=1), while
1970 * UDCCSR0_OPC is not yet raised (delta can be as big as 100ms 1998 * UDCCSR0_OPC is not yet raised (delta can be as big as 100ms
1971 * from experimentation). 1999 * from experimentation).
@@ -1998,7 +2026,7 @@ static void handle_ep0(struct pxa_udc *udc, int fifo_irq, int opc_irq)
1998 if (udccsr0 & UDCCSR0_SST) { 2026 if (udccsr0 & UDCCSR0_SST) {
1999 ep_dbg(ep, "clearing stall status\n"); 2027 ep_dbg(ep, "clearing stall status\n");
2000 nuke(ep, -EPIPE); 2028 nuke(ep, -EPIPE);
2001 udc_ep_writel(ep, UDCCSR, UDCCSR0_SST); 2029 ep_write_UDCCSR(ep, UDCCSR0_SST);
2002 ep0_idle(udc); 2030 ep0_idle(udc);
2003 } 2031 }
2004 2032
@@ -2023,7 +2051,7 @@ static void handle_ep0(struct pxa_udc *udc, int fifo_irq, int opc_irq)
2023 break; 2051 break;
2024 case IN_DATA_STAGE: /* GET_DESCRIPTOR */ 2052 case IN_DATA_STAGE: /* GET_DESCRIPTOR */
2025 if (epout_has_pkt(ep)) 2053 if (epout_has_pkt(ep))
2026 udc_ep_writel(ep, UDCCSR, UDCCSR0_OPC); 2054 ep_write_UDCCSR(ep, UDCCSR0_OPC);
2027 if (req && !ep_is_full(ep)) 2055 if (req && !ep_is_full(ep))
2028 completed = write_ep0_fifo(ep, req); 2056 completed = write_ep0_fifo(ep, req);
2029 if (completed) 2057 if (completed)
@@ -2036,7 +2064,7 @@ static void handle_ep0(struct pxa_udc *udc, int fifo_irq, int opc_irq)
2036 ep0_end_out_req(ep, req); 2064 ep0_end_out_req(ep, req);
2037 break; 2065 break;
2038 case STALL: 2066 case STALL:
2039 udc_ep_writel(ep, UDCCSR, UDCCSR0_FST); 2067 ep_write_UDCCSR(ep, UDCCSR0_FST);
2040 break; 2068 break;
2041 case IN_STATUS_STAGE: 2069 case IN_STATUS_STAGE:
2042 /* 2070 /*
@@ -2131,6 +2159,7 @@ static void pxa27x_change_configuration(struct pxa_udc *udc, int config)
2131 2159
2132 set_ep0state(udc, WAIT_ACK_SET_CONF_INTERF); 2160 set_ep0state(udc, WAIT_ACK_SET_CONF_INTERF);
2133 udc->driver->setup(&udc->gadget, &req); 2161 udc->driver->setup(&udc->gadget, &req);
2162 ep_write_UDCCSR(&udc->pxa_ep[0], UDCCSR0_AREN);
2134} 2163}
2135 2164
2136/** 2165/**
@@ -2159,6 +2188,7 @@ static void pxa27x_change_interface(struct pxa_udc *udc, int iface, int alt)
2159 2188
2160 set_ep0state(udc, WAIT_ACK_SET_CONF_INTERF); 2189 set_ep0state(udc, WAIT_ACK_SET_CONF_INTERF);
2161 udc->driver->setup(&udc->gadget, &req); 2190 udc->driver->setup(&udc->gadget, &req);
2191 ep_write_UDCCSR(&udc->pxa_ep[0], UDCCSR0_AREN);
2162} 2192}
2163 2193
2164/* 2194/*
@@ -2280,7 +2310,7 @@ static void irq_udc_reset(struct pxa_udc *udc)
2280 memset(&udc->stats, 0, sizeof udc->stats); 2310 memset(&udc->stats, 0, sizeof udc->stats);
2281 2311
2282 nuke(ep, -EPROTO); 2312 nuke(ep, -EPROTO);
2283 udc_ep_writel(ep, UDCCSR, UDCCSR0_FTF | UDCCSR0_OPC); 2313 ep_write_UDCCSR(ep, UDCCSR0_FTF | UDCCSR0_OPC);
2284 ep0_idle(udc); 2314 ep0_idle(udc);
2285} 2315}
2286 2316
@@ -2479,6 +2509,12 @@ static void pxa_udc_shutdown(struct platform_device *_dev)
2479 udc_disable(udc); 2509 udc_disable(udc);
2480} 2510}
2481 2511
2512#ifdef CONFIG_CPU_PXA27x
2513extern void pxa27x_clear_otgph(void);
2514#else
2515#define pxa27x_clear_otgph() do {} while (0)
2516#endif
2517
2482#ifdef CONFIG_PM 2518#ifdef CONFIG_PM
2483/** 2519/**
2484 * pxa_udc_suspend - Suspend udc device 2520 * pxa_udc_suspend - Suspend udc device
@@ -2546,8 +2582,7 @@ static int pxa_udc_resume(struct platform_device *_dev)
2546 * Software must configure the USB OTG pad, UDC, and UHC 2582 * Software must configure the USB OTG pad, UDC, and UHC
2547 * to the state they were in before entering sleep mode. 2583 * to the state they were in before entering sleep mode.
2548 */ 2584 */
2549 if (cpu_is_pxa27x()) 2585 pxa27x_clear_otgph();
2550 PSSR |= PSSR_OTGPH;
2551 2586
2552 return 0; 2587 return 0;
2553} 2588}
@@ -2571,7 +2606,7 @@ static struct platform_driver udc_driver = {
2571 2606
2572static int __init udc_init(void) 2607static int __init udc_init(void)
2573{ 2608{
2574 if (!cpu_is_pxa27x()) 2609 if (!cpu_is_pxa27x() && !cpu_is_pxa3xx())
2575 return -ENODEV; 2610 return -ENODEV;
2576 2611
2577 printk(KERN_INFO "%s: version %s\n", driver_name, DRIVER_VERSION); 2612 printk(KERN_INFO "%s: version %s\n", driver_name, DRIVER_VERSION);
diff --git a/drivers/usb/gadget/pxa27x_udc.h b/drivers/usb/gadget/pxa27x_udc.h
index db58125331da..e25225e26586 100644
--- a/drivers/usb/gadget/pxa27x_udc.h
+++ b/drivers/usb/gadget/pxa27x_udc.h
@@ -130,6 +130,8 @@
130#define UP2OCR_HXOE (1 << 17) /* Transceiver Output Enable */ 130#define UP2OCR_HXOE (1 << 17) /* Transceiver Output Enable */
131#define UP2OCR_SEOS (1 << 24) /* Single-Ended Output Select */ 131#define UP2OCR_SEOS (1 << 24) /* Single-Ended Output Select */
132 132
133#define UDCCSR0_ACM (1 << 9) /* Ack Control Mode */
134#define UDCCSR0_AREN (1 << 8) /* Ack Response Enable */
133#define UDCCSR0_SA (1 << 7) /* Setup Active */ 135#define UDCCSR0_SA (1 << 7) /* Setup Active */
134#define UDCCSR0_RNE (1 << 6) /* Receive FIFO Not Empty */ 136#define UDCCSR0_RNE (1 << 6) /* Receive FIFO Not Empty */
135#define UDCCSR0_FST (1 << 5) /* Force Stall */ 137#define UDCCSR0_FST (1 << 5) /* Force Stall */
diff --git a/drivers/usb/gadget/s3c-hsotg.c b/drivers/usb/gadget/s3c-hsotg.c
new file mode 100644
index 000000000000..50c71aae2cc2
--- /dev/null
+++ b/drivers/usb/gadget/s3c-hsotg.c
@@ -0,0 +1,3269 @@
1/* linux/drivers/usb/gadget/s3c-hsotg.c
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * S3C USB2.0 High-speed / OtG driver
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#include <linux/kernel.h>
16#include <linux/module.h>
17#include <linux/spinlock.h>
18#include <linux/interrupt.h>
19#include <linux/platform_device.h>
20#include <linux/dma-mapping.h>
21#include <linux/debugfs.h>
22#include <linux/seq_file.h>
23#include <linux/delay.h>
24#include <linux/io.h>
25
26#include <linux/usb/ch9.h>
27#include <linux/usb/gadget.h>
28
29#include <mach/map.h>
30
31#include <plat/regs-usb-hsotg-phy.h>
32#include <plat/regs-usb-hsotg.h>
33#include <plat/regs-sys.h>
34#include <plat/udc-hs.h>
35
36#define DMA_ADDR_INVALID (~((dma_addr_t)0))
37
38/* EP0_MPS_LIMIT
39 *
40 * Unfortunately there seems to be a limit of the amount of data that can
41 * be transfered by IN transactions on EP0. This is either 127 bytes or 3
42 * packets (which practially means 1 packet and 63 bytes of data) when the
43 * MPS is set to 64.
44 *
45 * This means if we are wanting to move >127 bytes of data, we need to
46 * split the transactions up, but just doing one packet at a time does
47 * not work (this may be an implicit DATA0 PID on first packet of the
48 * transaction) and doing 2 packets is outside the controller's limits.
49 *
50 * If we try to lower the MPS size for EP0, then no transfers work properly
51 * for EP0, and the system will fail basic enumeration. As no cause for this
52 * has currently been found, we cannot support any large IN transfers for
53 * EP0.
54 */
55#define EP0_MPS_LIMIT 64
56
57struct s3c_hsotg;
58struct s3c_hsotg_req;
59
60/**
61 * struct s3c_hsotg_ep - driver endpoint definition.
62 * @ep: The gadget layer representation of the endpoint.
63 * @name: The driver generated name for the endpoint.
64 * @queue: Queue of requests for this endpoint.
65 * @parent: Reference back to the parent device structure.
66 * @req: The current request that the endpoint is processing. This is
67 * used to indicate an request has been loaded onto the endpoint
68 * and has yet to be completed (maybe due to data move, or simply
69 * awaiting an ack from the core all the data has been completed).
70 * @debugfs: File entry for debugfs file for this endpoint.
71 * @lock: State lock to protect contents of endpoint.
72 * @dir_in: Set to true if this endpoint is of the IN direction, which
73 * means that it is sending data to the Host.
74 * @index: The index for the endpoint registers.
75 * @name: The name array passed to the USB core.
76 * @halted: Set if the endpoint has been halted.
77 * @periodic: Set if this is a periodic ep, such as Interrupt
78 * @sent_zlp: Set if we've sent a zero-length packet.
79 * @total_data: The total number of data bytes done.
80 * @fifo_size: The size of the FIFO (for periodic IN endpoints)
81 * @fifo_load: The amount of data loaded into the FIFO (periodic IN)
82 * @last_load: The offset of data for the last start of request.
83 * @size_loaded: The last loaded size for DxEPTSIZE for periodic IN
84 *
85 * This is the driver's state for each registered enpoint, allowing it
86 * to keep track of transactions that need doing. Each endpoint has a
87 * lock to protect the state, to try and avoid using an overall lock
88 * for the host controller as much as possible.
89 *
90 * For periodic IN endpoints, we have fifo_size and fifo_load to try
91 * and keep track of the amount of data in the periodic FIFO for each
92 * of these as we don't have a status register that tells us how much
93 * is in each of them.
94 */
95struct s3c_hsotg_ep {
96 struct usb_ep ep;
97 struct list_head queue;
98 struct s3c_hsotg *parent;
99 struct s3c_hsotg_req *req;
100 struct dentry *debugfs;
101
102 spinlock_t lock;
103
104 unsigned long total_data;
105 unsigned int size_loaded;
106 unsigned int last_load;
107 unsigned int fifo_load;
108 unsigned short fifo_size;
109
110 unsigned char dir_in;
111 unsigned char index;
112
113 unsigned int halted:1;
114 unsigned int periodic:1;
115 unsigned int sent_zlp:1;
116
117 char name[10];
118};
119
120#define S3C_HSOTG_EPS (8+1) /* limit to 9 for the moment */
121
122/**
123 * struct s3c_hsotg - driver state.
124 * @dev: The parent device supplied to the probe function
125 * @driver: USB gadget driver
126 * @plat: The platform specific configuration data.
127 * @regs: The memory area mapped for accessing registers.
128 * @regs_res: The resource that was allocated when claiming register space.
129 * @irq: The IRQ number we are using
130 * @debug_root: root directrory for debugfs.
131 * @debug_file: main status file for debugfs.
132 * @debug_fifo: FIFO status file for debugfs.
133 * @ep0_reply: Request used for ep0 reply.
134 * @ep0_buff: Buffer for EP0 reply data, if needed.
135 * @ctrl_buff: Buffer for EP0 control requests.
136 * @ctrl_req: Request for EP0 control packets.
137 * @eps: The endpoints being supplied to the gadget framework
138 */
139struct s3c_hsotg {
140 struct device *dev;
141 struct usb_gadget_driver *driver;
142 struct s3c_hsotg_plat *plat;
143
144 void __iomem *regs;
145 struct resource *regs_res;
146 int irq;
147
148 struct dentry *debug_root;
149 struct dentry *debug_file;
150 struct dentry *debug_fifo;
151
152 struct usb_request *ep0_reply;
153 struct usb_request *ctrl_req;
154 u8 ep0_buff[8];
155 u8 ctrl_buff[8];
156
157 struct usb_gadget gadget;
158 struct s3c_hsotg_ep eps[];
159};
160
161/**
162 * struct s3c_hsotg_req - data transfer request
163 * @req: The USB gadget request
164 * @queue: The list of requests for the endpoint this is queued for.
165 * @in_progress: Has already had size/packets written to core
166 * @mapped: DMA buffer for this request has been mapped via dma_map_single().
167 */
168struct s3c_hsotg_req {
169 struct usb_request req;
170 struct list_head queue;
171 unsigned char in_progress;
172 unsigned char mapped;
173};
174
175/* conversion functions */
176static inline struct s3c_hsotg_req *our_req(struct usb_request *req)
177{
178 return container_of(req, struct s3c_hsotg_req, req);
179}
180
181static inline struct s3c_hsotg_ep *our_ep(struct usb_ep *ep)
182{
183 return container_of(ep, struct s3c_hsotg_ep, ep);
184}
185
186static inline struct s3c_hsotg *to_hsotg(struct usb_gadget *gadget)
187{
188 return container_of(gadget, struct s3c_hsotg, gadget);
189}
190
191static inline void __orr32(void __iomem *ptr, u32 val)
192{
193 writel(readl(ptr) | val, ptr);
194}
195
196static inline void __bic32(void __iomem *ptr, u32 val)
197{
198 writel(readl(ptr) & ~val, ptr);
199}
200
201/* forward decleration of functions */
202static void s3c_hsotg_dump(struct s3c_hsotg *hsotg);
203
204/**
205 * using_dma - return the DMA status of the driver.
206 * @hsotg: The driver state.
207 *
208 * Return true if we're using DMA.
209 *
210 * Currently, we have the DMA support code worked into everywhere
211 * that needs it, but the AMBA DMA implementation in the hardware can
212 * only DMA from 32bit aligned addresses. This means that gadgets such
213 * as the CDC Ethernet cannot work as they often pass packets which are
214 * not 32bit aligned.
215 *
216 * Unfortunately the choice to use DMA or not is global to the controller
217 * and seems to be only settable when the controller is being put through
218 * a core reset. This means we either need to fix the gadgets to take
219 * account of DMA alignment, or add bounce buffers (yuerk).
220 *
221 * Until this issue is sorted out, we always return 'false'.
222 */
223static inline bool using_dma(struct s3c_hsotg *hsotg)
224{
225 return false; /* support is not complete */
226}
227
228/**
229 * s3c_hsotg_en_gsint - enable one or more of the general interrupt
230 * @hsotg: The device state
231 * @ints: A bitmask of the interrupts to enable
232 */
233static void s3c_hsotg_en_gsint(struct s3c_hsotg *hsotg, u32 ints)
234{
235 u32 gsintmsk = readl(hsotg->regs + S3C_GINTMSK);
236 u32 new_gsintmsk;
237
238 new_gsintmsk = gsintmsk | ints;
239
240 if (new_gsintmsk != gsintmsk) {
241 dev_dbg(hsotg->dev, "gsintmsk now 0x%08x\n", new_gsintmsk);
242 writel(new_gsintmsk, hsotg->regs + S3C_GINTMSK);
243 }
244}
245
246/**
247 * s3c_hsotg_disable_gsint - disable one or more of the general interrupt
248 * @hsotg: The device state
249 * @ints: A bitmask of the interrupts to enable
250 */
251static void s3c_hsotg_disable_gsint(struct s3c_hsotg *hsotg, u32 ints)
252{
253 u32 gsintmsk = readl(hsotg->regs + S3C_GINTMSK);
254 u32 new_gsintmsk;
255
256 new_gsintmsk = gsintmsk & ~ints;
257
258 if (new_gsintmsk != gsintmsk)
259 writel(new_gsintmsk, hsotg->regs + S3C_GINTMSK);
260}
261
262/**
263 * s3c_hsotg_ctrl_epint - enable/disable an endpoint irq
264 * @hsotg: The device state
265 * @ep: The endpoint index
266 * @dir_in: True if direction is in.
267 * @en: The enable value, true to enable
268 *
269 * Set or clear the mask for an individual endpoint's interrupt
270 * request.
271 */
272static void s3c_hsotg_ctrl_epint(struct s3c_hsotg *hsotg,
273 unsigned int ep, unsigned int dir_in,
274 unsigned int en)
275{
276 unsigned long flags;
277 u32 bit = 1 << ep;
278 u32 daint;
279
280 if (!dir_in)
281 bit <<= 16;
282
283 local_irq_save(flags);
284 daint = readl(hsotg->regs + S3C_DAINTMSK);
285 if (en)
286 daint |= bit;
287 else
288 daint &= ~bit;
289 writel(daint, hsotg->regs + S3C_DAINTMSK);
290 local_irq_restore(flags);
291}
292
293/**
294 * s3c_hsotg_init_fifo - initialise non-periodic FIFOs
295 * @hsotg: The device instance.
296 */
297static void s3c_hsotg_init_fifo(struct s3c_hsotg *hsotg)
298{
299 /* the ryu 2.6.24 release ahs
300 writel(0x1C0, hsotg->regs + S3C_GRXFSIZ);
301 writel(S3C_GNPTXFSIZ_NPTxFStAddr(0x200) |
302 S3C_GNPTXFSIZ_NPTxFDep(0x1C0),
303 hsotg->regs + S3C_GNPTXFSIZ);
304 */
305
306 /* set FIFO sizes to 2048/0x1C0 */
307
308 writel(2048, hsotg->regs + S3C_GRXFSIZ);
309 writel(S3C_GNPTXFSIZ_NPTxFStAddr(2048) |
310 S3C_GNPTXFSIZ_NPTxFDep(0x1C0),
311 hsotg->regs + S3C_GNPTXFSIZ);
312}
313
314/**
315 * @ep: USB endpoint to allocate request for.
316 * @flags: Allocation flags
317 *
318 * Allocate a new USB request structure appropriate for the specified endpoint
319 */
320struct usb_request *s3c_hsotg_ep_alloc_request(struct usb_ep *ep, gfp_t flags)
321{
322 struct s3c_hsotg_req *req;
323
324 req = kzalloc(sizeof(struct s3c_hsotg_req), flags);
325 if (!req)
326 return NULL;
327
328 INIT_LIST_HEAD(&req->queue);
329
330 req->req.dma = DMA_ADDR_INVALID;
331 return &req->req;
332}
333
334/**
335 * is_ep_periodic - return true if the endpoint is in periodic mode.
336 * @hs_ep: The endpoint to query.
337 *
338 * Returns true if the endpoint is in periodic mode, meaning it is being
339 * used for an Interrupt or ISO transfer.
340 */
341static inline int is_ep_periodic(struct s3c_hsotg_ep *hs_ep)
342{
343 return hs_ep->periodic;
344}
345
346/**
347 * s3c_hsotg_unmap_dma - unmap the DMA memory being used for the request
348 * @hsotg: The device state.
349 * @hs_ep: The endpoint for the request
350 * @hs_req: The request being processed.
351 *
352 * This is the reverse of s3c_hsotg_map_dma(), called for the completion
353 * of a request to ensure the buffer is ready for access by the caller.
354*/
355static void s3c_hsotg_unmap_dma(struct s3c_hsotg *hsotg,
356 struct s3c_hsotg_ep *hs_ep,
357 struct s3c_hsotg_req *hs_req)
358{
359 struct usb_request *req = &hs_req->req;
360 enum dma_data_direction dir;
361
362 dir = hs_ep->dir_in ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
363
364 /* ignore this if we're not moving any data */
365 if (hs_req->req.length == 0)
366 return;
367
368 if (hs_req->mapped) {
369 /* we mapped this, so unmap and remove the dma */
370
371 dma_unmap_single(hsotg->dev, req->dma, req->length, dir);
372
373 req->dma = DMA_ADDR_INVALID;
374 hs_req->mapped = 0;
375 } else {
376 dma_sync_single(hsotg->dev, req->dma, req->length, dir);
377 }
378}
379
380/**
381 * s3c_hsotg_write_fifo - write packet Data to the TxFIFO
382 * @hsotg: The controller state.
383 * @hs_ep: The endpoint we're going to write for.
384 * @hs_req: The request to write data for.
385 *
386 * This is called when the TxFIFO has some space in it to hold a new
387 * transmission and we have something to give it. The actual setup of
388 * the data size is done elsewhere, so all we have to do is to actually
389 * write the data.
390 *
391 * The return value is zero if there is more space (or nothing was done)
392 * otherwise -ENOSPC is returned if the FIFO space was used up.
393 *
394 * This routine is only needed for PIO
395*/
396static int s3c_hsotg_write_fifo(struct s3c_hsotg *hsotg,
397 struct s3c_hsotg_ep *hs_ep,
398 struct s3c_hsotg_req *hs_req)
399{
400 bool periodic = is_ep_periodic(hs_ep);
401 u32 gnptxsts = readl(hsotg->regs + S3C_GNPTXSTS);
402 int buf_pos = hs_req->req.actual;
403 int to_write = hs_ep->size_loaded;
404 void *data;
405 int can_write;
406 int pkt_round;
407
408 to_write -= (buf_pos - hs_ep->last_load);
409
410 /* if there's nothing to write, get out early */
411 if (to_write == 0)
412 return 0;
413
414 if (periodic) {
415 u32 epsize = readl(hsotg->regs + S3C_DIEPTSIZ(hs_ep->index));
416 int size_left;
417 int size_done;
418
419 /* work out how much data was loaded so we can calculate
420 * how much data is left in the fifo. */
421
422 size_left = S3C_DxEPTSIZ_XferSize_GET(epsize);
423
424 dev_dbg(hsotg->dev, "%s: left=%d, load=%d, fifo=%d, size %d\n",
425 __func__, size_left,
426 hs_ep->size_loaded, hs_ep->fifo_load, hs_ep->fifo_size);
427
428 /* how much of the data has moved */
429 size_done = hs_ep->size_loaded - size_left;
430
431 /* how much data is left in the fifo */
432 can_write = hs_ep->fifo_load - size_done;
433 dev_dbg(hsotg->dev, "%s: => can_write1=%d\n",
434 __func__, can_write);
435
436 can_write = hs_ep->fifo_size - can_write;
437 dev_dbg(hsotg->dev, "%s: => can_write2=%d\n",
438 __func__, can_write);
439
440 if (can_write <= 0) {
441 s3c_hsotg_en_gsint(hsotg, S3C_GINTSTS_PTxFEmp);
442 return -ENOSPC;
443 }
444 } else {
445 if (S3C_GNPTXSTS_NPTxQSpcAvail_GET(gnptxsts) == 0) {
446 dev_dbg(hsotg->dev,
447 "%s: no queue slots available (0x%08x)\n",
448 __func__, gnptxsts);
449
450 s3c_hsotg_en_gsint(hsotg, S3C_GINTSTS_NPTxFEmp);
451 return -ENOSPC;
452 }
453
454 can_write = S3C_GNPTXSTS_NPTxFSpcAvail_GET(gnptxsts);
455 }
456
457 dev_dbg(hsotg->dev, "%s: GNPTXSTS=%08x, can=%d, to=%d, mps %d\n",
458 __func__, gnptxsts, can_write, to_write, hs_ep->ep.maxpacket);
459
460 /* limit to 512 bytes of data, it seems at least on the non-periodic
461 * FIFO, requests of >512 cause the endpoint to get stuck with a
462 * fragment of the end of the transfer in it.
463 */
464 if (can_write > 512)
465 can_write = 512;
466
467 /* see if we can write data */
468
469 if (to_write > can_write) {
470 to_write = can_write;
471 pkt_round = to_write % hs_ep->ep.maxpacket;
472
473 /* Not sure, but we probably shouldn't be writing partial
474 * packets into the FIFO, so round the write down to an
475 * exact number of packets.
476 *
477 * Note, we do not currently check to see if we can ever
478 * write a full packet or not to the FIFO.
479 */
480
481 if (pkt_round)
482 to_write -= pkt_round;
483
484 /* enable correct FIFO interrupt to alert us when there
485 * is more room left. */
486
487 s3c_hsotg_en_gsint(hsotg,
488 periodic ? S3C_GINTSTS_PTxFEmp :
489 S3C_GINTSTS_NPTxFEmp);
490 }
491
492 dev_dbg(hsotg->dev, "write %d/%d, can_write %d, done %d\n",
493 to_write, hs_req->req.length, can_write, buf_pos);
494
495 if (to_write <= 0)
496 return -ENOSPC;
497
498 hs_req->req.actual = buf_pos + to_write;
499 hs_ep->total_data += to_write;
500
501 if (periodic)
502 hs_ep->fifo_load += to_write;
503
504 to_write = DIV_ROUND_UP(to_write, 4);
505 data = hs_req->req.buf + buf_pos;
506
507 writesl(hsotg->regs + S3C_EPFIFO(hs_ep->index), data, to_write);
508
509 return (to_write >= can_write) ? -ENOSPC : 0;
510}
511
512/**
513 * get_ep_limit - get the maximum data legnth for this endpoint
514 * @hs_ep: The endpoint
515 *
516 * Return the maximum data that can be queued in one go on a given endpoint
517 * so that transfers that are too long can be split.
518 */
519static unsigned get_ep_limit(struct s3c_hsotg_ep *hs_ep)
520{
521 int index = hs_ep->index;
522 unsigned maxsize;
523 unsigned maxpkt;
524
525 if (index != 0) {
526 maxsize = S3C_DxEPTSIZ_XferSize_LIMIT + 1;
527 maxpkt = S3C_DxEPTSIZ_PktCnt_LIMIT + 1;
528 } else {
529 if (hs_ep->dir_in) {
530 /* maxsize = S3C_DIEPTSIZ0_XferSize_LIMIT + 1; */
531 maxsize = 64+64+1;
532 maxpkt = S3C_DIEPTSIZ0_PktCnt_LIMIT + 1;
533 } else {
534 maxsize = 0x3f;
535 maxpkt = 2;
536 }
537 }
538
539 /* we made the constant loading easier above by using +1 */
540 maxpkt--;
541 maxsize--;
542
543 /* constrain by packet count if maxpkts*pktsize is greater
544 * than the length register size. */
545
546 if ((maxpkt * hs_ep->ep.maxpacket) < maxsize)
547 maxsize = maxpkt * hs_ep->ep.maxpacket;
548
549 return maxsize;
550}
551
552/**
553 * s3c_hsotg_start_req - start a USB request from an endpoint's queue
554 * @hsotg: The controller state.
555 * @hs_ep: The endpoint to process a request for
556 * @hs_req: The request to start.
557 * @continuing: True if we are doing more for the current request.
558 *
559 * Start the given request running by setting the endpoint registers
560 * appropriately, and writing any data to the FIFOs.
561 */
562static void s3c_hsotg_start_req(struct s3c_hsotg *hsotg,
563 struct s3c_hsotg_ep *hs_ep,
564 struct s3c_hsotg_req *hs_req,
565 bool continuing)
566{
567 struct usb_request *ureq = &hs_req->req;
568 int index = hs_ep->index;
569 int dir_in = hs_ep->dir_in;
570 u32 epctrl_reg;
571 u32 epsize_reg;
572 u32 epsize;
573 u32 ctrl;
574 unsigned length;
575 unsigned packets;
576 unsigned maxreq;
577
578 if (index != 0) {
579 if (hs_ep->req && !continuing) {
580 dev_err(hsotg->dev, "%s: active request\n", __func__);
581 WARN_ON(1);
582 return;
583 } else if (hs_ep->req != hs_req && continuing) {
584 dev_err(hsotg->dev,
585 "%s: continue different req\n", __func__);
586 WARN_ON(1);
587 return;
588 }
589 }
590
591 epctrl_reg = dir_in ? S3C_DIEPCTL(index) : S3C_DOEPCTL(index);
592 epsize_reg = dir_in ? S3C_DIEPTSIZ(index) : S3C_DOEPTSIZ(index);
593
594 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x, ep %d, dir %s\n",
595 __func__, readl(hsotg->regs + epctrl_reg), index,
596 hs_ep->dir_in ? "in" : "out");
597
598 length = ureq->length - ureq->actual;
599
600 if (0)
601 dev_dbg(hsotg->dev,
602 "REQ buf %p len %d dma 0x%08x noi=%d zp=%d snok=%d\n",
603 ureq->buf, length, ureq->dma,
604 ureq->no_interrupt, ureq->zero, ureq->short_not_ok);
605
606 maxreq = get_ep_limit(hs_ep);
607 if (length > maxreq) {
608 int round = maxreq % hs_ep->ep.maxpacket;
609
610 dev_dbg(hsotg->dev, "%s: length %d, max-req %d, r %d\n",
611 __func__, length, maxreq, round);
612
613 /* round down to multiple of packets */
614 if (round)
615 maxreq -= round;
616
617 length = maxreq;
618 }
619
620 if (length)
621 packets = DIV_ROUND_UP(length, hs_ep->ep.maxpacket);
622 else
623 packets = 1; /* send one packet if length is zero. */
624
625 if (dir_in && index != 0)
626 epsize = S3C_DxEPTSIZ_MC(1);
627 else
628 epsize = 0;
629
630 if (index != 0 && ureq->zero) {
631 /* test for the packets being exactly right for the
632 * transfer */
633
634 if (length == (packets * hs_ep->ep.maxpacket))
635 packets++;
636 }
637
638 epsize |= S3C_DxEPTSIZ_PktCnt(packets);
639 epsize |= S3C_DxEPTSIZ_XferSize(length);
640
641 dev_dbg(hsotg->dev, "%s: %d@%d/%d, 0x%08x => 0x%08x\n",
642 __func__, packets, length, ureq->length, epsize, epsize_reg);
643
644 /* store the request as the current one we're doing */
645 hs_ep->req = hs_req;
646
647 /* write size / packets */
648 writel(epsize, hsotg->regs + epsize_reg);
649
650 ctrl = readl(hsotg->regs + epctrl_reg);
651
652 if (ctrl & S3C_DxEPCTL_Stall) {
653 dev_warn(hsotg->dev, "%s: ep%d is stalled\n", __func__, index);
654
655 /* not sure what we can do here, if it is EP0 then we should
656 * get this cleared once the endpoint has transmitted the
657 * STALL packet, otherwise it needs to be cleared by the
658 * host.
659 */
660 }
661
662 if (using_dma(hsotg)) {
663 unsigned int dma_reg;
664
665 /* write DMA address to control register, buffer already
666 * synced by s3c_hsotg_ep_queue(). */
667
668 dma_reg = dir_in ? S3C_DIEPDMA(index) : S3C_DOEPDMA(index);
669 writel(ureq->dma, hsotg->regs + dma_reg);
670
671 dev_dbg(hsotg->dev, "%s: 0x%08x => 0x%08x\n",
672 __func__, ureq->dma, dma_reg);
673 }
674
675 ctrl |= S3C_DxEPCTL_EPEna; /* ensure ep enabled */
676 ctrl |= S3C_DxEPCTL_USBActEp;
677 ctrl |= S3C_DxEPCTL_CNAK; /* clear NAK set by core */
678
679 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
680 writel(ctrl, hsotg->regs + epctrl_reg);
681
682 /* set these, it seems that DMA support increments past the end
683 * of the packet buffer so we need to calculate the length from
684 * this information. */
685 hs_ep->size_loaded = length;
686 hs_ep->last_load = ureq->actual;
687
688 if (dir_in && !using_dma(hsotg)) {
689 /* set these anyway, we may need them for non-periodic in */
690 hs_ep->fifo_load = 0;
691
692 s3c_hsotg_write_fifo(hsotg, hs_ep, hs_req);
693 }
694
695 /* clear the INTknTXFEmpMsk when we start request, more as a aide
696 * to debugging to see what is going on. */
697 if (dir_in)
698 writel(S3C_DIEPMSK_INTknTXFEmpMsk,
699 hsotg->regs + S3C_DIEPINT(index));
700
701 /* Note, trying to clear the NAK here causes problems with transmit
702 * on the S3C6400 ending up with the TXFIFO becomming full. */
703
704 /* check ep is enabled */
705 if (!(readl(hsotg->regs + epctrl_reg) & S3C_DxEPCTL_EPEna))
706 dev_warn(hsotg->dev,
707 "ep%d: failed to become enabled (DxEPCTL=0x%08x)?\n",
708 index, readl(hsotg->regs + epctrl_reg));
709
710 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n",
711 __func__, readl(hsotg->regs + epctrl_reg));
712}
713
714/**
715 * s3c_hsotg_map_dma - map the DMA memory being used for the request
716 * @hsotg: The device state.
717 * @hs_ep: The endpoint the request is on.
718 * @req: The request being processed.
719 *
720 * We've been asked to queue a request, so ensure that the memory buffer
721 * is correctly setup for DMA. If we've been passed an extant DMA address
722 * then ensure the buffer has been synced to memory. If our buffer has no
723 * DMA memory, then we map the memory and mark our request to allow us to
724 * cleanup on completion.
725*/
726static int s3c_hsotg_map_dma(struct s3c_hsotg *hsotg,
727 struct s3c_hsotg_ep *hs_ep,
728 struct usb_request *req)
729{
730 enum dma_data_direction dir;
731 struct s3c_hsotg_req *hs_req = our_req(req);
732
733 dir = hs_ep->dir_in ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
734
735 /* if the length is zero, ignore the DMA data */
736 if (hs_req->req.length == 0)
737 return 0;
738
739 if (req->dma == DMA_ADDR_INVALID) {
740 dma_addr_t dma;
741
742 dma = dma_map_single(hsotg->dev, req->buf, req->length, dir);
743
744 if (unlikely(dma_mapping_error(hsotg->dev, dma)))
745 goto dma_error;
746
747 if (dma & 3) {
748 dev_err(hsotg->dev, "%s: unaligned dma buffer\n",
749 __func__);
750
751 dma_unmap_single(hsotg->dev, dma, req->length, dir);
752 return -EINVAL;
753 }
754
755 hs_req->mapped = 1;
756 req->dma = dma;
757 } else {
758 dma_sync_single(hsotg->dev, req->dma, req->length, dir);
759 hs_req->mapped = 0;
760 }
761
762 return 0;
763
764dma_error:
765 dev_err(hsotg->dev, "%s: failed to map buffer %p, %d bytes\n",
766 __func__, req->buf, req->length);
767
768 return -EIO;
769}
770
771static int s3c_hsotg_ep_queue(struct usb_ep *ep, struct usb_request *req,
772 gfp_t gfp_flags)
773{
774 struct s3c_hsotg_req *hs_req = our_req(req);
775 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
776 struct s3c_hsotg *hs = hs_ep->parent;
777 unsigned long irqflags;
778 bool first;
779
780 dev_dbg(hs->dev, "%s: req %p: %d@%p, noi=%d, zero=%d, snok=%d\n",
781 ep->name, req, req->length, req->buf, req->no_interrupt,
782 req->zero, req->short_not_ok);
783
784 /* initialise status of the request */
785 INIT_LIST_HEAD(&hs_req->queue);
786 req->actual = 0;
787 req->status = -EINPROGRESS;
788
789 /* if we're using DMA, sync the buffers as necessary */
790 if (using_dma(hs)) {
791 int ret = s3c_hsotg_map_dma(hs, hs_ep, req);
792 if (ret)
793 return ret;
794 }
795
796 spin_lock_irqsave(&hs_ep->lock, irqflags);
797
798 first = list_empty(&hs_ep->queue);
799 list_add_tail(&hs_req->queue, &hs_ep->queue);
800
801 if (first)
802 s3c_hsotg_start_req(hs, hs_ep, hs_req, false);
803
804 spin_unlock_irqrestore(&hs_ep->lock, irqflags);
805
806 return 0;
807}
808
809static void s3c_hsotg_ep_free_request(struct usb_ep *ep,
810 struct usb_request *req)
811{
812 struct s3c_hsotg_req *hs_req = our_req(req);
813
814 kfree(hs_req);
815}
816
817/**
818 * s3c_hsotg_complete_oursetup - setup completion callback
819 * @ep: The endpoint the request was on.
820 * @req: The request completed.
821 *
822 * Called on completion of any requests the driver itself
823 * submitted that need cleaning up.
824 */
825static void s3c_hsotg_complete_oursetup(struct usb_ep *ep,
826 struct usb_request *req)
827{
828 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
829 struct s3c_hsotg *hsotg = hs_ep->parent;
830
831 dev_dbg(hsotg->dev, "%s: ep %p, req %p\n", __func__, ep, req);
832
833 s3c_hsotg_ep_free_request(ep, req);
834}
835
836/**
837 * ep_from_windex - convert control wIndex value to endpoint
838 * @hsotg: The driver state.
839 * @windex: The control request wIndex field (in host order).
840 *
841 * Convert the given wIndex into a pointer to an driver endpoint
842 * structure, or return NULL if it is not a valid endpoint.
843*/
844static struct s3c_hsotg_ep *ep_from_windex(struct s3c_hsotg *hsotg,
845 u32 windex)
846{
847 struct s3c_hsotg_ep *ep = &hsotg->eps[windex & 0x7F];
848 int dir = (windex & USB_DIR_IN) ? 1 : 0;
849 int idx = windex & 0x7F;
850
851 if (windex >= 0x100)
852 return NULL;
853
854 if (idx > S3C_HSOTG_EPS)
855 return NULL;
856
857 if (idx && ep->dir_in != dir)
858 return NULL;
859
860 return ep;
861}
862
863/**
864 * s3c_hsotg_send_reply - send reply to control request
865 * @hsotg: The device state
866 * @ep: Endpoint 0
867 * @buff: Buffer for request
868 * @length: Length of reply.
869 *
870 * Create a request and queue it on the given endpoint. This is useful as
871 * an internal method of sending replies to certain control requests, etc.
872 */
873static int s3c_hsotg_send_reply(struct s3c_hsotg *hsotg,
874 struct s3c_hsotg_ep *ep,
875 void *buff,
876 int length)
877{
878 struct usb_request *req;
879 int ret;
880
881 dev_dbg(hsotg->dev, "%s: buff %p, len %d\n", __func__, buff, length);
882
883 req = s3c_hsotg_ep_alloc_request(&ep->ep, GFP_ATOMIC);
884 hsotg->ep0_reply = req;
885 if (!req) {
886 dev_warn(hsotg->dev, "%s: cannot alloc req\n", __func__);
887 return -ENOMEM;
888 }
889
890 req->buf = hsotg->ep0_buff;
891 req->length = length;
892 req->zero = 1; /* always do zero-length final transfer */
893 req->complete = s3c_hsotg_complete_oursetup;
894
895 if (length)
896 memcpy(req->buf, buff, length);
897 else
898 ep->sent_zlp = 1;
899
900 ret = s3c_hsotg_ep_queue(&ep->ep, req, GFP_ATOMIC);
901 if (ret) {
902 dev_warn(hsotg->dev, "%s: cannot queue req\n", __func__);
903 return ret;
904 }
905
906 return 0;
907}
908
909/**
910 * s3c_hsotg_process_req_status - process request GET_STATUS
911 * @hsotg: The device state
912 * @ctrl: USB control request
913 */
914static int s3c_hsotg_process_req_status(struct s3c_hsotg *hsotg,
915 struct usb_ctrlrequest *ctrl)
916{
917 struct s3c_hsotg_ep *ep0 = &hsotg->eps[0];
918 struct s3c_hsotg_ep *ep;
919 __le16 reply;
920 int ret;
921
922 dev_dbg(hsotg->dev, "%s: USB_REQ_GET_STATUS\n", __func__);
923
924 if (!ep0->dir_in) {
925 dev_warn(hsotg->dev, "%s: direction out?\n", __func__);
926 return -EINVAL;
927 }
928
929 switch (ctrl->bRequestType & USB_RECIP_MASK) {
930 case USB_RECIP_DEVICE:
931 reply = cpu_to_le16(0); /* bit 0 => self powered,
932 * bit 1 => remote wakeup */
933 break;
934
935 case USB_RECIP_INTERFACE:
936 /* currently, the data result should be zero */
937 reply = cpu_to_le16(0);
938 break;
939
940 case USB_RECIP_ENDPOINT:
941 ep = ep_from_windex(hsotg, le16_to_cpu(ctrl->wIndex));
942 if (!ep)
943 return -ENOENT;
944
945 reply = cpu_to_le16(ep->halted ? 1 : 0);
946 break;
947
948 default:
949 return 0;
950 }
951
952 if (le16_to_cpu(ctrl->wLength) != 2)
953 return -EINVAL;
954
955 ret = s3c_hsotg_send_reply(hsotg, ep0, &reply, 2);
956 if (ret) {
957 dev_err(hsotg->dev, "%s: failed to send reply\n", __func__);
958 return ret;
959 }
960
961 return 1;
962}
963
964static int s3c_hsotg_ep_sethalt(struct usb_ep *ep, int value);
965
966/**
967 * s3c_hsotg_process_req_featire - process request {SET,CLEAR}_FEATURE
968 * @hsotg: The device state
969 * @ctrl: USB control request
970 */
971static int s3c_hsotg_process_req_feature(struct s3c_hsotg *hsotg,
972 struct usb_ctrlrequest *ctrl)
973{
974 bool set = (ctrl->bRequest == USB_REQ_SET_FEATURE);
975 struct s3c_hsotg_ep *ep;
976
977 dev_dbg(hsotg->dev, "%s: %s_FEATURE\n",
978 __func__, set ? "SET" : "CLEAR");
979
980 if (ctrl->bRequestType == USB_RECIP_ENDPOINT) {
981 ep = ep_from_windex(hsotg, le16_to_cpu(ctrl->wIndex));
982 if (!ep) {
983 dev_dbg(hsotg->dev, "%s: no endpoint for 0x%04x\n",
984 __func__, le16_to_cpu(ctrl->wIndex));
985 return -ENOENT;
986 }
987
988 switch (le16_to_cpu(ctrl->wValue)) {
989 case USB_ENDPOINT_HALT:
990 s3c_hsotg_ep_sethalt(&ep->ep, set);
991 break;
992
993 default:
994 return -ENOENT;
995 }
996 } else
997 return -ENOENT; /* currently only deal with endpoint */
998
999 return 1;
1000}
1001
1002/**
1003 * s3c_hsotg_process_control - process a control request
1004 * @hsotg: The device state
1005 * @ctrl: The control request received
1006 *
1007 * The controller has received the SETUP phase of a control request, and
1008 * needs to work out what to do next (and whether to pass it on to the
1009 * gadget driver).
1010 */
1011static void s3c_hsotg_process_control(struct s3c_hsotg *hsotg,
1012 struct usb_ctrlrequest *ctrl)
1013{
1014 struct s3c_hsotg_ep *ep0 = &hsotg->eps[0];
1015 int ret = 0;
1016 u32 dcfg;
1017
1018 ep0->sent_zlp = 0;
1019
1020 dev_dbg(hsotg->dev, "ctrl Req=%02x, Type=%02x, V=%04x, L=%04x\n",
1021 ctrl->bRequest, ctrl->bRequestType,
1022 ctrl->wValue, ctrl->wLength);
1023
1024 /* record the direction of the request, for later use when enquing
1025 * packets onto EP0. */
1026
1027 ep0->dir_in = (ctrl->bRequestType & USB_DIR_IN) ? 1 : 0;
1028 dev_dbg(hsotg->dev, "ctrl: dir_in=%d\n", ep0->dir_in);
1029
1030 /* if we've no data with this request, then the last part of the
1031 * transaction is going to implicitly be IN. */
1032 if (ctrl->wLength == 0)
1033 ep0->dir_in = 1;
1034
1035 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
1036 switch (ctrl->bRequest) {
1037 case USB_REQ_SET_ADDRESS:
1038 dcfg = readl(hsotg->regs + S3C_DCFG);
1039 dcfg &= ~S3C_DCFG_DevAddr_MASK;
1040 dcfg |= ctrl->wValue << S3C_DCFG_DevAddr_SHIFT;
1041 writel(dcfg, hsotg->regs + S3C_DCFG);
1042
1043 dev_info(hsotg->dev, "new address %d\n", ctrl->wValue);
1044
1045 ret = s3c_hsotg_send_reply(hsotg, ep0, NULL, 0);
1046 return;
1047
1048 case USB_REQ_GET_STATUS:
1049 ret = s3c_hsotg_process_req_status(hsotg, ctrl);
1050 break;
1051
1052 case USB_REQ_CLEAR_FEATURE:
1053 case USB_REQ_SET_FEATURE:
1054 ret = s3c_hsotg_process_req_feature(hsotg, ctrl);
1055 break;
1056 }
1057 }
1058
1059 /* as a fallback, try delivering it to the driver to deal with */
1060
1061 if (ret == 0 && hsotg->driver) {
1062 ret = hsotg->driver->setup(&hsotg->gadget, ctrl);
1063 if (ret < 0)
1064 dev_dbg(hsotg->dev, "driver->setup() ret %d\n", ret);
1065 }
1066
1067 if (ret > 0) {
1068 if (!ep0->dir_in) {
1069 /* need to generate zlp in reply or take data */
1070 /* todo - deal with any data we might be sent? */
1071 ret = s3c_hsotg_send_reply(hsotg, ep0, NULL, 0);
1072 }
1073 }
1074
1075 /* the request is either unhandlable, or is not formatted correctly
1076 * so respond with a STALL for the status stage to indicate failure.
1077 */
1078
1079 if (ret < 0) {
1080 u32 reg;
1081 u32 ctrl;
1082
1083 dev_dbg(hsotg->dev, "ep0 stall (dir=%d)\n", ep0->dir_in);
1084 reg = (ep0->dir_in) ? S3C_DIEPCTL0 : S3C_DOEPCTL0;
1085
1086 /* S3C_DxEPCTL_Stall will be cleared by EP once it has
1087 * taken effect, so no need to clear later. */
1088
1089 ctrl = readl(hsotg->regs + reg);
1090 ctrl |= S3C_DxEPCTL_Stall;
1091 ctrl |= S3C_DxEPCTL_CNAK;
1092 writel(ctrl, hsotg->regs + reg);
1093
1094 dev_dbg(hsotg->dev,
1095 "writen DxEPCTL=0x%08x to %08x (DxEPCTL=0x%08x)\n",
1096 ctrl, reg, readl(hsotg->regs + reg));
1097
1098 /* don't belive we need to anything more to get the EP
1099 * to reply with a STALL packet */
1100 }
1101}
1102
1103static void s3c_hsotg_enqueue_setup(struct s3c_hsotg *hsotg);
1104
1105/**
1106 * s3c_hsotg_complete_setup - completion of a setup transfer
1107 * @ep: The endpoint the request was on.
1108 * @req: The request completed.
1109 *
1110 * Called on completion of any requests the driver itself submitted for
1111 * EP0 setup packets
1112 */
1113static void s3c_hsotg_complete_setup(struct usb_ep *ep,
1114 struct usb_request *req)
1115{
1116 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
1117 struct s3c_hsotg *hsotg = hs_ep->parent;
1118
1119 if (req->status < 0) {
1120 dev_dbg(hsotg->dev, "%s: failed %d\n", __func__, req->status);
1121 return;
1122 }
1123
1124 if (req->actual == 0)
1125 s3c_hsotg_enqueue_setup(hsotg);
1126 else
1127 s3c_hsotg_process_control(hsotg, req->buf);
1128}
1129
1130/**
1131 * s3c_hsotg_enqueue_setup - start a request for EP0 packets
1132 * @hsotg: The device state.
1133 *
1134 * Enqueue a request on EP0 if necessary to received any SETUP packets
1135 * received from the host.
1136 */
1137static void s3c_hsotg_enqueue_setup(struct s3c_hsotg *hsotg)
1138{
1139 struct usb_request *req = hsotg->ctrl_req;
1140 struct s3c_hsotg_req *hs_req = our_req(req);
1141 int ret;
1142
1143 dev_dbg(hsotg->dev, "%s: queueing setup request\n", __func__);
1144
1145 req->zero = 0;
1146 req->length = 8;
1147 req->buf = hsotg->ctrl_buff;
1148 req->complete = s3c_hsotg_complete_setup;
1149
1150 if (!list_empty(&hs_req->queue)) {
1151 dev_dbg(hsotg->dev, "%s already queued???\n", __func__);
1152 return;
1153 }
1154
1155 hsotg->eps[0].dir_in = 0;
1156
1157 ret = s3c_hsotg_ep_queue(&hsotg->eps[0].ep, req, GFP_ATOMIC);
1158 if (ret < 0) {
1159 dev_err(hsotg->dev, "%s: failed queue (%d)\n", __func__, ret);
1160 /* Don't think there's much we can do other than watch the
1161 * driver fail. */
1162 }
1163}
1164
1165/**
1166 * get_ep_head - return the first request on the endpoint
1167 * @hs_ep: The controller endpoint to get
1168 *
1169 * Get the first request on the endpoint.
1170*/
1171static struct s3c_hsotg_req *get_ep_head(struct s3c_hsotg_ep *hs_ep)
1172{
1173 if (list_empty(&hs_ep->queue))
1174 return NULL;
1175
1176 return list_first_entry(&hs_ep->queue, struct s3c_hsotg_req, queue);
1177}
1178
1179/**
1180 * s3c_hsotg_complete_request - complete a request given to us
1181 * @hsotg: The device state.
1182 * @hs_ep: The endpoint the request was on.
1183 * @hs_req: The request to complete.
1184 * @result: The result code (0 => Ok, otherwise errno)
1185 *
1186 * The given request has finished, so call the necessary completion
1187 * if it has one and then look to see if we can start a new request
1188 * on the endpoint.
1189 *
1190 * Note, expects the ep to already be locked as appropriate.
1191*/
1192static void s3c_hsotg_complete_request(struct s3c_hsotg *hsotg,
1193 struct s3c_hsotg_ep *hs_ep,
1194 struct s3c_hsotg_req *hs_req,
1195 int result)
1196{
1197 bool restart;
1198
1199 if (!hs_req) {
1200 dev_dbg(hsotg->dev, "%s: nothing to complete?\n", __func__);
1201 return;
1202 }
1203
1204 dev_dbg(hsotg->dev, "complete: ep %p %s, req %p, %d => %p\n",
1205 hs_ep, hs_ep->ep.name, hs_req, result, hs_req->req.complete);
1206
1207 /* only replace the status if we've not already set an error
1208 * from a previous transaction */
1209
1210 if (hs_req->req.status == -EINPROGRESS)
1211 hs_req->req.status = result;
1212
1213 hs_ep->req = NULL;
1214 list_del_init(&hs_req->queue);
1215
1216 if (using_dma(hsotg))
1217 s3c_hsotg_unmap_dma(hsotg, hs_ep, hs_req);
1218
1219 /* call the complete request with the locks off, just in case the
1220 * request tries to queue more work for this endpoint. */
1221
1222 if (hs_req->req.complete) {
1223 spin_unlock(&hs_ep->lock);
1224 hs_req->req.complete(&hs_ep->ep, &hs_req->req);
1225 spin_lock(&hs_ep->lock);
1226 }
1227
1228 /* Look to see if there is anything else to do. Note, the completion
1229 * of the previous request may have caused a new request to be started
1230 * so be careful when doing this. */
1231
1232 if (!hs_ep->req && result >= 0) {
1233 restart = !list_empty(&hs_ep->queue);
1234 if (restart) {
1235 hs_req = get_ep_head(hs_ep);
1236 s3c_hsotg_start_req(hsotg, hs_ep, hs_req, false);
1237 }
1238 }
1239}
1240
1241/**
1242 * s3c_hsotg_complete_request_lock - complete a request given to us (locked)
1243 * @hsotg: The device state.
1244 * @hs_ep: The endpoint the request was on.
1245 * @hs_req: The request to complete.
1246 * @result: The result code (0 => Ok, otherwise errno)
1247 *
1248 * See s3c_hsotg_complete_request(), but called with the endpoint's
1249 * lock held.
1250*/
1251static void s3c_hsotg_complete_request_lock(struct s3c_hsotg *hsotg,
1252 struct s3c_hsotg_ep *hs_ep,
1253 struct s3c_hsotg_req *hs_req,
1254 int result)
1255{
1256 unsigned long flags;
1257
1258 spin_lock_irqsave(&hs_ep->lock, flags);
1259 s3c_hsotg_complete_request(hsotg, hs_ep, hs_req, result);
1260 spin_unlock_irqrestore(&hs_ep->lock, flags);
1261}
1262
1263/**
1264 * s3c_hsotg_rx_data - receive data from the FIFO for an endpoint
1265 * @hsotg: The device state.
1266 * @ep_idx: The endpoint index for the data
1267 * @size: The size of data in the fifo, in bytes
1268 *
1269 * The FIFO status shows there is data to read from the FIFO for a given
1270 * endpoint, so sort out whether we need to read the data into a request
1271 * that has been made for that endpoint.
1272 */
1273static void s3c_hsotg_rx_data(struct s3c_hsotg *hsotg, int ep_idx, int size)
1274{
1275 struct s3c_hsotg_ep *hs_ep = &hsotg->eps[ep_idx];
1276 struct s3c_hsotg_req *hs_req = hs_ep->req;
1277 void __iomem *fifo = hsotg->regs + S3C_EPFIFO(ep_idx);
1278 int to_read;
1279 int max_req;
1280 int read_ptr;
1281
1282 if (!hs_req) {
1283 u32 epctl = readl(hsotg->regs + S3C_DOEPCTL(ep_idx));
1284 int ptr;
1285
1286 dev_warn(hsotg->dev,
1287 "%s: FIFO %d bytes on ep%d but no req (DxEPCTl=0x%08x)\n",
1288 __func__, size, ep_idx, epctl);
1289
1290 /* dump the data from the FIFO, we've nothing we can do */
1291 for (ptr = 0; ptr < size; ptr += 4)
1292 (void)readl(fifo);
1293
1294 return;
1295 }
1296
1297 spin_lock(&hs_ep->lock);
1298
1299 to_read = size;
1300 read_ptr = hs_req->req.actual;
1301 max_req = hs_req->req.length - read_ptr;
1302
1303 if (to_read > max_req) {
1304 /* more data appeared than we where willing
1305 * to deal with in this request.
1306 */
1307
1308 /* currently we don't deal this */
1309 WARN_ON_ONCE(1);
1310 }
1311
1312 dev_dbg(hsotg->dev, "%s: read %d/%d, done %d/%d\n",
1313 __func__, to_read, max_req, read_ptr, hs_req->req.length);
1314
1315 hs_ep->total_data += to_read;
1316 hs_req->req.actual += to_read;
1317 to_read = DIV_ROUND_UP(to_read, 4);
1318
1319 /* note, we might over-write the buffer end by 3 bytes depending on
1320 * alignment of the data. */
1321 readsl(fifo, hs_req->req.buf + read_ptr, to_read);
1322
1323 spin_unlock(&hs_ep->lock);
1324}
1325
1326/**
1327 * s3c_hsotg_send_zlp - send zero-length packet on control endpoint
1328 * @hsotg: The device instance
1329 * @req: The request currently on this endpoint
1330 *
1331 * Generate a zero-length IN packet request for terminating a SETUP
1332 * transaction.
1333 *
1334 * Note, since we don't write any data to the TxFIFO, then it is
1335 * currently belived that we do not need to wait for any space in
1336 * the TxFIFO.
1337 */
1338static void s3c_hsotg_send_zlp(struct s3c_hsotg *hsotg,
1339 struct s3c_hsotg_req *req)
1340{
1341 u32 ctrl;
1342
1343 if (!req) {
1344 dev_warn(hsotg->dev, "%s: no request?\n", __func__);
1345 return;
1346 }
1347
1348 if (req->req.length == 0) {
1349 hsotg->eps[0].sent_zlp = 1;
1350 s3c_hsotg_enqueue_setup(hsotg);
1351 return;
1352 }
1353
1354 hsotg->eps[0].dir_in = 1;
1355 hsotg->eps[0].sent_zlp = 1;
1356
1357 dev_dbg(hsotg->dev, "sending zero-length packet\n");
1358
1359 /* issue a zero-sized packet to terminate this */
1360 writel(S3C_DxEPTSIZ_MC(1) | S3C_DxEPTSIZ_PktCnt(1) |
1361 S3C_DxEPTSIZ_XferSize(0), hsotg->regs + S3C_DIEPTSIZ(0));
1362
1363 ctrl = readl(hsotg->regs + S3C_DIEPCTL0);
1364 ctrl |= S3C_DxEPCTL_CNAK; /* clear NAK set by core */
1365 ctrl |= S3C_DxEPCTL_EPEna; /* ensure ep enabled */
1366 ctrl |= S3C_DxEPCTL_USBActEp;
1367 writel(ctrl, hsotg->regs + S3C_DIEPCTL0);
1368}
1369
1370/**
1371 * s3c_hsotg_handle_outdone - handle receiving OutDone/SetupDone from RXFIFO
1372 * @hsotg: The device instance
1373 * @epnum: The endpoint received from
1374 * @was_setup: Set if processing a SetupDone event.
1375 *
1376 * The RXFIFO has delivered an OutDone event, which means that the data
1377 * transfer for an OUT endpoint has been completed, either by a short
1378 * packet or by the finish of a transfer.
1379*/
1380static void s3c_hsotg_handle_outdone(struct s3c_hsotg *hsotg,
1381 int epnum, bool was_setup)
1382{
1383 struct s3c_hsotg_ep *hs_ep = &hsotg->eps[epnum];
1384 struct s3c_hsotg_req *hs_req = hs_ep->req;
1385 struct usb_request *req = &hs_req->req;
1386 int result = 0;
1387
1388 if (!hs_req) {
1389 dev_dbg(hsotg->dev, "%s: no request active\n", __func__);
1390 return;
1391 }
1392
1393 if (using_dma(hsotg)) {
1394 u32 epsize = readl(hsotg->regs + S3C_DOEPTSIZ(epnum));
1395 unsigned size_done;
1396 unsigned size_left;
1397
1398 /* Calculate the size of the transfer by checking how much
1399 * is left in the endpoint size register and then working it
1400 * out from the amount we loaded for the transfer.
1401 *
1402 * We need to do this as DMA pointers are always 32bit aligned
1403 * so may overshoot/undershoot the transfer.
1404 */
1405
1406 size_left = S3C_DxEPTSIZ_XferSize_GET(epsize);
1407
1408 size_done = hs_ep->size_loaded - size_left;
1409 size_done += hs_ep->last_load;
1410
1411 req->actual = size_done;
1412 }
1413
1414 if (req->actual < req->length && req->short_not_ok) {
1415 dev_dbg(hsotg->dev, "%s: got %d/%d (short not ok) => error\n",
1416 __func__, req->actual, req->length);
1417
1418 /* todo - what should we return here? there's no one else
1419 * even bothering to check the status. */
1420 }
1421
1422 if (epnum == 0) {
1423 if (!was_setup && req->complete != s3c_hsotg_complete_setup)
1424 s3c_hsotg_send_zlp(hsotg, hs_req);
1425 }
1426
1427 s3c_hsotg_complete_request_lock(hsotg, hs_ep, hs_req, result);
1428}
1429
1430/**
1431 * s3c_hsotg_read_frameno - read current frame number
1432 * @hsotg: The device instance
1433 *
1434 * Return the current frame number
1435*/
1436static u32 s3c_hsotg_read_frameno(struct s3c_hsotg *hsotg)
1437{
1438 u32 dsts;
1439
1440 dsts = readl(hsotg->regs + S3C_DSTS);
1441 dsts &= S3C_DSTS_SOFFN_MASK;
1442 dsts >>= S3C_DSTS_SOFFN_SHIFT;
1443
1444 return dsts;
1445}
1446
1447/**
1448 * s3c_hsotg_handle_rx - RX FIFO has data
1449 * @hsotg: The device instance
1450 *
1451 * The IRQ handler has detected that the RX FIFO has some data in it
1452 * that requires processing, so find out what is in there and do the
1453 * appropriate read.
1454 *
1455 * The RXFIFO is a true FIFO, the packets comming out are still in packet
1456 * chunks, so if you have x packets received on an endpoint you'll get x
1457 * FIFO events delivered, each with a packet's worth of data in it.
1458 *
1459 * When using DMA, we should not be processing events from the RXFIFO
1460 * as the actual data should be sent to the memory directly and we turn
1461 * on the completion interrupts to get notifications of transfer completion.
1462 */
1463void s3c_hsotg_handle_rx(struct s3c_hsotg *hsotg)
1464{
1465 u32 grxstsr = readl(hsotg->regs + S3C_GRXSTSP);
1466 u32 epnum, status, size;
1467
1468 WARN_ON(using_dma(hsotg));
1469
1470 epnum = grxstsr & S3C_GRXSTS_EPNum_MASK;
1471 status = grxstsr & S3C_GRXSTS_PktSts_MASK;
1472
1473 size = grxstsr & S3C_GRXSTS_ByteCnt_MASK;
1474 size >>= S3C_GRXSTS_ByteCnt_SHIFT;
1475
1476 if (1)
1477 dev_dbg(hsotg->dev, "%s: GRXSTSP=0x%08x (%d@%d)\n",
1478 __func__, grxstsr, size, epnum);
1479
1480#define __status(x) ((x) >> S3C_GRXSTS_PktSts_SHIFT)
1481
1482 switch (status >> S3C_GRXSTS_PktSts_SHIFT) {
1483 case __status(S3C_GRXSTS_PktSts_GlobalOutNAK):
1484 dev_dbg(hsotg->dev, "GlobalOutNAK\n");
1485 break;
1486
1487 case __status(S3C_GRXSTS_PktSts_OutDone):
1488 dev_dbg(hsotg->dev, "OutDone (Frame=0x%08x)\n",
1489 s3c_hsotg_read_frameno(hsotg));
1490
1491 if (!using_dma(hsotg))
1492 s3c_hsotg_handle_outdone(hsotg, epnum, false);
1493 break;
1494
1495 case __status(S3C_GRXSTS_PktSts_SetupDone):
1496 dev_dbg(hsotg->dev,
1497 "SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
1498 s3c_hsotg_read_frameno(hsotg),
1499 readl(hsotg->regs + S3C_DOEPCTL(0)));
1500
1501 s3c_hsotg_handle_outdone(hsotg, epnum, true);
1502 break;
1503
1504 case __status(S3C_GRXSTS_PktSts_OutRX):
1505 s3c_hsotg_rx_data(hsotg, epnum, size);
1506 break;
1507
1508 case __status(S3C_GRXSTS_PktSts_SetupRX):
1509 dev_dbg(hsotg->dev,
1510 "SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
1511 s3c_hsotg_read_frameno(hsotg),
1512 readl(hsotg->regs + S3C_DOEPCTL(0)));
1513
1514 s3c_hsotg_rx_data(hsotg, epnum, size);
1515 break;
1516
1517 default:
1518 dev_warn(hsotg->dev, "%s: unknown status %08x\n",
1519 __func__, grxstsr);
1520
1521 s3c_hsotg_dump(hsotg);
1522 break;
1523 }
1524}
1525
1526/**
1527 * s3c_hsotg_ep0_mps - turn max packet size into register setting
1528 * @mps: The maximum packet size in bytes.
1529*/
1530static u32 s3c_hsotg_ep0_mps(unsigned int mps)
1531{
1532 switch (mps) {
1533 case 64:
1534 return S3C_D0EPCTL_MPS_64;
1535 case 32:
1536 return S3C_D0EPCTL_MPS_32;
1537 case 16:
1538 return S3C_D0EPCTL_MPS_16;
1539 case 8:
1540 return S3C_D0EPCTL_MPS_8;
1541 }
1542
1543 /* bad max packet size, warn and return invalid result */
1544 WARN_ON(1);
1545 return (u32)-1;
1546}
1547
1548/**
1549 * s3c_hsotg_set_ep_maxpacket - set endpoint's max-packet field
1550 * @hsotg: The driver state.
1551 * @ep: The index number of the endpoint
1552 * @mps: The maximum packet size in bytes
1553 *
1554 * Configure the maximum packet size for the given endpoint, updating
1555 * the hardware control registers to reflect this.
1556 */
1557static void s3c_hsotg_set_ep_maxpacket(struct s3c_hsotg *hsotg,
1558 unsigned int ep, unsigned int mps)
1559{
1560 struct s3c_hsotg_ep *hs_ep = &hsotg->eps[ep];
1561 void __iomem *regs = hsotg->regs;
1562 u32 mpsval;
1563 u32 reg;
1564
1565 if (ep == 0) {
1566 /* EP0 is a special case */
1567 mpsval = s3c_hsotg_ep0_mps(mps);
1568 if (mpsval > 3)
1569 goto bad_mps;
1570 } else {
1571 if (mps >= S3C_DxEPCTL_MPS_LIMIT+1)
1572 goto bad_mps;
1573
1574 mpsval = mps;
1575 }
1576
1577 hs_ep->ep.maxpacket = mps;
1578
1579 /* update both the in and out endpoint controldir_ registers, even
1580 * if one of the directions may not be in use. */
1581
1582 reg = readl(regs + S3C_DIEPCTL(ep));
1583 reg &= ~S3C_DxEPCTL_MPS_MASK;
1584 reg |= mpsval;
1585 writel(reg, regs + S3C_DIEPCTL(ep));
1586
1587 reg = readl(regs + S3C_DOEPCTL(ep));
1588 reg &= ~S3C_DxEPCTL_MPS_MASK;
1589 reg |= mpsval;
1590 writel(reg, regs + S3C_DOEPCTL(ep));
1591
1592 return;
1593
1594bad_mps:
1595 dev_err(hsotg->dev, "ep%d: bad mps of %d\n", ep, mps);
1596}
1597
1598
1599/**
1600 * s3c_hsotg_trytx - check to see if anything needs transmitting
1601 * @hsotg: The driver state
1602 * @hs_ep: The driver endpoint to check.
1603 *
1604 * Check to see if there is a request that has data to send, and if so
1605 * make an attempt to write data into the FIFO.
1606 */
1607static int s3c_hsotg_trytx(struct s3c_hsotg *hsotg,
1608 struct s3c_hsotg_ep *hs_ep)
1609{
1610 struct s3c_hsotg_req *hs_req = hs_ep->req;
1611
1612 if (!hs_ep->dir_in || !hs_req)
1613 return 0;
1614
1615 if (hs_req->req.actual < hs_req->req.length) {
1616 dev_dbg(hsotg->dev, "trying to write more for ep%d\n",
1617 hs_ep->index);
1618 return s3c_hsotg_write_fifo(hsotg, hs_ep, hs_req);
1619 }
1620
1621 return 0;
1622}
1623
1624/**
1625 * s3c_hsotg_complete_in - complete IN transfer
1626 * @hsotg: The device state.
1627 * @hs_ep: The endpoint that has just completed.
1628 *
1629 * An IN transfer has been completed, update the transfer's state and then
1630 * call the relevant completion routines.
1631 */
1632static void s3c_hsotg_complete_in(struct s3c_hsotg *hsotg,
1633 struct s3c_hsotg_ep *hs_ep)
1634{
1635 struct s3c_hsotg_req *hs_req = hs_ep->req;
1636 u32 epsize = readl(hsotg->regs + S3C_DIEPTSIZ(hs_ep->index));
1637 int size_left, size_done;
1638
1639 if (!hs_req) {
1640 dev_dbg(hsotg->dev, "XferCompl but no req\n");
1641 return;
1642 }
1643
1644 /* Calculate the size of the transfer by checking how much is left
1645 * in the endpoint size register and then working it out from
1646 * the amount we loaded for the transfer.
1647 *
1648 * We do this even for DMA, as the transfer may have incremented
1649 * past the end of the buffer (DMA transfers are always 32bit
1650 * aligned).
1651 */
1652
1653 size_left = S3C_DxEPTSIZ_XferSize_GET(epsize);
1654
1655 size_done = hs_ep->size_loaded - size_left;
1656 size_done += hs_ep->last_load;
1657
1658 if (hs_req->req.actual != size_done)
1659 dev_dbg(hsotg->dev, "%s: adjusting size done %d => %d\n",
1660 __func__, hs_req->req.actual, size_done);
1661
1662 hs_req->req.actual = size_done;
1663
1664 /* if we did all of the transfer, and there is more data left
1665 * around, then try restarting the rest of the request */
1666
1667 if (!size_left && hs_req->req.actual < hs_req->req.length) {
1668 dev_dbg(hsotg->dev, "%s trying more for req...\n", __func__);
1669 s3c_hsotg_start_req(hsotg, hs_ep, hs_req, true);
1670 } else
1671 s3c_hsotg_complete_request_lock(hsotg, hs_ep, hs_req, 0);
1672}
1673
1674/**
1675 * s3c_hsotg_epint - handle an in/out endpoint interrupt
1676 * @hsotg: The driver state
1677 * @idx: The index for the endpoint (0..15)
1678 * @dir_in: Set if this is an IN endpoint
1679 *
1680 * Process and clear any interrupt pending for an individual endpoint
1681*/
1682static void s3c_hsotg_epint(struct s3c_hsotg *hsotg, unsigned int idx,
1683 int dir_in)
1684{
1685 struct s3c_hsotg_ep *hs_ep = &hsotg->eps[idx];
1686 u32 epint_reg = dir_in ? S3C_DIEPINT(idx) : S3C_DOEPINT(idx);
1687 u32 epctl_reg = dir_in ? S3C_DIEPCTL(idx) : S3C_DOEPCTL(idx);
1688 u32 epsiz_reg = dir_in ? S3C_DIEPTSIZ(idx) : S3C_DOEPTSIZ(idx);
1689 u32 ints;
1690 u32 clear = 0;
1691
1692 ints = readl(hsotg->regs + epint_reg);
1693
1694 dev_dbg(hsotg->dev, "%s: ep%d(%s) DxEPINT=0x%08x\n",
1695 __func__, idx, dir_in ? "in" : "out", ints);
1696
1697 if (ints & S3C_DxEPINT_XferCompl) {
1698 dev_dbg(hsotg->dev,
1699 "%s: XferCompl: DxEPCTL=0x%08x, DxEPTSIZ=%08x\n",
1700 __func__, readl(hsotg->regs + epctl_reg),
1701 readl(hsotg->regs + epsiz_reg));
1702
1703 /* we get OutDone from the FIFO, so we only need to look
1704 * at completing IN requests here */
1705 if (dir_in) {
1706 s3c_hsotg_complete_in(hsotg, hs_ep);
1707
1708 if (idx == 0)
1709 s3c_hsotg_enqueue_setup(hsotg);
1710 } else if (using_dma(hsotg)) {
1711 /* We're using DMA, we need to fire an OutDone here
1712 * as we ignore the RXFIFO. */
1713
1714 s3c_hsotg_handle_outdone(hsotg, idx, false);
1715 }
1716
1717 clear |= S3C_DxEPINT_XferCompl;
1718 }
1719
1720 if (ints & S3C_DxEPINT_EPDisbld) {
1721 dev_dbg(hsotg->dev, "%s: EPDisbld\n", __func__);
1722 clear |= S3C_DxEPINT_EPDisbld;
1723 }
1724
1725 if (ints & S3C_DxEPINT_AHBErr) {
1726 dev_dbg(hsotg->dev, "%s: AHBErr\n", __func__);
1727 clear |= S3C_DxEPINT_AHBErr;
1728 }
1729
1730 if (ints & S3C_DxEPINT_Setup) { /* Setup or Timeout */
1731 dev_dbg(hsotg->dev, "%s: Setup/Timeout\n", __func__);
1732
1733 if (using_dma(hsotg) && idx == 0) {
1734 /* this is the notification we've received a
1735 * setup packet. In non-DMA mode we'd get this
1736 * from the RXFIFO, instead we need to process
1737 * the setup here. */
1738
1739 if (dir_in)
1740 WARN_ON_ONCE(1);
1741 else
1742 s3c_hsotg_handle_outdone(hsotg, 0, true);
1743 }
1744
1745 clear |= S3C_DxEPINT_Setup;
1746 }
1747
1748 if (ints & S3C_DxEPINT_Back2BackSetup) {
1749 dev_dbg(hsotg->dev, "%s: B2BSetup/INEPNakEff\n", __func__);
1750 clear |= S3C_DxEPINT_Back2BackSetup;
1751 }
1752
1753 if (dir_in) {
1754 /* not sure if this is important, but we'll clear it anyway
1755 */
1756 if (ints & S3C_DIEPMSK_INTknTXFEmpMsk) {
1757 dev_dbg(hsotg->dev, "%s: ep%d: INTknTXFEmpMsk\n",
1758 __func__, idx);
1759 clear |= S3C_DIEPMSK_INTknTXFEmpMsk;
1760 }
1761
1762 /* this probably means something bad is happening */
1763 if (ints & S3C_DIEPMSK_INTknEPMisMsk) {
1764 dev_warn(hsotg->dev, "%s: ep%d: INTknEP\n",
1765 __func__, idx);
1766 clear |= S3C_DIEPMSK_INTknEPMisMsk;
1767 }
1768 }
1769
1770 writel(clear, hsotg->regs + epint_reg);
1771}
1772
1773/**
1774 * s3c_hsotg_irq_enumdone - Handle EnumDone interrupt (enumeration done)
1775 * @hsotg: The device state.
1776 *
1777 * Handle updating the device settings after the enumeration phase has
1778 * been completed.
1779*/
1780static void s3c_hsotg_irq_enumdone(struct s3c_hsotg *hsotg)
1781{
1782 u32 dsts = readl(hsotg->regs + S3C_DSTS);
1783 int ep0_mps = 0, ep_mps;
1784
1785 /* This should signal the finish of the enumeration phase
1786 * of the USB handshaking, so we should now know what rate
1787 * we connected at. */
1788
1789 dev_dbg(hsotg->dev, "EnumDone (DSTS=0x%08x)\n", dsts);
1790
1791 /* note, since we're limited by the size of transfer on EP0, and
1792 * it seems IN transfers must be a even number of packets we do
1793 * not advertise a 64byte MPS on EP0. */
1794
1795 /* catch both EnumSpd_FS and EnumSpd_FS48 */
1796 switch (dsts & S3C_DSTS_EnumSpd_MASK) {
1797 case S3C_DSTS_EnumSpd_FS:
1798 case S3C_DSTS_EnumSpd_FS48:
1799 hsotg->gadget.speed = USB_SPEED_FULL;
1800 dev_info(hsotg->dev, "new device is full-speed\n");
1801
1802 ep0_mps = EP0_MPS_LIMIT;
1803 ep_mps = 64;
1804 break;
1805
1806 case S3C_DSTS_EnumSpd_HS:
1807 dev_info(hsotg->dev, "new device is high-speed\n");
1808 hsotg->gadget.speed = USB_SPEED_HIGH;
1809
1810 ep0_mps = EP0_MPS_LIMIT;
1811 ep_mps = 512;
1812 break;
1813
1814 case S3C_DSTS_EnumSpd_LS:
1815 hsotg->gadget.speed = USB_SPEED_LOW;
1816 dev_info(hsotg->dev, "new device is low-speed\n");
1817
1818 /* note, we don't actually support LS in this driver at the
1819 * moment, and the documentation seems to imply that it isn't
1820 * supported by the PHYs on some of the devices.
1821 */
1822 break;
1823 }
1824
1825 /* we should now know the maximum packet size for an
1826 * endpoint, so set the endpoints to a default value. */
1827
1828 if (ep0_mps) {
1829 int i;
1830 s3c_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps);
1831 for (i = 1; i < S3C_HSOTG_EPS; i++)
1832 s3c_hsotg_set_ep_maxpacket(hsotg, i, ep_mps);
1833 }
1834
1835 /* ensure after enumeration our EP0 is active */
1836
1837 s3c_hsotg_enqueue_setup(hsotg);
1838
1839 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
1840 readl(hsotg->regs + S3C_DIEPCTL0),
1841 readl(hsotg->regs + S3C_DOEPCTL0));
1842}
1843
1844/**
1845 * kill_all_requests - remove all requests from the endpoint's queue
1846 * @hsotg: The device state.
1847 * @ep: The endpoint the requests may be on.
1848 * @result: The result code to use.
1849 * @force: Force removal of any current requests
1850 *
1851 * Go through the requests on the given endpoint and mark them
1852 * completed with the given result code.
1853 */
1854static void kill_all_requests(struct s3c_hsotg *hsotg,
1855 struct s3c_hsotg_ep *ep,
1856 int result, bool force)
1857{
1858 struct s3c_hsotg_req *req, *treq;
1859 unsigned long flags;
1860
1861 spin_lock_irqsave(&ep->lock, flags);
1862
1863 list_for_each_entry_safe(req, treq, &ep->queue, queue) {
1864 /* currently, we can't do much about an already
1865 * running request on an in endpoint */
1866
1867 if (ep->req == req && ep->dir_in && !force)
1868 continue;
1869
1870 s3c_hsotg_complete_request(hsotg, ep, req,
1871 result);
1872 }
1873
1874 spin_unlock_irqrestore(&ep->lock, flags);
1875}
1876
1877#define call_gadget(_hs, _entry) \
1878 if ((_hs)->gadget.speed != USB_SPEED_UNKNOWN && \
1879 (_hs)->driver && (_hs)->driver->_entry) \
1880 (_hs)->driver->_entry(&(_hs)->gadget);
1881
1882/**
1883 * s3c_hsotg_disconnect_irq - disconnect irq service
1884 * @hsotg: The device state.
1885 *
1886 * A disconnect IRQ has been received, meaning that the host has
1887 * lost contact with the bus. Remove all current transactions
1888 * and signal the gadget driver that this has happened.
1889*/
1890static void s3c_hsotg_disconnect_irq(struct s3c_hsotg *hsotg)
1891{
1892 unsigned ep;
1893
1894 for (ep = 0; ep < S3C_HSOTG_EPS; ep++)
1895 kill_all_requests(hsotg, &hsotg->eps[ep], -ESHUTDOWN, true);
1896
1897 call_gadget(hsotg, disconnect);
1898}
1899
1900/**
1901 * s3c_hsotg_irq_fifoempty - TX FIFO empty interrupt handler
1902 * @hsotg: The device state:
1903 * @periodic: True if this is a periodic FIFO interrupt
1904 */
1905static void s3c_hsotg_irq_fifoempty(struct s3c_hsotg *hsotg, bool periodic)
1906{
1907 struct s3c_hsotg_ep *ep;
1908 int epno, ret;
1909
1910 /* look through for any more data to transmit */
1911
1912 for (epno = 0; epno < S3C_HSOTG_EPS; epno++) {
1913 ep = &hsotg->eps[epno];
1914
1915 if (!ep->dir_in)
1916 continue;
1917
1918 if ((periodic && !ep->periodic) ||
1919 (!periodic && ep->periodic))
1920 continue;
1921
1922 ret = s3c_hsotg_trytx(hsotg, ep);
1923 if (ret < 0)
1924 break;
1925 }
1926}
1927
1928static struct s3c_hsotg *our_hsotg;
1929
1930/* IRQ flags which will trigger a retry around the IRQ loop */
1931#define IRQ_RETRY_MASK (S3C_GINTSTS_NPTxFEmp | \
1932 S3C_GINTSTS_PTxFEmp | \
1933 S3C_GINTSTS_RxFLvl)
1934
1935/**
1936 * s3c_hsotg_irq - handle device interrupt
1937 * @irq: The IRQ number triggered
1938 * @pw: The pw value when registered the handler.
1939 */
1940static irqreturn_t s3c_hsotg_irq(int irq, void *pw)
1941{
1942 struct s3c_hsotg *hsotg = pw;
1943 int retry_count = 8;
1944 u32 gintsts;
1945 u32 gintmsk;
1946
1947irq_retry:
1948 gintsts = readl(hsotg->regs + S3C_GINTSTS);
1949 gintmsk = readl(hsotg->regs + S3C_GINTMSK);
1950
1951 dev_dbg(hsotg->dev, "%s: %08x %08x (%08x) retry %d\n",
1952 __func__, gintsts, gintsts & gintmsk, gintmsk, retry_count);
1953
1954 gintsts &= gintmsk;
1955
1956 if (gintsts & S3C_GINTSTS_OTGInt) {
1957 u32 otgint = readl(hsotg->regs + S3C_GOTGINT);
1958
1959 dev_info(hsotg->dev, "OTGInt: %08x\n", otgint);
1960
1961 writel(otgint, hsotg->regs + S3C_GOTGINT);
1962 writel(S3C_GINTSTS_OTGInt, hsotg->regs + S3C_GINTSTS);
1963 }
1964
1965 if (gintsts & S3C_GINTSTS_DisconnInt) {
1966 dev_dbg(hsotg->dev, "%s: DisconnInt\n", __func__);
1967 writel(S3C_GINTSTS_DisconnInt, hsotg->regs + S3C_GINTSTS);
1968
1969 s3c_hsotg_disconnect_irq(hsotg);
1970 }
1971
1972 if (gintsts & S3C_GINTSTS_SessReqInt) {
1973 dev_dbg(hsotg->dev, "%s: SessReqInt\n", __func__);
1974 writel(S3C_GINTSTS_SessReqInt, hsotg->regs + S3C_GINTSTS);
1975 }
1976
1977 if (gintsts & S3C_GINTSTS_EnumDone) {
1978 s3c_hsotg_irq_enumdone(hsotg);
1979 writel(S3C_GINTSTS_EnumDone, hsotg->regs + S3C_GINTSTS);
1980 }
1981
1982 if (gintsts & S3C_GINTSTS_ConIDStsChng) {
1983 dev_dbg(hsotg->dev, "ConIDStsChg (DSTS=0x%08x, GOTCTL=%08x)\n",
1984 readl(hsotg->regs + S3C_DSTS),
1985 readl(hsotg->regs + S3C_GOTGCTL));
1986
1987 writel(S3C_GINTSTS_ConIDStsChng, hsotg->regs + S3C_GINTSTS);
1988 }
1989
1990 if (gintsts & (S3C_GINTSTS_OEPInt | S3C_GINTSTS_IEPInt)) {
1991 u32 daint = readl(hsotg->regs + S3C_DAINT);
1992 u32 daint_out = daint >> S3C_DAINT_OutEP_SHIFT;
1993 u32 daint_in = daint & ~(daint_out << S3C_DAINT_OutEP_SHIFT);
1994 int ep;
1995
1996 dev_dbg(hsotg->dev, "%s: daint=%08x\n", __func__, daint);
1997
1998 for (ep = 0; ep < 15 && daint_out; ep++, daint_out >>= 1) {
1999 if (daint_out & 1)
2000 s3c_hsotg_epint(hsotg, ep, 0);
2001 }
2002
2003 for (ep = 0; ep < 15 && daint_in; ep++, daint_in >>= 1) {
2004 if (daint_in & 1)
2005 s3c_hsotg_epint(hsotg, ep, 1);
2006 }
2007
2008 writel(daint, hsotg->regs + S3C_DAINT);
2009 writel(gintsts & (S3C_GINTSTS_OEPInt | S3C_GINTSTS_IEPInt),
2010 hsotg->regs + S3C_GINTSTS);
2011 }
2012
2013 if (gintsts & S3C_GINTSTS_USBRst) {
2014 dev_info(hsotg->dev, "%s: USBRst\n", __func__);
2015 dev_dbg(hsotg->dev, "GNPTXSTS=%08x\n",
2016 readl(hsotg->regs + S3C_GNPTXSTS));
2017
2018 kill_all_requests(hsotg, &hsotg->eps[0], -ECONNRESET, true);
2019
2020 /* it seems after a reset we can end up with a situation
2021 * where the TXFIFO still has data in it... try flushing
2022 * it to remove anything that may still be in it.
2023 */
2024
2025 if (1) {
2026 writel(S3C_GRSTCTL_TxFNum(0) | S3C_GRSTCTL_TxFFlsh,
2027 hsotg->regs + S3C_GRSTCTL);
2028
2029 dev_info(hsotg->dev, "GNPTXSTS=%08x\n",
2030 readl(hsotg->regs + S3C_GNPTXSTS));
2031 }
2032
2033 s3c_hsotg_enqueue_setup(hsotg);
2034
2035 writel(S3C_GINTSTS_USBRst, hsotg->regs + S3C_GINTSTS);
2036 }
2037
2038 /* check both FIFOs */
2039
2040 if (gintsts & S3C_GINTSTS_NPTxFEmp) {
2041 dev_dbg(hsotg->dev, "NPTxFEmp\n");
2042
2043 /* Disable the interrupt to stop it happening again
2044 * unless one of these endpoint routines decides that
2045 * it needs re-enabling */
2046
2047 s3c_hsotg_disable_gsint(hsotg, S3C_GINTSTS_NPTxFEmp);
2048 s3c_hsotg_irq_fifoempty(hsotg, false);
2049
2050 writel(S3C_GINTSTS_NPTxFEmp, hsotg->regs + S3C_GINTSTS);
2051 }
2052
2053 if (gintsts & S3C_GINTSTS_PTxFEmp) {
2054 dev_dbg(hsotg->dev, "PTxFEmp\n");
2055
2056 /* See note in S3C_GINTSTS_NPTxFEmp */
2057
2058 s3c_hsotg_disable_gsint(hsotg, S3C_GINTSTS_PTxFEmp);
2059 s3c_hsotg_irq_fifoempty(hsotg, true);
2060
2061 writel(S3C_GINTSTS_PTxFEmp, hsotg->regs + S3C_GINTSTS);
2062 }
2063
2064 if (gintsts & S3C_GINTSTS_RxFLvl) {
2065 /* note, since GINTSTS_RxFLvl doubles as FIFO-not-empty,
2066 * we need to retry s3c_hsotg_handle_rx if this is still
2067 * set. */
2068
2069 s3c_hsotg_handle_rx(hsotg);
2070 writel(S3C_GINTSTS_RxFLvl, hsotg->regs + S3C_GINTSTS);
2071 }
2072
2073 if (gintsts & S3C_GINTSTS_ModeMis) {
2074 dev_warn(hsotg->dev, "warning, mode mismatch triggered\n");
2075 writel(S3C_GINTSTS_ModeMis, hsotg->regs + S3C_GINTSTS);
2076 }
2077
2078 if (gintsts & S3C_GINTSTS_USBSusp) {
2079 dev_info(hsotg->dev, "S3C_GINTSTS_USBSusp\n");
2080 writel(S3C_GINTSTS_USBSusp, hsotg->regs + S3C_GINTSTS);
2081
2082 call_gadget(hsotg, suspend);
2083 }
2084
2085 if (gintsts & S3C_GINTSTS_WkUpInt) {
2086 dev_info(hsotg->dev, "S3C_GINTSTS_WkUpIn\n");
2087 writel(S3C_GINTSTS_WkUpInt, hsotg->regs + S3C_GINTSTS);
2088
2089 call_gadget(hsotg, resume);
2090 }
2091
2092 if (gintsts & S3C_GINTSTS_ErlySusp) {
2093 dev_dbg(hsotg->dev, "S3C_GINTSTS_ErlySusp\n");
2094 writel(S3C_GINTSTS_ErlySusp, hsotg->regs + S3C_GINTSTS);
2095 }
2096
2097 /* these next two seem to crop-up occasionally causing the core
2098 * to shutdown the USB transfer, so try clearing them and logging
2099 * the occurence. */
2100
2101 if (gintsts & S3C_GINTSTS_GOUTNakEff) {
2102 dev_info(hsotg->dev, "GOUTNakEff triggered\n");
2103
2104 s3c_hsotg_dump(hsotg);
2105
2106 writel(S3C_DCTL_CGOUTNak, hsotg->regs + S3C_DCTL);
2107 writel(S3C_GINTSTS_GOUTNakEff, hsotg->regs + S3C_GINTSTS);
2108 }
2109
2110 if (gintsts & S3C_GINTSTS_GINNakEff) {
2111 dev_info(hsotg->dev, "GINNakEff triggered\n");
2112
2113 s3c_hsotg_dump(hsotg);
2114
2115 writel(S3C_DCTL_CGNPInNAK, hsotg->regs + S3C_DCTL);
2116 writel(S3C_GINTSTS_GINNakEff, hsotg->regs + S3C_GINTSTS);
2117 }
2118
2119 /* if we've had fifo events, we should try and go around the
2120 * loop again to see if there's any point in returning yet. */
2121
2122 if (gintsts & IRQ_RETRY_MASK && --retry_count > 0)
2123 goto irq_retry;
2124
2125 return IRQ_HANDLED;
2126}
2127
2128/**
2129 * s3c_hsotg_ep_enable - enable the given endpoint
2130 * @ep: The USB endpint to configure
2131 * @desc: The USB endpoint descriptor to configure with.
2132 *
2133 * This is called from the USB gadget code's usb_ep_enable().
2134*/
2135static int s3c_hsotg_ep_enable(struct usb_ep *ep,
2136 const struct usb_endpoint_descriptor *desc)
2137{
2138 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
2139 struct s3c_hsotg *hsotg = hs_ep->parent;
2140 unsigned long flags;
2141 int index = hs_ep->index;
2142 u32 epctrl_reg;
2143 u32 epctrl;
2144 u32 mps;
2145 int dir_in;
2146
2147 dev_dbg(hsotg->dev,
2148 "%s: ep %s: a 0x%02x, attr 0x%02x, mps 0x%04x, intr %d\n",
2149 __func__, ep->name, desc->bEndpointAddress, desc->bmAttributes,
2150 desc->wMaxPacketSize, desc->bInterval);
2151
2152 /* not to be called for EP0 */
2153 WARN_ON(index == 0);
2154
2155 dir_in = (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK) ? 1 : 0;
2156 if (dir_in != hs_ep->dir_in) {
2157 dev_err(hsotg->dev, "%s: direction mismatch!\n", __func__);
2158 return -EINVAL;
2159 }
2160
2161 mps = le16_to_cpu(desc->wMaxPacketSize);
2162
2163 /* note, we handle this here instead of s3c_hsotg_set_ep_maxpacket */
2164
2165 epctrl_reg = dir_in ? S3C_DIEPCTL(index) : S3C_DOEPCTL(index);
2166 epctrl = readl(hsotg->regs + epctrl_reg);
2167
2168 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x from 0x%08x\n",
2169 __func__, epctrl, epctrl_reg);
2170
2171 spin_lock_irqsave(&hs_ep->lock, flags);
2172
2173 epctrl &= ~(S3C_DxEPCTL_EPType_MASK | S3C_DxEPCTL_MPS_MASK);
2174 epctrl |= S3C_DxEPCTL_MPS(mps);
2175
2176 /* mark the endpoint as active, otherwise the core may ignore
2177 * transactions entirely for this endpoint */
2178 epctrl |= S3C_DxEPCTL_USBActEp;
2179
2180 /* set the NAK status on the endpoint, otherwise we might try and
2181 * do something with data that we've yet got a request to process
2182 * since the RXFIFO will take data for an endpoint even if the
2183 * size register hasn't been set.
2184 */
2185
2186 epctrl |= S3C_DxEPCTL_SNAK;
2187
2188 /* update the endpoint state */
2189 hs_ep->ep.maxpacket = mps;
2190
2191 /* default, set to non-periodic */
2192 hs_ep->periodic = 0;
2193
2194 switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
2195 case USB_ENDPOINT_XFER_ISOC:
2196 dev_err(hsotg->dev, "no current ISOC support\n");
2197 return -EINVAL;
2198
2199 case USB_ENDPOINT_XFER_BULK:
2200 epctrl |= S3C_DxEPCTL_EPType_Bulk;
2201 break;
2202
2203 case USB_ENDPOINT_XFER_INT:
2204 if (dir_in) {
2205 /* Allocate our TxFNum by simply using the index
2206 * of the endpoint for the moment. We could do
2207 * something better if the host indicates how
2208 * many FIFOs we are expecting to use. */
2209
2210 hs_ep->periodic = 1;
2211 epctrl |= S3C_DxEPCTL_TxFNum(index);
2212 }
2213
2214 epctrl |= S3C_DxEPCTL_EPType_Intterupt;
2215 break;
2216
2217 case USB_ENDPOINT_XFER_CONTROL:
2218 epctrl |= S3C_DxEPCTL_EPType_Control;
2219 break;
2220 }
2221
2222 /* for non control endpoints, set PID to D0 */
2223 if (index)
2224 epctrl |= S3C_DxEPCTL_SetD0PID;
2225
2226 dev_dbg(hsotg->dev, "%s: write DxEPCTL=0x%08x\n",
2227 __func__, epctrl);
2228
2229 writel(epctrl, hsotg->regs + epctrl_reg);
2230 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x\n",
2231 __func__, readl(hsotg->regs + epctrl_reg));
2232
2233 /* enable the endpoint interrupt */
2234 s3c_hsotg_ctrl_epint(hsotg, index, dir_in, 1);
2235
2236 spin_unlock_irqrestore(&hs_ep->lock, flags);
2237 return 0;
2238}
2239
2240static int s3c_hsotg_ep_disable(struct usb_ep *ep)
2241{
2242 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
2243 struct s3c_hsotg *hsotg = hs_ep->parent;
2244 int dir_in = hs_ep->dir_in;
2245 int index = hs_ep->index;
2246 unsigned long flags;
2247 u32 epctrl_reg;
2248 u32 ctrl;
2249
2250 dev_info(hsotg->dev, "%s(ep %p)\n", __func__, ep);
2251
2252 if (ep == &hsotg->eps[0].ep) {
2253 dev_err(hsotg->dev, "%s: called for ep0\n", __func__);
2254 return -EINVAL;
2255 }
2256
2257 epctrl_reg = dir_in ? S3C_DIEPCTL(index) : S3C_DOEPCTL(index);
2258
2259 /* terminate all requests with shutdown */
2260 kill_all_requests(hsotg, hs_ep, -ESHUTDOWN, false);
2261
2262 spin_lock_irqsave(&hs_ep->lock, flags);
2263
2264 ctrl = readl(hsotg->regs + epctrl_reg);
2265 ctrl &= ~S3C_DxEPCTL_EPEna;
2266 ctrl &= ~S3C_DxEPCTL_USBActEp;
2267 ctrl |= S3C_DxEPCTL_SNAK;
2268
2269 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
2270 writel(ctrl, hsotg->regs + epctrl_reg);
2271
2272 /* disable endpoint interrupts */
2273 s3c_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 0);
2274
2275 spin_unlock_irqrestore(&hs_ep->lock, flags);
2276 return 0;
2277}
2278
2279/**
2280 * on_list - check request is on the given endpoint
2281 * @ep: The endpoint to check.
2282 * @test: The request to test if it is on the endpoint.
2283*/
2284static bool on_list(struct s3c_hsotg_ep *ep, struct s3c_hsotg_req *test)
2285{
2286 struct s3c_hsotg_req *req, *treq;
2287
2288 list_for_each_entry_safe(req, treq, &ep->queue, queue) {
2289 if (req == test)
2290 return true;
2291 }
2292
2293 return false;
2294}
2295
2296static int s3c_hsotg_ep_dequeue(struct usb_ep *ep, struct usb_request *req)
2297{
2298 struct s3c_hsotg_req *hs_req = our_req(req);
2299 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
2300 struct s3c_hsotg *hs = hs_ep->parent;
2301 unsigned long flags;
2302
2303 dev_info(hs->dev, "ep_dequeue(%p,%p)\n", ep, req);
2304
2305 if (hs_req == hs_ep->req) {
2306 dev_dbg(hs->dev, "%s: already in progress\n", __func__);
2307 return -EINPROGRESS;
2308 }
2309
2310 spin_lock_irqsave(&hs_ep->lock, flags);
2311
2312 if (!on_list(hs_ep, hs_req)) {
2313 spin_unlock_irqrestore(&hs_ep->lock, flags);
2314 return -EINVAL;
2315 }
2316
2317 s3c_hsotg_complete_request(hs, hs_ep, hs_req, -ECONNRESET);
2318 spin_unlock_irqrestore(&hs_ep->lock, flags);
2319
2320 return 0;
2321}
2322
2323static int s3c_hsotg_ep_sethalt(struct usb_ep *ep, int value)
2324{
2325 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
2326 struct s3c_hsotg *hs = hs_ep->parent;
2327 int index = hs_ep->index;
2328 unsigned long irqflags;
2329 u32 epreg;
2330 u32 epctl;
2331
2332 dev_info(hs->dev, "%s(ep %p %s, %d)\n", __func__, ep, ep->name, value);
2333
2334 spin_lock_irqsave(&hs_ep->lock, irqflags);
2335
2336 /* write both IN and OUT control registers */
2337
2338 epreg = S3C_DIEPCTL(index);
2339 epctl = readl(hs->regs + epreg);
2340
2341 if (value)
2342 epctl |= S3C_DxEPCTL_Stall;
2343 else
2344 epctl &= ~S3C_DxEPCTL_Stall;
2345
2346 writel(epctl, hs->regs + epreg);
2347
2348 epreg = S3C_DOEPCTL(index);
2349 epctl = readl(hs->regs + epreg);
2350
2351 if (value)
2352 epctl |= S3C_DxEPCTL_Stall;
2353 else
2354 epctl &= ~S3C_DxEPCTL_Stall;
2355
2356 writel(epctl, hs->regs + epreg);
2357
2358 spin_unlock_irqrestore(&hs_ep->lock, irqflags);
2359
2360 return 0;
2361}
2362
2363static struct usb_ep_ops s3c_hsotg_ep_ops = {
2364 .enable = s3c_hsotg_ep_enable,
2365 .disable = s3c_hsotg_ep_disable,
2366 .alloc_request = s3c_hsotg_ep_alloc_request,
2367 .free_request = s3c_hsotg_ep_free_request,
2368 .queue = s3c_hsotg_ep_queue,
2369 .dequeue = s3c_hsotg_ep_dequeue,
2370 .set_halt = s3c_hsotg_ep_sethalt,
2371 /* note, don't belive we have any call for the fifo routines */
2372};
2373
2374/**
2375 * s3c_hsotg_corereset - issue softreset to the core
2376 * @hsotg: The device state
2377 *
2378 * Issue a soft reset to the core, and await the core finishing it.
2379*/
2380static int s3c_hsotg_corereset(struct s3c_hsotg *hsotg)
2381{
2382 int timeout;
2383 u32 grstctl;
2384
2385 dev_dbg(hsotg->dev, "resetting core\n");
2386
2387 /* issue soft reset */
2388 writel(S3C_GRSTCTL_CSftRst, hsotg->regs + S3C_GRSTCTL);
2389
2390 timeout = 1000;
2391 do {
2392 grstctl = readl(hsotg->regs + S3C_GRSTCTL);
2393 } while (!(grstctl & S3C_GRSTCTL_CSftRst) && timeout-- > 0);
2394
2395 if (!grstctl & S3C_GRSTCTL_CSftRst) {
2396 dev_err(hsotg->dev, "Failed to get CSftRst asserted\n");
2397 return -EINVAL;
2398 }
2399
2400 timeout = 1000;
2401
2402 while (1) {
2403 u32 grstctl = readl(hsotg->regs + S3C_GRSTCTL);
2404
2405 if (timeout-- < 0) {
2406 dev_info(hsotg->dev,
2407 "%s: reset failed, GRSTCTL=%08x\n",
2408 __func__, grstctl);
2409 return -ETIMEDOUT;
2410 }
2411
2412 if (grstctl & S3C_GRSTCTL_CSftRst)
2413 continue;
2414
2415 if (!(grstctl & S3C_GRSTCTL_AHBIdle))
2416 continue;
2417
2418 break; /* reset done */
2419 }
2420
2421 dev_dbg(hsotg->dev, "reset successful\n");
2422 return 0;
2423}
2424
2425int usb_gadget_register_driver(struct usb_gadget_driver *driver)
2426{
2427 struct s3c_hsotg *hsotg = our_hsotg;
2428 int ret;
2429
2430 if (!hsotg) {
2431 printk(KERN_ERR "%s: called with no device\n", __func__);
2432 return -ENODEV;
2433 }
2434
2435 if (!driver) {
2436 dev_err(hsotg->dev, "%s: no driver\n", __func__);
2437 return -EINVAL;
2438 }
2439
2440 if (driver->speed != USB_SPEED_HIGH &&
2441 driver->speed != USB_SPEED_FULL) {
2442 dev_err(hsotg->dev, "%s: bad speed\n", __func__);
2443 }
2444
2445 if (!driver->bind || !driver->setup) {
2446 dev_err(hsotg->dev, "%s: missing entry points\n", __func__);
2447 return -EINVAL;
2448 }
2449
2450 WARN_ON(hsotg->driver);
2451
2452 driver->driver.bus = NULL;
2453 hsotg->driver = driver;
2454 hsotg->gadget.dev.driver = &driver->driver;
2455 hsotg->gadget.dev.dma_mask = hsotg->dev->dma_mask;
2456 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
2457
2458 ret = device_add(&hsotg->gadget.dev);
2459 if (ret) {
2460 dev_err(hsotg->dev, "failed to register gadget device\n");
2461 goto err;
2462 }
2463
2464 ret = driver->bind(&hsotg->gadget);
2465 if (ret) {
2466 dev_err(hsotg->dev, "failed bind %s\n", driver->driver.name);
2467
2468 hsotg->gadget.dev.driver = NULL;
2469 hsotg->driver = NULL;
2470 goto err;
2471 }
2472
2473 /* we must now enable ep0 ready for host detection and then
2474 * set configuration. */
2475
2476 s3c_hsotg_corereset(hsotg);
2477
2478 /* set the PLL on, remove the HNP/SRP and set the PHY */
2479 writel(S3C_GUSBCFG_PHYIf16 | S3C_GUSBCFG_TOutCal(7) |
2480 (0x5 << 10), hsotg->regs + S3C_GUSBCFG);
2481
2482 /* looks like soft-reset changes state of FIFOs */
2483 s3c_hsotg_init_fifo(hsotg);
2484
2485 __orr32(hsotg->regs + S3C_DCTL, S3C_DCTL_SftDiscon);
2486
2487 writel(1 << 18 | S3C_DCFG_DevSpd_HS, hsotg->regs + S3C_DCFG);
2488
2489 writel(S3C_GINTSTS_DisconnInt | S3C_GINTSTS_SessReqInt |
2490 S3C_GINTSTS_ConIDStsChng | S3C_GINTSTS_USBRst |
2491 S3C_GINTSTS_EnumDone | S3C_GINTSTS_OTGInt |
2492 S3C_GINTSTS_USBSusp | S3C_GINTSTS_WkUpInt |
2493 S3C_GINTSTS_GOUTNakEff | S3C_GINTSTS_GINNakEff |
2494 S3C_GINTSTS_ErlySusp,
2495 hsotg->regs + S3C_GINTMSK);
2496
2497 if (using_dma(hsotg))
2498 writel(S3C_GAHBCFG_GlblIntrEn | S3C_GAHBCFG_DMAEn |
2499 S3C_GAHBCFG_HBstLen_Incr4,
2500 hsotg->regs + S3C_GAHBCFG);
2501 else
2502 writel(S3C_GAHBCFG_GlblIntrEn, hsotg->regs + S3C_GAHBCFG);
2503
2504 /* Enabling INTknTXFEmpMsk here seems to be a big mistake, we end
2505 * up being flooded with interrupts if the host is polling the
2506 * endpoint to try and read data. */
2507
2508 writel(S3C_DIEPMSK_TimeOUTMsk | S3C_DIEPMSK_AHBErrMsk |
2509 S3C_DIEPMSK_INTknEPMisMsk |
2510 S3C_DIEPMSK_EPDisbldMsk | S3C_DIEPMSK_XferComplMsk,
2511 hsotg->regs + S3C_DIEPMSK);
2512
2513 /* don't need XferCompl, we get that from RXFIFO in slave mode. In
2514 * DMA mode we may need this. */
2515 writel(S3C_DOEPMSK_SetupMsk | S3C_DOEPMSK_AHBErrMsk |
2516 S3C_DOEPMSK_EPDisbldMsk |
2517 using_dma(hsotg) ? (S3C_DIEPMSK_XferComplMsk |
2518 S3C_DIEPMSK_TimeOUTMsk) : 0,
2519 hsotg->regs + S3C_DOEPMSK);
2520
2521 writel(0, hsotg->regs + S3C_DAINTMSK);
2522
2523 dev_info(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
2524 readl(hsotg->regs + S3C_DIEPCTL0),
2525 readl(hsotg->regs + S3C_DOEPCTL0));
2526
2527 /* enable in and out endpoint interrupts */
2528 s3c_hsotg_en_gsint(hsotg, S3C_GINTSTS_OEPInt | S3C_GINTSTS_IEPInt);
2529
2530 /* Enable the RXFIFO when in slave mode, as this is how we collect
2531 * the data. In DMA mode, we get events from the FIFO but also
2532 * things we cannot process, so do not use it. */
2533 if (!using_dma(hsotg))
2534 s3c_hsotg_en_gsint(hsotg, S3C_GINTSTS_RxFLvl);
2535
2536 /* Enable interrupts for EP0 in and out */
2537 s3c_hsotg_ctrl_epint(hsotg, 0, 0, 1);
2538 s3c_hsotg_ctrl_epint(hsotg, 0, 1, 1);
2539
2540 __orr32(hsotg->regs + S3C_DCTL, S3C_DCTL_PWROnPrgDone);
2541 udelay(10); /* see openiboot */
2542 __bic32(hsotg->regs + S3C_DCTL, S3C_DCTL_PWROnPrgDone);
2543
2544 dev_info(hsotg->dev, "DCTL=0x%08x\n", readl(hsotg->regs + S3C_DCTL));
2545
2546 /* S3C_DxEPCTL_USBActEp says RO in manual, but seems to be set by
2547 writing to the EPCTL register.. */
2548
2549 /* set to read 1 8byte packet */
2550 writel(S3C_DxEPTSIZ_MC(1) | S3C_DxEPTSIZ_PktCnt(1) |
2551 S3C_DxEPTSIZ_XferSize(8), hsotg->regs + DOEPTSIZ0);
2552
2553 writel(s3c_hsotg_ep0_mps(hsotg->eps[0].ep.maxpacket) |
2554 S3C_DxEPCTL_CNAK | S3C_DxEPCTL_EPEna |
2555 S3C_DxEPCTL_USBActEp,
2556 hsotg->regs + S3C_DOEPCTL0);
2557
2558 /* enable, but don't activate EP0in */
2559 writel(s3c_hsotg_ep0_mps(hsotg->eps[0].ep.maxpacket) |
2560 S3C_DxEPCTL_USBActEp, hsotg->regs + S3C_DIEPCTL0);
2561
2562 s3c_hsotg_enqueue_setup(hsotg);
2563
2564 dev_info(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
2565 readl(hsotg->regs + S3C_DIEPCTL0),
2566 readl(hsotg->regs + S3C_DOEPCTL0));
2567
2568 /* clear global NAKs */
2569 writel(S3C_DCTL_CGOUTNak | S3C_DCTL_CGNPInNAK,
2570 hsotg->regs + S3C_DCTL);
2571
2572 /* remove the soft-disconnect and let's go */
2573 __bic32(hsotg->regs + S3C_DCTL, S3C_DCTL_SftDiscon);
2574
2575 /* report to the user, and return */
2576
2577 dev_info(hsotg->dev, "bound driver %s\n", driver->driver.name);
2578 return 0;
2579
2580err:
2581 hsotg->driver = NULL;
2582 hsotg->gadget.dev.driver = NULL;
2583 return ret;
2584}
2585
2586int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
2587{
2588 struct s3c_hsotg *hsotg = our_hsotg;
2589 int ep;
2590
2591 if (!hsotg)
2592 return -ENODEV;
2593
2594 if (!driver || driver != hsotg->driver || !driver->unbind)
2595 return -EINVAL;
2596
2597 /* all endpoints should be shutdown */
2598 for (ep = 0; ep < S3C_HSOTG_EPS; ep++)
2599 s3c_hsotg_ep_disable(&hsotg->eps[ep].ep);
2600
2601 call_gadget(hsotg, disconnect);
2602
2603 driver->unbind(&hsotg->gadget);
2604 hsotg->driver = NULL;
2605 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
2606
2607 device_del(&hsotg->gadget.dev);
2608
2609 dev_info(hsotg->dev, "unregistered gadget driver '%s'\n",
2610 driver->driver.name);
2611
2612 return 0;
2613}
2614EXPORT_SYMBOL(usb_gadget_unregister_driver);
2615
2616static int s3c_hsotg_gadget_getframe(struct usb_gadget *gadget)
2617{
2618 return s3c_hsotg_read_frameno(to_hsotg(gadget));
2619}
2620
2621static struct usb_gadget_ops s3c_hsotg_gadget_ops = {
2622 .get_frame = s3c_hsotg_gadget_getframe,
2623};
2624
2625/**
2626 * s3c_hsotg_initep - initialise a single endpoint
2627 * @hsotg: The device state.
2628 * @hs_ep: The endpoint to be initialised.
2629 * @epnum: The endpoint number
2630 *
2631 * Initialise the given endpoint (as part of the probe and device state
2632 * creation) to give to the gadget driver. Setup the endpoint name, any
2633 * direction information and other state that may be required.
2634 */
2635static void __devinit s3c_hsotg_initep(struct s3c_hsotg *hsotg,
2636 struct s3c_hsotg_ep *hs_ep,
2637 int epnum)
2638{
2639 u32 ptxfifo;
2640 char *dir;
2641
2642 if (epnum == 0)
2643 dir = "";
2644 else if ((epnum % 2) == 0) {
2645 dir = "out";
2646 } else {
2647 dir = "in";
2648 hs_ep->dir_in = 1;
2649 }
2650
2651 hs_ep->index = epnum;
2652
2653 snprintf(hs_ep->name, sizeof(hs_ep->name), "ep%d%s", epnum, dir);
2654
2655 INIT_LIST_HEAD(&hs_ep->queue);
2656 INIT_LIST_HEAD(&hs_ep->ep.ep_list);
2657
2658 spin_lock_init(&hs_ep->lock);
2659
2660 /* add to the list of endpoints known by the gadget driver */
2661 if (epnum)
2662 list_add_tail(&hs_ep->ep.ep_list, &hsotg->gadget.ep_list);
2663
2664 hs_ep->parent = hsotg;
2665 hs_ep->ep.name = hs_ep->name;
2666 hs_ep->ep.maxpacket = epnum ? 512 : EP0_MPS_LIMIT;
2667 hs_ep->ep.ops = &s3c_hsotg_ep_ops;
2668
2669 /* Read the FIFO size for the Periodic TX FIFO, even if we're
2670 * an OUT endpoint, we may as well do this if in future the
2671 * code is changed to make each endpoint's direction changeable.
2672 */
2673
2674 ptxfifo = readl(hsotg->regs + S3C_DPTXFSIZn(epnum));
2675 hs_ep->fifo_size = S3C_DPTXFSIZn_DPTxFSize_GET(ptxfifo);
2676
2677 /* if we're using dma, we need to set the next-endpoint pointer
2678 * to be something valid.
2679 */
2680
2681 if (using_dma(hsotg)) {
2682 u32 next = S3C_DxEPCTL_NextEp((epnum + 1) % 15);
2683 writel(next, hsotg->regs + S3C_DIEPCTL(epnum));
2684 writel(next, hsotg->regs + S3C_DOEPCTL(epnum));
2685 }
2686}
2687
2688/**
2689 * s3c_hsotg_otgreset - reset the OtG phy block
2690 * @hsotg: The host state.
2691 *
2692 * Power up the phy, set the basic configuration and start the PHY.
2693 */
2694static void s3c_hsotg_otgreset(struct s3c_hsotg *hsotg)
2695{
2696 u32 osc;
2697
2698 writel(0, S3C_PHYPWR);
2699 mdelay(1);
2700
2701 osc = hsotg->plat->is_osc ? S3C_PHYCLK_EXT_OSC : 0;
2702
2703 writel(osc | 0x10, S3C_PHYCLK);
2704
2705 /* issue a full set of resets to the otg and core */
2706
2707 writel(S3C_RSTCON_PHY, S3C_RSTCON);
2708 udelay(20); /* at-least 10uS */
2709 writel(0, S3C_RSTCON);
2710}
2711
2712
2713static void s3c_hsotg_init(struct s3c_hsotg *hsotg)
2714{
2715 /* unmask subset of endpoint interrupts */
2716
2717 writel(S3C_DIEPMSK_TimeOUTMsk | S3C_DIEPMSK_AHBErrMsk |
2718 S3C_DIEPMSK_EPDisbldMsk | S3C_DIEPMSK_XferComplMsk,
2719 hsotg->regs + S3C_DIEPMSK);
2720
2721 writel(S3C_DOEPMSK_SetupMsk | S3C_DOEPMSK_AHBErrMsk |
2722 S3C_DOEPMSK_EPDisbldMsk | S3C_DOEPMSK_XferComplMsk,
2723 hsotg->regs + S3C_DOEPMSK);
2724
2725 writel(0, hsotg->regs + S3C_DAINTMSK);
2726
2727 if (0) {
2728 /* post global nak until we're ready */
2729 writel(S3C_DCTL_SGNPInNAK | S3C_DCTL_SGOUTNak,
2730 hsotg->regs + S3C_DCTL);
2731 }
2732
2733 /* setup fifos */
2734
2735 dev_info(hsotg->dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
2736 readl(hsotg->regs + S3C_GRXFSIZ),
2737 readl(hsotg->regs + S3C_GNPTXFSIZ));
2738
2739 s3c_hsotg_init_fifo(hsotg);
2740
2741 /* set the PLL on, remove the HNP/SRP and set the PHY */
2742 writel(S3C_GUSBCFG_PHYIf16 | S3C_GUSBCFG_TOutCal(7) | (0x5 << 10),
2743 hsotg->regs + S3C_GUSBCFG);
2744
2745 writel(using_dma(hsotg) ? S3C_GAHBCFG_DMAEn : 0x0,
2746 hsotg->regs + S3C_GAHBCFG);
2747}
2748
2749static void s3c_hsotg_dump(struct s3c_hsotg *hsotg)
2750{
2751 struct device *dev = hsotg->dev;
2752 void __iomem *regs = hsotg->regs;
2753 u32 val;
2754 int idx;
2755
2756 dev_info(dev, "DCFG=0x%08x, DCTL=0x%08x, DIEPMSK=%08x\n",
2757 readl(regs + S3C_DCFG), readl(regs + S3C_DCTL),
2758 readl(regs + S3C_DIEPMSK));
2759
2760 dev_info(dev, "GAHBCFG=0x%08x, 0x44=0x%08x\n",
2761 readl(regs + S3C_GAHBCFG), readl(regs + 0x44));
2762
2763 dev_info(dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
2764 readl(regs + S3C_GRXFSIZ), readl(regs + S3C_GNPTXFSIZ));
2765
2766 /* show periodic fifo settings */
2767
2768 for (idx = 1; idx <= 15; idx++) {
2769 val = readl(regs + S3C_DPTXFSIZn(idx));
2770 dev_info(dev, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx,
2771 val >> S3C_DPTXFSIZn_DPTxFSize_SHIFT,
2772 val & S3C_DPTXFSIZn_DPTxFStAddr_MASK);
2773 }
2774
2775 for (idx = 0; idx < 15; idx++) {
2776 dev_info(dev,
2777 "ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx,
2778 readl(regs + S3C_DIEPCTL(idx)),
2779 readl(regs + S3C_DIEPTSIZ(idx)),
2780 readl(regs + S3C_DIEPDMA(idx)));
2781
2782 val = readl(regs + S3C_DOEPCTL(idx));
2783 dev_info(dev,
2784 "ep%d-out: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n",
2785 idx, readl(regs + S3C_DOEPCTL(idx)),
2786 readl(regs + S3C_DOEPTSIZ(idx)),
2787 readl(regs + S3C_DOEPDMA(idx)));
2788
2789 }
2790
2791 dev_info(dev, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n",
2792 readl(regs + S3C_DVBUSDIS), readl(regs + S3C_DVBUSPULSE));
2793}
2794
2795
2796/**
2797 * state_show - debugfs: show overall driver and device state.
2798 * @seq: The seq file to write to.
2799 * @v: Unused parameter.
2800 *
2801 * This debugfs entry shows the overall state of the hardware and
2802 * some general information about each of the endpoints available
2803 * to the system.
2804 */
2805static int state_show(struct seq_file *seq, void *v)
2806{
2807 struct s3c_hsotg *hsotg = seq->private;
2808 void __iomem *regs = hsotg->regs;
2809 int idx;
2810
2811 seq_printf(seq, "DCFG=0x%08x, DCTL=0x%08x, DSTS=0x%08x\n",
2812 readl(regs + S3C_DCFG),
2813 readl(regs + S3C_DCTL),
2814 readl(regs + S3C_DSTS));
2815
2816 seq_printf(seq, "DIEPMSK=0x%08x, DOEPMASK=0x%08x\n",
2817 readl(regs + S3C_DIEPMSK), readl(regs + S3C_DOEPMSK));
2818
2819 seq_printf(seq, "GINTMSK=0x%08x, GINTSTS=0x%08x\n",
2820 readl(regs + S3C_GINTMSK),
2821 readl(regs + S3C_GINTSTS));
2822
2823 seq_printf(seq, "DAINTMSK=0x%08x, DAINT=0x%08x\n",
2824 readl(regs + S3C_DAINTMSK),
2825 readl(regs + S3C_DAINT));
2826
2827 seq_printf(seq, "GNPTXSTS=0x%08x, GRXSTSR=%08x\n",
2828 readl(regs + S3C_GNPTXSTS),
2829 readl(regs + S3C_GRXSTSR));
2830
2831 seq_printf(seq, "\nEndpoint status:\n");
2832
2833 for (idx = 0; idx < 15; idx++) {
2834 u32 in, out;
2835
2836 in = readl(regs + S3C_DIEPCTL(idx));
2837 out = readl(regs + S3C_DOEPCTL(idx));
2838
2839 seq_printf(seq, "ep%d: DIEPCTL=0x%08x, DOEPCTL=0x%08x",
2840 idx, in, out);
2841
2842 in = readl(regs + S3C_DIEPTSIZ(idx));
2843 out = readl(regs + S3C_DOEPTSIZ(idx));
2844
2845 seq_printf(seq, ", DIEPTSIZ=0x%08x, DOEPTSIZ=0x%08x",
2846 in, out);
2847
2848 seq_printf(seq, "\n");
2849 }
2850
2851 return 0;
2852}
2853
2854static int state_open(struct inode *inode, struct file *file)
2855{
2856 return single_open(file, state_show, inode->i_private);
2857}
2858
2859static const struct file_operations state_fops = {
2860 .owner = THIS_MODULE,
2861 .open = state_open,
2862 .read = seq_read,
2863 .llseek = seq_lseek,
2864 .release = single_release,
2865};
2866
2867/**
2868 * fifo_show - debugfs: show the fifo information
2869 * @seq: The seq_file to write data to.
2870 * @v: Unused parameter.
2871 *
2872 * Show the FIFO information for the overall fifo and all the
2873 * periodic transmission FIFOs.
2874*/
2875static int fifo_show(struct seq_file *seq, void *v)
2876{
2877 struct s3c_hsotg *hsotg = seq->private;
2878 void __iomem *regs = hsotg->regs;
2879 u32 val;
2880 int idx;
2881
2882 seq_printf(seq, "Non-periodic FIFOs:\n");
2883 seq_printf(seq, "RXFIFO: Size %d\n", readl(regs + S3C_GRXFSIZ));
2884
2885 val = readl(regs + S3C_GNPTXFSIZ);
2886 seq_printf(seq, "NPTXFIFO: Size %d, Start 0x%08x\n",
2887 val >> S3C_GNPTXFSIZ_NPTxFDep_SHIFT,
2888 val & S3C_GNPTXFSIZ_NPTxFStAddr_MASK);
2889
2890 seq_printf(seq, "\nPeriodic TXFIFOs:\n");
2891
2892 for (idx = 1; idx <= 15; idx++) {
2893 val = readl(regs + S3C_DPTXFSIZn(idx));
2894
2895 seq_printf(seq, "\tDPTXFIFO%2d: Size %d, Start 0x%08x\n", idx,
2896 val >> S3C_DPTXFSIZn_DPTxFSize_SHIFT,
2897 val & S3C_DPTXFSIZn_DPTxFStAddr_MASK);
2898 }
2899
2900 return 0;
2901}
2902
2903static int fifo_open(struct inode *inode, struct file *file)
2904{
2905 return single_open(file, fifo_show, inode->i_private);
2906}
2907
2908static const struct file_operations fifo_fops = {
2909 .owner = THIS_MODULE,
2910 .open = fifo_open,
2911 .read = seq_read,
2912 .llseek = seq_lseek,
2913 .release = single_release,
2914};
2915
2916
2917static const char *decode_direction(int is_in)
2918{
2919 return is_in ? "in" : "out";
2920}
2921
2922/**
2923 * ep_show - debugfs: show the state of an endpoint.
2924 * @seq: The seq_file to write data to.
2925 * @v: Unused parameter.
2926 *
2927 * This debugfs entry shows the state of the given endpoint (one is
2928 * registered for each available).
2929*/
2930static int ep_show(struct seq_file *seq, void *v)
2931{
2932 struct s3c_hsotg_ep *ep = seq->private;
2933 struct s3c_hsotg *hsotg = ep->parent;
2934 struct s3c_hsotg_req *req;
2935 void __iomem *regs = hsotg->regs;
2936 int index = ep->index;
2937 int show_limit = 15;
2938 unsigned long flags;
2939
2940 seq_printf(seq, "Endpoint index %d, named %s, dir %s:\n",
2941 ep->index, ep->ep.name, decode_direction(ep->dir_in));
2942
2943 /* first show the register state */
2944
2945 seq_printf(seq, "\tDIEPCTL=0x%08x, DOEPCTL=0x%08x\n",
2946 readl(regs + S3C_DIEPCTL(index)),
2947 readl(regs + S3C_DOEPCTL(index)));
2948
2949 seq_printf(seq, "\tDIEPDMA=0x%08x, DOEPDMA=0x%08x\n",
2950 readl(regs + S3C_DIEPDMA(index)),
2951 readl(regs + S3C_DOEPDMA(index)));
2952
2953 seq_printf(seq, "\tDIEPINT=0x%08x, DOEPINT=0x%08x\n",
2954 readl(regs + S3C_DIEPINT(index)),
2955 readl(regs + S3C_DOEPINT(index)));
2956
2957 seq_printf(seq, "\tDIEPTSIZ=0x%08x, DOEPTSIZ=0x%08x\n",
2958 readl(regs + S3C_DIEPTSIZ(index)),
2959 readl(regs + S3C_DOEPTSIZ(index)));
2960
2961 seq_printf(seq, "\n");
2962 seq_printf(seq, "mps %d\n", ep->ep.maxpacket);
2963 seq_printf(seq, "total_data=%ld\n", ep->total_data);
2964
2965 seq_printf(seq, "request list (%p,%p):\n",
2966 ep->queue.next, ep->queue.prev);
2967
2968 spin_lock_irqsave(&ep->lock, flags);
2969
2970 list_for_each_entry(req, &ep->queue, queue) {
2971 if (--show_limit < 0) {
2972 seq_printf(seq, "not showing more requests...\n");
2973 break;
2974 }
2975
2976 seq_printf(seq, "%c req %p: %d bytes @%p, ",
2977 req == ep->req ? '*' : ' ',
2978 req, req->req.length, req->req.buf);
2979 seq_printf(seq, "%d done, res %d\n",
2980 req->req.actual, req->req.status);
2981 }
2982
2983 spin_unlock_irqrestore(&ep->lock, flags);
2984
2985 return 0;
2986}
2987
2988static int ep_open(struct inode *inode, struct file *file)
2989{
2990 return single_open(file, ep_show, inode->i_private);
2991}
2992
2993static const struct file_operations ep_fops = {
2994 .owner = THIS_MODULE,
2995 .open = ep_open,
2996 .read = seq_read,
2997 .llseek = seq_lseek,
2998 .release = single_release,
2999};
3000
3001/**
3002 * s3c_hsotg_create_debug - create debugfs directory and files
3003 * @hsotg: The driver state
3004 *
3005 * Create the debugfs files to allow the user to get information
3006 * about the state of the system. The directory name is created
3007 * with the same name as the device itself, in case we end up
3008 * with multiple blocks in future systems.
3009*/
3010static void __devinit s3c_hsotg_create_debug(struct s3c_hsotg *hsotg)
3011{
3012 struct dentry *root;
3013 unsigned epidx;
3014
3015 root = debugfs_create_dir(dev_name(hsotg->dev), NULL);
3016 hsotg->debug_root = root;
3017 if (IS_ERR(root)) {
3018 dev_err(hsotg->dev, "cannot create debug root\n");
3019 return;
3020 }
3021
3022 /* create general state file */
3023
3024 hsotg->debug_file = debugfs_create_file("state", 0444, root,
3025 hsotg, &state_fops);
3026
3027 if (IS_ERR(hsotg->debug_file))
3028 dev_err(hsotg->dev, "%s: failed to create state\n", __func__);
3029
3030 hsotg->debug_fifo = debugfs_create_file("fifo", 0444, root,
3031 hsotg, &fifo_fops);
3032
3033 if (IS_ERR(hsotg->debug_fifo))
3034 dev_err(hsotg->dev, "%s: failed to create fifo\n", __func__);
3035
3036 /* create one file for each endpoint */
3037
3038 for (epidx = 0; epidx < S3C_HSOTG_EPS; epidx++) {
3039 struct s3c_hsotg_ep *ep = &hsotg->eps[epidx];
3040
3041 ep->debugfs = debugfs_create_file(ep->name, 0444,
3042 root, ep, &ep_fops);
3043
3044 if (IS_ERR(ep->debugfs))
3045 dev_err(hsotg->dev, "failed to create %s debug file\n",
3046 ep->name);
3047 }
3048}
3049
3050/**
3051 * s3c_hsotg_delete_debug - cleanup debugfs entries
3052 * @hsotg: The driver state
3053 *
3054 * Cleanup (remove) the debugfs files for use on module exit.
3055*/
3056static void __devexit s3c_hsotg_delete_debug(struct s3c_hsotg *hsotg)
3057{
3058 unsigned epidx;
3059
3060 for (epidx = 0; epidx < S3C_HSOTG_EPS; epidx++) {
3061 struct s3c_hsotg_ep *ep = &hsotg->eps[epidx];
3062 debugfs_remove(ep->debugfs);
3063 }
3064
3065 debugfs_remove(hsotg->debug_file);
3066 debugfs_remove(hsotg->debug_fifo);
3067 debugfs_remove(hsotg->debug_root);
3068}
3069
3070/**
3071 * s3c_hsotg_gate - set the hardware gate for the block
3072 * @pdev: The device we bound to
3073 * @on: On or off.
3074 *
3075 * Set the hardware gate setting into the block. If we end up on
3076 * something other than an S3C64XX, then we might need to change this
3077 * to using a platform data callback, or some other mechanism.
3078 */
3079static void s3c_hsotg_gate(struct platform_device *pdev, bool on)
3080{
3081 unsigned long flags;
3082 u32 others;
3083
3084 local_irq_save(flags);
3085
3086 others = __raw_readl(S3C64XX_OTHERS);
3087 if (on)
3088 others |= S3C64XX_OTHERS_USBMASK;
3089 else
3090 others &= ~S3C64XX_OTHERS_USBMASK;
3091 __raw_writel(others, S3C64XX_OTHERS);
3092
3093 local_irq_restore(flags);
3094}
3095
3096struct s3c_hsotg_plat s3c_hsotg_default_pdata;
3097
3098static int __devinit s3c_hsotg_probe(struct platform_device *pdev)
3099{
3100 struct s3c_hsotg_plat *plat = pdev->dev.platform_data;
3101 struct device *dev = &pdev->dev;
3102 struct s3c_hsotg *hsotg;
3103 struct resource *res;
3104 int epnum;
3105 int ret;
3106
3107 if (!plat)
3108 plat = &s3c_hsotg_default_pdata;
3109
3110 hsotg = kzalloc(sizeof(struct s3c_hsotg) +
3111 sizeof(struct s3c_hsotg_ep) * S3C_HSOTG_EPS,
3112 GFP_KERNEL);
3113 if (!hsotg) {
3114 dev_err(dev, "cannot get memory\n");
3115 return -ENOMEM;
3116 }
3117
3118 hsotg->dev = dev;
3119 hsotg->plat = plat;
3120
3121 platform_set_drvdata(pdev, hsotg);
3122
3123 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3124 if (!res) {
3125 dev_err(dev, "cannot find register resource 0\n");
3126 ret = -EINVAL;
3127 goto err_mem;
3128 }
3129
3130 hsotg->regs_res = request_mem_region(res->start, resource_size(res),
3131 dev_name(dev));
3132 if (!hsotg->regs_res) {
3133 dev_err(dev, "cannot reserve registers\n");
3134 ret = -ENOENT;
3135 goto err_mem;
3136 }
3137
3138 hsotg->regs = ioremap(res->start, resource_size(res));
3139 if (!hsotg->regs) {
3140 dev_err(dev, "cannot map registers\n");
3141 ret = -ENXIO;
3142 goto err_regs_res;
3143 }
3144
3145 ret = platform_get_irq(pdev, 0);
3146 if (ret < 0) {
3147 dev_err(dev, "cannot find IRQ\n");
3148 goto err_regs;
3149 }
3150
3151 hsotg->irq = ret;
3152
3153 ret = request_irq(ret, s3c_hsotg_irq, 0, dev_name(dev), hsotg);
3154 if (ret < 0) {
3155 dev_err(dev, "cannot claim IRQ\n");
3156 goto err_regs;
3157 }
3158
3159 dev_info(dev, "regs %p, irq %d\n", hsotg->regs, hsotg->irq);
3160
3161 device_initialize(&hsotg->gadget.dev);
3162
3163 dev_set_name(&hsotg->gadget.dev, "gadget");
3164
3165 hsotg->gadget.is_dualspeed = 1;
3166 hsotg->gadget.ops = &s3c_hsotg_gadget_ops;
3167 hsotg->gadget.name = dev_name(dev);
3168
3169 hsotg->gadget.dev.parent = dev;
3170 hsotg->gadget.dev.dma_mask = dev->dma_mask;
3171
3172 /* setup endpoint information */
3173
3174 INIT_LIST_HEAD(&hsotg->gadget.ep_list);
3175 hsotg->gadget.ep0 = &hsotg->eps[0].ep;
3176
3177 /* allocate EP0 request */
3178
3179 hsotg->ctrl_req = s3c_hsotg_ep_alloc_request(&hsotg->eps[0].ep,
3180 GFP_KERNEL);
3181 if (!hsotg->ctrl_req) {
3182 dev_err(dev, "failed to allocate ctrl req\n");
3183 goto err_regs;
3184 }
3185
3186 /* reset the system */
3187
3188 s3c_hsotg_gate(pdev, true);
3189
3190 s3c_hsotg_otgreset(hsotg);
3191 s3c_hsotg_corereset(hsotg);
3192 s3c_hsotg_init(hsotg);
3193
3194 /* initialise the endpoints now the core has been initialised */
3195 for (epnum = 0; epnum < S3C_HSOTG_EPS; epnum++)
3196 s3c_hsotg_initep(hsotg, &hsotg->eps[epnum], epnum);
3197
3198 s3c_hsotg_create_debug(hsotg);
3199
3200 s3c_hsotg_dump(hsotg);
3201
3202 our_hsotg = hsotg;
3203 return 0;
3204
3205err_regs:
3206 iounmap(hsotg->regs);
3207
3208err_regs_res:
3209 release_resource(hsotg->regs_res);
3210 kfree(hsotg->regs_res);
3211
3212err_mem:
3213 kfree(hsotg);
3214 return ret;
3215}
3216
3217static int __devexit s3c_hsotg_remove(struct platform_device *pdev)
3218{
3219 struct s3c_hsotg *hsotg = platform_get_drvdata(pdev);
3220
3221 s3c_hsotg_delete_debug(hsotg);
3222
3223 usb_gadget_unregister_driver(hsotg->driver);
3224
3225 free_irq(hsotg->irq, hsotg);
3226 iounmap(hsotg->regs);
3227
3228 release_resource(hsotg->regs_res);
3229 kfree(hsotg->regs_res);
3230
3231 s3c_hsotg_gate(pdev, false);
3232
3233 kfree(hsotg);
3234 return 0;
3235}
3236
3237#if 1
3238#define s3c_hsotg_suspend NULL
3239#define s3c_hsotg_resume NULL
3240#endif
3241
3242static struct platform_driver s3c_hsotg_driver = {
3243 .driver = {
3244 .name = "s3c-hsotg",
3245 .owner = THIS_MODULE,
3246 },
3247 .probe = s3c_hsotg_probe,
3248 .remove = __devexit_p(s3c_hsotg_remove),
3249 .suspend = s3c_hsotg_suspend,
3250 .resume = s3c_hsotg_resume,
3251};
3252
3253static int __init s3c_hsotg_modinit(void)
3254{
3255 return platform_driver_register(&s3c_hsotg_driver);
3256}
3257
3258static void __exit s3c_hsotg_modexit(void)
3259{
3260 platform_driver_unregister(&s3c_hsotg_driver);
3261}
3262
3263module_init(s3c_hsotg_modinit);
3264module_exit(s3c_hsotg_modexit);
3265
3266MODULE_DESCRIPTION("Samsung S3C USB High-speed/OtG device");
3267MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
3268MODULE_LICENSE("GPL");
3269MODULE_ALIAS("platform:s3c-hsotg");
diff --git a/drivers/usb/gadget/u_audio.c b/drivers/usb/gadget/u_audio.c
new file mode 100644
index 000000000000..0f3d22fc030e
--- /dev/null
+++ b/drivers/usb/gadget/u_audio.c
@@ -0,0 +1,319 @@
1/*
2 * u_audio.c -- ALSA audio utilities for Gadget stack
3 *
4 * Copyright (C) 2008 Bryan Wu <cooloney@kernel.org>
5 * Copyright (C) 2008 Analog Devices, Inc
6 *
7 * Enter bugs at http://blackfin.uclinux.org/
8 *
9 * Licensed under the GPL-2 or later.
10 */
11
12#include <linux/kernel.h>
13#include <linux/utsname.h>
14#include <linux/device.h>
15#include <linux/delay.h>
16#include <linux/ctype.h>
17#include <linux/random.h>
18#include <linux/syscalls.h>
19
20#include "u_audio.h"
21
22/*
23 * This component encapsulates the ALSA devices for USB audio gadget
24 */
25
26#define FILE_PCM_PLAYBACK "/dev/snd/pcmC0D0p"
27#define FILE_PCM_CAPTURE "/dev/snd/pcmC0D0c"
28#define FILE_CONTROL "/dev/snd/controlC0"
29
30static char *fn_play = FILE_PCM_PLAYBACK;
31module_param(fn_play, charp, S_IRUGO);
32MODULE_PARM_DESC(fn_play, "Playback PCM device file name");
33
34static char *fn_cap = FILE_PCM_CAPTURE;
35module_param(fn_cap, charp, S_IRUGO);
36MODULE_PARM_DESC(fn_cap, "Capture PCM device file name");
37
38static char *fn_cntl = FILE_CONTROL;
39module_param(fn_cntl, charp, S_IRUGO);
40MODULE_PARM_DESC(fn_cntl, "Control device file name");
41
42/*-------------------------------------------------------------------------*/
43
44/**
45 * Some ALSA internal helper functions
46 */
47static int snd_interval_refine_set(struct snd_interval *i, unsigned int val)
48{
49 struct snd_interval t;
50 t.empty = 0;
51 t.min = t.max = val;
52 t.openmin = t.openmax = 0;
53 t.integer = 1;
54 return snd_interval_refine(i, &t);
55}
56
57static int _snd_pcm_hw_param_set(struct snd_pcm_hw_params *params,
58 snd_pcm_hw_param_t var, unsigned int val,
59 int dir)
60{
61 int changed;
62 if (hw_is_mask(var)) {
63 struct snd_mask *m = hw_param_mask(params, var);
64 if (val == 0 && dir < 0) {
65 changed = -EINVAL;
66 snd_mask_none(m);
67 } else {
68 if (dir > 0)
69 val++;
70 else if (dir < 0)
71 val--;
72 changed = snd_mask_refine_set(
73 hw_param_mask(params, var), val);
74 }
75 } else if (hw_is_interval(var)) {
76 struct snd_interval *i = hw_param_interval(params, var);
77 if (val == 0 && dir < 0) {
78 changed = -EINVAL;
79 snd_interval_none(i);
80 } else if (dir == 0)
81 changed = snd_interval_refine_set(i, val);
82 else {
83 struct snd_interval t;
84 t.openmin = 1;
85 t.openmax = 1;
86 t.empty = 0;
87 t.integer = 0;
88 if (dir < 0) {
89 t.min = val - 1;
90 t.max = val;
91 } else {
92 t.min = val;
93 t.max = val+1;
94 }
95 changed = snd_interval_refine(i, &t);
96 }
97 } else
98 return -EINVAL;
99 if (changed) {
100 params->cmask |= 1 << var;
101 params->rmask |= 1 << var;
102 }
103 return changed;
104}
105/*-------------------------------------------------------------------------*/
106
107/**
108 * Set default hardware params
109 */
110static int playback_default_hw_params(struct gaudio_snd_dev *snd)
111{
112 struct snd_pcm_substream *substream = snd->substream;
113 struct snd_pcm_hw_params *params;
114 snd_pcm_sframes_t result;
115
116 /*
117 * SNDRV_PCM_ACCESS_RW_INTERLEAVED,
118 * SNDRV_PCM_FORMAT_S16_LE
119 * CHANNELS: 2
120 * RATE: 48000
121 */
122 snd->access = SNDRV_PCM_ACCESS_RW_INTERLEAVED;
123 snd->format = SNDRV_PCM_FORMAT_S16_LE;
124 snd->channels = 2;
125 snd->rate = 48000;
126
127 params = kzalloc(sizeof(*params), GFP_KERNEL);
128 if (!params)
129 return -ENOMEM;
130
131 _snd_pcm_hw_params_any(params);
132 _snd_pcm_hw_param_set(params, SNDRV_PCM_HW_PARAM_ACCESS,
133 snd->access, 0);
134 _snd_pcm_hw_param_set(params, SNDRV_PCM_HW_PARAM_FORMAT,
135 snd->format, 0);
136 _snd_pcm_hw_param_set(params, SNDRV_PCM_HW_PARAM_CHANNELS,
137 snd->channels, 0);
138 _snd_pcm_hw_param_set(params, SNDRV_PCM_HW_PARAM_RATE,
139 snd->rate, 0);
140
141 snd_pcm_kernel_ioctl(substream, SNDRV_PCM_IOCTL_DROP, NULL);
142 snd_pcm_kernel_ioctl(substream, SNDRV_PCM_IOCTL_HW_PARAMS, params);
143
144 result = snd_pcm_kernel_ioctl(substream, SNDRV_PCM_IOCTL_PREPARE, NULL);
145 if (result < 0) {
146 ERROR(snd->card,
147 "Preparing sound card failed: %d\n", (int)result);
148 kfree(params);
149 return result;
150 }
151
152 /* Store the hardware parameters */
153 snd->access = params_access(params);
154 snd->format = params_format(params);
155 snd->channels = params_channels(params);
156 snd->rate = params_rate(params);
157
158 kfree(params);
159
160 INFO(snd->card,
161 "Hardware params: access %x, format %x, channels %d, rate %d\n",
162 snd->access, snd->format, snd->channels, snd->rate);
163
164 return 0;
165}
166
167/**
168 * Playback audio buffer data by ALSA PCM device
169 */
170static size_t u_audio_playback(struct gaudio *card, void *buf, size_t count)
171{
172 struct gaudio_snd_dev *snd = &card->playback;
173 struct snd_pcm_substream *substream = snd->substream;
174 struct snd_pcm_runtime *runtime = substream->runtime;
175 mm_segment_t old_fs;
176 ssize_t result;
177 snd_pcm_sframes_t frames;
178
179try_again:
180 if (runtime->status->state == SNDRV_PCM_STATE_XRUN ||
181 runtime->status->state == SNDRV_PCM_STATE_SUSPENDED) {
182 result = snd_pcm_kernel_ioctl(substream,
183 SNDRV_PCM_IOCTL_PREPARE, NULL);
184 if (result < 0) {
185 ERROR(card, "Preparing sound card failed: %d\n",
186 (int)result);
187 return result;
188 }
189 }
190
191 frames = bytes_to_frames(runtime, count);
192 old_fs = get_fs();
193 set_fs(KERNEL_DS);
194 result = snd_pcm_lib_write(snd->substream, buf, frames);
195 if (result != frames) {
196 ERROR(card, "Playback error: %d\n", (int)result);
197 set_fs(old_fs);
198 goto try_again;
199 }
200 set_fs(old_fs);
201
202 return 0;
203}
204
205static int u_audio_get_playback_channels(struct gaudio *card)
206{
207 return card->playback.channels;
208}
209
210static int u_audio_get_playback_rate(struct gaudio *card)
211{
212 return card->playback.rate;
213}
214
215/**
216 * Open ALSA PCM and control device files
217 * Initial the PCM or control device
218 */
219static int gaudio_open_snd_dev(struct gaudio *card)
220{
221 struct snd_pcm_file *pcm_file;
222 struct gaudio_snd_dev *snd;
223
224 if (!card)
225 return -ENODEV;
226
227 /* Open control device */
228 snd = &card->control;
229 snd->filp = filp_open(fn_cntl, O_RDWR, 0);
230 if (IS_ERR(snd->filp)) {
231 int ret = PTR_ERR(snd->filp);
232 ERROR(card, "unable to open sound control device file: %s\n",
233 fn_cntl);
234 snd->filp = NULL;
235 return ret;
236 }
237 snd->card = card;
238
239 /* Open PCM playback device and setup substream */
240 snd = &card->playback;
241 snd->filp = filp_open(fn_play, O_WRONLY, 0);
242 if (IS_ERR(snd->filp)) {
243 ERROR(card, "No such PCM playback device: %s\n", fn_play);
244 snd->filp = NULL;
245 }
246 pcm_file = snd->filp->private_data;
247 snd->substream = pcm_file->substream;
248 snd->card = card;
249 playback_default_hw_params(snd);
250
251 /* Open PCM capture device and setup substream */
252 snd = &card->capture;
253 snd->filp = filp_open(fn_cap, O_RDONLY, 0);
254 if (IS_ERR(snd->filp)) {
255 ERROR(card, "No such PCM capture device: %s\n", fn_cap);
256 snd->filp = NULL;
257 }
258 pcm_file = snd->filp->private_data;
259 snd->substream = pcm_file->substream;
260 snd->card = card;
261
262 return 0;
263}
264
265/**
266 * Close ALSA PCM and control device files
267 */
268static int gaudio_close_snd_dev(struct gaudio *gau)
269{
270 struct gaudio_snd_dev *snd;
271
272 /* Close control device */
273 snd = &gau->control;
274 if (!IS_ERR(snd->filp))
275 filp_close(snd->filp, current->files);
276
277 /* Close PCM playback device and setup substream */
278 snd = &gau->playback;
279 if (!IS_ERR(snd->filp))
280 filp_close(snd->filp, current->files);
281
282 /* Close PCM capture device and setup substream */
283 snd = &gau->capture;
284 if (!IS_ERR(snd->filp))
285 filp_close(snd->filp, current->files);
286
287 return 0;
288}
289
290/**
291 * gaudio_setup - setup ALSA interface and preparing for USB transfer
292 *
293 * This sets up PCM, mixer or MIDI ALSA devices fore USB gadget using.
294 *
295 * Returns negative errno, or zero on success
296 */
297int __init gaudio_setup(struct gaudio *card)
298{
299 int ret;
300
301 ret = gaudio_open_snd_dev(card);
302 if (ret)
303 ERROR(card, "we need at least one control device\n");
304
305 return ret;
306
307}
308
309/**
310 * gaudio_cleanup - remove ALSA device interface
311 *
312 * This is called to free all resources allocated by @gaudio_setup().
313 */
314void gaudio_cleanup(struct gaudio *card)
315{
316 if (card)
317 gaudio_close_snd_dev(card);
318}
319
diff --git a/drivers/usb/gadget/u_audio.h b/drivers/usb/gadget/u_audio.h
new file mode 100644
index 000000000000..cc8d159c648a
--- /dev/null
+++ b/drivers/usb/gadget/u_audio.h
@@ -0,0 +1,56 @@
1/*
2 * u_audio.h -- interface to USB gadget "ALSA AUDIO" utilities
3 *
4 * Copyright (C) 2008 Bryan Wu <cooloney@kernel.org>
5 * Copyright (C) 2008 Analog Devices, Inc
6 *
7 * Enter bugs at http://blackfin.uclinux.org/
8 *
9 * Licensed under the GPL-2 or later.
10 */
11
12#ifndef __U_AUDIO_H
13#define __U_AUDIO_H
14
15#include <linux/device.h>
16#include <linux/err.h>
17#include <linux/usb/audio.h>
18#include <linux/usb/composite.h>
19
20#include <sound/core.h>
21#include <sound/pcm.h>
22#include <sound/pcm_params.h>
23
24#include "gadget_chips.h"
25
26/*
27 * This represents the USB side of an audio card device, managed by a USB
28 * function which provides control and stream interfaces.
29 */
30
31struct gaudio_snd_dev {
32 struct gaudio *card;
33 struct file *filp;
34 struct snd_pcm_substream *substream;
35 int access;
36 int format;
37 int channels;
38 int rate;
39};
40
41struct gaudio {
42 struct usb_function func;
43 struct usb_gadget *gadget;
44
45 /* ALSA sound device interfaces */
46 struct gaudio_snd_dev control;
47 struct gaudio_snd_dev playback;
48 struct gaudio_snd_dev capture;
49
50 /* TODO */
51};
52
53int gaudio_setup(struct gaudio *card);
54void gaudio_cleanup(struct gaudio *card);
55
56#endif /* __U_AUDIO_H */
diff --git a/drivers/usb/gadget/u_serial.c b/drivers/usb/gadget/u_serial.c
index 0a4d99ab40d8..fc6e709f45b1 100644
--- a/drivers/usb/gadget/u_serial.c
+++ b/drivers/usb/gadget/u_serial.c
@@ -371,6 +371,7 @@ __acquires(&port->port_lock)
371 371
372 req->length = len; 372 req->length = len;
373 list_del(&req->list); 373 list_del(&req->list);
374 req->zero = (gs_buf_data_avail(&port->port_write_buf) == 0);
374 375
375 pr_vdebug(PREFIX "%d: tx len=%d, 0x%02x 0x%02x 0x%02x ...\n", 376 pr_vdebug(PREFIX "%d: tx len=%d, 0x%02x 0x%02x 0x%02x ...\n",
376 port->port_num, len, *((u8 *)req->buf), 377 port->port_num, len, *((u8 *)req->buf),
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-22 20:49:19 -0500