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authorYoshihiro Shimoda <shimoda.yoshihiro@renesas.com>2007-05-10 00:18:23 -0400
committerGreg Kroah-Hartman <gregkh@suse.de>2007-07-12 19:29:45 -0400
commit4cf2503c6801a69fee25030475eceeefb36d1b56 (patch)
treed18f2d67a0fc83411458ff581bad53e0fd972ce9 /drivers/usb/gadget
parent0ca1268e109acf6d71507398cb95cab2e670b654 (diff)
USB: m66592-udc: peripheral controller driver for M66592
I would like to submit Renesas M66592 udc driver. The M66592 is Renesas USB 2.0 peripheral controller. This controller supports USB high-speed. The driver has been tested Gadget Zero, Ethernet Gadget, File-backed Storage Gadget, and passed usbtest script. Signed-off-by : Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'drivers/usb/gadget')
-rw-r--r--drivers/usb/gadget/Kconfig18
-rw-r--r--drivers/usb/gadget/Makefile1
-rw-r--r--drivers/usb/gadget/ether.c4
-rw-r--r--drivers/usb/gadget/gadget_chips.h9
-rw-r--r--drivers/usb/gadget/m66592-udc.c1653
-rw-r--r--drivers/usb/gadget/m66592-udc.h577
6 files changed, 2262 insertions, 0 deletions
diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig
index f771a7cae9ec..05768889497b 100644
--- a/drivers/usb/gadget/Kconfig
+++ b/drivers/usb/gadget/Kconfig
@@ -226,6 +226,24 @@ config USB_AT91
226 depends on USB_GADGET_AT91 226 depends on USB_GADGET_AT91
227 default USB_GADGET 227 default USB_GADGET
228 228
229config USB_GADGET_M66592
230 boolean "M66592 driver"
231 select USB_GADGET_DUALSPEED
232 help
233 M66592 is a USB 2.0 peripheral controller.
234
235 It has seven configurable endpoints, and endpoint zero.
236
237 Say "y" to link the driver statically, or "m" to build a
238 dynamically linked module called "m66592_udc" and force all
239 gadget drivers to also be dynamically linked.
240
241config USB_M66592
242 tristate
243 depends on USB_GADGET_M66592
244 default USB_GADGET
245 select USB_GADGET_SELECTED
246
229config USB_GADGET_DUMMY_HCD 247config USB_GADGET_DUMMY_HCD
230 boolean "Dummy HCD (DEVELOPMENT)" 248 boolean "Dummy HCD (DEVELOPMENT)"
231 depends on (USB=y || (USB=m && USB_GADGET=m)) && EXPERIMENTAL 249 depends on (USB=y || (USB=m && USB_GADGET=m)) && EXPERIMENTAL
diff --git a/drivers/usb/gadget/Makefile b/drivers/usb/gadget/Makefile
index 5db19396631c..2d41e849c9ee 100644
--- a/drivers/usb/gadget/Makefile
+++ b/drivers/usb/gadget/Makefile
@@ -9,6 +9,7 @@ obj-$(CONFIG_USB_OMAP) += omap_udc.o
9obj-$(CONFIG_USB_LH7A40X) += lh7a40x_udc.o 9obj-$(CONFIG_USB_LH7A40X) += lh7a40x_udc.o
10obj-$(CONFIG_USB_AT91) += at91_udc.o 10obj-$(CONFIG_USB_AT91) += at91_udc.o
11obj-$(CONFIG_USB_FSL_USB2) += fsl_usb2_udc.o 11obj-$(CONFIG_USB_FSL_USB2) += fsl_usb2_udc.o
12obj-$(CONFIG_USB_M66592) += m66592-udc.o
12 13
13# 14#
14# USB gadget drivers 15# USB gadget drivers
diff --git a/drivers/usb/gadget/ether.c b/drivers/usb/gadget/ether.c
index 325bf7cfb83f..49630ab569bf 100644
--- a/drivers/usb/gadget/ether.c
+++ b/drivers/usb/gadget/ether.c
@@ -301,6 +301,10 @@ MODULE_PARM_DESC(host_addr, "Host Ethernet Address");
301#define DEV_CONFIG_SUBSET 301#define DEV_CONFIG_SUBSET
302#endif 302#endif
303 303
304#ifdef CONFIG_USB_GADGET_M66592
305#define DEV_CONFIG_CDC
306#endif
307
304 308
305/*-------------------------------------------------------------------------*/ 309/*-------------------------------------------------------------------------*/
306 310
diff --git a/drivers/usb/gadget/gadget_chips.h b/drivers/usb/gadget/gadget_chips.h
index d041b919e7b8..96f50e35819f 100644
--- a/drivers/usb/gadget/gadget_chips.h
+++ b/drivers/usb/gadget/gadget_chips.h
@@ -125,6 +125,13 @@
125#define gadget_is_mpc8272(g) 0 125#define gadget_is_mpc8272(g) 0
126#endif 126#endif
127 127
128#ifdef CONFIG_USB_GADGET_M66592
129#define gadget_is_m66592(g) !strcmp("m66592_udc", (g)->name)
130#else
131#define gadget_is_m66592(g) 0
132#endif
133
134
128// CONFIG_USB_GADGET_SX2 135// CONFIG_USB_GADGET_SX2
129// CONFIG_USB_GADGET_AU1X00 136// CONFIG_USB_GADGET_AU1X00
130// ... 137// ...
@@ -185,5 +192,7 @@ static inline int usb_gadget_controller_number(struct usb_gadget *gadget)
185 return 0x18; 192 return 0x18;
186 else if (gadget_is_fsl_usb2(gadget)) 193 else if (gadget_is_fsl_usb2(gadget))
187 return 0x19; 194 return 0x19;
195 else if (gadget_is_m66592(gadget))
196 return 0x20;
188 return -ENOENT; 197 return -ENOENT;
189} 198}
diff --git a/drivers/usb/gadget/m66592-udc.c b/drivers/usb/gadget/m66592-udc.c
new file mode 100644
index 000000000000..611130c8983b
--- /dev/null
+++ b/drivers/usb/gadget/m66592-udc.c
@@ -0,0 +1,1653 @@
1/*
2 * M66592 UDC (USB gadget)
3 *
4 * Copyright (C) 2006-2007 Renesas Solutions Corp.
5 *
6 * Author : Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 *
21 */
22
23#include <linux/module.h>
24#include <linux/kernel.h>
25#include <linux/sched.h>
26#include <linux/smp_lock.h>
27#include <linux/errno.h>
28#include <linux/init.h>
29#include <linux/timer.h>
30#include <linux/delay.h>
31#include <linux/list.h>
32#include <linux/interrupt.h>
33#include <linux/platform_device.h>
34#include <linux/usb/ch9.h>
35#include <linux/usb_gadget.h>
36
37#include <asm/io.h>
38#include <asm/irq.h>
39#include <asm/system.h>
40
41#include "m66592-udc.h"
42
43MODULE_DESCRIPTION("M66592 USB gadget driiver");
44MODULE_LICENSE("GPL");
45MODULE_AUTHOR("Yoshihiro Shimoda");
46
47#define DRIVER_VERSION "9 May 2007"
48
49/* module parameters */
50static unsigned short clock = M66592_XTAL24;
51module_param(clock, ushort, 0644);
52MODULE_PARM_DESC(clock, "input clock: 48MHz=32768, 24MHz=16384, 12MHz=0(default=16384)");
53static unsigned short vif = M66592_LDRV;
54module_param(vif, ushort, 0644);
55MODULE_PARM_DESC(vif, "input VIF: 3.3V=32768, 1.5V=0(default=32768)");
56static unsigned short endian = 0;
57module_param(endian, ushort, 0644);
58MODULE_PARM_DESC(endian, "data endian: big=256, little=0(default=0)");
59static unsigned short irq_sense = M66592_INTL;
60module_param(irq_sense, ushort, 0644);
61MODULE_PARM_DESC(irq_sense, "IRQ sense: low level=2, falling edge=0(default=2)");
62
63static const char udc_name[] = "m66592_udc";
64static const char *m66592_ep_name[] = {
65 "ep0", "ep1", "ep2", "ep3", "ep4", "ep5", "ep6", "ep7"
66};
67
68static void disable_controller(struct m66592 *m66592);
69static void irq_ep0_write(struct m66592_ep *ep, struct m66592_request *req);
70static void irq_packet_write(struct m66592_ep *ep, struct m66592_request *req);
71static int m66592_queue(struct usb_ep *_ep, struct usb_request *_req,
72 gfp_t gfp_flags);
73
74static void transfer_complete(struct m66592_ep *ep,
75 struct m66592_request *req,
76 int status);
77/*-------------------------------------------------------------------------*/
78static inline u16 get_usb_speed(struct m66592 *m66592)
79{
80 return (m66592_read(m66592, M66592_DVSTCTR) & M66592_RHST);
81}
82
83static void enable_pipe_irq(struct m66592 *m66592, u16 pipenum,
84 unsigned long reg)
85{
86 u16 tmp;
87
88 tmp = m66592_read(m66592, M66592_INTENB0);
89 m66592_bclr(m66592, M66592_BEMPE | M66592_NRDYE | M66592_BRDYE,
90 M66592_INTENB0);
91 m66592_bset(m66592, (1 << pipenum), reg);
92 m66592_write(m66592, tmp, M66592_INTENB0);
93}
94
95static void disable_pipe_irq(struct m66592 *m66592, u16 pipenum,
96 unsigned long reg)
97{
98 u16 tmp;
99
100 tmp = m66592_read(m66592, M66592_INTENB0);
101 m66592_bclr(m66592, M66592_BEMPE | M66592_NRDYE | M66592_BRDYE,
102 M66592_INTENB0);
103 m66592_bclr(m66592, (1 << pipenum), reg);
104 m66592_write(m66592, tmp, M66592_INTENB0);
105}
106
107static void m66592_usb_connect(struct m66592 *m66592)
108{
109 m66592_bset(m66592, M66592_CTRE, M66592_INTENB0);
110 m66592_bset(m66592, M66592_WDST | M66592_RDST | M66592_CMPL,
111 M66592_INTENB0);
112 m66592_bset(m66592, M66592_BEMPE | M66592_BRDYE, M66592_INTENB0);
113
114 m66592_bset(m66592, M66592_DPRPU, M66592_SYSCFG);
115}
116
117static void m66592_usb_disconnect(struct m66592 *m66592)
118{
119 m66592_bclr(m66592, M66592_CTRE, M66592_INTENB0);
120 m66592_bclr(m66592, M66592_WDST | M66592_RDST | M66592_CMPL,
121 M66592_INTENB0);
122 m66592_bclr(m66592, M66592_BEMPE | M66592_BRDYE, M66592_INTENB0);
123 m66592_bclr(m66592, M66592_DPRPU, M66592_SYSCFG);
124
125 m66592->gadget.speed = USB_SPEED_UNKNOWN;
126 spin_unlock(&m66592->lock);
127 m66592->driver->disconnect(&m66592->gadget);
128 spin_lock(&m66592->lock);
129
130 disable_controller(m66592);
131 INIT_LIST_HEAD(&m66592->ep[0].queue);
132}
133
134static inline u16 control_reg_get_pid(struct m66592 *m66592, u16 pipenum)
135{
136 u16 pid = 0;
137 unsigned long offset;
138
139 if (pipenum == 0)
140 pid = m66592_read(m66592, M66592_DCPCTR) & M66592_PID;
141 else if (pipenum < M66592_MAX_NUM_PIPE) {
142 offset = get_pipectr_addr(pipenum);
143 pid = m66592_read(m66592, offset) & M66592_PID;
144 } else
145 printk(KERN_ERR "unexpect pipe num (%d)\n", pipenum);
146
147 return pid;
148}
149
150static inline void control_reg_set_pid(struct m66592 *m66592, u16 pipenum,
151 u16 pid)
152{
153 unsigned long offset;
154
155 if (pipenum == 0)
156 m66592_mdfy(m66592, pid, M66592_PID, M66592_DCPCTR);
157 else if (pipenum < M66592_MAX_NUM_PIPE) {
158 offset = get_pipectr_addr(pipenum);
159 m66592_mdfy(m66592, pid, M66592_PID, offset);
160 } else
161 printk(KERN_ERR "unexpect pipe num (%d)\n", pipenum);
162}
163
164static inline void pipe_start(struct m66592 *m66592, u16 pipenum)
165{
166 control_reg_set_pid(m66592, pipenum, M66592_PID_BUF);
167}
168
169static inline void pipe_stop(struct m66592 *m66592, u16 pipenum)
170{
171 control_reg_set_pid(m66592, pipenum, M66592_PID_NAK);
172}
173
174static inline void pipe_stall(struct m66592 *m66592, u16 pipenum)
175{
176 control_reg_set_pid(m66592, pipenum, M66592_PID_STALL);
177}
178
179static inline u16 control_reg_get(struct m66592 *m66592, u16 pipenum)
180{
181 u16 ret = 0;
182 unsigned long offset;
183
184 if (pipenum == 0)
185 ret = m66592_read(m66592, M66592_DCPCTR);
186 else if (pipenum < M66592_MAX_NUM_PIPE) {
187 offset = get_pipectr_addr(pipenum);
188 ret = m66592_read(m66592, offset);
189 } else
190 printk(KERN_ERR "unexpect pipe num (%d)\n", pipenum);
191
192 return ret;
193}
194
195static inline void control_reg_sqclr(struct m66592 *m66592, u16 pipenum)
196{
197 unsigned long offset;
198
199 pipe_stop(m66592, pipenum);
200
201 if (pipenum == 0)
202 m66592_bset(m66592, M66592_SQCLR, M66592_DCPCTR);
203 else if (pipenum < M66592_MAX_NUM_PIPE) {
204 offset = get_pipectr_addr(pipenum);
205 m66592_bset(m66592, M66592_SQCLR, offset);
206 } else
207 printk(KERN_ERR "unexpect pipe num(%d)\n", pipenum);
208}
209
210static inline int get_buffer_size(struct m66592 *m66592, u16 pipenum)
211{
212 u16 tmp;
213 int size;
214
215 if (pipenum == 0) {
216 tmp = m66592_read(m66592, M66592_DCPCFG);
217 if ((tmp & M66592_CNTMD) != 0)
218 size = 256;
219 else {
220 tmp = m66592_read(m66592, M66592_DCPMAXP);
221 size = tmp & M66592_MAXP;
222 }
223 } else {
224 m66592_write(m66592, pipenum, M66592_PIPESEL);
225 tmp = m66592_read(m66592, M66592_PIPECFG);
226 if ((tmp & M66592_CNTMD) != 0) {
227 tmp = m66592_read(m66592, M66592_PIPEBUF);
228 size = ((tmp >> 10) + 1) * 64;
229 } else {
230 tmp = m66592_read(m66592, M66592_PIPEMAXP);
231 size = tmp & M66592_MXPS;
232 }
233 }
234
235 return size;
236}
237
238static inline void pipe_change(struct m66592 *m66592, u16 pipenum)
239{
240 struct m66592_ep *ep = m66592->pipenum2ep[pipenum];
241
242 if (ep->use_dma)
243 return;
244
245 m66592_mdfy(m66592, pipenum, M66592_CURPIPE, ep->fifosel);
246
247 ndelay(450);
248
249 m66592_bset(m66592, M66592_MBW, ep->fifosel);
250}
251
252static int pipe_buffer_setting(struct m66592 *m66592,
253 struct m66592_pipe_info *info)
254{
255 u16 bufnum = 0, buf_bsize = 0;
256 u16 pipecfg = 0;
257
258 if (info->pipe == 0)
259 return -EINVAL;
260
261 m66592_write(m66592, info->pipe, M66592_PIPESEL);
262
263 if (info->dir_in)
264 pipecfg |= M66592_DIR;
265 pipecfg |= info->type;
266 pipecfg |= info->epnum;
267 switch (info->type) {
268 case M66592_INT:
269 bufnum = 4 + (info->pipe - M66592_BASE_PIPENUM_INT);
270 buf_bsize = 0;
271 break;
272 case M66592_BULK:
273 bufnum = m66592->bi_bufnum +
274 (info->pipe - M66592_BASE_PIPENUM_BULK) * 16;
275 m66592->bi_bufnum += 16;
276 buf_bsize = 7;
277 pipecfg |= M66592_DBLB;
278 if (!info->dir_in)
279 pipecfg |= M66592_SHTNAK;
280 break;
281 case M66592_ISO:
282 bufnum = m66592->bi_bufnum +
283 (info->pipe - M66592_BASE_PIPENUM_ISOC) * 16;
284 m66592->bi_bufnum += 16;
285 buf_bsize = 7;
286 break;
287 }
288 if (m66592->bi_bufnum > M66592_MAX_BUFNUM) {
289 printk(KERN_ERR "m66592 pipe memory is insufficient(%d)\n",
290 m66592->bi_bufnum);
291 return -ENOMEM;
292 }
293
294 m66592_write(m66592, pipecfg, M66592_PIPECFG);
295 m66592_write(m66592, (buf_bsize << 10) | (bufnum), M66592_PIPEBUF);
296 m66592_write(m66592, info->maxpacket, M66592_PIPEMAXP);
297 if (info->interval)
298 info->interval--;
299 m66592_write(m66592, info->interval, M66592_PIPEPERI);
300
301 return 0;
302}
303
304static void pipe_buffer_release(struct m66592 *m66592,
305 struct m66592_pipe_info *info)
306{
307 if (info->pipe == 0)
308 return;
309
310 switch (info->type) {
311 case M66592_BULK:
312 if (is_bulk_pipe(info->pipe))
313 m66592->bi_bufnum -= 16;
314 break;
315 case M66592_ISO:
316 if (is_isoc_pipe(info->pipe))
317 m66592->bi_bufnum -= 16;
318 break;
319 }
320
321 if (is_bulk_pipe(info->pipe)) {
322 m66592->bulk--;
323 } else if (is_interrupt_pipe(info->pipe))
324 m66592->interrupt--;
325 else if (is_isoc_pipe(info->pipe)) {
326 m66592->isochronous--;
327 if (info->type == M66592_BULK)
328 m66592->bulk--;
329 } else
330 printk(KERN_ERR "ep_release: unexpect pipenum (%d)\n",
331 info->pipe);
332}
333
334static void pipe_initialize(struct m66592_ep *ep)
335{
336 struct m66592 *m66592 = ep->m66592;
337
338 m66592_mdfy(m66592, 0, M66592_CURPIPE, ep->fifosel);
339
340 m66592_write(m66592, M66592_ACLRM, ep->pipectr);
341 m66592_write(m66592, 0, ep->pipectr);
342 m66592_write(m66592, M66592_SQCLR, ep->pipectr);
343 if (ep->use_dma) {
344 m66592_mdfy(m66592, ep->pipenum, M66592_CURPIPE, ep->fifosel);
345
346 ndelay(450);
347
348 m66592_bset(m66592, M66592_MBW, ep->fifosel);
349 }
350}
351
352static void m66592_ep_setting(struct m66592 *m66592, struct m66592_ep *ep,
353 const struct usb_endpoint_descriptor *desc,
354 u16 pipenum, int dma)
355{
356 if ((pipenum != 0) && dma) {
357 if (m66592->num_dma == 0) {
358 m66592->num_dma++;
359 ep->use_dma = 1;
360 ep->fifoaddr = M66592_D0FIFO;
361 ep->fifosel = M66592_D0FIFOSEL;
362 ep->fifoctr = M66592_D0FIFOCTR;
363 ep->fifotrn = M66592_D0FIFOTRN;
364 } else if (m66592->num_dma == 1) {
365 m66592->num_dma++;
366 ep->use_dma = 1;
367 ep->fifoaddr = M66592_D1FIFO;
368 ep->fifosel = M66592_D1FIFOSEL;
369 ep->fifoctr = M66592_D1FIFOCTR;
370 ep->fifotrn = M66592_D1FIFOTRN;
371 } else {
372 ep->use_dma = 0;
373 ep->fifoaddr = M66592_CFIFO;
374 ep->fifosel = M66592_CFIFOSEL;
375 ep->fifoctr = M66592_CFIFOCTR;
376 ep->fifotrn = 0;
377 }
378 } else {
379 ep->use_dma = 0;
380 ep->fifoaddr = M66592_CFIFO;
381 ep->fifosel = M66592_CFIFOSEL;
382 ep->fifoctr = M66592_CFIFOCTR;
383 ep->fifotrn = 0;
384 }
385
386 ep->pipectr = get_pipectr_addr(pipenum);
387 ep->pipenum = pipenum;
388 ep->ep.maxpacket = desc->wMaxPacketSize;
389 m66592->pipenum2ep[pipenum] = ep;
390 m66592->epaddr2ep[desc->bEndpointAddress&USB_ENDPOINT_NUMBER_MASK] = ep;
391 INIT_LIST_HEAD(&ep->queue);
392}
393
394static void m66592_ep_release(struct m66592_ep *ep)
395{
396 struct m66592 *m66592 = ep->m66592;
397 u16 pipenum = ep->pipenum;
398
399 if (pipenum == 0)
400 return;
401
402 if (ep->use_dma)
403 m66592->num_dma--;
404 ep->pipenum = 0;
405 ep->busy = 0;
406 ep->use_dma = 0;
407}
408
409static int alloc_pipe_config(struct m66592_ep *ep,
410 const struct usb_endpoint_descriptor *desc)
411{
412 struct m66592 *m66592 = ep->m66592;
413 struct m66592_pipe_info info;
414 int dma = 0;
415 int *counter;
416 int ret;
417
418 ep->desc = desc;
419
420 BUG_ON(ep->pipenum);
421
422 switch(desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
423 case USB_ENDPOINT_XFER_BULK:
424 if (m66592->bulk >= M66592_MAX_NUM_BULK) {
425 if (m66592->isochronous >= M66592_MAX_NUM_ISOC) {
426 printk(KERN_ERR "bulk pipe is insufficient\n");
427 return -ENODEV;
428 } else {
429 info.pipe = M66592_BASE_PIPENUM_ISOC +
430 m66592->isochronous;
431 counter = &m66592->isochronous;
432 }
433 } else {
434 info.pipe = M66592_BASE_PIPENUM_BULK + m66592->bulk;
435 counter = &m66592->bulk;
436 }
437 info.type = M66592_BULK;
438 dma = 1;
439 break;
440 case USB_ENDPOINT_XFER_INT:
441 if (m66592->interrupt >= M66592_MAX_NUM_INT) {
442 printk(KERN_ERR "interrupt pipe is insufficient\n");
443 return -ENODEV;
444 }
445 info.pipe = M66592_BASE_PIPENUM_INT + m66592->interrupt;
446 info.type = M66592_INT;
447 counter = &m66592->interrupt;
448 break;
449 case USB_ENDPOINT_XFER_ISOC:
450 if (m66592->isochronous >= M66592_MAX_NUM_ISOC) {
451 printk(KERN_ERR "isochronous pipe is insufficient\n");
452 return -ENODEV;
453 }
454 info.pipe = M66592_BASE_PIPENUM_ISOC + m66592->isochronous;
455 info.type = M66592_ISO;
456 counter = &m66592->isochronous;
457 break;
458 default:
459 printk(KERN_ERR "unexpect xfer type\n");
460 return -EINVAL;
461 }
462 ep->type = info.type;
463
464 info.epnum = desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
465 info.maxpacket = desc->wMaxPacketSize;
466 info.interval = desc->bInterval;
467 if (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK)
468 info.dir_in = 1;
469 else
470 info.dir_in = 0;
471
472 ret = pipe_buffer_setting(m66592, &info);
473 if (ret < 0) {
474 printk(KERN_ERR "pipe_buffer_setting fail\n");
475 return ret;
476 }
477
478 (*counter)++;
479 if ((counter == &m66592->isochronous) && info.type == M66592_BULK)
480 m66592->bulk++;
481
482 m66592_ep_setting(m66592, ep, desc, info.pipe, dma);
483 pipe_initialize(ep);
484
485 return 0;
486}
487
488static int free_pipe_config(struct m66592_ep *ep)
489{
490 struct m66592 *m66592 = ep->m66592;
491 struct m66592_pipe_info info;
492
493 info.pipe = ep->pipenum;
494 info.type = ep->type;
495 pipe_buffer_release(m66592, &info);
496 m66592_ep_release(ep);
497
498 return 0;
499}
500
501/*-------------------------------------------------------------------------*/
502static void pipe_irq_enable(struct m66592 *m66592, u16 pipenum)
503{
504 enable_irq_ready(m66592, pipenum);
505 enable_irq_nrdy(m66592, pipenum);
506}
507
508static void pipe_irq_disable(struct m66592 *m66592, u16 pipenum)
509{
510 disable_irq_ready(m66592, pipenum);
511 disable_irq_nrdy(m66592, pipenum);
512}
513
514/* if complete is true, gadget driver complete function is not call */
515static void control_end(struct m66592 *m66592, unsigned ccpl)
516{
517 m66592->ep[0].internal_ccpl = ccpl;
518 pipe_start(m66592, 0);
519 m66592_bset(m66592, M66592_CCPL, M66592_DCPCTR);
520}
521
522static void start_ep0_write(struct m66592_ep *ep, struct m66592_request *req)
523{
524 struct m66592 *m66592 = ep->m66592;
525
526 pipe_change(m66592, ep->pipenum);
527 m66592_mdfy(m66592, M66592_ISEL | M66592_PIPE0,
528 (M66592_ISEL | M66592_CURPIPE),
529 M66592_CFIFOSEL);
530 m66592_write(m66592, M66592_BCLR, ep->fifoctr);
531 if (req->req.length == 0) {
532 m66592_bset(m66592, M66592_BVAL, ep->fifoctr);
533 pipe_start(m66592, 0);
534 transfer_complete(ep, req, 0);
535 } else {
536 m66592_write(m66592, ~M66592_BEMP0, M66592_BEMPSTS);
537 irq_ep0_write(ep, req);
538 }
539}
540
541static void start_packet_write(struct m66592_ep *ep, struct m66592_request *req)
542{
543 struct m66592 *m66592 = ep->m66592;
544 u16 tmp;
545
546 pipe_change(m66592, ep->pipenum);
547 disable_irq_empty(m66592, ep->pipenum);
548 pipe_start(m66592, ep->pipenum);
549
550 tmp = m66592_read(m66592, ep->fifoctr);
551 if (unlikely((tmp & M66592_FRDY) == 0))
552 pipe_irq_enable(m66592, ep->pipenum);
553 else
554 irq_packet_write(ep, req);
555}
556
557static void start_packet_read(struct m66592_ep *ep, struct m66592_request *req)
558{
559 struct m66592 *m66592 = ep->m66592;
560 u16 pipenum = ep->pipenum;
561
562 if (ep->pipenum == 0) {
563 m66592_mdfy(m66592, M66592_PIPE0,
564 (M66592_ISEL | M66592_CURPIPE),
565 M66592_CFIFOSEL);
566 m66592_write(m66592, M66592_BCLR, ep->fifoctr);
567 pipe_start(m66592, pipenum);
568 pipe_irq_enable(m66592, pipenum);
569 } else {
570 if (ep->use_dma) {
571 m66592_bset(m66592, M66592_TRCLR, ep->fifosel);
572 pipe_change(m66592, pipenum);
573 m66592_bset(m66592, M66592_TRENB, ep->fifosel);
574 m66592_write(m66592,
575 (req->req.length + ep->ep.maxpacket - 1) /
576 ep->ep.maxpacket, ep->fifotrn);
577 }
578 pipe_start(m66592, pipenum); /* trigger once */
579 pipe_irq_enable(m66592, pipenum);
580 }
581}
582
583static void start_packet(struct m66592_ep *ep, struct m66592_request *req)
584{
585 if (ep->desc->bEndpointAddress & USB_DIR_IN)
586 start_packet_write(ep, req);
587 else
588 start_packet_read(ep, req);
589}
590
591static void start_ep0(struct m66592_ep *ep, struct m66592_request *req)
592{
593 u16 ctsq;
594
595 ctsq = m66592_read(ep->m66592, M66592_INTSTS0) & M66592_CTSQ;
596
597 switch (ctsq) {
598 case M66592_CS_RDDS:
599 start_ep0_write(ep, req);
600 break;
601 case M66592_CS_WRDS:
602 start_packet_read(ep, req);
603 break;
604
605 case M66592_CS_WRND:
606 control_end(ep->m66592, 0);
607 break;
608 default:
609 printk(KERN_ERR "start_ep0: unexpect ctsq(%x)\n", ctsq);
610 break;
611 }
612}
613
614static void init_controller(struct m66592 *m66592)
615{
616 m66592_bset(m66592, (vif & M66592_LDRV) | (endian & M66592_BIGEND),
617 M66592_PINCFG);
618 m66592_bset(m66592, M66592_HSE, M66592_SYSCFG); /* High spd */
619 m66592_mdfy(m66592, clock & M66592_XTAL, M66592_XTAL, M66592_SYSCFG);
620
621 m66592_bclr(m66592, M66592_USBE, M66592_SYSCFG);
622 m66592_bclr(m66592, M66592_DPRPU, M66592_SYSCFG);
623 m66592_bset(m66592, M66592_USBE, M66592_SYSCFG);
624
625 m66592_bset(m66592, M66592_XCKE, M66592_SYSCFG);
626
627 msleep(3);
628
629 m66592_bset(m66592, M66592_RCKE | M66592_PLLC, M66592_SYSCFG);
630
631 msleep(1);
632
633 m66592_bset(m66592, M66592_SCKE, M66592_SYSCFG);
634
635 m66592_bset(m66592, irq_sense & M66592_INTL, M66592_INTENB1);
636 m66592_write(m66592, M66592_BURST | M66592_CPU_ADR_RD_WR,
637 M66592_DMA0CFG);
638}
639
640static void disable_controller(struct m66592 *m66592)
641{
642 m66592_bclr(m66592, M66592_SCKE, M66592_SYSCFG);
643 udelay(1);
644 m66592_bclr(m66592, M66592_PLLC, M66592_SYSCFG);
645 udelay(1);
646 m66592_bclr(m66592, M66592_RCKE, M66592_SYSCFG);
647 udelay(1);
648 m66592_bclr(m66592, M66592_XCKE, M66592_SYSCFG);
649}
650
651static void m66592_start_xclock(struct m66592 *m66592)
652{
653 u16 tmp;
654
655 tmp = m66592_read(m66592, M66592_SYSCFG);
656 if (!(tmp & M66592_XCKE))
657 m66592_bset(m66592, M66592_XCKE, M66592_SYSCFG);
658}
659
660/*-------------------------------------------------------------------------*/
661static void transfer_complete(struct m66592_ep *ep,
662 struct m66592_request *req,
663 int status)
664{
665 int restart = 0;
666
667 if (unlikely(ep->pipenum == 0)) {
668 if (ep->internal_ccpl) {
669 ep->internal_ccpl = 0;
670 return;
671 }
672 }
673
674 list_del_init(&req->queue);
675 if (ep->m66592->gadget.speed == USB_SPEED_UNKNOWN)
676 req->req.status = -ESHUTDOWN;
677 else
678 req->req.status = status;
679
680 if (!list_empty(&ep->queue))
681 restart = 1;
682
683 if (likely(req->req.complete))
684 req->req.complete(&ep->ep, &req->req);
685
686 if (restart) {
687 req = list_entry(ep->queue.next, struct m66592_request, queue);
688 if (ep->desc)
689 start_packet(ep, req);
690 }
691}
692
693static void irq_ep0_write(struct m66592_ep *ep, struct m66592_request *req)
694{
695 int i;
696 volatile u16 tmp;
697 unsigned bufsize;
698 size_t size;
699 void *buf;
700 u16 pipenum = ep->pipenum;
701 struct m66592 *m66592 = ep->m66592;
702
703 pipe_change(m66592, pipenum);
704 m66592_bset(m66592, M66592_ISEL, ep->fifosel);
705
706 i = 0;
707 do {
708 tmp = m66592_read(m66592, ep->fifoctr);
709 if (i++ > 100000) {
710 printk(KERN_ERR "pipe0 is busy. maybe cpu i/o bus"
711 "conflict. please power off this controller.");
712 return;
713 }
714 ndelay(1);
715 } while ((tmp & M66592_FRDY) == 0);
716
717 /* prepare parameters */
718 bufsize = get_buffer_size(m66592, pipenum);
719 buf = req->req.buf + req->req.actual;
720 size = min(bufsize, req->req.length - req->req.actual);
721
722 /* write fifo */
723 if (req->req.buf) {
724 if (size > 0)
725 m66592_write_fifo(m66592, ep->fifoaddr, buf, size);
726 if ((size == 0) || ((size % ep->ep.maxpacket) != 0))
727 m66592_bset(m66592, M66592_BVAL, ep->fifoctr);
728 }
729
730 /* update parameters */
731 req->req.actual += size;
732
733 /* check transfer finish */
734 if ((!req->req.zero && (req->req.actual == req->req.length)) ||
735 (size % ep->ep.maxpacket) || (size == 0)) {
736 disable_irq_ready(m66592, pipenum);
737 disable_irq_empty(m66592, pipenum);
738 } else {
739 disable_irq_ready(m66592, pipenum);
740 enable_irq_empty(m66592, pipenum);
741 }
742 pipe_start(m66592, pipenum);
743}
744
745static void irq_packet_write(struct m66592_ep *ep, struct m66592_request *req)
746{
747 u16 tmp;
748 unsigned bufsize;
749 size_t size;
750 void *buf;
751 u16 pipenum = ep->pipenum;
752 struct m66592 *m66592 = ep->m66592;
753
754 pipe_change(m66592, pipenum);
755 tmp = m66592_read(m66592, ep->fifoctr);
756 if (unlikely((tmp & M66592_FRDY) == 0)) {
757 pipe_stop(m66592, pipenum);
758 pipe_irq_disable(m66592, pipenum);
759 printk(KERN_ERR "write fifo not ready. pipnum=%d\n", pipenum);
760 return;
761 }
762
763 /* prepare parameters */
764 bufsize = get_buffer_size(m66592, pipenum);
765 buf = req->req.buf + req->req.actual;
766 size = min(bufsize, req->req.length - req->req.actual);
767
768 /* write fifo */
769 if (req->req.buf) {
770 m66592_write_fifo(m66592, ep->fifoaddr, buf, size);
771 if ((size == 0) || ((size % ep->ep.maxpacket) != 0) ||
772 ((bufsize != ep->ep.maxpacket) && (bufsize > size)))
773 m66592_bset(m66592, M66592_BVAL, ep->fifoctr);
774 }
775
776 /* update parameters */
777 req->req.actual += size;
778 /* check transfer finish */
779 if ((!req->req.zero && (req->req.actual == req->req.length)) ||
780 (size % ep->ep.maxpacket) || (size == 0)) {
781 disable_irq_ready(m66592, pipenum);
782 enable_irq_empty(m66592, pipenum);
783 } else {
784 disable_irq_empty(m66592, pipenum);
785 pipe_irq_enable(m66592, pipenum);
786 }
787}
788
789static void irq_packet_read(struct m66592_ep *ep, struct m66592_request *req)
790{
791 u16 tmp;
792 int rcv_len, bufsize, req_len;
793 int size;
794 void *buf;
795 u16 pipenum = ep->pipenum;
796 struct m66592 *m66592 = ep->m66592;
797 int finish = 0;
798
799 pipe_change(m66592, pipenum);
800 tmp = m66592_read(m66592, ep->fifoctr);
801 if (unlikely((tmp & M66592_FRDY) == 0)) {
802 req->req.status = -EPIPE;
803 pipe_stop(m66592, pipenum);
804 pipe_irq_disable(m66592, pipenum);
805 printk(KERN_ERR "read fifo not ready");
806 return;
807 }
808
809 /* prepare parameters */
810 rcv_len = tmp & M66592_DTLN;
811 bufsize = get_buffer_size(m66592, pipenum);
812
813 buf = req->req.buf + req->req.actual;
814 req_len = req->req.length - req->req.actual;
815 if (rcv_len < bufsize)
816 size = min(rcv_len, req_len);
817 else
818 size = min(bufsize, req_len);
819
820 /* update parameters */
821 req->req.actual += size;
822
823 /* check transfer finish */
824 if ((!req->req.zero && (req->req.actual == req->req.length)) ||
825 (size % ep->ep.maxpacket) || (size == 0)) {
826 pipe_stop(m66592, pipenum);
827 pipe_irq_disable(m66592, pipenum);
828 finish = 1;
829 }
830
831 /* read fifo */
832 if (req->req.buf) {
833 if (size == 0)
834 m66592_write(m66592, M66592_BCLR, ep->fifoctr);
835 else
836 m66592_read_fifo(m66592, ep->fifoaddr, buf, size);
837 }
838
839 if ((ep->pipenum != 0) && finish)
840 transfer_complete(ep, req, 0);
841}
842
843static void irq_pipe_ready(struct m66592 *m66592, u16 status, u16 enb)
844{
845 u16 check;
846 u16 pipenum;
847 struct m66592_ep *ep;
848 struct m66592_request *req;
849
850 if ((status & M66592_BRDY0) && (enb & M66592_BRDY0)) {
851 m66592_write(m66592, ~M66592_BRDY0, M66592_BRDYSTS);
852 m66592_mdfy(m66592, M66592_PIPE0, M66592_CURPIPE,
853 M66592_CFIFOSEL);
854
855 ep = &m66592->ep[0];
856 req = list_entry(ep->queue.next, struct m66592_request, queue);
857 irq_packet_read(ep, req);
858 } else {
859 for (pipenum = 1; pipenum < M66592_MAX_NUM_PIPE; pipenum++) {
860 check = 1 << pipenum;
861 if ((status & check) && (enb & check)) {
862 m66592_write(m66592, ~check, M66592_BRDYSTS);
863 ep = m66592->pipenum2ep[pipenum];
864 req = list_entry(ep->queue.next,
865 struct m66592_request, queue);
866 if (ep->desc->bEndpointAddress & USB_DIR_IN)
867 irq_packet_write(ep, req);
868 else
869 irq_packet_read(ep, req);
870 }
871 }
872 }
873}
874
875static void irq_pipe_empty(struct m66592 *m66592, u16 status, u16 enb)
876{
877 u16 tmp;
878 u16 check;
879 u16 pipenum;
880 struct m66592_ep *ep;
881 struct m66592_request *req;
882
883 if ((status & M66592_BEMP0) && (enb & M66592_BEMP0)) {
884 m66592_write(m66592, ~M66592_BEMP0, M66592_BEMPSTS);
885
886 ep = &m66592->ep[0];
887 req = list_entry(ep->queue.next, struct m66592_request, queue);
888 irq_ep0_write(ep, req);
889 } else {
890 for (pipenum = 1; pipenum < M66592_MAX_NUM_PIPE; pipenum++) {
891 check = 1 << pipenum;
892 if ((status & check) && (enb & check)) {
893 m66592_write(m66592, ~check, M66592_BEMPSTS);
894 tmp = control_reg_get(m66592, pipenum);
895 if ((tmp & M66592_INBUFM) == 0) {
896 disable_irq_empty(m66592, pipenum);
897 pipe_irq_disable(m66592, pipenum);
898 pipe_stop(m66592, pipenum);
899 ep = m66592->pipenum2ep[pipenum];
900 req = list_entry(ep->queue.next,
901 struct m66592_request,
902 queue);
903 if (!list_empty(&ep->queue))
904 transfer_complete(ep, req, 0);
905 }
906 }
907 }
908 }
909}
910
911static void get_status(struct m66592 *m66592, struct usb_ctrlrequest *ctrl)
912{
913 struct m66592_ep *ep;
914 u16 pid;
915 u16 status = 0;
916
917 switch (ctrl->bRequestType & USB_RECIP_MASK) {
918 case USB_RECIP_DEVICE:
919 status = 1; /* selfpower */
920 break;
921 case USB_RECIP_INTERFACE:
922 status = 0;
923 break;
924 case USB_RECIP_ENDPOINT:
925 ep = m66592->epaddr2ep[ctrl->wIndex&USB_ENDPOINT_NUMBER_MASK];
926 pid = control_reg_get_pid(m66592, ep->pipenum);
927 if (pid == M66592_PID_STALL)
928 status = 1;
929 else
930 status = 0;
931 break;
932 default:
933 pipe_stall(m66592, 0);
934 return; /* exit */
935 }
936
937 *m66592->ep0_buf = status;
938 m66592->ep0_req->buf = m66592->ep0_buf;
939 m66592->ep0_req->length = 2;
940 m66592_queue(m66592->gadget.ep0, m66592->ep0_req, GFP_KERNEL);
941}
942
943static void clear_feature(struct m66592 *m66592, struct usb_ctrlrequest *ctrl)
944{
945 switch (ctrl->bRequestType & USB_RECIP_MASK) {
946 case USB_RECIP_DEVICE:
947 control_end(m66592, 1);
948 break;
949 case USB_RECIP_INTERFACE:
950 control_end(m66592, 1);
951 break;
952 case USB_RECIP_ENDPOINT: {
953 struct m66592_ep *ep;
954 struct m66592_request *req;
955
956 ep = m66592->epaddr2ep[ctrl->wIndex&USB_ENDPOINT_NUMBER_MASK];
957 pipe_stop(m66592, ep->pipenum);
958 control_reg_sqclr(m66592, ep->pipenum);
959
960 control_end(m66592, 1);
961
962 req = list_entry(ep->queue.next,
963 struct m66592_request, queue);
964 if (ep->busy) {
965 ep->busy = 0;
966 if (list_empty(&ep->queue))
967 break;
968 start_packet(ep, req);
969 } else if (!list_empty(&ep->queue))
970 pipe_start(m66592, ep->pipenum);
971 }
972 break;
973 default:
974 pipe_stall(m66592, 0);
975 break;
976 }
977}
978
979static void set_feature(struct m66592 *m66592, struct usb_ctrlrequest *ctrl)
980{
981
982 switch (ctrl->bRequestType & USB_RECIP_MASK) {
983 case USB_RECIP_DEVICE:
984 control_end(m66592, 1);
985 break;
986 case USB_RECIP_INTERFACE:
987 control_end(m66592, 1);
988 break;
989 case USB_RECIP_ENDPOINT: {
990 struct m66592_ep *ep;
991
992 ep = m66592->epaddr2ep[ctrl->wIndex&USB_ENDPOINT_NUMBER_MASK];
993 pipe_stall(m66592, ep->pipenum);
994
995 control_end(m66592, 1);
996 }
997 break;
998 default:
999 pipe_stall(m66592, 0);
1000 break;
1001 }
1002}
1003
1004/* if return value is true, call class driver's setup() */
1005static int setup_packet(struct m66592 *m66592, struct usb_ctrlrequest *ctrl)
1006{
1007 u16 *p = (u16 *)ctrl;
1008 unsigned long offset = M66592_USBREQ;
1009 int i, ret = 0;
1010
1011 /* read fifo */
1012 m66592_write(m66592, ~M66592_VALID, M66592_INTSTS0);
1013
1014 for (i = 0; i < 4; i++)
1015 p[i] = m66592_read(m66592, offset + i*2);
1016
1017 /* check request */
1018 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
1019 switch (ctrl->bRequest) {
1020 case USB_REQ_GET_STATUS:
1021 get_status(m66592, ctrl);
1022 break;
1023 case USB_REQ_CLEAR_FEATURE:
1024 clear_feature(m66592, ctrl);
1025 break;
1026 case USB_REQ_SET_FEATURE:
1027 set_feature(m66592, ctrl);
1028 break;
1029 default:
1030 ret = 1;
1031 break;
1032 }
1033 } else
1034 ret = 1;
1035 return ret;
1036}
1037
1038static void m66592_update_usb_speed(struct m66592 *m66592)
1039{
1040 u16 speed = get_usb_speed(m66592);
1041
1042 switch (speed) {
1043 case M66592_HSMODE:
1044 m66592->gadget.speed = USB_SPEED_HIGH;
1045 break;
1046 case M66592_FSMODE:
1047 m66592->gadget.speed = USB_SPEED_FULL;
1048 break;
1049 default:
1050 m66592->gadget.speed = USB_SPEED_UNKNOWN;
1051 printk(KERN_ERR "USB speed unknown\n");
1052 }
1053}
1054
1055static void irq_device_state(struct m66592 *m66592)
1056{
1057 u16 dvsq;
1058
1059 dvsq = m66592_read(m66592, M66592_INTSTS0) & M66592_DVSQ;
1060 m66592_write(m66592, ~M66592_DVST, M66592_INTSTS0);
1061
1062 if (dvsq == M66592_DS_DFLT) { /* bus reset */
1063 m66592->driver->disconnect(&m66592->gadget);
1064 m66592_update_usb_speed(m66592);
1065 }
1066 if (m66592->old_dvsq == M66592_DS_CNFG && dvsq != M66592_DS_CNFG)
1067 m66592_update_usb_speed(m66592);
1068 if ((dvsq == M66592_DS_CNFG || dvsq == M66592_DS_ADDS) &&
1069 m66592->gadget.speed == USB_SPEED_UNKNOWN)
1070 m66592_update_usb_speed(m66592);
1071
1072 m66592->old_dvsq = dvsq;
1073}
1074
1075static void irq_control_stage(struct m66592 *m66592)
1076{
1077 struct usb_ctrlrequest ctrl;
1078 u16 ctsq;
1079
1080 ctsq = m66592_read(m66592, M66592_INTSTS0) & M66592_CTSQ;
1081 m66592_write(m66592, ~M66592_CTRT, M66592_INTSTS0);
1082
1083 switch (ctsq) {
1084 case M66592_CS_IDST: {
1085 struct m66592_ep *ep;
1086 struct m66592_request *req;
1087 ep = &m66592->ep[0];
1088 req = list_entry(ep->queue.next, struct m66592_request, queue);
1089 transfer_complete(ep, req, 0);
1090 }
1091 break;
1092
1093 case M66592_CS_RDDS:
1094 case M66592_CS_WRDS:
1095 case M66592_CS_WRND:
1096 if (setup_packet(m66592, &ctrl)) {
1097 if (m66592->driver->setup(&m66592->gadget, &ctrl) < 0)
1098 pipe_stall(m66592, 0);
1099 }
1100 break;
1101 case M66592_CS_RDSS:
1102 case M66592_CS_WRSS:
1103 control_end(m66592, 0);
1104 break;
1105 default:
1106 printk(KERN_ERR "ctrl_stage: unexpect ctsq(%x)\n", ctsq);
1107 break;
1108 }
1109}
1110
1111static irqreturn_t m66592_irq(int irq, void *_m66592)
1112{
1113 struct m66592 *m66592 = _m66592;
1114 u16 intsts0;
1115 u16 intenb0;
1116 u16 brdysts, nrdysts, bempsts;
1117 u16 brdyenb, nrdyenb, bempenb;
1118 u16 savepipe;
1119 u16 mask0;
1120
1121 intsts0 = m66592_read(m66592, M66592_INTSTS0);
1122 intenb0 = m66592_read(m66592, M66592_INTENB0);
1123
1124 savepipe = m66592_read(m66592, M66592_CFIFOSEL);
1125
1126 mask0 = intsts0 & intenb0;
1127 if (mask0) {
1128 brdysts = m66592_read(m66592, M66592_BRDYSTS);
1129 nrdysts = m66592_read(m66592, M66592_NRDYSTS);
1130 bempsts = m66592_read(m66592, M66592_BEMPSTS);
1131 brdyenb = m66592_read(m66592, M66592_BRDYENB);
1132 nrdyenb = m66592_read(m66592, M66592_NRDYENB);
1133 bempenb = m66592_read(m66592, M66592_BEMPENB);
1134
1135 if (mask0 & M66592_VBINT) {
1136 m66592_write(m66592, (u16)~M66592_VBINT,
1137 M66592_INTSTS0);
1138 m66592_start_xclock(m66592);
1139
1140 /* start vbus sampling */
1141 m66592->old_vbus = m66592_read(m66592, M66592_INTSTS0)
1142 & M66592_VBSTS;
1143 m66592->scount = M66592_MAX_SAMPLING;
1144
1145 mod_timer(&m66592->timer,
1146 jiffies + msecs_to_jiffies(50));
1147 }
1148 if (intsts0 & M66592_DVSQ)
1149 irq_device_state(m66592);
1150
1151 if ((intsts0 & M66592_BRDY) && (intenb0 & M66592_BRDYE) &&
1152 (brdysts & brdyenb)) {
1153 irq_pipe_ready(m66592, brdysts, brdyenb);
1154 }
1155 if ((intsts0 & M66592_BEMP) && (intenb0 & M66592_BEMPE) &&
1156 (bempsts & bempenb)) {
1157 irq_pipe_empty(m66592, bempsts, bempenb);
1158 }
1159
1160 if (intsts0 & M66592_CTRT)
1161 irq_control_stage(m66592);
1162 }
1163
1164 m66592_write(m66592, savepipe, M66592_CFIFOSEL);
1165
1166 return IRQ_HANDLED;
1167}
1168
1169static void m66592_timer(unsigned long _m66592)
1170{
1171 struct m66592 *m66592 = (struct m66592 *)_m66592;
1172 unsigned long flags;
1173 u16 tmp;
1174
1175 spin_lock_irqsave(&m66592->lock, flags);
1176 tmp = m66592_read(m66592, M66592_SYSCFG);
1177 if (!(tmp & M66592_RCKE)) {
1178 m66592_bset(m66592, M66592_RCKE | M66592_PLLC, M66592_SYSCFG);
1179 udelay(10);
1180 m66592_bset(m66592, M66592_SCKE, M66592_SYSCFG);
1181 }
1182 if (m66592->scount > 0) {
1183 tmp = m66592_read(m66592, M66592_INTSTS0) & M66592_VBSTS;
1184 if (tmp == m66592->old_vbus) {
1185 m66592->scount--;
1186 if (m66592->scount == 0) {
1187 if (tmp == M66592_VBSTS)
1188 m66592_usb_connect(m66592);
1189 else
1190 m66592_usb_disconnect(m66592);
1191 } else {
1192 mod_timer(&m66592->timer,
1193 jiffies + msecs_to_jiffies(50));
1194 }
1195 } else {
1196 m66592->scount = M66592_MAX_SAMPLING;
1197 m66592->old_vbus = tmp;
1198 mod_timer(&m66592->timer,
1199 jiffies + msecs_to_jiffies(50));
1200 }
1201 }
1202 spin_unlock_irqrestore(&m66592->lock, flags);
1203}
1204
1205/*-------------------------------------------------------------------------*/
1206static int m66592_enable(struct usb_ep *_ep,
1207 const struct usb_endpoint_descriptor *desc)
1208{
1209 struct m66592_ep *ep;
1210
1211 ep = container_of(_ep, struct m66592_ep, ep);
1212 return alloc_pipe_config(ep, desc);
1213}
1214
1215static int m66592_disable(struct usb_ep *_ep)
1216{
1217 struct m66592_ep *ep;
1218 struct m66592_request *req;
1219 unsigned long flags;
1220
1221 ep = container_of(_ep, struct m66592_ep, ep);
1222 BUG_ON(!ep);
1223
1224 while (!list_empty(&ep->queue)) {
1225 req = list_entry(ep->queue.next, struct m66592_request, queue);
1226 spin_lock_irqsave(&ep->m66592->lock, flags);
1227 transfer_complete(ep, req, -ECONNRESET);
1228 spin_unlock_irqrestore(&ep->m66592->lock, flags);
1229 }
1230
1231 pipe_irq_disable(ep->m66592, ep->pipenum);
1232 return free_pipe_config(ep);
1233}
1234
1235static struct usb_request *m66592_alloc_request(struct usb_ep *_ep,
1236 gfp_t gfp_flags)
1237{
1238 struct m66592_request *req;
1239
1240 req = kzalloc(sizeof(struct m66592_request), gfp_flags);
1241 if (!req)
1242 return NULL;
1243
1244 INIT_LIST_HEAD(&req->queue);
1245
1246 return &req->req;
1247}
1248
1249static void m66592_free_request(struct usb_ep *_ep, struct usb_request *_req)
1250{
1251 struct m66592_request *req;
1252
1253 req = container_of(_req, struct m66592_request, req);
1254 kfree(req);
1255}
1256
1257static void *m66592_alloc_buffer(struct usb_ep *_ep, unsigned bytes,
1258 dma_addr_t *dma, gfp_t gfp_flags)
1259{
1260 void *buf;
1261
1262 buf = kzalloc(bytes, gfp_flags);
1263 if (dma)
1264 *dma = virt_to_bus(buf);
1265
1266 return buf;
1267}
1268
1269static void m66592_free_buffer(struct usb_ep *_ep, void *buf,
1270 dma_addr_t dma, unsigned bytes)
1271{
1272 kfree(buf);
1273}
1274
1275static int m66592_queue(struct usb_ep *_ep, struct usb_request *_req,
1276 gfp_t gfp_flags)
1277{
1278 struct m66592_ep *ep;
1279 struct m66592_request *req;
1280 unsigned long flags;
1281 int request = 0;
1282
1283 ep = container_of(_ep, struct m66592_ep, ep);
1284 req = container_of(_req, struct m66592_request, req);
1285
1286 if (ep->m66592->gadget.speed == USB_SPEED_UNKNOWN)
1287 return -ESHUTDOWN;
1288
1289 spin_lock_irqsave(&ep->m66592->lock, flags);
1290
1291 if (list_empty(&ep->queue))
1292 request = 1;
1293
1294 list_add_tail(&req->queue, &ep->queue);
1295 req->req.actual = 0;
1296 req->req.status = -EINPROGRESS;
1297
1298 if (ep->desc == 0) /* control */
1299 start_ep0(ep, req);
1300 else {
1301 if (request && !ep->busy)
1302 start_packet(ep, req);
1303 }
1304
1305 spin_unlock_irqrestore(&ep->m66592->lock, flags);
1306
1307 return 0;
1308}
1309
1310static int m66592_dequeue(struct usb_ep *_ep, struct usb_request *_req)
1311{
1312 struct m66592_ep *ep;
1313 struct m66592_request *req;
1314 unsigned long flags;
1315
1316 ep = container_of(_ep, struct m66592_ep, ep);
1317 req = container_of(_req, struct m66592_request, req);
1318
1319 spin_lock_irqsave(&ep->m66592->lock, flags);
1320 if (!list_empty(&ep->queue))
1321 transfer_complete(ep, req, -ECONNRESET);
1322 spin_unlock_irqrestore(&ep->m66592->lock, flags);
1323
1324 return 0;
1325}
1326
1327static int m66592_set_halt(struct usb_ep *_ep, int value)
1328{
1329 struct m66592_ep *ep;
1330 struct m66592_request *req;
1331 unsigned long flags;
1332 int ret = 0;
1333
1334 ep = container_of(_ep, struct m66592_ep, ep);
1335 req = list_entry(ep->queue.next, struct m66592_request, queue);
1336
1337 spin_lock_irqsave(&ep->m66592->lock, flags);
1338 if (!list_empty(&ep->queue)) {
1339 ret = -EAGAIN;
1340 goto out;
1341 }
1342 if (value) {
1343 ep->busy = 1;
1344 pipe_stall(ep->m66592, ep->pipenum);
1345 } else {
1346 ep->busy = 0;
1347 pipe_stop(ep->m66592, ep->pipenum);
1348 }
1349
1350out:
1351 spin_unlock_irqrestore(&ep->m66592->lock, flags);
1352 return ret;
1353}
1354
1355static int m66592_fifo_status(struct usb_ep *_ep)
1356{
1357 return -EOPNOTSUPP;
1358}
1359
1360static void m66592_fifo_flush(struct usb_ep *_ep)
1361{
1362 struct m66592_ep *ep;
1363 unsigned long flags;
1364
1365 ep = container_of(_ep, struct m66592_ep, ep);
1366 spin_lock_irqsave(&ep->m66592->lock, flags);
1367 if (list_empty(&ep->queue) && !ep->busy) {
1368 pipe_stop(ep->m66592, ep->pipenum);
1369 m66592_bclr(ep->m66592, M66592_BCLR, ep->fifoctr);
1370 }
1371 spin_unlock_irqrestore(&ep->m66592->lock, flags);
1372}
1373
1374static struct usb_ep_ops m66592_ep_ops = {
1375 .enable = m66592_enable,
1376 .disable = m66592_disable,
1377
1378 .alloc_request = m66592_alloc_request,
1379 .free_request = m66592_free_request,
1380
1381 .alloc_buffer = m66592_alloc_buffer,
1382 .free_buffer = m66592_free_buffer,
1383
1384 .queue = m66592_queue,
1385 .dequeue = m66592_dequeue,
1386
1387 .set_halt = m66592_set_halt,
1388 .fifo_status = m66592_fifo_status,
1389 .fifo_flush = m66592_fifo_flush,
1390};
1391
1392/*-------------------------------------------------------------------------*/
1393static struct m66592 *the_controller;
1394
1395int usb_gadget_register_driver(struct usb_gadget_driver *driver)
1396{
1397 struct m66592 *m66592 = the_controller;
1398 int retval;
1399
1400 if (!driver ||
1401 driver->speed != USB_SPEED_HIGH ||
1402 !driver->bind ||
1403 !driver->unbind ||
1404 !driver->setup)
1405 return -EINVAL;
1406 if (!m66592)
1407 return -ENODEV;
1408 if (m66592->driver)
1409 return -EBUSY;
1410
1411 /* hook up the driver */
1412 driver->driver.bus = NULL;
1413 m66592->driver = driver;
1414 m66592->gadget.dev.driver = &driver->driver;
1415
1416 retval = device_add(&m66592->gadget.dev);
1417 if (retval) {
1418 printk(KERN_ERR "device_add error (%d)\n", retval);
1419 goto error;
1420 }
1421
1422 retval = driver->bind (&m66592->gadget);
1423 if (retval) {
1424 printk(KERN_ERR "bind to driver error (%d)\n", retval);
1425 device_del(&m66592->gadget.dev);
1426 goto error;
1427 }
1428
1429 m66592_bset(m66592, M66592_VBSE | M66592_URST, M66592_INTENB0);
1430 if (m66592_read(m66592, M66592_INTSTS0) & M66592_VBSTS) {
1431 m66592_start_xclock(m66592);
1432 /* start vbus sampling */
1433 m66592->old_vbus = m66592_read(m66592,
1434 M66592_INTSTS0) & M66592_VBSTS;
1435 m66592->scount = M66592_MAX_SAMPLING;
1436 mod_timer(&m66592->timer,
1437 jiffies + msecs_to_jiffies(50));
1438 }
1439
1440 return 0;
1441
1442error:
1443 m66592->driver = NULL;
1444 m66592->gadget.dev.driver = NULL;
1445
1446 return retval;
1447}
1448EXPORT_SYMBOL(usb_gadget_register_driver);
1449
1450int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
1451{
1452 struct m66592 *m66592 = the_controller;
1453 unsigned long flags;
1454
1455 spin_lock_irqsave(&m66592->lock, flags);
1456 if (m66592->gadget.speed != USB_SPEED_UNKNOWN)
1457 m66592_usb_disconnect(m66592);
1458 spin_unlock_irqrestore(&m66592->lock, flags);
1459
1460 m66592_bclr(m66592, M66592_VBSE | M66592_URST, M66592_INTENB0);
1461
1462 driver->unbind(&m66592->gadget);
1463
1464 init_controller(m66592);
1465 disable_controller(m66592);
1466
1467 device_del(&m66592->gadget.dev);
1468 m66592->driver = NULL;
1469 return 0;
1470}
1471EXPORT_SYMBOL(usb_gadget_unregister_driver);
1472
1473/*-------------------------------------------------------------------------*/
1474static int m66592_get_frame(struct usb_gadget *_gadget)
1475{
1476 struct m66592 *m66592 = gadget_to_m66592(_gadget);
1477 return m66592_read(m66592, M66592_FRMNUM) & 0x03FF;
1478}
1479
1480static struct usb_gadget_ops m66592_gadget_ops = {
1481 .get_frame = m66592_get_frame,
1482};
1483
1484#if defined(CONFIG_PM)
1485static int m66592_suspend(struct platform_device *pdev, pm_message_t state)
1486{
1487 pdev->dev.power.power_state = state;
1488 return 0;
1489}
1490
1491static int m66592_resume(struct platform_device *pdev)
1492{
1493 pdev->dev.power.power_state = PMSG_ON;
1494 return 0;
1495}
1496#else /* if defined(CONFIG_PM) */
1497#define m66592_suspend NULL
1498#define m66592_resume NULL
1499#endif
1500
1501static int __init_or_module m66592_remove(struct platform_device *pdev)
1502{
1503 struct m66592 *m66592 = dev_get_drvdata(&pdev->dev);
1504
1505 del_timer_sync(&m66592->timer);
1506 iounmap(m66592->reg);
1507 free_irq(platform_get_irq(pdev, 0), m66592);
1508 kfree(m66592);
1509 return 0;
1510}
1511
1512#define resource_len(r) (((r)->end - (r)->start) + 1)
1513static int __init m66592_probe(struct platform_device *pdev)
1514{
1515 struct resource *res = NULL;
1516 int irq = -1;
1517 void __iomem *reg = NULL;
1518 struct m66592 *m66592 = NULL;
1519 int ret = 0;
1520 int i;
1521
1522 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
1523 (char *)udc_name);
1524 if (!res) {
1525 ret = -ENODEV;
1526 printk(KERN_ERR "platform_get_resource_byname error.\n");
1527 goto clean_up;
1528 }
1529
1530 irq = platform_get_irq(pdev, 0);
1531 if (irq < 0) {
1532 ret = -ENODEV;
1533 printk(KERN_ERR "platform_get_irq error.\n");
1534 goto clean_up;
1535 }
1536
1537 reg = ioremap(res->start, resource_len(res));
1538 if (reg == NULL) {
1539 ret = -ENOMEM;
1540 printk(KERN_ERR "ioremap error.\n");
1541 goto clean_up;
1542 }
1543
1544 /* initialize ucd */
1545 m66592 = kzalloc(sizeof(struct m66592), GFP_KERNEL);
1546 if (m66592 == NULL) {
1547 printk(KERN_ERR "kzalloc error\n");
1548 goto clean_up;
1549 }
1550
1551 spin_lock_init(&m66592->lock);
1552 dev_set_drvdata(&pdev->dev, m66592);
1553
1554 m66592->gadget.ops = &m66592_gadget_ops;
1555 device_initialize(&m66592->gadget.dev);
1556 strcpy(m66592->gadget.dev.bus_id, "gadget");
1557 m66592->gadget.is_dualspeed = 1;
1558 m66592->gadget.dev.parent = &pdev->dev;
1559 m66592->gadget.dev.dma_mask = pdev->dev.dma_mask;
1560 m66592->gadget.dev.release = pdev->dev.release;
1561 m66592->gadget.name = udc_name;
1562
1563 init_timer(&m66592->timer);
1564 m66592->timer.function = m66592_timer;
1565 m66592->timer.data = (unsigned long)m66592;
1566 m66592->reg = reg;
1567
1568 m66592->bi_bufnum = M66592_BASE_BUFNUM;
1569
1570 ret = request_irq(irq, m66592_irq, SA_INTERRUPT | SA_SHIRQ,
1571 udc_name, m66592);
1572 if (ret < 0) {
1573 printk(KERN_ERR "request_irq error (%d)\n", ret);
1574 goto clean_up;
1575 }
1576
1577 INIT_LIST_HEAD(&m66592->gadget.ep_list);
1578 m66592->gadget.ep0 = &m66592->ep[0].ep;
1579 INIT_LIST_HEAD(&m66592->gadget.ep0->ep_list);
1580 for (i = 0; i < M66592_MAX_NUM_PIPE; i++) {
1581 struct m66592_ep *ep = &m66592->ep[i];
1582
1583 if (i != 0) {
1584 INIT_LIST_HEAD(&m66592->ep[i].ep.ep_list);
1585 list_add_tail(&m66592->ep[i].ep.ep_list,
1586 &m66592->gadget.ep_list);
1587 }
1588 ep->m66592 = m66592;
1589 INIT_LIST_HEAD(&ep->queue);
1590 ep->ep.name = m66592_ep_name[i];
1591 ep->ep.ops = &m66592_ep_ops;
1592 ep->ep.maxpacket = 512;
1593 }
1594 m66592->ep[0].ep.maxpacket = 64;
1595 m66592->ep[0].pipenum = 0;
1596 m66592->ep[0].fifoaddr = M66592_CFIFO;
1597 m66592->ep[0].fifosel = M66592_CFIFOSEL;
1598 m66592->ep[0].fifoctr = M66592_CFIFOCTR;
1599 m66592->ep[0].fifotrn = 0;
1600 m66592->ep[0].pipectr = get_pipectr_addr(0);
1601 m66592->pipenum2ep[0] = &m66592->ep[0];
1602 m66592->epaddr2ep[0] = &m66592->ep[0];
1603
1604 the_controller = m66592;
1605
1606 m66592->ep0_req = m66592_alloc_request(&m66592->ep[0].ep, GFP_KERNEL);
1607 if (m66592->ep0_req == NULL)
1608 goto clean_up;
1609 m66592->ep0_buf = m66592_alloc_buffer(&m66592->ep[0].ep, 2, NULL,
1610 GFP_KERNEL);
1611 if (m66592->ep0_buf == NULL)
1612 goto clean_up;
1613
1614 init_controller(m66592);
1615
1616 printk("driver %s, %s\n", udc_name, DRIVER_VERSION);
1617 return 0;
1618
1619clean_up:
1620 if (m66592) {
1621 if (m66592->ep0_req)
1622 m66592_free_request(&m66592->ep[0].ep, m66592->ep0_req);
1623 kfree(m66592);
1624 }
1625 if (reg)
1626 iounmap(reg);
1627
1628 return ret;
1629}
1630
1631/*-------------------------------------------------------------------------*/
1632static struct platform_driver m66592_driver = {
1633 .probe = m66592_probe,
1634 .remove = m66592_remove,
1635 .suspend = m66592_suspend,
1636 .resume = m66592_resume,
1637 .driver = {
1638 .name = (char *) udc_name,
1639 },
1640};
1641
1642static int __init m66592_udc_init(void)
1643{
1644 return platform_driver_register(&m66592_driver);
1645}
1646module_init(m66592_udc_init);
1647
1648static void __exit m66592_udc_cleanup(void)
1649{
1650 platform_driver_unregister(&m66592_driver);
1651}
1652module_exit(m66592_udc_cleanup);
1653
diff --git a/drivers/usb/gadget/m66592-udc.h b/drivers/usb/gadget/m66592-udc.h
new file mode 100644
index 000000000000..26b54f8b8945
--- /dev/null
+++ b/drivers/usb/gadget/m66592-udc.h
@@ -0,0 +1,577 @@
1/*
2 * M66592 UDC (USB gadget)
3 *
4 * Copyright (C) 2006-2007 Renesas Solutions Corp.
5 *
6 * Author : Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 *
21 */
22
23#ifndef __M66592_UDC_H__
24#define __M66592_UDC_H__
25
26#define M66592_SYSCFG 0x00
27#define M66592_XTAL 0xC000 /* b15-14: Crystal selection */
28#define M66592_XTAL48 0x8000 /* 48MHz */
29#define M66592_XTAL24 0x4000 /* 24MHz */
30#define M66592_XTAL12 0x0000 /* 12MHz */
31#define M66592_XCKE 0x2000 /* b13: External clock enable */
32#define M66592_RCKE 0x1000 /* b12: Register clock enable */
33#define M66592_PLLC 0x0800 /* b11: PLL control */
34#define M66592_SCKE 0x0400 /* b10: USB clock enable */
35#define M66592_ATCKM 0x0100 /* b8: Automatic supply functional enable */
36#define M66592_HSE 0x0080 /* b7: Hi-speed enable */
37#define M66592_DCFM 0x0040 /* b6: Controller function select */
38#define M66592_DMRPD 0x0020 /* b5: D- pull down control */
39#define M66592_DPRPU 0x0010 /* b4: D+ pull up control */
40#define M66592_FSRPC 0x0004 /* b2: Full-speed receiver enable */
41#define M66592_PCUT 0x0002 /* b1: Low power sleep enable */
42#define M66592_USBE 0x0001 /* b0: USB module operation enable */
43
44#define M66592_SYSSTS 0x02
45#define M66592_LNST 0x0003 /* b1-0: D+, D- line status */
46#define M66592_SE1 0x0003 /* SE1 */
47#define M66592_KSTS 0x0002 /* K State */
48#define M66592_JSTS 0x0001 /* J State */
49#define M66592_SE0 0x0000 /* SE0 */
50
51#define M66592_DVSTCTR 0x04
52#define M66592_WKUP 0x0100 /* b8: Remote wakeup */
53#define M66592_RWUPE 0x0080 /* b7: Remote wakeup sense */
54#define M66592_USBRST 0x0040 /* b6: USB reset enable */
55#define M66592_RESUME 0x0020 /* b5: Resume enable */
56#define M66592_UACT 0x0010 /* b4: USB bus enable */
57#define M66592_RHST 0x0003 /* b1-0: Reset handshake status */
58#define M66592_HSMODE 0x0003 /* Hi-Speed mode */
59#define M66592_FSMODE 0x0002 /* Full-Speed mode */
60#define M66592_HSPROC 0x0001 /* HS handshake is processing */
61
62#define M66592_TESTMODE 0x06
63#define M66592_UTST 0x000F /* b4-0: Test select */
64#define M66592_H_TST_PACKET 0x000C /* HOST TEST Packet */
65#define M66592_H_TST_SE0_NAK 0x000B /* HOST TEST SE0 NAK */
66#define M66592_H_TST_K 0x000A /* HOST TEST K */
67#define M66592_H_TST_J 0x0009 /* HOST TEST J */
68#define M66592_H_TST_NORMAL 0x0000 /* HOST Normal Mode */
69#define M66592_P_TST_PACKET 0x0004 /* PERI TEST Packet */
70#define M66592_P_TST_SE0_NAK 0x0003 /* PERI TEST SE0 NAK */
71#define M66592_P_TST_K 0x0002 /* PERI TEST K */
72#define M66592_P_TST_J 0x0001 /* PERI TEST J */
73#define M66592_P_TST_NORMAL 0x0000 /* PERI Normal Mode */
74
75#define M66592_PINCFG 0x0A
76#define M66592_LDRV 0x8000 /* b15: Drive Current Adjust */
77#define M66592_BIGEND 0x0100 /* b8: Big endian mode */
78
79#define M66592_DMA0CFG 0x0C
80#define M66592_DMA1CFG 0x0E
81#define M66592_DREQA 0x4000 /* b14: Dreq active select */
82#define M66592_BURST 0x2000 /* b13: Burst mode */
83#define M66592_DACKA 0x0400 /* b10: Dack active select */
84#define M66592_DFORM 0x0380 /* b9-7: DMA mode select */
85#define M66592_CPU_ADR_RD_WR 0x0000 /* Address + RD/WR mode (CPU bus) */
86#define M66592_CPU_DACK_RD_WR 0x0100 /* DACK + RD/WR mode (CPU bus) */
87#define M66592_CPU_DACK_ONLY 0x0180 /* DACK only mode (CPU bus) */
88#define M66592_SPLIT_DACK_ONLY 0x0200 /* DACK only mode (SPLIT bus) */
89#define M66592_SPLIT_DACK_DSTB 0x0300 /* DACK + DSTB0 mode (SPLIT bus) */
90#define M66592_DENDA 0x0040 /* b6: Dend active select */
91#define M66592_PKTM 0x0020 /* b5: Packet mode */
92#define M66592_DENDE 0x0010 /* b4: Dend enable */
93#define M66592_OBUS 0x0004 /* b2: OUTbus mode */
94
95#define M66592_CFIFO 0x10
96#define M66592_D0FIFO 0x14
97#define M66592_D1FIFO 0x18
98
99#define M66592_CFIFOSEL 0x1E
100#define M66592_D0FIFOSEL 0x24
101#define M66592_D1FIFOSEL 0x2A
102#define M66592_RCNT 0x8000 /* b15: Read count mode */
103#define M66592_REW 0x4000 /* b14: Buffer rewind */
104#define M66592_DCLRM 0x2000 /* b13: DMA buffer clear mode */
105#define M66592_DREQE 0x1000 /* b12: DREQ output enable */
106#define M66592_MBW 0x0400 /* b10: Maximum bit width for FIFO access */
107#define M66592_MBW_8 0x0000 /* 8bit */
108#define M66592_MBW_16 0x0400 /* 16bit */
109#define M66592_TRENB 0x0200 /* b9: Transaction counter enable */
110#define M66592_TRCLR 0x0100 /* b8: Transaction counter clear */
111#define M66592_DEZPM 0x0080 /* b7: Zero-length packet additional mode */
112#define M66592_ISEL 0x0020 /* b5: DCP FIFO port direction select */
113#define M66592_CURPIPE 0x0007 /* b2-0: PIPE select */
114
115#define M66592_CFIFOCTR 0x20
116#define M66592_D0FIFOCTR 0x26
117#define M66592_D1FIFOCTR 0x2c
118#define M66592_BVAL 0x8000 /* b15: Buffer valid flag */
119#define M66592_BCLR 0x4000 /* b14: Buffer clear */
120#define M66592_FRDY 0x2000 /* b13: FIFO ready */
121#define M66592_DTLN 0x0FFF /* b11-0: FIFO received data length */
122
123#define M66592_CFIFOSIE 0x22
124#define M66592_TGL 0x8000 /* b15: Buffer toggle */
125#define M66592_SCLR 0x4000 /* b14: Buffer clear */
126#define M66592_SBUSY 0x2000 /* b13: SIE_FIFO busy */
127
128#define M66592_D0FIFOTRN 0x28
129#define M66592_D1FIFOTRN 0x2E
130#define M66592_TRNCNT 0xFFFF /* b15-0: Transaction counter */
131
132#define M66592_INTENB0 0x30
133#define M66592_VBSE 0x8000 /* b15: VBUS interrupt */
134#define M66592_RSME 0x4000 /* b14: Resume interrupt */
135#define M66592_SOFE 0x2000 /* b13: Frame update interrupt */
136#define M66592_DVSE 0x1000 /* b12: Device state transition interrupt */
137#define M66592_CTRE 0x0800 /* b11: Control transfer stage transition interrupt */
138#define M66592_BEMPE 0x0400 /* b10: Buffer empty interrupt */
139#define M66592_NRDYE 0x0200 /* b9: Buffer not ready interrupt */
140#define M66592_BRDYE 0x0100 /* b8: Buffer ready interrupt */
141#define M66592_URST 0x0080 /* b7: USB reset detected interrupt */
142#define M66592_SADR 0x0040 /* b6: Set address executed interrupt */
143#define M66592_SCFG 0x0020 /* b5: Set configuration executed interrupt */
144#define M66592_SUSP 0x0010 /* b4: Suspend detected interrupt */
145#define M66592_WDST 0x0008 /* b3: Control write data stage completed interrupt */
146#define M66592_RDST 0x0004 /* b2: Control read data stage completed interrupt */
147#define M66592_CMPL 0x0002 /* b1: Control transfer complete interrupt */
148#define M66592_SERR 0x0001 /* b0: Sequence error interrupt */
149
150#define M66592_INTENB1 0x32
151#define M66592_BCHGE 0x4000 /* b14: USB us chenge interrupt */
152#define M66592_DTCHE 0x1000 /* b12: Detach sense interrupt */
153#define M66592_SIGNE 0x0020 /* b5: SETUP IGNORE interrupt */
154#define M66592_SACKE 0x0010 /* b4: SETUP ACK interrupt */
155#define M66592_BRDYM 0x0004 /* b2: BRDY clear timing */
156#define M66592_INTL 0x0002 /* b1: Interrupt sense select */
157#define M66592_PCSE 0x0001 /* b0: PCUT enable by CS assert */
158
159#define M66592_BRDYENB 0x36
160#define M66592_BRDYSTS 0x46
161#define M66592_BRDY7 0x0080 /* b7: PIPE7 */
162#define M66592_BRDY6 0x0040 /* b6: PIPE6 */
163#define M66592_BRDY5 0x0020 /* b5: PIPE5 */
164#define M66592_BRDY4 0x0010 /* b4: PIPE4 */
165#define M66592_BRDY3 0x0008 /* b3: PIPE3 */
166#define M66592_BRDY2 0x0004 /* b2: PIPE2 */
167#define M66592_BRDY1 0x0002 /* b1: PIPE1 */
168#define M66592_BRDY0 0x0001 /* b1: PIPE0 */
169
170#define M66592_NRDYENB 0x38
171#define M66592_NRDYSTS 0x48
172#define M66592_NRDY7 0x0080 /* b7: PIPE7 */
173#define M66592_NRDY6 0x0040 /* b6: PIPE6 */
174#define M66592_NRDY5 0x0020 /* b5: PIPE5 */
175#define M66592_NRDY4 0x0010 /* b4: PIPE4 */
176#define M66592_NRDY3 0x0008 /* b3: PIPE3 */
177#define M66592_NRDY2 0x0004 /* b2: PIPE2 */
178#define M66592_NRDY1 0x0002 /* b1: PIPE1 */
179#define M66592_NRDY0 0x0001 /* b1: PIPE0 */
180
181#define M66592_BEMPENB 0x3A
182#define M66592_BEMPSTS 0x4A
183#define M66592_BEMP7 0x0080 /* b7: PIPE7 */
184#define M66592_BEMP6 0x0040 /* b6: PIPE6 */
185#define M66592_BEMP5 0x0020 /* b5: PIPE5 */
186#define M66592_BEMP4 0x0010 /* b4: PIPE4 */
187#define M66592_BEMP3 0x0008 /* b3: PIPE3 */
188#define M66592_BEMP2 0x0004 /* b2: PIPE2 */
189#define M66592_BEMP1 0x0002 /* b1: PIPE1 */
190#define M66592_BEMP0 0x0001 /* b0: PIPE0 */
191
192#define M66592_SOFCFG 0x3C
193#define M66592_SOFM 0x000C /* b3-2: SOF palse mode */
194#define M66592_SOF_125US 0x0008 /* SOF OUT 125us uFrame Signal */
195#define M66592_SOF_1MS 0x0004 /* SOF OUT 1ms Frame Signal */
196#define M66592_SOF_DISABLE 0x0000 /* SOF OUT Disable */
197
198#define M66592_INTSTS0 0x40
199#define M66592_VBINT 0x8000 /* b15: VBUS interrupt */
200#define M66592_RESM 0x4000 /* b14: Resume interrupt */
201#define M66592_SOFR 0x2000 /* b13: SOF frame update interrupt */
202#define M66592_DVST 0x1000 /* b12: Device state transition interrupt */
203#define M66592_CTRT 0x0800 /* b11: Control transfer stage transition interrupt */
204#define M66592_BEMP 0x0400 /* b10: Buffer empty interrupt */
205#define M66592_NRDY 0x0200 /* b9: Buffer not ready interrupt */
206#define M66592_BRDY 0x0100 /* b8: Buffer ready interrupt */
207#define M66592_VBSTS 0x0080 /* b7: VBUS input port */
208#define M66592_DVSQ 0x0070 /* b6-4: Device state */
209#define M66592_DS_SPD_CNFG 0x0070 /* Suspend Configured */
210#define M66592_DS_SPD_ADDR 0x0060 /* Suspend Address */
211#define M66592_DS_SPD_DFLT 0x0050 /* Suspend Default */
212#define M66592_DS_SPD_POWR 0x0040 /* Suspend Powered */
213#define M66592_DS_SUSP 0x0040 /* Suspend */
214#define M66592_DS_CNFG 0x0030 /* Configured */
215#define M66592_DS_ADDS 0x0020 /* Address */
216#define M66592_DS_DFLT 0x0010 /* Default */
217#define M66592_DS_POWR 0x0000 /* Powered */
218#define M66592_DVSQS 0x0030 /* b5-4: Device state */
219#define M66592_VALID 0x0008 /* b3: Setup packet detected flag */
220#define M66592_CTSQ 0x0007 /* b2-0: Control transfer stage */
221#define M66592_CS_SQER 0x0006 /* Sequence error */
222#define M66592_CS_WRND 0x0005 /* Control write nodata status stage */
223#define M66592_CS_WRSS 0x0004 /* Control write status stage */
224#define M66592_CS_WRDS 0x0003 /* Control write data stage */
225#define M66592_CS_RDSS 0x0002 /* Control read status stage */
226#define M66592_CS_RDDS 0x0001 /* Control read data stage */
227#define M66592_CS_IDST 0x0000 /* Idle or setup stage */
228
229#define M66592_INTSTS1 0x42
230#define M66592_BCHG 0x4000 /* b14: USB bus chenge interrupt */
231#define M66592_DTCH 0x1000 /* b12: Detach sense interrupt */
232#define M66592_SIGN 0x0020 /* b5: SETUP IGNORE interrupt */
233#define M66592_SACK 0x0010 /* b4: SETUP ACK interrupt */
234
235#define M66592_FRMNUM 0x4C
236#define M66592_OVRN 0x8000 /* b15: Overrun error */
237#define M66592_CRCE 0x4000 /* b14: Received data error */
238#define M66592_SOFRM 0x0800 /* b11: SOF output mode */
239#define M66592_FRNM 0x07FF /* b10-0: Frame number */
240
241#define M66592_UFRMNUM 0x4E
242#define M66592_UFRNM 0x0007 /* b2-0: Micro frame number */
243
244#define M66592_RECOVER 0x50
245#define M66592_STSRECOV 0x0700 /* Status recovery */
246#define M66592_STSR_HI 0x0400 /* FULL(0) or HI(1) Speed */
247#define M66592_STSR_DEFAULT 0x0100 /* Default state */
248#define M66592_STSR_ADDRESS 0x0200 /* Address state */
249#define M66592_STSR_CONFIG 0x0300 /* Configured state */
250#define M66592_USBADDR 0x007F /* b6-0: USB address */
251
252#define M66592_USBREQ 0x54
253#define M66592_bRequest 0xFF00 /* b15-8: bRequest */
254#define M66592_GET_STATUS 0x0000
255#define M66592_CLEAR_FEATURE 0x0100
256#define M66592_ReqRESERVED 0x0200
257#define M66592_SET_FEATURE 0x0300
258#define M66592_ReqRESERVED1 0x0400
259#define M66592_SET_ADDRESS 0x0500
260#define M66592_GET_DESCRIPTOR 0x0600
261#define M66592_SET_DESCRIPTOR 0x0700
262#define M66592_GET_CONFIGURATION 0x0800
263#define M66592_SET_CONFIGURATION 0x0900
264#define M66592_GET_INTERFACE 0x0A00
265#define M66592_SET_INTERFACE 0x0B00
266#define M66592_SYNCH_FRAME 0x0C00
267#define M66592_bmRequestType 0x00FF /* b7-0: bmRequestType */
268#define M66592_bmRequestTypeDir 0x0080 /* b7 : Data transfer direction */
269#define M66592_HOST_TO_DEVICE 0x0000
270#define M66592_DEVICE_TO_HOST 0x0080
271#define M66592_bmRequestTypeType 0x0060 /* b6-5: Type */
272#define M66592_STANDARD 0x0000
273#define M66592_CLASS 0x0020
274#define M66592_VENDOR 0x0040
275#define M66592_bmRequestTypeRecip 0x001F /* b4-0: Recipient */
276#define M66592_DEVICE 0x0000
277#define M66592_INTERFACE 0x0001
278#define M66592_ENDPOINT 0x0002
279
280#define M66592_USBVAL 0x56
281#define M66592_wValue 0xFFFF /* b15-0: wValue */
282/* Standard Feature Selector */
283#define M66592_ENDPOINT_HALT 0x0000
284#define M66592_DEVICE_REMOTE_WAKEUP 0x0001
285#define M66592_TEST_MODE 0x0002
286/* Descriptor Types */
287#define M66592_DT_TYPE 0xFF00
288#define M66592_GET_DT_TYPE(v) (((v) & DT_TYPE) >> 8)
289#define M66592_DT_DEVICE 0x01
290#define M66592_DT_CONFIGURATION 0x02
291#define M66592_DT_STRING 0x03
292#define M66592_DT_INTERFACE 0x04
293#define M66592_DT_ENDPOINT 0x05
294#define M66592_DT_DEVICE_QUALIFIER 0x06
295#define M66592_DT_OTHER_SPEED_CONFIGURATION 0x07
296#define M66592_DT_INTERFACE_POWER 0x08
297#define M66592_DT_INDEX 0x00FF
298#define M66592_CONF_NUM 0x00FF
299#define M66592_ALT_SET 0x00FF
300
301#define M66592_USBINDEX 0x58
302#define M66592_wIndex 0xFFFF /* b15-0: wIndex */
303#define M66592_TEST_SELECT 0xFF00 /* b15-b8: Test Mode Selectors */
304#define M66592_TEST_J 0x0100 /* Test_J */
305#define M66592_TEST_K 0x0200 /* Test_K */
306#define M66592_TEST_SE0_NAK 0x0300 /* Test_SE0_NAK */
307#define M66592_TEST_PACKET 0x0400 /* Test_Packet */
308#define M66592_TEST_FORCE_ENABLE 0x0500 /* Test_Force_Enable */
309#define M66592_TEST_STSelectors 0x0600 /* Standard test selectors */
310#define M66592_TEST_Reserved 0x4000 /* Reserved */
311#define M66592_TEST_VSTModes 0xC000 /* Vendor-specific test modes */
312#define M66592_EP_DIR 0x0080 /* b7: Endpoint Direction */
313#define M66592_EP_DIR_IN 0x0080
314#define M66592_EP_DIR_OUT 0x0000
315
316#define M66592_USBLENG 0x5A
317#define M66592_wLength 0xFFFF /* b15-0: wLength */
318
319#define M66592_DCPCFG 0x5C
320#define M66592_CNTMD 0x0100 /* b8: Continuous transfer mode select */
321#define M66592_DIR 0x0010 /* b4: Control transfer DIR select */
322
323#define M66592_DCPMAXP 0x5E
324#define M66592_DEVSEL 0xC000 /* b15-14: Device address select */
325#define M66592_DEVICE_0 0x0000 /* Device address 0 */
326#define M66592_DEVICE_1 0x4000 /* Device address 1 */
327#define M66592_DEVICE_2 0x8000 /* Device address 2 */
328#define M66592_DEVICE_3 0xC000 /* Device address 3 */
329#define M66592_MAXP 0x007F /* b6-0: Maxpacket size of default control pipe */
330
331#define M66592_DCPCTR 0x60
332#define M66592_BSTS 0x8000 /* b15: Buffer status */
333#define M66592_SUREQ 0x4000 /* b14: Send USB request */
334#define M66592_SQCLR 0x0100 /* b8: Sequence toggle bit clear */
335#define M66592_SQSET 0x0080 /* b7: Sequence toggle bit set */
336#define M66592_SQMON 0x0040 /* b6: Sequence toggle bit monitor */
337#define M66592_CCPL 0x0004 /* b2: Enable control transfer complete */
338#define M66592_PID 0x0003 /* b1-0: Response PID */
339#define M66592_PID_STALL 0x0002 /* STALL */
340#define M66592_PID_BUF 0x0001 /* BUF */
341#define M66592_PID_NAK 0x0000 /* NAK */
342
343#define M66592_PIPESEL 0x64
344#define M66592_PIPENM 0x0007 /* b2-0: Pipe select */
345#define M66592_PIPE0 0x0000 /* PIPE 0 */
346#define M66592_PIPE1 0x0001 /* PIPE 1 */
347#define M66592_PIPE2 0x0002 /* PIPE 2 */
348#define M66592_PIPE3 0x0003 /* PIPE 3 */
349#define M66592_PIPE4 0x0004 /* PIPE 4 */
350#define M66592_PIPE5 0x0005 /* PIPE 5 */
351#define M66592_PIPE6 0x0006 /* PIPE 6 */
352#define M66592_PIPE7 0x0007 /* PIPE 7 */
353
354#define M66592_PIPECFG 0x66
355#define M66592_TYP 0xC000 /* b15-14: Transfer type */
356#define M66592_ISO 0xC000 /* Isochronous */
357#define M66592_INT 0x8000 /* Interrupt */
358#define M66592_BULK 0x4000 /* Bulk */
359#define M66592_BFRE 0x0400 /* b10: Buffer ready interrupt mode select */
360#define M66592_DBLB 0x0200 /* b9: Double buffer mode select */
361#define M66592_CNTMD 0x0100 /* b8: Continuous transfer mode select */
362#define M66592_SHTNAK 0x0080 /* b7: Transfer end NAK */
363#define M66592_DIR 0x0010 /* b4: Transfer direction select */
364#define M66592_DIR_H_OUT 0x0010 /* HOST OUT */
365#define M66592_DIR_P_IN 0x0010 /* PERI IN */
366#define M66592_DIR_H_IN 0x0000 /* HOST IN */
367#define M66592_DIR_P_OUT 0x0000 /* PERI OUT */
368#define M66592_EPNUM 0x000F /* b3-0: Eendpoint number select */
369#define M66592_EP1 0x0001
370#define M66592_EP2 0x0002
371#define M66592_EP3 0x0003
372#define M66592_EP4 0x0004
373#define M66592_EP5 0x0005
374#define M66592_EP6 0x0006
375#define M66592_EP7 0x0007
376#define M66592_EP8 0x0008
377#define M66592_EP9 0x0009
378#define M66592_EP10 0x000A
379#define M66592_EP11 0x000B
380#define M66592_EP12 0x000C
381#define M66592_EP13 0x000D
382#define M66592_EP14 0x000E
383#define M66592_EP15 0x000F
384
385#define M66592_PIPEBUF 0x68
386#define M66592_BUFSIZE 0x7C00 /* b14-10: Pipe buffer size */
387#define M66592_BUF_SIZE(x) ((((x) / 64) - 1) << 10)
388#define M66592_BUFNMB 0x00FF /* b7-0: Pipe buffer number */
389
390#define M66592_PIPEMAXP 0x6A
391#define M66592_MXPS 0x07FF /* b10-0: Maxpacket size */
392
393#define M66592_PIPEPERI 0x6C
394#define M66592_IFIS 0x1000 /* b12: Isochronous in-buffer flush mode select */
395#define M66592_IITV 0x0007 /* b2-0: Isochronous interval */
396
397#define M66592_PIPE1CTR 0x70
398#define M66592_PIPE2CTR 0x72
399#define M66592_PIPE3CTR 0x74
400#define M66592_PIPE4CTR 0x76
401#define M66592_PIPE5CTR 0x78
402#define M66592_PIPE6CTR 0x7A
403#define M66592_PIPE7CTR 0x7C
404#define M66592_BSTS 0x8000 /* b15: Buffer status */
405#define M66592_INBUFM 0x4000 /* b14: IN buffer monitor (Only for PIPE1 to 5) */
406#define M66592_ACLRM 0x0200 /* b9: Out buffer auto clear mode */
407#define M66592_SQCLR 0x0100 /* b8: Sequence toggle bit clear */
408#define M66592_SQSET 0x0080 /* b7: Sequence toggle bit set */
409#define M66592_SQMON 0x0040 /* b6: Sequence toggle bit monitor */
410#define M66592_PID 0x0003 /* b1-0: Response PID */
411
412#define M66592_INVALID_REG 0x7E
413
414
415#define __iomem
416
417#define get_pipectr_addr(pipenum) (M66592_PIPE1CTR + (pipenum - 1) * 2)
418
419#define M66592_MAX_SAMPLING 10
420
421#define M66592_MAX_NUM_PIPE 8
422#define M66592_MAX_NUM_BULK 3
423#define M66592_MAX_NUM_ISOC 2
424#define M66592_MAX_NUM_INT 2
425
426#define M66592_BASE_PIPENUM_BULK 3
427#define M66592_BASE_PIPENUM_ISOC 1
428#define M66592_BASE_PIPENUM_INT 6
429
430#define M66592_BASE_BUFNUM 6
431#define M66592_MAX_BUFNUM 0x4F
432
433struct m66592_pipe_info {
434 u16 pipe;
435 u16 epnum;
436 u16 maxpacket;
437 u16 type;
438 u16 interval;
439 u16 dir_in;
440};
441
442struct m66592_request {
443 struct usb_request req;
444 struct list_head queue;
445};
446
447struct m66592_ep {
448 struct usb_ep ep;
449 struct m66592 *m66592;
450
451 struct list_head queue;
452 unsigned busy:1;
453 unsigned internal_ccpl:1; /* use only control */
454
455 /* this member can able to after m66592_enable */
456 unsigned use_dma:1;
457 u16 pipenum;
458 u16 type;
459 const struct usb_endpoint_descriptor *desc;
460 /* register address */
461 unsigned long fifoaddr;
462 unsigned long fifosel;
463 unsigned long fifoctr;
464 unsigned long fifotrn;
465 unsigned long pipectr;
466};
467
468struct m66592 {
469 spinlock_t lock;
470 void __iomem *reg;
471
472 struct usb_gadget gadget;
473 struct usb_gadget_driver *driver;
474
475 struct m66592_ep ep[M66592_MAX_NUM_PIPE];
476 struct m66592_ep *pipenum2ep[M66592_MAX_NUM_PIPE];
477 struct m66592_ep *epaddr2ep[16];
478
479 struct usb_request *ep0_req; /* for internal request */
480 u16 *ep0_buf; /* for internal request */
481
482 struct timer_list timer;
483
484 u16 old_vbus;
485 int scount;
486
487 int old_dvsq;
488
489 /* pipe config */
490 int bulk;
491 int interrupt;
492 int isochronous;
493 int num_dma;
494 int bi_bufnum; /* bulk and isochronous's bufnum */
495};
496
497#define gadget_to_m66592(_gadget) container_of(_gadget, struct m66592, gadget)
498#define m66592_to_gadget(m66592) (&m66592->gadget)
499
500#define is_bulk_pipe(pipenum) \
501 ((pipenum >= M66592_BASE_PIPENUM_BULK) && \
502 (pipenum < (M66592_BASE_PIPENUM_BULK + M66592_MAX_NUM_BULK)))
503#define is_interrupt_pipe(pipenum) \
504 ((pipenum >= M66592_BASE_PIPENUM_INT) && \
505 (pipenum < (M66592_BASE_PIPENUM_INT + M66592_MAX_NUM_INT)))
506#define is_isoc_pipe(pipenum) \
507 ((pipenum >= M66592_BASE_PIPENUM_ISOC) && \
508 (pipenum < (M66592_BASE_PIPENUM_ISOC + M66592_MAX_NUM_ISOC)))
509
510#define enable_irq_ready(m66592, pipenum) \
511 enable_pipe_irq(m66592, pipenum, M66592_BRDYENB)
512#define disable_irq_ready(m66592, pipenum) \
513 disable_pipe_irq(m66592, pipenum, M66592_BRDYENB)
514#define enable_irq_empty(m66592, pipenum) \
515 enable_pipe_irq(m66592, pipenum, M66592_BEMPENB)
516#define disable_irq_empty(m66592, pipenum) \
517 disable_pipe_irq(m66592, pipenum, M66592_BEMPENB)
518#define enable_irq_nrdy(m66592, pipenum) \
519 enable_pipe_irq(m66592, pipenum, M66592_NRDYENB)
520#define disable_irq_nrdy(m66592, pipenum) \
521 disable_pipe_irq(m66592, pipenum, M66592_NRDYENB)
522
523/*-------------------------------------------------------------------------*/
524static inline u16 m66592_read(struct m66592 *m66592, unsigned long offset)
525{
526 return inw((unsigned long)m66592->reg + offset);
527}
528
529static inline void m66592_read_fifo(struct m66592 *m66592,
530 unsigned long offset,
531 void *buf, unsigned long len)
532{
533 unsigned long fifoaddr = (unsigned long)m66592->reg + offset;
534
535 len = (len + 1) / 2;
536 insw(fifoaddr, buf, len);
537}
538
539static inline void m66592_write(struct m66592 *m66592, u16 val,
540 unsigned long offset)
541{
542 outw(val, (unsigned long)m66592->reg + offset);
543}
544
545static inline void m66592_write_fifo(struct m66592 *m66592,
546 unsigned long offset,
547 void *buf, unsigned long len)
548{
549 unsigned long fifoaddr = (unsigned long)m66592->reg + offset;
550 unsigned long odd = len & 0x0001;
551
552 len = len / 2;
553 outsw(fifoaddr, buf, len);
554 if (odd) {
555 unsigned char *p = buf + len*2;
556 outb(*p, fifoaddr);
557 }
558}
559
560static inline void m66592_mdfy(struct m66592 *m66592, u16 val, u16 pat,
561 unsigned long offset)
562{
563 u16 tmp;
564 tmp = m66592_read(m66592, offset);
565 tmp = tmp & (~pat);
566 tmp = tmp | val;
567 m66592_write(m66592, tmp, offset);
568}
569
570#define m66592_bclr(m66592, val, offset) \
571 m66592_mdfy(m66592, 0, val, offset)
572#define m66592_bset(m66592, val, offset) \
573 m66592_mdfy(m66592, val, 0, offset)
574
575#endif /* ifndef __M66592_UDC_H__ */
576
577
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-18 16:25:51 -0500