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authorRoland Stigge <stigge@antcom.de>2012-04-29 10:47:05 -0400
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2012-05-01 13:34:55 -0400
commit24a28e4283510dcd58890379a42b8a7d3201d9d3 (patch)
treea73c25e5dc9bcde312084f07f23804c1e8a0ffcf /drivers/usb/gadget
parent8b7c3b68104d687a16dbcc803a18c72148fdfdac (diff)
USB: gadget driver for LPC32xx
This patch adds a USB gadget driver for the LPC32xx ARM SoC. Signed-off-by: Roland Stigge <stigge@antcom.de> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/usb/gadget')
-rw-r--r--drivers/usb/gadget/Kconfig11
-rw-r--r--drivers/usb/gadget/Makefile1
-rw-r--r--drivers/usb/gadget/gadget_chips.h3
-rw-r--r--drivers/usb/gadget/lpc32xx_udc.c3538
4 files changed, 3553 insertions, 0 deletions
diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig
index 2633f7595116..827697271316 100644
--- a/drivers/usb/gadget/Kconfig
+++ b/drivers/usb/gadget/Kconfig
@@ -147,6 +147,17 @@ config USB_AT91
147 dynamically linked module called "at91_udc" and force all 147 dynamically linked module called "at91_udc" and force all
148 gadget drivers to also be dynamically linked. 148 gadget drivers to also be dynamically linked.
149 149
150config USB_LPC32XX
151 tristate "LPC32XX USB Peripheral Controller"
152 depends on ARCH_LPC32XX
153 select USB_ISP1301
154 help
155 This option selects the USB device controller in the LPC32xx SoC.
156
157 Say "y" to link the driver statically, or "m" to build a
158 dynamically linked module called "lpc32xx_udc" and force all
159 gadget drivers to also be dynamically linked.
160
150config USB_ATMEL_USBA 161config USB_ATMEL_USBA
151 tristate "Atmel USBA" 162 tristate "Atmel USBA"
152 select USB_GADGET_DUALSPEED 163 select USB_GADGET_DUALSPEED
diff --git a/drivers/usb/gadget/Makefile b/drivers/usb/gadget/Makefile
index b7f6eefc3927..1565253bfdd2 100644
--- a/drivers/usb/gadget/Makefile
+++ b/drivers/usb/gadget/Makefile
@@ -26,6 +26,7 @@ obj-$(CONFIG_USB_CI13XXX_PCI) += ci13xxx_pci.o
26obj-$(CONFIG_USB_S3C_HSOTG) += s3c-hsotg.o 26obj-$(CONFIG_USB_S3C_HSOTG) += s3c-hsotg.o
27obj-$(CONFIG_USB_S3C_HSUDC) += s3c-hsudc.o 27obj-$(CONFIG_USB_S3C_HSUDC) += s3c-hsudc.o
28obj-$(CONFIG_USB_LANGWELL) += langwell_udc.o 28obj-$(CONFIG_USB_LANGWELL) += langwell_udc.o
29obj-$(CONFIG_USB_LPC32XX) += lpc32xx_udc.o
29obj-$(CONFIG_USB_EG20T) += pch_udc.o 30obj-$(CONFIG_USB_EG20T) += pch_udc.o
30obj-$(CONFIG_USB_MV_UDC) += mv_udc.o 31obj-$(CONFIG_USB_MV_UDC) += mv_udc.o
31mv_udc-y := mv_udc_core.o 32mv_udc-y := mv_udc_core.o
diff --git a/drivers/usb/gadget/gadget_chips.h b/drivers/usb/gadget/gadget_chips.h
index a8855d0b7f3b..b8b3a3411218 100644
--- a/drivers/usb/gadget/gadget_chips.h
+++ b/drivers/usb/gadget/gadget_chips.h
@@ -37,6 +37,7 @@
37#define gadget_is_goku(g) (!strcmp("goku_udc", (g)->name)) 37#define gadget_is_goku(g) (!strcmp("goku_udc", (g)->name))
38#define gadget_is_imx(g) (!strcmp("imx_udc", (g)->name)) 38#define gadget_is_imx(g) (!strcmp("imx_udc", (g)->name))
39#define gadget_is_langwell(g) (!strcmp("langwell_udc", (g)->name)) 39#define gadget_is_langwell(g) (!strcmp("langwell_udc", (g)->name))
40#define gadget_is_lpc32xx(g) (!strcmp("lpc32xx_udc", (g)->name))
40#define gadget_is_m66592(g) (!strcmp("m66592_udc", (g)->name)) 41#define gadget_is_m66592(g) (!strcmp("m66592_udc", (g)->name))
41#define gadget_is_musbhdrc(g) (!strcmp("musb-hdrc", (g)->name)) 42#define gadget_is_musbhdrc(g) (!strcmp("musb-hdrc", (g)->name))
42#define gadget_is_net2272(g) (!strcmp("net2272", (g)->name)) 43#define gadget_is_net2272(g) (!strcmp("net2272", (g)->name))
@@ -118,6 +119,8 @@ static inline int usb_gadget_controller_number(struct usb_gadget *gadget)
118 return 0x31; 119 return 0x31;
119 else if (gadget_is_dwc3(gadget)) 120 else if (gadget_is_dwc3(gadget))
120 return 0x32; 121 return 0x32;
122 else if (gadget_is_lpc32xx(gadget))
123 return 0x33;
121 124
122 return -ENOENT; 125 return -ENOENT;
123} 126}
diff --git a/drivers/usb/gadget/lpc32xx_udc.c b/drivers/usb/gadget/lpc32xx_udc.c
new file mode 100644
index 000000000000..262acfd53e32
--- /dev/null
+++ b/drivers/usb/gadget/lpc32xx_udc.c
@@ -0,0 +1,3538 @@
1/*
2 * USB Gadget driver for LPC32xx
3 *
4 * Authors:
5 * Kevin Wells <kevin.wells@nxp.com>
6 * Mike James
7 * Roland Stigge <stigge@antcom.de>
8 *
9 * Copyright (C) 2006 Philips Semiconductors
10 * Copyright (C) 2009 NXP Semiconductors
11 * Copyright (C) 2012 Roland Stigge
12 *
13 * Note: This driver is based on original work done by Mike James for
14 * the LPC3180.
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2 of the License, or
19 * (at your option) any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software
28 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
29 */
30
31#include <linux/kernel.h>
32#include <linux/module.h>
33#include <linux/platform_device.h>
34#include <linux/delay.h>
35#include <linux/ioport.h>
36#include <linux/slab.h>
37#include <linux/errno.h>
38#include <linux/init.h>
39#include <linux/list.h>
40#include <linux/interrupt.h>
41#include <linux/proc_fs.h>
42#include <linux/clk.h>
43#include <linux/usb/ch9.h>
44#include <linux/usb/gadget.h>
45#include <linux/i2c.h>
46#include <linux/kthread.h>
47#include <linux/freezer.h>
48#include <linux/dma-mapping.h>
49#include <linux/dmapool.h>
50#include <linux/workqueue.h>
51#include <linux/of.h>
52#include <linux/usb/isp1301.h>
53
54#include <asm/byteorder.h>
55#include <mach/hardware.h>
56#include <linux/io.h>
57#include <asm/irq.h>
58#include <asm/system.h>
59
60#include <mach/platform.h>
61#include <mach/irqs.h>
62#include <mach/board.h>
63#ifdef CONFIG_USB_GADGET_DEBUG_FILES
64#include <linux/seq_file.h>
65#endif
66
67/*
68 * USB device configuration structure
69 */
70typedef void (*usc_chg_event)(int);
71struct lpc32xx_usbd_cfg {
72 int vbus_drv_pol; /* 0=active low drive for VBUS via ISP1301 */
73 usc_chg_event conn_chgb; /* Connection change event (optional) */
74 usc_chg_event susp_chgb; /* Suspend/resume event (optional) */
75 usc_chg_event rmwk_chgb; /* Enable/disable remote wakeup */
76};
77
78/*
79 * controller driver data structures
80 */
81
82/* 16 endpoints (not to be confused with 32 hardware endpoints) */
83#define NUM_ENDPOINTS 16
84
85/*
86 * IRQ indices make reading the code a little easier
87 */
88#define IRQ_USB_LP 0
89#define IRQ_USB_HP 1
90#define IRQ_USB_DEVDMA 2
91#define IRQ_USB_ATX 3
92
93#define EP_OUT 0 /* RX (from host) */
94#define EP_IN 1 /* TX (to host) */
95
96/* Returns the interrupt mask for the selected hardware endpoint */
97#define EP_MASK_SEL(ep, dir) (1 << (((ep) * 2) + dir))
98
99#define EP_INT_TYPE 0
100#define EP_ISO_TYPE 1
101#define EP_BLK_TYPE 2
102#define EP_CTL_TYPE 3
103
104/* EP0 states */
105#define WAIT_FOR_SETUP 0 /* Wait for setup packet */
106#define DATA_IN 1 /* Expect dev->host transfer */
107#define DATA_OUT 2 /* Expect host->dev transfer */
108
109/* DD (DMA Descriptor) structure, requires word alignment, this is already
110 * defined in the LPC32XX USB device header file, but this version is slightly
111 * modified to tag some work data with each DMA descriptor. */
112struct lpc32xx_usbd_dd_gad {
113 u32 dd_next_phy;
114 u32 dd_setup;
115 u32 dd_buffer_addr;
116 u32 dd_status;
117 u32 dd_iso_ps_mem_addr;
118 u32 this_dma;
119 u32 iso_status[6]; /* 5 spare */
120 u32 dd_next_v;
121};
122
123/*
124 * Logical endpoint structure
125 */
126struct lpc32xx_ep {
127 struct usb_ep ep;
128 struct list_head queue;
129 struct lpc32xx_udc *udc;
130
131 u32 hwep_num_base; /* Physical hardware EP */
132 u32 hwep_num; /* Maps to hardware endpoint */
133 u32 maxpacket;
134 u32 lep;
135
136 bool is_in;
137 bool req_pending;
138 u32 eptype;
139
140 u32 totalints;
141
142 bool wedge;
143
144 const struct usb_endpoint_descriptor *desc;
145};
146
147/*
148 * Common UDC structure
149 */
150struct lpc32xx_udc {
151 struct usb_gadget gadget;
152 struct usb_gadget_driver *driver;
153 struct platform_device *pdev;
154 struct device *dev;
155 struct dentry *pde;
156 spinlock_t lock;
157 struct i2c_client *isp1301_i2c_client;
158
159 /* Board and device specific */
160 struct lpc32xx_usbd_cfg *board;
161 u32 io_p_start;
162 u32 io_p_size;
163 void __iomem *udp_baseaddr;
164 int udp_irq[4];
165 struct clk *usb_pll_clk;
166 struct clk *usb_slv_clk;
167
168 /* DMA support */
169 u32 *udca_v_base;
170 u32 udca_p_base;
171 struct dma_pool *dd_cache;
172
173 /* Common EP and control data */
174 u32 enabled_devints;
175 u32 enabled_hwepints;
176 u32 dev_status;
177 u32 realized_eps;
178
179 /* VBUS detection, pullup, and power flags */
180 u8 vbus;
181 u8 last_vbus;
182 int pullup;
183 int poweron;
184
185 /* Work queues related to I2C support */
186 struct work_struct pullup_job;
187 struct work_struct vbus_job;
188 struct work_struct power_job;
189
190 /* USB device peripheral - various */
191 struct lpc32xx_ep ep[NUM_ENDPOINTS];
192 bool enabled;
193 bool clocked;
194 bool suspended;
195 bool selfpowered;
196 int ep0state;
197 atomic_t enabled_ep_cnt;
198 wait_queue_head_t ep_disable_wait_queue;
199};
200
201/*
202 * Endpoint request
203 */
204struct lpc32xx_request {
205 struct usb_request req;
206 struct list_head queue;
207 struct lpc32xx_usbd_dd_gad *dd_desc_ptr;
208 bool mapped;
209 bool send_zlp;
210};
211
212static inline struct lpc32xx_udc *to_udc(struct usb_gadget *g)
213{
214 return container_of(g, struct lpc32xx_udc, gadget);
215}
216
217#define ep_dbg(epp, fmt, arg...) \
218 dev_dbg(epp->udc->dev, "%s: " fmt, __func__, ## arg)
219#define ep_err(epp, fmt, arg...) \
220 dev_err(epp->udc->dev, "%s: " fmt, __func__, ## arg)
221#define ep_info(epp, fmt, arg...) \
222 dev_info(epp->udc->dev, "%s: " fmt, __func__, ## arg)
223#define ep_warn(epp, fmt, arg...) \
224 dev_warn(epp->udc->dev, "%s:" fmt, __func__, ## arg)
225
226#define UDCA_BUFF_SIZE (128)
227
228/* TODO: When the clock framework is introduced in LPC32xx, IO_ADDRESS will
229 * be replaced with an inremap()ed pointer, see USB_OTG_CLK_CTRL()
230 * */
231#define USB_CTRL IO_ADDRESS(LPC32XX_CLK_PM_BASE + 0x64)
232#define USB_CLOCK_MASK (AHB_M_CLOCK_ON | OTG_CLOCK_ON | \
233 DEV_CLOCK_ON | I2C_CLOCK_ON)
234
235/* USB_CTRL bit defines */
236#define USB_SLAVE_HCLK_EN (1 << 24)
237#define USB_HOST_NEED_CLK_EN (1 << 21)
238#define USB_DEV_NEED_CLK_EN (1 << 22)
239
240#define USB_OTG_CLK_CTRL(udc) ((udc)->udp_baseaddr + 0xFF4)
241#define USB_OTG_CLK_STAT(udc) ((udc)->udp_baseaddr + 0xFF8)
242
243/* USB_OTG_CLK_CTRL bit defines */
244#define AHB_M_CLOCK_ON (1 << 4)
245#define OTG_CLOCK_ON (1 << 3)
246#define I2C_CLOCK_ON (1 << 2)
247#define DEV_CLOCK_ON (1 << 1)
248#define HOST_CLOCK_ON (1 << 0)
249
250#define USB_OTG_STAT_CONTROL(udc) (udc->udp_baseaddr + 0x110)
251
252/* USB_OTG_STAT_CONTROL bit defines */
253#define TRANSPARENT_I2C_EN (1 << 7)
254#define HOST_EN (1 << 0)
255
256/**********************************************************************
257 * USB device controller register offsets
258 **********************************************************************/
259
260#define USBD_DEVINTST(x) ((x) + 0x200)
261#define USBD_DEVINTEN(x) ((x) + 0x204)
262#define USBD_DEVINTCLR(x) ((x) + 0x208)
263#define USBD_DEVINTSET(x) ((x) + 0x20C)
264#define USBD_CMDCODE(x) ((x) + 0x210)
265#define USBD_CMDDATA(x) ((x) + 0x214)
266#define USBD_RXDATA(x) ((x) + 0x218)
267#define USBD_TXDATA(x) ((x) + 0x21C)
268#define USBD_RXPLEN(x) ((x) + 0x220)
269#define USBD_TXPLEN(x) ((x) + 0x224)
270#define USBD_CTRL(x) ((x) + 0x228)
271#define USBD_DEVINTPRI(x) ((x) + 0x22C)
272#define USBD_EPINTST(x) ((x) + 0x230)
273#define USBD_EPINTEN(x) ((x) + 0x234)
274#define USBD_EPINTCLR(x) ((x) + 0x238)
275#define USBD_EPINTSET(x) ((x) + 0x23C)
276#define USBD_EPINTPRI(x) ((x) + 0x240)
277#define USBD_REEP(x) ((x) + 0x244)
278#define USBD_EPIND(x) ((x) + 0x248)
279#define USBD_EPMAXPSIZE(x) ((x) + 0x24C)
280/* DMA support registers only below */
281/* Set, clear, or get enabled state of the DMA request status. If
282 * enabled, an IN or OUT token will start a DMA transfer for the EP */
283#define USBD_DMARST(x) ((x) + 0x250)
284#define USBD_DMARCLR(x) ((x) + 0x254)
285#define USBD_DMARSET(x) ((x) + 0x258)
286/* DMA UDCA head pointer */
287#define USBD_UDCAH(x) ((x) + 0x280)
288/* EP DMA status, enable, and disable. This is used to specifically
289 * enabled or disable DMA for a specific EP */
290#define USBD_EPDMAST(x) ((x) + 0x284)
291#define USBD_EPDMAEN(x) ((x) + 0x288)
292#define USBD_EPDMADIS(x) ((x) + 0x28C)
293/* DMA master interrupts enable and pending interrupts */
294#define USBD_DMAINTST(x) ((x) + 0x290)
295#define USBD_DMAINTEN(x) ((x) + 0x294)
296/* DMA end of transfer interrupt enable, disable, status */
297#define USBD_EOTINTST(x) ((x) + 0x2A0)
298#define USBD_EOTINTCLR(x) ((x) + 0x2A4)
299#define USBD_EOTINTSET(x) ((x) + 0x2A8)
300/* New DD request interrupt enable, disable, status */
301#define USBD_NDDRTINTST(x) ((x) + 0x2AC)
302#define USBD_NDDRTINTCLR(x) ((x) + 0x2B0)
303#define USBD_NDDRTINTSET(x) ((x) + 0x2B4)
304/* DMA error interrupt enable, disable, status */
305#define USBD_SYSERRTINTST(x) ((x) + 0x2B8)
306#define USBD_SYSERRTINTCLR(x) ((x) + 0x2BC)
307#define USBD_SYSERRTINTSET(x) ((x) + 0x2C0)
308
309/**********************************************************************
310 * USBD_DEVINTST/USBD_DEVINTEN/USBD_DEVINTCLR/USBD_DEVINTSET/
311 * USBD_DEVINTPRI register definitions
312 **********************************************************************/
313#define USBD_ERR_INT (1 << 9)
314#define USBD_EP_RLZED (1 << 8)
315#define USBD_TXENDPKT (1 << 7)
316#define USBD_RXENDPKT (1 << 6)
317#define USBD_CDFULL (1 << 5)
318#define USBD_CCEMPTY (1 << 4)
319#define USBD_DEV_STAT (1 << 3)
320#define USBD_EP_SLOW (1 << 2)
321#define USBD_EP_FAST (1 << 1)
322#define USBD_FRAME (1 << 0)
323
324/**********************************************************************
325 * USBD_EPINTST/USBD_EPINTEN/USBD_EPINTCLR/USBD_EPINTSET/
326 * USBD_EPINTPRI register definitions
327 **********************************************************************/
328/* End point selection macro (RX) */
329#define USBD_RX_EP_SEL(e) (1 << ((e) << 1))
330
331/* End point selection macro (TX) */
332#define USBD_TX_EP_SEL(e) (1 << (((e) << 1) + 1))
333
334/**********************************************************************
335 * USBD_REEP/USBD_DMARST/USBD_DMARCLR/USBD_DMARSET/USBD_EPDMAST/
336 * USBD_EPDMAEN/USBD_EPDMADIS/
337 * USBD_NDDRTINTST/USBD_NDDRTINTCLR/USBD_NDDRTINTSET/
338 * USBD_EOTINTST/USBD_EOTINTCLR/USBD_EOTINTSET/
339 * USBD_SYSERRTINTST/USBD_SYSERRTINTCLR/USBD_SYSERRTINTSET
340 * register definitions
341 **********************************************************************/
342/* Endpoint selection macro */
343#define USBD_EP_SEL(e) (1 << (e))
344
345/**********************************************************************
346 * SBD_DMAINTST/USBD_DMAINTEN
347 **********************************************************************/
348#define USBD_SYS_ERR_INT (1 << 2)
349#define USBD_NEW_DD_INT (1 << 1)
350#define USBD_EOT_INT (1 << 0)
351
352/**********************************************************************
353 * USBD_RXPLEN register definitions
354 **********************************************************************/
355#define USBD_PKT_RDY (1 << 11)
356#define USBD_DV (1 << 10)
357#define USBD_PK_LEN_MASK 0x3FF
358
359/**********************************************************************
360 * USBD_CTRL register definitions
361 **********************************************************************/
362#define USBD_LOG_ENDPOINT(e) ((e) << 2)
363#define USBD_WR_EN (1 << 1)
364#define USBD_RD_EN (1 << 0)
365
366/**********************************************************************
367 * USBD_CMDCODE register definitions
368 **********************************************************************/
369#define USBD_CMD_CODE(c) ((c) << 16)
370#define USBD_CMD_PHASE(p) ((p) << 8)
371
372/**********************************************************************
373 * USBD_DMARST/USBD_DMARCLR/USBD_DMARSET register definitions
374 **********************************************************************/
375#define USBD_DMAEP(e) (1 << (e))
376
377/* DD (DMA Descriptor) structure, requires word alignment */
378struct lpc32xx_usbd_dd {
379 u32 *dd_next;
380 u32 dd_setup;
381 u32 dd_buffer_addr;
382 u32 dd_status;
383 u32 dd_iso_ps_mem_addr;
384};
385
386/* dd_setup bit defines */
387#define DD_SETUP_ATLE_DMA_MODE 0x01
388#define DD_SETUP_NEXT_DD_VALID 0x04
389#define DD_SETUP_ISO_EP 0x10
390#define DD_SETUP_PACKETLEN(n) (((n) & 0x7FF) << 5)
391#define DD_SETUP_DMALENBYTES(n) (((n) & 0xFFFF) << 16)
392
393/* dd_status bit defines */
394#define DD_STATUS_DD_RETIRED 0x01
395#define DD_STATUS_STS_MASK 0x1E
396#define DD_STATUS_STS_NS 0x00 /* Not serviced */
397#define DD_STATUS_STS_BS 0x02 /* Being serviced */
398#define DD_STATUS_STS_NC 0x04 /* Normal completion */
399#define DD_STATUS_STS_DUR 0x06 /* Data underrun (short packet) */
400#define DD_STATUS_STS_DOR 0x08 /* Data overrun */
401#define DD_STATUS_STS_SE 0x12 /* System error */
402#define DD_STATUS_PKT_VAL 0x20 /* Packet valid */
403#define DD_STATUS_LSB_EX 0x40 /* LS byte extracted (ATLE) */
404#define DD_STATUS_MSB_EX 0x80 /* MS byte extracted (ATLE) */
405#define DD_STATUS_MLEN(n) (((n) >> 8) & 0x3F)
406#define DD_STATUS_CURDMACNT(n) (((n) >> 16) & 0xFFFF)
407
408/*
409 *
410 * Protocol engine bits below
411 *
412 */
413/* Device Interrupt Bit Definitions */
414#define FRAME_INT 0x00000001
415#define EP_FAST_INT 0x00000002
416#define EP_SLOW_INT 0x00000004
417#define DEV_STAT_INT 0x00000008
418#define CCEMTY_INT 0x00000010
419#define CDFULL_INT 0x00000020
420#define RxENDPKT_INT 0x00000040
421#define TxENDPKT_INT 0x00000080
422#define EP_RLZED_INT 0x00000100
423#define ERR_INT 0x00000200
424
425/* Rx & Tx Packet Length Definitions */
426#define PKT_LNGTH_MASK 0x000003FF
427#define PKT_DV 0x00000400
428#define PKT_RDY 0x00000800
429
430/* USB Control Definitions */
431#define CTRL_RD_EN 0x00000001
432#define CTRL_WR_EN 0x00000002
433
434/* Command Codes */
435#define CMD_SET_ADDR 0x00D00500
436#define CMD_CFG_DEV 0x00D80500
437#define CMD_SET_MODE 0x00F30500
438#define CMD_RD_FRAME 0x00F50500
439#define DAT_RD_FRAME 0x00F50200
440#define CMD_RD_TEST 0x00FD0500
441#define DAT_RD_TEST 0x00FD0200
442#define CMD_SET_DEV_STAT 0x00FE0500
443#define CMD_GET_DEV_STAT 0x00FE0500
444#define DAT_GET_DEV_STAT 0x00FE0200
445#define CMD_GET_ERR_CODE 0x00FF0500
446#define DAT_GET_ERR_CODE 0x00FF0200
447#define CMD_RD_ERR_STAT 0x00FB0500
448#define DAT_RD_ERR_STAT 0x00FB0200
449#define DAT_WR_BYTE(x) (0x00000100 | ((x) << 16))
450#define CMD_SEL_EP(x) (0x00000500 | ((x) << 16))
451#define DAT_SEL_EP(x) (0x00000200 | ((x) << 16))
452#define CMD_SEL_EP_CLRI(x) (0x00400500 | ((x) << 16))
453#define DAT_SEL_EP_CLRI(x) (0x00400200 | ((x) << 16))
454#define CMD_SET_EP_STAT(x) (0x00400500 | ((x) << 16))
455#define CMD_CLR_BUF 0x00F20500
456#define DAT_CLR_BUF 0x00F20200
457#define CMD_VALID_BUF 0x00FA0500
458
459/* Device Address Register Definitions */
460#define DEV_ADDR_MASK 0x7F
461#define DEV_EN 0x80
462
463/* Device Configure Register Definitions */
464#define CONF_DVICE 0x01
465
466/* Device Mode Register Definitions */
467#define AP_CLK 0x01
468#define INAK_CI 0x02
469#define INAK_CO 0x04
470#define INAK_II 0x08
471#define INAK_IO 0x10
472#define INAK_BI 0x20
473#define INAK_BO 0x40
474
475/* Device Status Register Definitions */
476#define DEV_CON 0x01
477#define DEV_CON_CH 0x02
478#define DEV_SUS 0x04
479#define DEV_SUS_CH 0x08
480#define DEV_RST 0x10
481
482/* Error Code Register Definitions */
483#define ERR_EC_MASK 0x0F
484#define ERR_EA 0x10
485
486/* Error Status Register Definitions */
487#define ERR_PID 0x01
488#define ERR_UEPKT 0x02
489#define ERR_DCRC 0x04
490#define ERR_TIMOUT 0x08
491#define ERR_EOP 0x10
492#define ERR_B_OVRN 0x20
493#define ERR_BTSTF 0x40
494#define ERR_TGL 0x80
495
496/* Endpoint Select Register Definitions */
497#define EP_SEL_F 0x01
498#define EP_SEL_ST 0x02
499#define EP_SEL_STP 0x04
500#define EP_SEL_PO 0x08
501#define EP_SEL_EPN 0x10
502#define EP_SEL_B_1_FULL 0x20
503#define EP_SEL_B_2_FULL 0x40
504
505/* Endpoint Status Register Definitions */
506#define EP_STAT_ST 0x01
507#define EP_STAT_DA 0x20
508#define EP_STAT_RF_MO 0x40
509#define EP_STAT_CND_ST 0x80
510
511/* Clear Buffer Register Definitions */
512#define CLR_BUF_PO 0x01
513
514/* DMA Interrupt Bit Definitions */
515#define EOT_INT 0x01
516#define NDD_REQ_INT 0x02
517#define SYS_ERR_INT 0x04
518
519#define DRIVER_VERSION "1.03"
520static const char driver_name[] = "lpc32xx_udc";
521
522/*
523 *
524 * proc interface support
525 *
526 */
527#ifdef CONFIG_USB_GADGET_DEBUG_FILES
528static char *epnames[] = {"INT", "ISO", "BULK", "CTRL"};
529static const char debug_filename[] = "driver/udc";
530
531static void proc_ep_show(struct seq_file *s, struct lpc32xx_ep *ep)
532{
533 struct lpc32xx_request *req;
534
535 seq_printf(s, "\n");
536 seq_printf(s, "%12s, maxpacket %4d %3s",
537 ep->ep.name, ep->ep.maxpacket,
538 ep->is_in ? "in" : "out");
539 seq_printf(s, " type %4s", epnames[ep->eptype]);
540 seq_printf(s, " ints: %12d", ep->totalints);
541
542 if (list_empty(&ep->queue))
543 seq_printf(s, "\t(queue empty)\n");
544 else {
545 list_for_each_entry(req, &ep->queue, queue) {
546 u32 length = req->req.actual;
547
548 seq_printf(s, "\treq %p len %d/%d buf %p\n",
549 &req->req, length,
550 req->req.length, req->req.buf);
551 }
552 }
553}
554
555static int proc_udc_show(struct seq_file *s, void *unused)
556{
557 struct lpc32xx_udc *udc = s->private;
558 struct lpc32xx_ep *ep;
559 unsigned long flags;
560
561 seq_printf(s, "%s: version %s\n", driver_name, DRIVER_VERSION);
562
563 spin_lock_irqsave(&udc->lock, flags);
564
565 seq_printf(s, "vbus %s, pullup %s, %s powered%s, gadget %s\n\n",
566 udc->vbus ? "present" : "off",
567 udc->enabled ? (udc->vbus ? "active" : "enabled") :
568 "disabled",
569 udc->selfpowered ? "self" : "VBUS",
570 udc->suspended ? ", suspended" : "",
571 udc->driver ? udc->driver->driver.name : "(none)");
572
573 if (udc->enabled && udc->vbus) {
574 proc_ep_show(s, &udc->ep[0]);
575 list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list) {
576 if (ep->desc)
577 proc_ep_show(s, ep);
578 }
579 }
580
581 spin_unlock_irqrestore(&udc->lock, flags);
582
583 return 0;
584}
585
586static int proc_udc_open(struct inode *inode, struct file *file)
587{
588 return single_open(file, proc_udc_show, PDE(inode)->data);
589}
590
591static const struct file_operations proc_ops = {
592 .owner = THIS_MODULE,
593 .open = proc_udc_open,
594 .read = seq_read,
595 .llseek = seq_lseek,
596 .release = single_release,
597};
598
599static void create_debug_file(struct lpc32xx_udc *udc)
600{
601 udc->pde = debugfs_create_file(debug_filename, 0, NULL, udc, &proc_ops);
602}
603
604static void remove_debug_file(struct lpc32xx_udc *udc)
605{
606 if (udc->pde)
607 debugfs_remove(udc->pde);
608}
609
610#else
611static inline void create_debug_file(struct lpc32xx_udc *udc) {}
612static inline void remove_debug_file(struct lpc32xx_udc *udc) {}
613#endif
614
615/* Primary initialization sequence for the ISP1301 transceiver */
616static void isp1301_udc_configure(struct lpc32xx_udc *udc)
617{
618 /* LPC32XX only supports DAT_SE0 USB mode */
619 /* This sequence is important */
620
621 /* Disable transparent UART mode first */
622 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
623 (ISP1301_I2C_MODE_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR),
624 MC1_UART_EN);
625
626 /* Set full speed and SE0 mode */
627 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
628 (ISP1301_I2C_MODE_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR), ~0);
629 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
630 ISP1301_I2C_MODE_CONTROL_1, (MC1_SPEED_REG | MC1_DAT_SE0));
631
632 /*
633 * The PSW_OE enable bit state is reversed in the ISP1301 User's Guide
634 */
635 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
636 (ISP1301_I2C_MODE_CONTROL_2 | ISP1301_I2C_REG_CLEAR_ADDR), ~0);
637 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
638 ISP1301_I2C_MODE_CONTROL_2, (MC2_BI_DI | MC2_SPD_SUSP_CTRL));
639
640 /* Driver VBUS_DRV high or low depending on board setup */
641 if (udc->board->vbus_drv_pol != 0)
642 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
643 ISP1301_I2C_OTG_CONTROL_1, OTG1_VBUS_DRV);
644 else
645 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
646 ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR,
647 OTG1_VBUS_DRV);
648
649 /* Bi-directional mode with suspend control
650 * Enable both pulldowns for now - the pullup will be enable when VBUS
651 * is detected */
652 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
653 (ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR), ~0);
654 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
655 ISP1301_I2C_OTG_CONTROL_1,
656 (0 | OTG1_DM_PULLDOWN | OTG1_DP_PULLDOWN));
657
658 /* Discharge VBUS (just in case) */
659 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
660 ISP1301_I2C_OTG_CONTROL_1, OTG1_VBUS_DISCHRG);
661 msleep(1);
662 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
663 (ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR),
664 OTG1_VBUS_DISCHRG);
665
666 /* Clear and enable VBUS high edge interrupt */
667 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
668 ISP1301_I2C_INTERRUPT_LATCH | ISP1301_I2C_REG_CLEAR_ADDR, ~0);
669 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
670 ISP1301_I2C_INTERRUPT_FALLING | ISP1301_I2C_REG_CLEAR_ADDR, ~0);
671 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
672 ISP1301_I2C_INTERRUPT_FALLING, INT_VBUS_VLD);
673 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
674 ISP1301_I2C_INTERRUPT_RISING | ISP1301_I2C_REG_CLEAR_ADDR, ~0);
675 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
676 ISP1301_I2C_INTERRUPT_RISING, INT_VBUS_VLD);
677
678 /* Enable usb_need_clk clock after transceiver is initialized */
679 writel((readl(USB_CTRL) | (1 << 22)), USB_CTRL);
680
681 dev_info(udc->dev, "ISP1301 Vendor ID : 0x%04x\n",
682 i2c_smbus_read_word_data(udc->isp1301_i2c_client, 0x00));
683 dev_info(udc->dev, "ISP1301 Product ID : 0x%04x\n",
684 i2c_smbus_read_word_data(udc->isp1301_i2c_client, 0x02));
685 dev_info(udc->dev, "ISP1301 Version ID : 0x%04x\n",
686 i2c_smbus_read_word_data(udc->isp1301_i2c_client, 0x14));
687}
688
689/* Enables or disables the USB device pullup via the ISP1301 transceiver */
690static void isp1301_pullup_set(struct lpc32xx_udc *udc)
691{
692 if (udc->pullup)
693 /* Enable pullup for bus signalling */
694 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
695 ISP1301_I2C_OTG_CONTROL_1, OTG1_DP_PULLUP);
696 else
697 /* Enable pullup for bus signalling */
698 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
699 ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR,
700 OTG1_DP_PULLUP);
701}
702
703static void pullup_work(struct work_struct *work)
704{
705 struct lpc32xx_udc *udc =
706 container_of(work, struct lpc32xx_udc, pullup_job);
707
708 isp1301_pullup_set(udc);
709}
710
711static void isp1301_pullup_enable(struct lpc32xx_udc *udc, int en_pullup,
712 int block)
713{
714 if (en_pullup == udc->pullup)
715 return;
716
717 udc->pullup = en_pullup;
718 if (block)
719 isp1301_pullup_set(udc);
720 else
721 /* defer slow i2c pull up setting */
722 schedule_work(&udc->pullup_job);
723}
724
725#ifdef CONFIG_PM
726/* Powers up or down the ISP1301 transceiver */
727static void isp1301_set_powerstate(struct lpc32xx_udc *udc, int enable)
728{
729 if (enable != 0)
730 /* Power up ISP1301 - this ISP1301 will automatically wakeup
731 when VBUS is detected */
732 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
733 ISP1301_I2C_MODE_CONTROL_2 | ISP1301_I2C_REG_CLEAR_ADDR,
734 MC2_GLOBAL_PWR_DN);
735 else
736 /* Power down ISP1301 */
737 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
738 ISP1301_I2C_MODE_CONTROL_2, MC2_GLOBAL_PWR_DN);
739}
740
741static void power_work(struct work_struct *work)
742{
743 struct lpc32xx_udc *udc =
744 container_of(work, struct lpc32xx_udc, power_job);
745
746 isp1301_set_powerstate(udc, udc->poweron);
747}
748#endif
749
750/*
751 *
752 * USB protocol engine command/data read/write helper functions
753 *
754 */
755/* Issues a single command to the USB device state machine */
756static void udc_protocol_cmd_w(struct lpc32xx_udc *udc, u32 cmd)
757{
758 u32 pass = 0;
759 int to;
760
761 /* EP may lock on CLRI if this read isn't done */
762 u32 tmp = readl(USBD_DEVINTST(udc->udp_baseaddr));
763 (void) tmp;
764
765 while (pass == 0) {
766 writel(USBD_CCEMPTY, USBD_DEVINTCLR(udc->udp_baseaddr));
767
768 /* Write command code */
769 writel(cmd, USBD_CMDCODE(udc->udp_baseaddr));
770 to = 10000;
771 while (((readl(USBD_DEVINTST(udc->udp_baseaddr)) &
772 USBD_CCEMPTY) == 0) && (to > 0)) {
773 to--;
774 }
775
776 if (to > 0)
777 pass = 1;
778
779 cpu_relax();
780 }
781}
782
783/* Issues 2 commands (or command and data) to the USB device state machine */
784static inline void udc_protocol_cmd_data_w(struct lpc32xx_udc *udc, u32 cmd,
785 u32 data)
786{
787 udc_protocol_cmd_w(udc, cmd);
788 udc_protocol_cmd_w(udc, data);
789}
790
791/* Issues a single command to the USB device state machine and reads
792 * response data */
793static u32 udc_protocol_cmd_r(struct lpc32xx_udc *udc, u32 cmd)
794{
795 u32 tmp;
796 int to = 1000;
797
798 /* Write a command and read data from the protocol engine */
799 writel((USBD_CDFULL | USBD_CCEMPTY),
800 USBD_DEVINTCLR(udc->udp_baseaddr));
801
802 /* Write command code */
803 udc_protocol_cmd_w(udc, cmd);
804
805 tmp = readl(USBD_DEVINTST(udc->udp_baseaddr));
806 while ((!(readl(USBD_DEVINTST(udc->udp_baseaddr)) & USBD_CDFULL))
807 && (to > 0))
808 to--;
809 if (!to)
810 dev_dbg(udc->dev,
811 "Protocol engine didn't receive response (CDFULL)\n");
812
813 return readl(USBD_CMDDATA(udc->udp_baseaddr));
814}
815
816/*
817 *
818 * USB device interrupt mask support functions
819 *
820 */
821/* Enable one or more USB device interrupts */
822static inline void uda_enable_devint(struct lpc32xx_udc *udc, u32 devmask)
823{
824 udc->enabled_devints |= devmask;
825 writel(udc->enabled_devints, USBD_DEVINTEN(udc->udp_baseaddr));
826}
827
828/* Disable one or more USB device interrupts */
829static inline void uda_disable_devint(struct lpc32xx_udc *udc, u32 mask)
830{
831 udc->enabled_devints &= ~mask;
832 writel(udc->enabled_devints, USBD_DEVINTEN(udc->udp_baseaddr));
833}
834
835/* Clear one or more USB device interrupts */
836static inline void uda_clear_devint(struct lpc32xx_udc *udc, u32 mask)
837{
838 writel(mask, USBD_DEVINTCLR(udc->udp_baseaddr));
839}
840
841/*
842 *
843 * Endpoint interrupt disable/enable functions
844 *
845 */
846/* Enable one or more USB endpoint interrupts */
847static void uda_enable_hwepint(struct lpc32xx_udc *udc, u32 hwep)
848{
849 udc->enabled_hwepints |= (1 << hwep);
850 writel(udc->enabled_hwepints, USBD_EPINTEN(udc->udp_baseaddr));
851}
852
853/* Disable one or more USB endpoint interrupts */
854static void uda_disable_hwepint(struct lpc32xx_udc *udc, u32 hwep)
855{
856 udc->enabled_hwepints &= ~(1 << hwep);
857 writel(udc->enabled_hwepints, USBD_EPINTEN(udc->udp_baseaddr));
858}
859
860/* Clear one or more USB endpoint interrupts */
861static inline void uda_clear_hwepint(struct lpc32xx_udc *udc, u32 hwep)
862{
863 writel((1 << hwep), USBD_EPINTCLR(udc->udp_baseaddr));
864}
865
866/* Enable DMA for the HW channel */
867static inline void udc_ep_dma_enable(struct lpc32xx_udc *udc, u32 hwep)
868{
869 writel((1 << hwep), USBD_EPDMAEN(udc->udp_baseaddr));
870}
871
872/* Disable DMA for the HW channel */
873static inline void udc_ep_dma_disable(struct lpc32xx_udc *udc, u32 hwep)
874{
875 writel((1 << hwep), USBD_EPDMADIS(udc->udp_baseaddr));
876}
877
878/*
879 *
880 * Endpoint realize/unrealize functions
881 *
882 */
883/* Before an endpoint can be used, it needs to be realized
884 * in the USB protocol engine - this realizes the endpoint.
885 * The interrupt (FIFO or DMA) is not enabled with this function */
886static void udc_realize_hwep(struct lpc32xx_udc *udc, u32 hwep,
887 u32 maxpacket)
888{
889 int to = 1000;
890
891 writel(USBD_EP_RLZED, USBD_DEVINTCLR(udc->udp_baseaddr));
892 writel(hwep, USBD_EPIND(udc->udp_baseaddr));
893 udc->realized_eps |= (1 << hwep);
894 writel(udc->realized_eps, USBD_REEP(udc->udp_baseaddr));
895 writel(maxpacket, USBD_EPMAXPSIZE(udc->udp_baseaddr));
896
897 /* Wait until endpoint is realized in hardware */
898 while ((!(readl(USBD_DEVINTST(udc->udp_baseaddr)) &
899 USBD_EP_RLZED)) && (to > 0))
900 to--;
901 if (!to)
902 dev_dbg(udc->dev, "EP not correctly realized in hardware\n");
903
904 writel(USBD_EP_RLZED, USBD_DEVINTCLR(udc->udp_baseaddr));
905}
906
907/* Unrealize an EP */
908static void udc_unrealize_hwep(struct lpc32xx_udc *udc, u32 hwep)
909{
910 udc->realized_eps &= ~(1 << hwep);
911 writel(udc->realized_eps, USBD_REEP(udc->udp_baseaddr));
912}
913
914/*
915 *
916 * Endpoint support functions
917 *
918 */
919/* Select and clear endpoint interrupt */
920static u32 udc_selep_clrint(struct lpc32xx_udc *udc, u32 hwep)
921{
922 udc_protocol_cmd_w(udc, CMD_SEL_EP_CLRI(hwep));
923 return udc_protocol_cmd_r(udc, DAT_SEL_EP_CLRI(hwep));
924}
925
926/* Disables the endpoint in the USB protocol engine */
927static void udc_disable_hwep(struct lpc32xx_udc *udc, u32 hwep)
928{
929 udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(hwep),
930 DAT_WR_BYTE(EP_STAT_DA));
931}
932
933/* Stalls the endpoint - endpoint will return STALL */
934static void udc_stall_hwep(struct lpc32xx_udc *udc, u32 hwep)
935{
936 udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(hwep),
937 DAT_WR_BYTE(EP_STAT_ST));
938}
939
940/* Clear stall or reset endpoint */
941static void udc_clrstall_hwep(struct lpc32xx_udc *udc, u32 hwep)
942{
943 udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(hwep),
944 DAT_WR_BYTE(0));
945}
946
947/* Select an endpoint for endpoint status, clear, validate */
948static void udc_select_hwep(struct lpc32xx_udc *udc, u32 hwep)
949{
950 udc_protocol_cmd_w(udc, CMD_SEL_EP(hwep));
951}
952
953/*
954 *
955 * Endpoint buffer management functions
956 *
957 */
958/* Clear the current endpoint's buffer */
959static void udc_clr_buffer_hwep(struct lpc32xx_udc *udc, u32 hwep)
960{
961 udc_select_hwep(udc, hwep);
962 udc_protocol_cmd_w(udc, CMD_CLR_BUF);
963}
964
965/* Validate the current endpoint's buffer */
966static void udc_val_buffer_hwep(struct lpc32xx_udc *udc, u32 hwep)
967{
968 udc_select_hwep(udc, hwep);
969 udc_protocol_cmd_w(udc, CMD_VALID_BUF);
970}
971
972static inline u32 udc_clearep_getsts(struct lpc32xx_udc *udc, u32 hwep)
973{
974 /* Clear EP interrupt */
975 uda_clear_hwepint(udc, hwep);
976 return udc_selep_clrint(udc, hwep);
977}
978
979/*
980 *
981 * USB EP DMA support
982 *
983 */
984/* Allocate a DMA Descriptor */
985static struct lpc32xx_usbd_dd_gad *udc_dd_alloc(struct lpc32xx_udc *udc)
986{
987 dma_addr_t dma;
988 struct lpc32xx_usbd_dd_gad *dd;
989
990 dd = (struct lpc32xx_usbd_dd_gad *) dma_pool_alloc(
991 udc->dd_cache, (GFP_KERNEL | GFP_DMA), &dma);
992 if (dd)
993 dd->this_dma = dma;
994
995 return dd;
996}
997
998/* Free a DMA Descriptor */
999static void udc_dd_free(struct lpc32xx_udc *udc, struct lpc32xx_usbd_dd_gad *dd)
1000{
1001 dma_pool_free(udc->dd_cache, dd, dd->this_dma);
1002}
1003
1004/*
1005 *
1006 * USB setup and shutdown functions
1007 *
1008 */
1009/* Enables or disables most of the USB system clocks when low power mode is
1010 * needed. Clocks are typically started on a connection event, and disabled
1011 * when a cable is disconnected */
1012#define OTGOFF_CLK_MASK (AHB_M_CLOCK_ON | I2C_CLOCK_ON)
1013static void udc_clk_set(struct lpc32xx_udc *udc, int enable)
1014{
1015 int to = 1000;
1016
1017 if (enable != 0) {
1018 if (udc->clocked)
1019 return;
1020
1021 udc->clocked = 1;
1022
1023 /* 48MHz PLL up */
1024 clk_enable(udc->usb_pll_clk);
1025
1026 /* Enable the USB device clock */
1027 writel(readl(USB_CTRL) | USB_DEV_NEED_CLK_EN,
1028 USB_CTRL);
1029
1030 /* Set to enable all needed USB OTG clocks */
1031 writel(USB_CLOCK_MASK, USB_OTG_CLK_CTRL(udc));
1032
1033 while (((readl(USB_OTG_CLK_STAT(udc)) & USB_CLOCK_MASK) !=
1034 USB_CLOCK_MASK) && (to > 0))
1035 to--;
1036 if (!to)
1037 dev_dbg(udc->dev, "Cannot enable USB OTG clocking\n");
1038 } else {
1039 if (!udc->clocked)
1040 return;
1041
1042 udc->clocked = 0;
1043
1044 /* Never disable the USB_HCLK during normal operation */
1045
1046 /* 48MHz PLL dpwn */
1047 clk_disable(udc->usb_pll_clk);
1048
1049 /* Enable the USB device clock */
1050 writel(readl(USB_CTRL) & ~USB_DEV_NEED_CLK_EN,
1051 USB_CTRL);
1052
1053 /* Set to enable all needed USB OTG clocks */
1054 writel(OTGOFF_CLK_MASK, USB_OTG_CLK_CTRL(udc));
1055
1056 while (((readl(USB_OTG_CLK_STAT(udc)) &
1057 OTGOFF_CLK_MASK) !=
1058 OTGOFF_CLK_MASK) && (to > 0))
1059 to--;
1060 if (!to)
1061 dev_dbg(udc->dev, "Cannot disable USB OTG clocking\n");
1062 }
1063}
1064
1065/* Set/reset USB device address */
1066static void udc_set_address(struct lpc32xx_udc *udc, u32 addr)
1067{
1068 /* Address will be latched at the end of the status phase, or
1069 latched immediately if function is called twice */
1070 udc_protocol_cmd_data_w(udc, CMD_SET_ADDR,
1071 DAT_WR_BYTE(DEV_EN | addr));
1072}
1073
1074/* Setup up a IN request for DMA transfer - this consists of determining the
1075 * list of DMA addresses for the transfer, allocating DMA Descriptors,
1076 * installing the DD into the UDCA, and then enabling the DMA for that EP */
1077static int udc_ep_in_req_dma(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep)
1078{
1079 struct lpc32xx_request *req;
1080 u32 hwep = ep->hwep_num;
1081
1082 ep->req_pending = 1;
1083
1084 /* There will always be a request waiting here */
1085 req = list_entry(ep->queue.next, struct lpc32xx_request, queue);
1086
1087 /* Place the DD Descriptor into the UDCA */
1088 udc->udca_v_base[hwep] = req->dd_desc_ptr->this_dma;
1089
1090 /* Enable DMA and interrupt for the HW EP */
1091 udc_ep_dma_enable(udc, hwep);
1092
1093 /* Clear ZLP if last packet is not of MAXP size */
1094 if (req->req.length % ep->ep.maxpacket)
1095 req->send_zlp = 0;
1096
1097 return 0;
1098}
1099
1100/* Setup up a OUT request for DMA transfer - this consists of determining the
1101 * list of DMA addresses for the transfer, allocating DMA Descriptors,
1102 * installing the DD into the UDCA, and then enabling the DMA for that EP */
1103static int udc_ep_out_req_dma(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep)
1104{
1105 struct lpc32xx_request *req;
1106 u32 hwep = ep->hwep_num;
1107
1108 ep->req_pending = 1;
1109
1110 /* There will always be a request waiting here */
1111 req = list_entry(ep->queue.next, struct lpc32xx_request, queue);
1112
1113 /* Place the DD Descriptor into the UDCA */
1114 udc->udca_v_base[hwep] = req->dd_desc_ptr->this_dma;
1115
1116 /* Enable DMA and interrupt for the HW EP */
1117 udc_ep_dma_enable(udc, hwep);
1118 return 0;
1119}
1120
1121static void udc_disable(struct lpc32xx_udc *udc)
1122{
1123 u32 i;
1124
1125 /* Disable device */
1126 udc_protocol_cmd_data_w(udc, CMD_CFG_DEV, DAT_WR_BYTE(0));
1127 udc_protocol_cmd_data_w(udc, CMD_SET_DEV_STAT, DAT_WR_BYTE(0));
1128
1129 /* Disable all device interrupts (including EP0) */
1130 uda_disable_devint(udc, 0x3FF);
1131
1132 /* Disable and reset all endpoint interrupts */
1133 for (i = 0; i < 32; i++) {
1134 uda_disable_hwepint(udc, i);
1135 uda_clear_hwepint(udc, i);
1136 udc_disable_hwep(udc, i);
1137 udc_unrealize_hwep(udc, i);
1138 udc->udca_v_base[i] = 0;
1139
1140 /* Disable and clear all interrupts and DMA */
1141 udc_ep_dma_disable(udc, i);
1142 writel((1 << i), USBD_EOTINTCLR(udc->udp_baseaddr));
1143 writel((1 << i), USBD_NDDRTINTCLR(udc->udp_baseaddr));
1144 writel((1 << i), USBD_SYSERRTINTCLR(udc->udp_baseaddr));
1145 writel((1 << i), USBD_DMARCLR(udc->udp_baseaddr));
1146 }
1147
1148 /* Disable DMA interrupts */
1149 writel(0, USBD_DMAINTEN(udc->udp_baseaddr));
1150
1151 writel(0, USBD_UDCAH(udc->udp_baseaddr));
1152}
1153
1154static void udc_enable(struct lpc32xx_udc *udc)
1155{
1156 u32 i;
1157 struct lpc32xx_ep *ep = &udc->ep[0];
1158
1159 /* Start with known state */
1160 udc_disable(udc);
1161
1162 /* Enable device */
1163 udc_protocol_cmd_data_w(udc, CMD_SET_DEV_STAT, DAT_WR_BYTE(DEV_CON));
1164
1165 /* EP interrupts on high priority, FRAME interrupt on low priority */
1166 writel(USBD_EP_FAST, USBD_DEVINTPRI(udc->udp_baseaddr));
1167 writel(0xFFFF, USBD_EPINTPRI(udc->udp_baseaddr));
1168
1169 /* Clear any pending device interrupts */
1170 writel(0x3FF, USBD_DEVINTCLR(udc->udp_baseaddr));
1171
1172 /* Setup UDCA - not yet used (DMA) */
1173 writel(udc->udca_p_base, USBD_UDCAH(udc->udp_baseaddr));
1174
1175 /* Only enable EP0 in and out for now, EP0 only works in FIFO mode */
1176 for (i = 0; i <= 1; i++) {
1177 udc_realize_hwep(udc, i, ep->ep.maxpacket);
1178 uda_enable_hwepint(udc, i);
1179 udc_select_hwep(udc, i);
1180 udc_clrstall_hwep(udc, i);
1181 udc_clr_buffer_hwep(udc, i);
1182 }
1183
1184 /* Device interrupt setup */
1185 uda_clear_devint(udc, (USBD_ERR_INT | USBD_DEV_STAT | USBD_EP_SLOW |
1186 USBD_EP_FAST));
1187 uda_enable_devint(udc, (USBD_ERR_INT | USBD_DEV_STAT | USBD_EP_SLOW |
1188 USBD_EP_FAST));
1189
1190 /* Set device address to 0 - called twice to force a latch in the USB
1191 engine without the need of a setup packet status closure */
1192 udc_set_address(udc, 0);
1193 udc_set_address(udc, 0);
1194
1195 /* Enable master DMA interrupts */
1196 writel((USBD_SYS_ERR_INT | USBD_EOT_INT),
1197 USBD_DMAINTEN(udc->udp_baseaddr));
1198
1199 udc->dev_status = 0;
1200}
1201
1202/*
1203 *
1204 * USB device board specific events handled via callbacks
1205 *
1206 */
1207/* Connection change event - notify board function of change */
1208static void uda_power_event(struct lpc32xx_udc *udc, u32 conn)
1209{
1210 /* Just notify of a connection change event (optional) */
1211 if (udc->board->conn_chgb != NULL)
1212 udc->board->conn_chgb(conn);
1213}
1214
1215/* Suspend/resume event - notify board function of change */
1216static void uda_resm_susp_event(struct lpc32xx_udc *udc, u32 conn)
1217{
1218 /* Just notify of a Suspend/resume change event (optional) */
1219 if (udc->board->susp_chgb != NULL)
1220 udc->board->susp_chgb(conn);
1221
1222 if (conn)
1223 udc->suspended = 0;
1224 else
1225 udc->suspended = 1;
1226}
1227
1228/* Remote wakeup enable/disable - notify board function of change */
1229static void uda_remwkp_cgh(struct lpc32xx_udc *udc)
1230{
1231 if (udc->board->rmwk_chgb != NULL)
1232 udc->board->rmwk_chgb(udc->dev_status &
1233 (1 << USB_DEVICE_REMOTE_WAKEUP));
1234}
1235
1236/* Reads data from FIFO, adjusts for alignment and data size */
1237static void udc_pop_fifo(struct lpc32xx_udc *udc, u8 *data, u32 bytes)
1238{
1239 int n, i, bl;
1240 u16 *p16;
1241 u32 *p32, tmp, cbytes;
1242
1243 /* Use optimal data transfer method based on source address and size */
1244 switch (((u32) data) & 0x3) {
1245 case 0: /* 32-bit aligned */
1246 p32 = (u32 *) data;
1247 cbytes = (bytes & ~0x3);
1248
1249 /* Copy 32-bit aligned data first */
1250 for (n = 0; n < cbytes; n += 4)
1251 *p32++ = readl(USBD_RXDATA(udc->udp_baseaddr));
1252
1253 /* Handle any remaining bytes */
1254 bl = bytes - cbytes;
1255 if (bl) {
1256 tmp = readl(USBD_RXDATA(udc->udp_baseaddr));
1257 for (n = 0; n < bl; n++)
1258 data[cbytes + n] = ((tmp >> (n * 8)) & 0xFF);
1259
1260 }
1261 break;
1262
1263 case 1: /* 8-bit aligned */
1264 case 3:
1265 /* Each byte has to be handled independently */
1266 for (n = 0; n < bytes; n += 4) {
1267 tmp = readl(USBD_RXDATA(udc->udp_baseaddr));
1268
1269 bl = bytes - n;
1270 if (bl > 3)
1271 bl = 3;
1272
1273 for (i = 0; i < bl; i++)
1274 data[n + i] = (u8) ((tmp >> (n * 8)) & 0xFF);
1275 }
1276 break;
1277
1278 case 2: /* 16-bit aligned */
1279 p16 = (u16 *) data;
1280 cbytes = (bytes & ~0x3);
1281
1282 /* Copy 32-bit sized objects first with 16-bit alignment */
1283 for (n = 0; n < cbytes; n += 4) {
1284 tmp = readl(USBD_RXDATA(udc->udp_baseaddr));
1285 *p16++ = (u16)(tmp & 0xFFFF);
1286 *p16++ = (u16)((tmp >> 16) & 0xFFFF);
1287 }
1288
1289 /* Handle any remaining bytes */
1290 bl = bytes - cbytes;
1291 if (bl) {
1292 tmp = readl(USBD_RXDATA(udc->udp_baseaddr));
1293 for (n = 0; n < bl; n++)
1294 data[cbytes + n] = ((tmp >> (n * 8)) & 0xFF);
1295 }
1296 break;
1297 }
1298}
1299
1300/* Read data from the FIFO for an endpoint. This function is for endpoints (such
1301 * as EP0) that don't use DMA. This function should only be called if a packet
1302 * is known to be ready to read for the endpoint. Note that the endpoint must
1303 * be selected in the protocol engine prior to this call. */
1304static u32 udc_read_hwep(struct lpc32xx_udc *udc, u32 hwep, u32 *data,
1305 u32 bytes)
1306{
1307 u32 tmpv;
1308 int to = 1000;
1309 u32 tmp, hwrep = ((hwep & 0x1E) << 1) | CTRL_RD_EN;
1310
1311 /* Setup read of endpoint */
1312 writel(hwrep, USBD_CTRL(udc->udp_baseaddr));
1313
1314 /* Wait until packet is ready */
1315 while ((((tmpv = readl(USBD_RXPLEN(udc->udp_baseaddr))) &
1316 PKT_RDY) == 0) && (to > 0))
1317 to--;
1318 if (!to)
1319 dev_dbg(udc->dev, "No packet ready on FIFO EP read\n");
1320
1321 /* Mask out count */
1322 tmp = tmpv & PKT_LNGTH_MASK;
1323 if (bytes < tmp)
1324 tmp = bytes;
1325
1326 if ((tmp > 0) && (data != NULL))
1327 udc_pop_fifo(udc, (u8 *) data, tmp);
1328
1329 writel(((hwep & 0x1E) << 1), USBD_CTRL(udc->udp_baseaddr));
1330
1331 /* Clear the buffer */
1332 udc_clr_buffer_hwep(udc, hwep);
1333
1334 return tmp;
1335}
1336
1337/* Stuffs data into the FIFO, adjusts for alignment and data size */
1338static void udc_stuff_fifo(struct lpc32xx_udc *udc, u8 *data, u32 bytes)
1339{
1340 int n, i, bl;
1341 u16 *p16;
1342 u32 *p32, tmp, cbytes;
1343
1344 /* Use optimal data transfer method based on source address and size */
1345 switch (((u32) data) & 0x3) {
1346 case 0: /* 32-bit aligned */
1347 p32 = (u32 *) data;
1348 cbytes = (bytes & ~0x3);
1349
1350 /* Copy 32-bit aligned data first */
1351 for (n = 0; n < cbytes; n += 4)
1352 writel(*p32++, USBD_TXDATA(udc->udp_baseaddr));
1353
1354 /* Handle any remaining bytes */
1355 bl = bytes - cbytes;
1356 if (bl) {
1357 tmp = 0;
1358 for (n = 0; n < bl; n++)
1359 tmp |= data[cbytes + n] << (n * 8);
1360
1361 writel(tmp, USBD_TXDATA(udc->udp_baseaddr));
1362 }
1363 break;
1364
1365 case 1: /* 8-bit aligned */
1366 case 3:
1367 /* Each byte has to be handled independently */
1368 for (n = 0; n < bytes; n += 4) {
1369 bl = bytes - n;
1370 if (bl > 4)
1371 bl = 4;
1372
1373 tmp = 0;
1374 for (i = 0; i < bl; i++)
1375 tmp |= data[n + i] << (i * 8);
1376
1377 writel(tmp, USBD_TXDATA(udc->udp_baseaddr));
1378 }
1379 break;
1380
1381 case 2: /* 16-bit aligned */
1382 p16 = (u16 *) data;
1383 cbytes = (bytes & ~0x3);
1384
1385 /* Copy 32-bit aligned data first */
1386 for (n = 0; n < cbytes; n += 4) {
1387 tmp = *p16++ & 0xFFFF;
1388 tmp |= (*p16++ & 0xFFFF) << 16;
1389 writel(tmp, USBD_TXDATA(udc->udp_baseaddr));
1390 }
1391
1392 /* Handle any remaining bytes */
1393 bl = bytes - cbytes;
1394 if (bl) {
1395 tmp = 0;
1396 for (n = 0; n < bl; n++)
1397 tmp |= data[cbytes + n] << (n * 8);
1398
1399 writel(tmp, USBD_TXDATA(udc->udp_baseaddr));
1400 }
1401 break;
1402 }
1403}
1404
1405/* Write data to the FIFO for an endpoint. This function is for endpoints (such
1406 * as EP0) that don't use DMA. Note that the endpoint must be selected in the
1407 * protocol engine prior to this call. */
1408static void udc_write_hwep(struct lpc32xx_udc *udc, u32 hwep, u32 *data,
1409 u32 bytes)
1410{
1411 u32 hwwep = ((hwep & 0x1E) << 1) | CTRL_WR_EN;
1412
1413 if ((bytes > 0) && (data == NULL))
1414 return;
1415
1416 /* Setup write of endpoint */
1417 writel(hwwep, USBD_CTRL(udc->udp_baseaddr));
1418
1419 writel(bytes, USBD_TXPLEN(udc->udp_baseaddr));
1420
1421 /* Need at least 1 byte to trigger TX */
1422 if (bytes == 0)
1423 writel(0, USBD_TXDATA(udc->udp_baseaddr));
1424 else
1425 udc_stuff_fifo(udc, (u8 *) data, bytes);
1426
1427 writel(((hwep & 0x1E) << 1), USBD_CTRL(udc->udp_baseaddr));
1428
1429 udc_val_buffer_hwep(udc, hwep);
1430}
1431
1432/* USB device reset - resets USB to a default state with just EP0
1433 enabled */
1434static void uda_usb_reset(struct lpc32xx_udc *udc)
1435{
1436 u32 i = 0;
1437 /* Re-init device controller and EP0 */
1438 udc_enable(udc);
1439 udc->gadget.speed = USB_SPEED_FULL;
1440
1441 for (i = 1; i < NUM_ENDPOINTS; i++) {
1442 struct lpc32xx_ep *ep = &udc->ep[i];
1443 ep->req_pending = 0;
1444 }
1445}
1446
1447/* Send a ZLP on EP0 */
1448static void udc_ep0_send_zlp(struct lpc32xx_udc *udc)
1449{
1450 udc_write_hwep(udc, EP_IN, NULL, 0);
1451}
1452
1453/* Get current frame number */
1454static u16 udc_get_current_frame(struct lpc32xx_udc *udc)
1455{
1456 u16 flo, fhi;
1457
1458 udc_protocol_cmd_w(udc, CMD_RD_FRAME);
1459 flo = (u16) udc_protocol_cmd_r(udc, DAT_RD_FRAME);
1460 fhi = (u16) udc_protocol_cmd_r(udc, DAT_RD_FRAME);
1461
1462 return (fhi << 8) | flo;
1463}
1464
1465/* Set the device as configured - enables all endpoints */
1466static inline void udc_set_device_configured(struct lpc32xx_udc *udc)
1467{
1468 udc_protocol_cmd_data_w(udc, CMD_CFG_DEV, DAT_WR_BYTE(CONF_DVICE));
1469}
1470
1471/* Set the device as unconfigured - disables all endpoints */
1472static inline void udc_set_device_unconfigured(struct lpc32xx_udc *udc)
1473{
1474 udc_protocol_cmd_data_w(udc, CMD_CFG_DEV, DAT_WR_BYTE(0));
1475}
1476
1477/* reinit == restore initial software state */
1478static void udc_reinit(struct lpc32xx_udc *udc)
1479{
1480 u32 i;
1481
1482 INIT_LIST_HEAD(&udc->gadget.ep_list);
1483 INIT_LIST_HEAD(&udc->gadget.ep0->ep_list);
1484
1485 for (i = 0; i < NUM_ENDPOINTS; i++) {
1486 struct lpc32xx_ep *ep = &udc->ep[i];
1487
1488 if (i != 0)
1489 list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
1490 ep->desc = NULL;
1491 ep->ep.maxpacket = ep->maxpacket;
1492 INIT_LIST_HEAD(&ep->queue);
1493 ep->req_pending = 0;
1494 }
1495
1496 udc->ep0state = WAIT_FOR_SETUP;
1497}
1498
1499/* Must be called with lock */
1500static void done(struct lpc32xx_ep *ep, struct lpc32xx_request *req, int status)
1501{
1502 struct lpc32xx_udc *udc = ep->udc;
1503
1504 list_del_init(&req->queue);
1505 if (req->req.status == -EINPROGRESS)
1506 req->req.status = status;
1507 else
1508 status = req->req.status;
1509
1510 if (ep->lep) {
1511 enum dma_data_direction direction;
1512
1513 if (ep->is_in)
1514 direction = DMA_TO_DEVICE;
1515 else
1516 direction = DMA_FROM_DEVICE;
1517
1518 if (req->mapped) {
1519 dma_unmap_single(ep->udc->gadget.dev.parent,
1520 req->req.dma, req->req.length,
1521 direction);
1522 req->req.dma = 0;
1523 req->mapped = 0;
1524 } else
1525 dma_sync_single_for_cpu(ep->udc->gadget.dev.parent,
1526 req->req.dma, req->req.length,
1527 direction);
1528
1529 /* Free DDs */
1530 udc_dd_free(udc, req->dd_desc_ptr);
1531 }
1532
1533 if (status && status != -ESHUTDOWN)
1534 ep_dbg(ep, "%s done %p, status %d\n", ep->ep.name, req, status);
1535
1536 ep->req_pending = 0;
1537 spin_unlock(&udc->lock);
1538 req->req.complete(&ep->ep, &req->req);
1539 spin_lock(&udc->lock);
1540}
1541
1542/* Must be called with lock */
1543static void nuke(struct lpc32xx_ep *ep, int status)
1544{
1545 struct lpc32xx_request *req;
1546
1547 while (!list_empty(&ep->queue)) {
1548 req = list_entry(ep->queue.next, struct lpc32xx_request, queue);
1549 done(ep, req, status);
1550 }
1551
1552 if (ep->desc && status == -ESHUTDOWN) {
1553 uda_disable_hwepint(ep->udc, ep->hwep_num);
1554 udc_disable_hwep(ep->udc, ep->hwep_num);
1555 }
1556}
1557
1558/* IN endpoint 0 transfer */
1559static int udc_ep0_in_req(struct lpc32xx_udc *udc)
1560{
1561 struct lpc32xx_request *req;
1562 struct lpc32xx_ep *ep0 = &udc->ep[0];
1563 u32 tsend, ts = 0;
1564
1565 if (list_empty(&ep0->queue))
1566 /* Nothing to send */
1567 return 0;
1568 else
1569 req = list_entry(ep0->queue.next, struct lpc32xx_request,
1570 queue);
1571
1572 tsend = ts = req->req.length - req->req.actual;
1573 if (ts == 0) {
1574 /* Send a ZLP */
1575 udc_ep0_send_zlp(udc);
1576 done(ep0, req, 0);
1577 return 1;
1578 } else if (ts > ep0->ep.maxpacket)
1579 ts = ep0->ep.maxpacket; /* Just send what we can */
1580
1581 /* Write data to the EP0 FIFO and start transfer */
1582 udc_write_hwep(udc, EP_IN, (req->req.buf + req->req.actual), ts);
1583
1584 /* Increment data pointer */
1585 req->req.actual += ts;
1586
1587 if (tsend >= ep0->ep.maxpacket)
1588 return 0; /* Stay in data transfer state */
1589
1590 /* Transfer request is complete */
1591 udc->ep0state = WAIT_FOR_SETUP;
1592 done(ep0, req, 0);
1593 return 1;
1594}
1595
1596/* OUT endpoint 0 transfer */
1597static int udc_ep0_out_req(struct lpc32xx_udc *udc)
1598{
1599 struct lpc32xx_request *req;
1600 struct lpc32xx_ep *ep0 = &udc->ep[0];
1601 u32 tr, bufferspace;
1602
1603 if (list_empty(&ep0->queue))
1604 return 0;
1605 else
1606 req = list_entry(ep0->queue.next, struct lpc32xx_request,
1607 queue);
1608
1609 if (req) {
1610 if (req->req.length == 0) {
1611 /* Just dequeue request */
1612 done(ep0, req, 0);
1613 udc->ep0state = WAIT_FOR_SETUP;
1614 return 1;
1615 }
1616
1617 /* Get data from FIFO */
1618 bufferspace = req->req.length - req->req.actual;
1619 if (bufferspace > ep0->ep.maxpacket)
1620 bufferspace = ep0->ep.maxpacket;
1621
1622 /* Copy data to buffer */
1623 prefetchw(req->req.buf + req->req.actual);
1624 tr = udc_read_hwep(udc, EP_OUT, req->req.buf + req->req.actual,
1625 bufferspace);
1626 req->req.actual += bufferspace;
1627
1628 if (tr < ep0->ep.maxpacket) {
1629 /* This is the last packet */
1630 done(ep0, req, 0);
1631 udc->ep0state = WAIT_FOR_SETUP;
1632 return 1;
1633 }
1634 }
1635
1636 return 0;
1637}
1638
1639/* Must be called with lock */
1640static void stop_activity(struct lpc32xx_udc *udc)
1641{
1642 struct usb_gadget_driver *driver = udc->driver;
1643 int i;
1644
1645 if (udc->gadget.speed == USB_SPEED_UNKNOWN)
1646 driver = NULL;
1647
1648 udc->gadget.speed = USB_SPEED_UNKNOWN;
1649 udc->suspended = 0;
1650
1651 for (i = 0; i < NUM_ENDPOINTS; i++) {
1652 struct lpc32xx_ep *ep = &udc->ep[i];
1653 nuke(ep, -ESHUTDOWN);
1654 }
1655 if (driver) {
1656 spin_unlock(&udc->lock);
1657 driver->disconnect(&udc->gadget);
1658 spin_lock(&udc->lock);
1659 }
1660
1661 isp1301_pullup_enable(udc, 0, 0);
1662 udc_disable(udc);
1663 udc_reinit(udc);
1664}
1665
1666/*
1667 * Activate or kill host pullup
1668 * Can be called with or without lock
1669 */
1670static void pullup(struct lpc32xx_udc *udc, int is_on)
1671{
1672 if (!udc->clocked)
1673 return;
1674
1675 if (!udc->enabled || !udc->vbus)
1676 is_on = 0;
1677
1678 if (is_on != udc->pullup)
1679 isp1301_pullup_enable(udc, is_on, 0);
1680}
1681
1682/* Must be called without lock */
1683static int lpc32xx_ep_disable(struct usb_ep *_ep)
1684{
1685 struct lpc32xx_ep *ep = container_of(_ep, struct lpc32xx_ep, ep);
1686 struct lpc32xx_udc *udc = ep->udc;
1687 unsigned long flags;
1688
1689 if ((ep->hwep_num_base == 0) || (ep->hwep_num == 0))
1690 return -EINVAL;
1691 spin_lock_irqsave(&udc->lock, flags);
1692
1693 nuke(ep, -ESHUTDOWN);
1694
1695 /* restore the endpoint's pristine config */
1696 ep->desc = NULL;
1697
1698 /* Clear all DMA statuses for this EP */
1699 udc_ep_dma_disable(udc, ep->hwep_num);
1700 writel(1 << ep->hwep_num, USBD_EOTINTCLR(udc->udp_baseaddr));
1701 writel(1 << ep->hwep_num, USBD_NDDRTINTCLR(udc->udp_baseaddr));
1702 writel(1 << ep->hwep_num, USBD_SYSERRTINTCLR(udc->udp_baseaddr));
1703 writel(1 << ep->hwep_num, USBD_DMARCLR(udc->udp_baseaddr));
1704
1705 /* Remove the DD pointer in the UDCA */
1706 udc->udca_v_base[ep->hwep_num] = 0;
1707
1708 /* Disable and reset endpoint and interrupt */
1709 uda_clear_hwepint(udc, ep->hwep_num);
1710 udc_unrealize_hwep(udc, ep->hwep_num);
1711
1712 ep->hwep_num = 0;
1713
1714 spin_unlock_irqrestore(&udc->lock, flags);
1715
1716 atomic_dec(&udc->enabled_ep_cnt);
1717 wake_up(&udc->ep_disable_wait_queue);
1718
1719 return 0;
1720}
1721
1722/* Must be called without lock */
1723static int lpc32xx_ep_enable(struct usb_ep *_ep,
1724 const struct usb_endpoint_descriptor *desc)
1725{
1726 struct lpc32xx_ep *ep = container_of(_ep, struct lpc32xx_ep, ep);
1727 struct lpc32xx_udc *udc = ep->udc;
1728 u16 maxpacket;
1729 u32 tmp;
1730 unsigned long flags;
1731
1732 /* Verify EP data */
1733 if ((!_ep) || (!ep) || (!desc) || (ep->desc) ||
1734 (desc->bDescriptorType != USB_DT_ENDPOINT)) {
1735 dev_dbg(udc->dev, "bad ep or descriptor\n");
1736 return -EINVAL;
1737 }
1738 maxpacket = usb_endpoint_maxp(desc);
1739 if ((maxpacket == 0) || (maxpacket > ep->maxpacket)) {
1740 dev_dbg(udc->dev, "bad ep descriptor's packet size\n");
1741 return -EINVAL;
1742 }
1743
1744 /* Don't touch EP0 */
1745 if (ep->hwep_num_base == 0) {
1746 dev_dbg(udc->dev, "Can't re-enable EP0!!!\n");
1747 return -EINVAL;
1748 }
1749
1750 /* Is driver ready? */
1751 if ((!udc->driver) || (udc->gadget.speed == USB_SPEED_UNKNOWN)) {
1752 dev_dbg(udc->dev, "bogus device state\n");
1753 return -ESHUTDOWN;
1754 }
1755
1756 tmp = desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK;
1757 switch (tmp) {
1758 case USB_ENDPOINT_XFER_CONTROL:
1759 return -EINVAL;
1760
1761 case USB_ENDPOINT_XFER_INT:
1762 if (maxpacket > ep->maxpacket) {
1763 dev_dbg(udc->dev,
1764 "Bad INT endpoint maxpacket %d\n", maxpacket);
1765 return -EINVAL;
1766 }
1767 break;
1768
1769 case USB_ENDPOINT_XFER_BULK:
1770 switch (maxpacket) {
1771 case 8:
1772 case 16:
1773 case 32:
1774 case 64:
1775 break;
1776
1777 default:
1778 dev_dbg(udc->dev,
1779 "Bad BULK endpoint maxpacket %d\n", maxpacket);
1780 return -EINVAL;
1781 }
1782 break;
1783
1784 case USB_ENDPOINT_XFER_ISOC:
1785 break;
1786 }
1787 spin_lock_irqsave(&udc->lock, flags);
1788
1789 /* Initialize endpoint to match the selected descriptor */
1790 ep->is_in = (desc->bEndpointAddress & USB_DIR_IN) != 0;
1791 ep->desc = desc;
1792 ep->ep.maxpacket = maxpacket;
1793
1794 /* Map hardware endpoint from base and direction */
1795 if (ep->is_in)
1796 /* IN endpoints are offset 1 from the OUT endpoint */
1797 ep->hwep_num = ep->hwep_num_base + EP_IN;
1798 else
1799 ep->hwep_num = ep->hwep_num_base;
1800
1801 ep_dbg(ep, "EP enabled: %s, HW:%d, MP:%d IN:%d\n", ep->ep.name,
1802 ep->hwep_num, maxpacket, (ep->is_in == 1));
1803
1804 /* Realize the endpoint, interrupt is enabled later when
1805 * buffers are queued, IN EPs will NAK until buffers are ready */
1806 udc_realize_hwep(udc, ep->hwep_num, ep->ep.maxpacket);
1807 udc_clr_buffer_hwep(udc, ep->hwep_num);
1808 uda_disable_hwepint(udc, ep->hwep_num);
1809 udc_clrstall_hwep(udc, ep->hwep_num);
1810
1811 /* Clear all DMA statuses for this EP */
1812 udc_ep_dma_disable(udc, ep->hwep_num);
1813 writel(1 << ep->hwep_num, USBD_EOTINTCLR(udc->udp_baseaddr));
1814 writel(1 << ep->hwep_num, USBD_NDDRTINTCLR(udc->udp_baseaddr));
1815 writel(1 << ep->hwep_num, USBD_SYSERRTINTCLR(udc->udp_baseaddr));
1816 writel(1 << ep->hwep_num, USBD_DMARCLR(udc->udp_baseaddr));
1817
1818 spin_unlock_irqrestore(&udc->lock, flags);
1819
1820 atomic_inc(&udc->enabled_ep_cnt);
1821 return 0;
1822}
1823
1824/*
1825 * Allocate a USB request list
1826 * Can be called with or without lock
1827 */
1828static struct usb_request *lpc32xx_ep_alloc_request(struct usb_ep *_ep,
1829 gfp_t gfp_flags)
1830{
1831 struct lpc32xx_request *req;
1832
1833 req = kzalloc(sizeof(struct lpc32xx_request), gfp_flags);
1834 if (!req)
1835 return NULL;
1836
1837 INIT_LIST_HEAD(&req->queue);
1838 return &req->req;
1839}
1840
1841/*
1842 * De-allocate a USB request list
1843 * Can be called with or without lock
1844 */
1845static void lpc32xx_ep_free_request(struct usb_ep *_ep,
1846 struct usb_request *_req)
1847{
1848 struct lpc32xx_request *req;
1849
1850 req = container_of(_req, struct lpc32xx_request, req);
1851 BUG_ON(!list_empty(&req->queue));
1852 kfree(req);
1853}
1854
1855/* Must be called without lock */
1856static int lpc32xx_ep_queue(struct usb_ep *_ep,
1857 struct usb_request *_req, gfp_t gfp_flags)
1858{
1859 struct lpc32xx_request *req;
1860 struct lpc32xx_ep *ep;
1861 struct lpc32xx_udc *udc;
1862 unsigned long flags;
1863 int status = 0;
1864
1865 req = container_of(_req, struct lpc32xx_request, req);
1866 ep = container_of(_ep, struct lpc32xx_ep, ep);
1867
1868 if (!_req || !_req->complete || !_req->buf ||
1869 !list_empty(&req->queue))
1870 return -EINVAL;
1871
1872 udc = ep->udc;
1873
1874 if (!_ep || (!ep->desc && ep->hwep_num_base != 0)) {
1875 dev_dbg(udc->dev, "invalid ep\n");
1876 return -EINVAL;
1877 }
1878
1879
1880 if ((!udc) || (!udc->driver) ||
1881 (udc->gadget.speed == USB_SPEED_UNKNOWN)) {
1882 dev_dbg(udc->dev, "invalid device\n");
1883 return -EINVAL;
1884 }
1885
1886 if (ep->lep) {
1887 enum dma_data_direction direction;
1888 struct lpc32xx_usbd_dd_gad *dd;
1889
1890 /* Map DMA pointer */
1891 if (ep->is_in)
1892 direction = DMA_TO_DEVICE;
1893 else
1894 direction = DMA_FROM_DEVICE;
1895
1896 if (req->req.dma == 0) {
1897 req->req.dma = dma_map_single(
1898 ep->udc->gadget.dev.parent,
1899 req->req.buf, req->req.length, direction);
1900 req->mapped = 1;
1901 } else {
1902 dma_sync_single_for_device(
1903 ep->udc->gadget.dev.parent, req->req.dma,
1904 req->req.length, direction);
1905 req->mapped = 0;
1906 }
1907
1908 /* For the request, build a list of DDs */
1909 dd = udc_dd_alloc(udc);
1910 if (!dd) {
1911 /* Error allocating DD */
1912 return -ENOMEM;
1913 }
1914 req->dd_desc_ptr = dd;
1915
1916 /* Setup the DMA descriptor */
1917 dd->dd_next_phy = dd->dd_next_v = 0;
1918 dd->dd_buffer_addr = req->req.dma;
1919 dd->dd_status = 0;
1920
1921 /* Special handling for ISO EPs */
1922 if (ep->eptype == EP_ISO_TYPE) {
1923 dd->dd_setup = DD_SETUP_ISO_EP |
1924 DD_SETUP_PACKETLEN(0) |
1925 DD_SETUP_DMALENBYTES(1);
1926 dd->dd_iso_ps_mem_addr = dd->this_dma + 24;
1927 if (ep->is_in)
1928 dd->iso_status[0] = req->req.length;
1929 else
1930 dd->iso_status[0] = 0;
1931 } else
1932 dd->dd_setup = DD_SETUP_PACKETLEN(ep->ep.maxpacket) |
1933 DD_SETUP_DMALENBYTES(req->req.length);
1934 }
1935
1936 ep_dbg(ep, "%s queue req %p len %d buf %p (in=%d) z=%d\n", _ep->name,
1937 _req, _req->length, _req->buf, ep->is_in, _req->zero);
1938
1939 spin_lock_irqsave(&udc->lock, flags);
1940
1941 _req->status = -EINPROGRESS;
1942 _req->actual = 0;
1943 req->send_zlp = _req->zero;
1944
1945 /* Kickstart empty queues */
1946 if (list_empty(&ep->queue)) {
1947 list_add_tail(&req->queue, &ep->queue);
1948
1949 if (ep->hwep_num_base == 0) {
1950 /* Handle expected data direction */
1951 if (ep->is_in) {
1952 /* IN packet to host */
1953 udc->ep0state = DATA_IN;
1954 status = udc_ep0_in_req(udc);
1955 } else {
1956 /* OUT packet from host */
1957 udc->ep0state = DATA_OUT;
1958 status = udc_ep0_out_req(udc);
1959 }
1960 } else if (ep->is_in) {
1961 /* IN packet to host and kick off transfer */
1962 if (!ep->req_pending)
1963 udc_ep_in_req_dma(udc, ep);
1964 } else
1965 /* OUT packet from host and kick off list */
1966 if (!ep->req_pending)
1967 udc_ep_out_req_dma(udc, ep);
1968 } else
1969 list_add_tail(&req->queue, &ep->queue);
1970
1971 spin_unlock_irqrestore(&udc->lock, flags);
1972
1973 return (status < 0) ? status : 0;
1974}
1975
1976/* Must be called without lock */
1977static int lpc32xx_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
1978{
1979 struct lpc32xx_ep *ep;
1980 struct lpc32xx_request *req;
1981 unsigned long flags;
1982
1983 ep = container_of(_ep, struct lpc32xx_ep, ep);
1984 if (!_ep || ep->hwep_num_base == 0)
1985 return -EINVAL;
1986
1987 spin_lock_irqsave(&ep->udc->lock, flags);
1988
1989 /* make sure it's actually queued on this endpoint */
1990 list_for_each_entry(req, &ep->queue, queue) {
1991 if (&req->req == _req)
1992 break;
1993 }
1994 if (&req->req != _req) {
1995 spin_unlock_irqrestore(&ep->udc->lock, flags);
1996 return -EINVAL;
1997 }
1998
1999 done(ep, req, -ECONNRESET);
2000
2001 spin_unlock_irqrestore(&ep->udc->lock, flags);
2002
2003 return 0;
2004}
2005
2006/* Must be called without lock */
2007static int lpc32xx_ep_set_halt(struct usb_ep *_ep, int value)
2008{
2009 struct lpc32xx_ep *ep = container_of(_ep, struct lpc32xx_ep, ep);
2010 struct lpc32xx_udc *udc = ep->udc;
2011 unsigned long flags;
2012
2013 if ((!ep) || (ep->desc == NULL) || (ep->hwep_num <= 1))
2014 return -EINVAL;
2015
2016 /* Don't halt an IN EP */
2017 if (ep->is_in)
2018 return -EAGAIN;
2019
2020 spin_lock_irqsave(&udc->lock, flags);
2021
2022 if (value == 1) {
2023 /* stall */
2024 udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(ep->hwep_num),
2025 DAT_WR_BYTE(EP_STAT_ST));
2026 } else {
2027 /* End stall */
2028 ep->wedge = 0;
2029 udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(ep->hwep_num),
2030 DAT_WR_BYTE(0));
2031 }
2032
2033 spin_unlock_irqrestore(&udc->lock, flags);
2034
2035 return 0;
2036}
2037
2038/* set the halt feature and ignores clear requests */
2039static int lpc32xx_ep_set_wedge(struct usb_ep *_ep)
2040{
2041 struct lpc32xx_ep *ep = container_of(_ep, struct lpc32xx_ep, ep);
2042
2043 if (!_ep || !ep->udc)
2044 return -EINVAL;
2045
2046 ep->wedge = 1;
2047
2048 return usb_ep_set_halt(_ep);
2049}
2050
2051static const struct usb_ep_ops lpc32xx_ep_ops = {
2052 .enable = lpc32xx_ep_enable,
2053 .disable = lpc32xx_ep_disable,
2054 .alloc_request = lpc32xx_ep_alloc_request,
2055 .free_request = lpc32xx_ep_free_request,
2056 .queue = lpc32xx_ep_queue,
2057 .dequeue = lpc32xx_ep_dequeue,
2058 .set_halt = lpc32xx_ep_set_halt,
2059 .set_wedge = lpc32xx_ep_set_wedge,
2060};
2061
2062/* Send a ZLP on a non-0 IN EP */
2063void udc_send_in_zlp(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep)
2064{
2065 /* Clear EP status */
2066 udc_clearep_getsts(udc, ep->hwep_num);
2067
2068 /* Send ZLP via FIFO mechanism */
2069 udc_write_hwep(udc, ep->hwep_num, NULL, 0);
2070}
2071
2072/*
2073 * Handle EP completion for ZLP
2074 * This function will only be called when a delayed ZLP needs to be sent out
2075 * after a DMA transfer has filled both buffers.
2076 */
2077void udc_handle_eps(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep)
2078{
2079 u32 epstatus;
2080 struct lpc32xx_request *req;
2081
2082 if (ep->hwep_num <= 0)
2083 return;
2084
2085 uda_clear_hwepint(udc, ep->hwep_num);
2086
2087 /* If this interrupt isn't enabled, return now */
2088 if (!(udc->enabled_hwepints & (1 << ep->hwep_num)))
2089 return;
2090
2091 /* Get endpoint status */
2092 epstatus = udc_clearep_getsts(udc, ep->hwep_num);
2093
2094 /*
2095 * This should never happen, but protect against writing to the
2096 * buffer when full.
2097 */
2098 if (epstatus & EP_SEL_F)
2099 return;
2100
2101 if (ep->is_in) {
2102 udc_send_in_zlp(udc, ep);
2103 uda_disable_hwepint(udc, ep->hwep_num);
2104 } else
2105 return;
2106
2107 /* If there isn't a request waiting, something went wrong */
2108 req = list_entry(ep->queue.next, struct lpc32xx_request, queue);
2109 if (req) {
2110 done(ep, req, 0);
2111
2112 /* Start another request if ready */
2113 if (!list_empty(&ep->queue)) {
2114 if (ep->is_in)
2115 udc_ep_in_req_dma(udc, ep);
2116 else
2117 udc_ep_out_req_dma(udc, ep);
2118 } else
2119 ep->req_pending = 0;
2120 }
2121}
2122
2123
2124/* DMA end of transfer completion */
2125static void udc_handle_dma_ep(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep)
2126{
2127 u32 status, epstatus;
2128 struct lpc32xx_request *req;
2129 struct lpc32xx_usbd_dd_gad *dd;
2130
2131#ifdef CONFIG_USB_GADGET_DEBUG_FILES
2132 ep->totalints++;
2133#endif
2134
2135 req = list_entry(ep->queue.next, struct lpc32xx_request, queue);
2136 if (!req) {
2137 ep_err(ep, "DMA interrupt on no req!\n");
2138 return;
2139 }
2140 dd = req->dd_desc_ptr;
2141
2142 /* DMA descriptor should always be retired for this call */
2143 if (!(dd->dd_status & DD_STATUS_DD_RETIRED))
2144 ep_warn(ep, "DMA descriptor did not retire\n");
2145
2146 /* Disable DMA */
2147 udc_ep_dma_disable(udc, ep->hwep_num);
2148 writel((1 << ep->hwep_num), USBD_EOTINTCLR(udc->udp_baseaddr));
2149 writel((1 << ep->hwep_num), USBD_NDDRTINTCLR(udc->udp_baseaddr));
2150
2151 /* System error? */
2152 if (readl(USBD_SYSERRTINTST(udc->udp_baseaddr)) &
2153 (1 << ep->hwep_num)) {
2154 writel((1 << ep->hwep_num),
2155 USBD_SYSERRTINTCLR(udc->udp_baseaddr));
2156 ep_err(ep, "AHB critical error!\n");
2157 ep->req_pending = 0;
2158
2159 /* The error could have occurred on a packet of a multipacket
2160 * transfer, so recovering the transfer is not possible. Close
2161 * the request with an error */
2162 done(ep, req, -ECONNABORTED);
2163 return;
2164 }
2165
2166 /* Handle the current DD's status */
2167 status = dd->dd_status;
2168 switch (status & DD_STATUS_STS_MASK) {
2169 case DD_STATUS_STS_NS:
2170 /* DD not serviced? This shouldn't happen! */
2171 ep->req_pending = 0;
2172 ep_err(ep, "DMA critical EP error: DD not serviced (0x%x)!\n",
2173 status);
2174
2175 done(ep, req, -ECONNABORTED);
2176 return;
2177
2178 case DD_STATUS_STS_BS:
2179 /* Interrupt only fires on EOT - This shouldn't happen! */
2180 ep->req_pending = 0;
2181 ep_err(ep, "DMA critical EP error: EOT prior to service completion (0x%x)!\n",
2182 status);
2183 done(ep, req, -ECONNABORTED);
2184 return;
2185
2186 case DD_STATUS_STS_NC:
2187 case DD_STATUS_STS_DUR:
2188 /* Really just a short packet, not an underrun */
2189 /* This is a good status and what we expect */
2190 break;
2191
2192 default:
2193 /* Data overrun, system error, or unknown */
2194 ep->req_pending = 0;
2195 ep_err(ep, "DMA critical EP error: System error (0x%x)!\n",
2196 status);
2197 done(ep, req, -ECONNABORTED);
2198 return;
2199 }
2200
2201 /* ISO endpoints are handled differently */
2202 if (ep->eptype == EP_ISO_TYPE) {
2203 if (ep->is_in)
2204 req->req.actual = req->req.length;
2205 else
2206 req->req.actual = dd->iso_status[0] & 0xFFFF;
2207 } else
2208 req->req.actual += DD_STATUS_CURDMACNT(status);
2209
2210 /* Send a ZLP if necessary. This will be done for non-int
2211 * packets which have a size that is a divisor of MAXP */
2212 if (req->send_zlp) {
2213 /*
2214 * If at least 1 buffer is available, send the ZLP now.
2215 * Otherwise, the ZLP send needs to be deferred until a
2216 * buffer is available.
2217 */
2218 if (udc_clearep_getsts(udc, ep->hwep_num) & EP_SEL_F) {
2219 udc_clearep_getsts(udc, ep->hwep_num);
2220 uda_enable_hwepint(udc, ep->hwep_num);
2221 epstatus = udc_clearep_getsts(udc, ep->hwep_num);
2222
2223 /* Let the EP interrupt handle the ZLP */
2224 return;
2225 } else
2226 udc_send_in_zlp(udc, ep);
2227 }
2228
2229 /* Transfer request is complete */
2230 done(ep, req, 0);
2231
2232 /* Start another request if ready */
2233 udc_clearep_getsts(udc, ep->hwep_num);
2234 if (!list_empty((&ep->queue))) {
2235 if (ep->is_in)
2236 udc_ep_in_req_dma(udc, ep);
2237 else
2238 udc_ep_out_req_dma(udc, ep);
2239 } else
2240 ep->req_pending = 0;
2241
2242}
2243
2244/*
2245 *
2246 * Endpoint 0 functions
2247 *
2248 */
2249static void udc_handle_dev(struct lpc32xx_udc *udc)
2250{
2251 u32 tmp;
2252
2253 udc_protocol_cmd_w(udc, CMD_GET_DEV_STAT);
2254 tmp = udc_protocol_cmd_r(udc, DAT_GET_DEV_STAT);
2255
2256 if (tmp & DEV_RST)
2257 uda_usb_reset(udc);
2258 else if (tmp & DEV_CON_CH)
2259 uda_power_event(udc, (tmp & DEV_CON));
2260 else if (tmp & DEV_SUS_CH) {
2261 if (tmp & DEV_SUS) {
2262 if (udc->vbus == 0)
2263 stop_activity(udc);
2264 else if ((udc->gadget.speed != USB_SPEED_UNKNOWN) &&
2265 udc->driver) {
2266 /* Power down transceiver */
2267 udc->poweron = 0;
2268 schedule_work(&udc->pullup_job);
2269 uda_resm_susp_event(udc, 1);
2270 }
2271 } else if ((udc->gadget.speed != USB_SPEED_UNKNOWN) &&
2272 udc->driver && udc->vbus) {
2273 uda_resm_susp_event(udc, 0);
2274 /* Power up transceiver */
2275 udc->poweron = 1;
2276 schedule_work(&udc->pullup_job);
2277 }
2278 }
2279}
2280
2281static int udc_get_status(struct lpc32xx_udc *udc, u16 reqtype, u16 wIndex)
2282{
2283 struct lpc32xx_ep *ep;
2284 u32 ep0buff = 0, tmp;
2285
2286 switch (reqtype & USB_RECIP_MASK) {
2287 case USB_RECIP_INTERFACE:
2288 break; /* Not supported */
2289
2290 case USB_RECIP_DEVICE:
2291 ep0buff = (udc->selfpowered << USB_DEVICE_SELF_POWERED);
2292 if (udc->dev_status & (1 << USB_DEVICE_REMOTE_WAKEUP))
2293 ep0buff |= (1 << USB_DEVICE_REMOTE_WAKEUP);
2294 break;
2295
2296 case USB_RECIP_ENDPOINT:
2297 tmp = wIndex & USB_ENDPOINT_NUMBER_MASK;
2298 ep = &udc->ep[tmp];
2299 if ((tmp == 0) || (tmp >= NUM_ENDPOINTS) || (tmp && !ep->desc))
2300 return -EOPNOTSUPP;
2301
2302 if (wIndex & USB_DIR_IN) {
2303 if (!ep->is_in)
2304 return -EOPNOTSUPP; /* Something's wrong */
2305 } else if (ep->is_in)
2306 return -EOPNOTSUPP; /* Not an IN endpoint */
2307
2308 /* Get status of the endpoint */
2309 udc_protocol_cmd_w(udc, CMD_SEL_EP(ep->hwep_num));
2310 tmp = udc_protocol_cmd_r(udc, DAT_SEL_EP(ep->hwep_num));
2311
2312 if (tmp & EP_SEL_ST)
2313 ep0buff = (1 << USB_ENDPOINT_HALT);
2314 else
2315 ep0buff = 0;
2316 break;
2317
2318 default:
2319 break;
2320 }
2321
2322 /* Return data */
2323 udc_write_hwep(udc, EP_IN, &ep0buff, 2);
2324
2325 return 0;
2326}
2327
2328static void udc_handle_ep0_setup(struct lpc32xx_udc *udc)
2329{
2330 struct lpc32xx_ep *ep, *ep0 = &udc->ep[0];
2331 struct usb_ctrlrequest ctrlpkt;
2332 int i, bytes;
2333 u16 wIndex, wValue, wLength, reqtype, req, tmp;
2334
2335 /* Nuke previous transfers */
2336 nuke(ep0, -EPROTO);
2337
2338 /* Get setup packet */
2339 bytes = udc_read_hwep(udc, EP_OUT, (u32 *) &ctrlpkt, 8);
2340 if (bytes != 8) {
2341 ep_warn(ep0, "Incorrectly sized setup packet (s/b 8, is %d)!\n",
2342 bytes);
2343 return;
2344 }
2345
2346 /* Native endianness */
2347 wIndex = le16_to_cpu(ctrlpkt.wIndex);
2348 wValue = le16_to_cpu(ctrlpkt.wValue);
2349 wLength = le16_to_cpu(ctrlpkt.wLength);
2350 reqtype = le16_to_cpu(ctrlpkt.bRequestType);
2351
2352 /* Set direction of EP0 */
2353 if (likely(reqtype & USB_DIR_IN))
2354 ep0->is_in = 1;
2355 else
2356 ep0->is_in = 0;
2357
2358 /* Handle SETUP packet */
2359 req = le16_to_cpu(ctrlpkt.bRequest);
2360 switch (req) {
2361 case USB_REQ_CLEAR_FEATURE:
2362 case USB_REQ_SET_FEATURE:
2363 switch (reqtype) {
2364 case (USB_TYPE_STANDARD | USB_RECIP_DEVICE):
2365 if (wValue != USB_DEVICE_REMOTE_WAKEUP)
2366 goto stall; /* Nothing else handled */
2367
2368 /* Tell board about event */
2369 if (req == USB_REQ_CLEAR_FEATURE)
2370 udc->dev_status &=
2371 ~(1 << USB_DEVICE_REMOTE_WAKEUP);
2372 else
2373 udc->dev_status |=
2374 (1 << USB_DEVICE_REMOTE_WAKEUP);
2375 uda_remwkp_cgh(udc);
2376 goto zlp_send;
2377
2378 case (USB_TYPE_STANDARD | USB_RECIP_ENDPOINT):
2379 tmp = wIndex & USB_ENDPOINT_NUMBER_MASK;
2380 if ((wValue != USB_ENDPOINT_HALT) ||
2381 (tmp >= NUM_ENDPOINTS))
2382 break;
2383
2384 /* Find hardware endpoint from logical endpoint */
2385 ep = &udc->ep[tmp];
2386 tmp = ep->hwep_num;
2387 if (tmp == 0)
2388 break;
2389
2390 if (req == USB_REQ_SET_FEATURE)
2391 udc_stall_hwep(udc, tmp);
2392 else if (!ep->wedge)
2393 udc_clrstall_hwep(udc, tmp);
2394
2395 goto zlp_send;
2396
2397 default:
2398 break;
2399 }
2400
2401
2402 case USB_REQ_SET_ADDRESS:
2403 if (reqtype == (USB_TYPE_STANDARD | USB_RECIP_DEVICE)) {
2404 udc_set_address(udc, wValue);
2405 goto zlp_send;
2406 }
2407 break;
2408
2409 case USB_REQ_GET_STATUS:
2410 udc_get_status(udc, reqtype, wIndex);
2411 return;
2412
2413 default:
2414 break; /* Let GadgetFS handle the descriptor instead */
2415 }
2416
2417 if (likely(udc->driver)) {
2418 /* device-2-host (IN) or no data setup command, process
2419 * immediately */
2420 spin_unlock(&udc->lock);
2421 i = udc->driver->setup(&udc->gadget, &ctrlpkt);
2422
2423 spin_lock(&udc->lock);
2424 if (req == USB_REQ_SET_CONFIGURATION) {
2425 /* Configuration is set after endpoints are realized */
2426 if (wValue) {
2427 /* Set configuration */
2428 udc_set_device_configured(udc);
2429
2430 udc_protocol_cmd_data_w(udc, CMD_SET_MODE,
2431 DAT_WR_BYTE(AP_CLK |
2432 INAK_BI | INAK_II));
2433 } else {
2434 /* Clear configuration */
2435 udc_set_device_unconfigured(udc);
2436
2437 /* Disable NAK interrupts */
2438 udc_protocol_cmd_data_w(udc, CMD_SET_MODE,
2439 DAT_WR_BYTE(AP_CLK));
2440 }
2441 }
2442
2443 if (i < 0) {
2444 /* setup processing failed, force stall */
2445 dev_err(udc->dev,
2446 "req %02x.%02x protocol STALL; stat %d\n",
2447 reqtype, req, i);
2448 udc->ep0state = WAIT_FOR_SETUP;
2449 goto stall;
2450 }
2451 }
2452
2453 if (!ep0->is_in)
2454 udc_ep0_send_zlp(udc); /* ZLP IN packet on data phase */
2455
2456 return;
2457
2458stall:
2459 udc_stall_hwep(udc, EP_IN);
2460 return;
2461
2462zlp_send:
2463 udc_ep0_send_zlp(udc);
2464 return;
2465}
2466
2467/* IN endpoint 0 transfer */
2468static void udc_handle_ep0_in(struct lpc32xx_udc *udc)
2469{
2470 struct lpc32xx_ep *ep0 = &udc->ep[0];
2471 u32 epstatus;
2472
2473 /* Clear EP interrupt */
2474 epstatus = udc_clearep_getsts(udc, EP_IN);
2475
2476#ifdef CONFIG_USB_GADGET_DEBUG_FILES
2477 ep0->totalints++;
2478#endif
2479
2480 /* Stalled? Clear stall and reset buffers */
2481 if (epstatus & EP_SEL_ST) {
2482 udc_clrstall_hwep(udc, EP_IN);
2483 nuke(ep0, -ECONNABORTED);
2484 udc->ep0state = WAIT_FOR_SETUP;
2485 return;
2486 }
2487
2488 /* Is a buffer available? */
2489 if (!(epstatus & EP_SEL_F)) {
2490 /* Handle based on current state */
2491 if (udc->ep0state == DATA_IN)
2492 udc_ep0_in_req(udc);
2493 else {
2494 /* Unknown state for EP0 oe end of DATA IN phase */
2495 nuke(ep0, -ECONNABORTED);
2496 udc->ep0state = WAIT_FOR_SETUP;
2497 }
2498 }
2499}
2500
2501/* OUT endpoint 0 transfer */
2502static void udc_handle_ep0_out(struct lpc32xx_udc *udc)
2503{
2504 struct lpc32xx_ep *ep0 = &udc->ep[0];
2505 u32 epstatus;
2506
2507 /* Clear EP interrupt */
2508 epstatus = udc_clearep_getsts(udc, EP_OUT);
2509
2510
2511#ifdef CONFIG_USB_GADGET_DEBUG_FILES
2512 ep0->totalints++;
2513#endif
2514
2515 /* Stalled? */
2516 if (epstatus & EP_SEL_ST) {
2517 udc_clrstall_hwep(udc, EP_OUT);
2518 nuke(ep0, -ECONNABORTED);
2519 udc->ep0state = WAIT_FOR_SETUP;
2520 return;
2521 }
2522
2523 /* A NAK may occur if a packet couldn't be received yet */
2524 if (epstatus & EP_SEL_EPN)
2525 return;
2526 /* Setup packet incoming? */
2527 if (epstatus & EP_SEL_STP) {
2528 nuke(ep0, 0);
2529 udc->ep0state = WAIT_FOR_SETUP;
2530 }
2531
2532 /* Data available? */
2533 if (epstatus & EP_SEL_F)
2534 /* Handle based on current state */
2535 switch (udc->ep0state) {
2536 case WAIT_FOR_SETUP:
2537 udc_handle_ep0_setup(udc);
2538 break;
2539
2540 case DATA_OUT:
2541 udc_ep0_out_req(udc);
2542 break;
2543
2544 default:
2545 /* Unknown state for EP0 */
2546 nuke(ep0, -ECONNABORTED);
2547 udc->ep0state = WAIT_FOR_SETUP;
2548 }
2549}
2550
2551/* Must be called without lock */
2552static int lpc32xx_get_frame(struct usb_gadget *gadget)
2553{
2554 int frame;
2555 unsigned long flags;
2556 struct lpc32xx_udc *udc = to_udc(gadget);
2557
2558 if (!udc->clocked)
2559 return -EINVAL;
2560
2561 spin_lock_irqsave(&udc->lock, flags);
2562
2563 frame = (int) udc_get_current_frame(udc);
2564
2565 spin_unlock_irqrestore(&udc->lock, flags);
2566
2567 return frame;
2568}
2569
2570static int lpc32xx_wakeup(struct usb_gadget *gadget)
2571{
2572 return -ENOTSUPP;
2573}
2574
2575static int lpc32xx_set_selfpowered(struct usb_gadget *gadget, int is_on)
2576{
2577 struct lpc32xx_udc *udc = to_udc(gadget);
2578
2579 /* Always self-powered */
2580 udc->selfpowered = (is_on != 0);
2581
2582 return 0;
2583}
2584
2585/*
2586 * vbus is here! turn everything on that's ready
2587 * Must be called without lock
2588 */
2589static int lpc32xx_vbus_session(struct usb_gadget *gadget, int is_active)
2590{
2591 unsigned long flags;
2592 struct lpc32xx_udc *udc = to_udc(gadget);
2593
2594 spin_lock_irqsave(&udc->lock, flags);
2595
2596 /* Doesn't need lock */
2597 if (udc->driver) {
2598 udc_clk_set(udc, 1);
2599 udc_enable(udc);
2600 pullup(udc, is_active);
2601 } else {
2602 stop_activity(udc);
2603 pullup(udc, 0);
2604
2605 spin_unlock_irqrestore(&udc->lock, flags);
2606 /*
2607 * Wait for all the endpoints to disable,
2608 * before disabling clocks. Don't wait if
2609 * endpoints are not enabled.
2610 */
2611 if (atomic_read(&udc->enabled_ep_cnt))
2612 wait_event_interruptible(udc->ep_disable_wait_queue,
2613 (atomic_read(&udc->enabled_ep_cnt) == 0));
2614
2615 spin_lock_irqsave(&udc->lock, flags);
2616
2617 udc_clk_set(udc, 0);
2618 }
2619
2620 spin_unlock_irqrestore(&udc->lock, flags);
2621
2622 return 0;
2623}
2624
2625/* Can be called with or without lock */
2626static int lpc32xx_pullup(struct usb_gadget *gadget, int is_on)
2627{
2628 struct lpc32xx_udc *udc = to_udc(gadget);
2629
2630 /* Doesn't need lock */
2631 pullup(udc, is_on);
2632
2633 return 0;
2634}
2635
2636static int lpc32xx_start(struct usb_gadget_driver *driver,
2637 int (*bind)(struct usb_gadget *));
2638static int lpc32xx_stop(struct usb_gadget_driver *driver);
2639
2640static const struct usb_gadget_ops lpc32xx_udc_ops = {
2641 .get_frame = lpc32xx_get_frame,
2642 .wakeup = lpc32xx_wakeup,
2643 .set_selfpowered = lpc32xx_set_selfpowered,
2644 .vbus_session = lpc32xx_vbus_session,
2645 .pullup = lpc32xx_pullup,
2646 .start = lpc32xx_start,
2647 .stop = lpc32xx_stop,
2648};
2649
2650static void nop_release(struct device *dev)
2651{
2652 /* nothing to free */
2653}
2654
2655static struct lpc32xx_udc controller = {
2656 .gadget = {
2657 .ops = &lpc32xx_udc_ops,
2658 .ep0 = &controller.ep[0].ep,
2659 .name = driver_name,
2660 .dev = {
2661 .init_name = "gadget",
2662 .release = nop_release,
2663 }
2664 },
2665 .ep[0] = {
2666 .ep = {
2667 .name = "ep0",
2668 .ops = &lpc32xx_ep_ops,
2669 },
2670 .udc = &controller,
2671 .maxpacket = 64,
2672 .hwep_num_base = 0,
2673 .hwep_num = 0, /* Can be 0 or 1, has special handling */
2674 .lep = 0,
2675 .eptype = EP_CTL_TYPE,
2676 },
2677 .ep[1] = {
2678 .ep = {
2679 .name = "ep1-int",
2680 .ops = &lpc32xx_ep_ops,
2681 },
2682 .udc = &controller,
2683 .maxpacket = 64,
2684 .hwep_num_base = 2,
2685 .hwep_num = 0, /* 2 or 3, will be set later */
2686 .lep = 1,
2687 .eptype = EP_INT_TYPE,
2688 },
2689 .ep[2] = {
2690 .ep = {
2691 .name = "ep2-bulk",
2692 .ops = &lpc32xx_ep_ops,
2693 },
2694 .udc = &controller,
2695 .maxpacket = 64,
2696 .hwep_num_base = 4,
2697 .hwep_num = 0, /* 4 or 5, will be set later */
2698 .lep = 2,
2699 .eptype = EP_BLK_TYPE,
2700 },
2701 .ep[3] = {
2702 .ep = {
2703 .name = "ep3-iso",
2704 .ops = &lpc32xx_ep_ops,
2705 },
2706 .udc = &controller,
2707 .maxpacket = 1023,
2708 .hwep_num_base = 6,
2709 .hwep_num = 0, /* 6 or 7, will be set later */
2710 .lep = 3,
2711 .eptype = EP_ISO_TYPE,
2712 },
2713 .ep[4] = {
2714 .ep = {
2715 .name = "ep4-int",
2716 .ops = &lpc32xx_ep_ops,
2717 },
2718 .udc = &controller,
2719 .maxpacket = 64,
2720 .hwep_num_base = 8,
2721 .hwep_num = 0, /* 8 or 9, will be set later */
2722 .lep = 4,
2723 .eptype = EP_INT_TYPE,
2724 },
2725 .ep[5] = {
2726 .ep = {
2727 .name = "ep5-bulk",
2728 .ops = &lpc32xx_ep_ops,
2729 },
2730 .udc = &controller,
2731 .maxpacket = 64,
2732 .hwep_num_base = 10,
2733 .hwep_num = 0, /* 10 or 11, will be set later */
2734 .lep = 5,
2735 .eptype = EP_BLK_TYPE,
2736 },
2737 .ep[6] = {
2738 .ep = {
2739 .name = "ep6-iso",
2740 .ops = &lpc32xx_ep_ops,
2741 },
2742 .udc = &controller,
2743 .maxpacket = 1023,
2744 .hwep_num_base = 12,
2745 .hwep_num = 0, /* 12 or 13, will be set later */
2746 .lep = 6,
2747 .eptype = EP_ISO_TYPE,
2748 },
2749 .ep[7] = {
2750 .ep = {
2751 .name = "ep7-int",
2752 .ops = &lpc32xx_ep_ops,
2753 },
2754 .udc = &controller,
2755 .maxpacket = 64,
2756 .hwep_num_base = 14,
2757 .hwep_num = 0,
2758 .lep = 7,
2759 .eptype = EP_INT_TYPE,
2760 },
2761 .ep[8] = {
2762 .ep = {
2763 .name = "ep8-bulk",
2764 .ops = &lpc32xx_ep_ops,
2765 },
2766 .udc = &controller,
2767 .maxpacket = 64,
2768 .hwep_num_base = 16,
2769 .hwep_num = 0,
2770 .lep = 8,
2771 .eptype = EP_BLK_TYPE,
2772 },
2773 .ep[9] = {
2774 .ep = {
2775 .name = "ep9-iso",
2776 .ops = &lpc32xx_ep_ops,
2777 },
2778 .udc = &controller,
2779 .maxpacket = 1023,
2780 .hwep_num_base = 18,
2781 .hwep_num = 0,
2782 .lep = 9,
2783 .eptype = EP_ISO_TYPE,
2784 },
2785 .ep[10] = {
2786 .ep = {
2787 .name = "ep10-int",
2788 .ops = &lpc32xx_ep_ops,
2789 },
2790 .udc = &controller,
2791 .maxpacket = 64,
2792 .hwep_num_base = 20,
2793 .hwep_num = 0,
2794 .lep = 10,
2795 .eptype = EP_INT_TYPE,
2796 },
2797 .ep[11] = {
2798 .ep = {
2799 .name = "ep11-bulk",
2800 .ops = &lpc32xx_ep_ops,
2801 },
2802 .udc = &controller,
2803 .maxpacket = 64,
2804 .hwep_num_base = 22,
2805 .hwep_num = 0,
2806 .lep = 11,
2807 .eptype = EP_BLK_TYPE,
2808 },
2809 .ep[12] = {
2810 .ep = {
2811 .name = "ep12-iso",
2812 .ops = &lpc32xx_ep_ops,
2813 },
2814 .udc = &controller,
2815 .maxpacket = 1023,
2816 .hwep_num_base = 24,
2817 .hwep_num = 0,
2818 .lep = 12,
2819 .eptype = EP_ISO_TYPE,
2820 },
2821 .ep[13] = {
2822 .ep = {
2823 .name = "ep13-int",
2824 .ops = &lpc32xx_ep_ops,
2825 },
2826 .udc = &controller,
2827 .maxpacket = 64,
2828 .hwep_num_base = 26,
2829 .hwep_num = 0,
2830 .lep = 13,
2831 .eptype = EP_INT_TYPE,
2832 },
2833 .ep[14] = {
2834 .ep = {
2835 .name = "ep14-bulk",
2836 .ops = &lpc32xx_ep_ops,
2837 },
2838 .udc = &controller,
2839 .maxpacket = 64,
2840 .hwep_num_base = 28,
2841 .hwep_num = 0,
2842 .lep = 14,
2843 .eptype = EP_BLK_TYPE,
2844 },
2845 .ep[15] = {
2846 .ep = {
2847 .name = "ep15-bulk",
2848 .ops = &lpc32xx_ep_ops,
2849 },
2850 .udc = &controller,
2851 .maxpacket = 1023,
2852 .hwep_num_base = 30,
2853 .hwep_num = 0,
2854 .lep = 15,
2855 .eptype = EP_BLK_TYPE,
2856 },
2857};
2858
2859/* ISO and status interrupts */
2860static irqreturn_t lpc32xx_usb_lp_irq(int irq, void *_udc)
2861{
2862 u32 tmp, devstat;
2863 struct lpc32xx_udc *udc = _udc;
2864
2865 spin_lock(&udc->lock);
2866
2867 /* Read the device status register */
2868 devstat = readl(USBD_DEVINTST(udc->udp_baseaddr));
2869
2870 devstat &= ~USBD_EP_FAST;
2871 writel(devstat, USBD_DEVINTCLR(udc->udp_baseaddr));
2872 devstat = devstat & udc->enabled_devints;
2873
2874 /* Device specific handling needed? */
2875 if (devstat & USBD_DEV_STAT)
2876 udc_handle_dev(udc);
2877
2878 /* Start of frame? (devstat & FRAME_INT):
2879 * The frame interrupt isn't really needed for ISO support,
2880 * as the driver will queue the necessary packets */
2881
2882 /* Error? */
2883 if (devstat & ERR_INT) {
2884 /* All types of errors, from cable removal during transfer to
2885 * misc protocol and bit errors. These are mostly for just info,
2886 * as the USB hardware will work around these. If these errors
2887 * happen alot, something is wrong. */
2888 udc_protocol_cmd_w(udc, CMD_RD_ERR_STAT);
2889 tmp = udc_protocol_cmd_r(udc, DAT_RD_ERR_STAT);
2890 dev_dbg(udc->dev, "Device error (0x%x)!\n", tmp);
2891 }
2892
2893 spin_unlock(&udc->lock);
2894
2895 return IRQ_HANDLED;
2896}
2897
2898/* EP interrupts */
2899static irqreturn_t lpc32xx_usb_hp_irq(int irq, void *_udc)
2900{
2901 u32 tmp;
2902 struct lpc32xx_udc *udc = _udc;
2903
2904 spin_lock(&udc->lock);
2905
2906 /* Read the device status register */
2907 writel(USBD_EP_FAST, USBD_DEVINTCLR(udc->udp_baseaddr));
2908
2909 /* Endpoints */
2910 tmp = readl(USBD_EPINTST(udc->udp_baseaddr));
2911
2912 /* Special handling for EP0 */
2913 if (tmp & (EP_MASK_SEL(0, EP_OUT) | EP_MASK_SEL(0, EP_IN))) {
2914 /* Handle EP0 IN */
2915 if (tmp & (EP_MASK_SEL(0, EP_IN)))
2916 udc_handle_ep0_in(udc);
2917
2918 /* Handle EP0 OUT */
2919 if (tmp & (EP_MASK_SEL(0, EP_OUT)))
2920 udc_handle_ep0_out(udc);
2921 }
2922
2923 /* All other EPs */
2924 if (tmp & ~(EP_MASK_SEL(0, EP_OUT) | EP_MASK_SEL(0, EP_IN))) {
2925 int i;
2926
2927 /* Handle other EP interrupts */
2928 for (i = 1; i < NUM_ENDPOINTS; i++) {
2929 if (tmp & (1 << udc->ep[i].hwep_num))
2930 udc_handle_eps(udc, &udc->ep[i]);
2931 }
2932 }
2933
2934 spin_unlock(&udc->lock);
2935
2936 return IRQ_HANDLED;
2937}
2938
2939static irqreturn_t lpc32xx_usb_devdma_irq(int irq, void *_udc)
2940{
2941 struct lpc32xx_udc *udc = _udc;
2942
2943 int i;
2944 u32 tmp;
2945
2946 spin_lock(&udc->lock);
2947
2948 /* Handle EP DMA EOT interrupts */
2949 tmp = readl(USBD_EOTINTST(udc->udp_baseaddr)) |
2950 (readl(USBD_EPDMAST(udc->udp_baseaddr)) &
2951 readl(USBD_NDDRTINTST(udc->udp_baseaddr))) |
2952 readl(USBD_SYSERRTINTST(udc->udp_baseaddr));
2953 for (i = 1; i < NUM_ENDPOINTS; i++) {
2954 if (tmp & (1 << udc->ep[i].hwep_num))
2955 udc_handle_dma_ep(udc, &udc->ep[i]);
2956 }
2957
2958 spin_unlock(&udc->lock);
2959
2960 return IRQ_HANDLED;
2961}
2962
2963/*
2964 *
2965 * VBUS detection, pullup handler, and Gadget cable state notification
2966 *
2967 */
2968static void vbus_work(struct work_struct *work)
2969{
2970 u8 value;
2971 struct lpc32xx_udc *udc = container_of(work, struct lpc32xx_udc,
2972 vbus_job);
2973
2974 if (udc->enabled != 0) {
2975 /* Discharge VBUS real quick */
2976 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
2977 ISP1301_I2C_OTG_CONTROL_1, OTG1_VBUS_DISCHRG);
2978
2979 /* Give VBUS some time (100mS) to discharge */
2980 msleep(100);
2981
2982 /* Disable VBUS discharge resistor */
2983 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
2984 ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR,
2985 OTG1_VBUS_DISCHRG);
2986
2987 /* Clear interrupt */
2988 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
2989 ISP1301_I2C_INTERRUPT_LATCH |
2990 ISP1301_I2C_REG_CLEAR_ADDR, ~0);
2991
2992 /* Get the VBUS status from the transceiver */
2993 value = i2c_smbus_read_byte_data(udc->isp1301_i2c_client,
2994 ISP1301_I2C_OTG_CONTROL_2);
2995
2996 /* VBUS on or off? */
2997 if (value & OTG_B_SESS_VLD)
2998 udc->vbus = 1;
2999 else
3000 udc->vbus = 0;
3001
3002 /* VBUS changed? */
3003 if (udc->last_vbus != udc->vbus) {
3004 udc->last_vbus = udc->vbus;
3005 lpc32xx_vbus_session(&udc->gadget, udc->vbus);
3006 }
3007 }
3008
3009 /* Re-enable after completion */
3010 enable_irq(udc->udp_irq[IRQ_USB_ATX]);
3011}
3012
3013static irqreturn_t lpc32xx_usb_vbus_irq(int irq, void *_udc)
3014{
3015 struct lpc32xx_udc *udc = _udc;
3016
3017 /* Defer handling of VBUS IRQ to work queue */
3018 disable_irq_nosync(udc->udp_irq[IRQ_USB_ATX]);
3019 schedule_work(&udc->vbus_job);
3020
3021 return IRQ_HANDLED;
3022}
3023
3024static int lpc32xx_start(struct usb_gadget_driver *driver,
3025 int (*bind)(struct usb_gadget *))
3026{
3027 struct lpc32xx_udc *udc = &controller;
3028 int retval, i;
3029
3030 if (!driver || driver->max_speed < USB_SPEED_FULL ||
3031 !bind || !driver->setup) {
3032 dev_err(udc->dev, "bad parameter.\n");
3033 return -EINVAL;
3034 }
3035
3036 if (udc->driver) {
3037 dev_err(udc->dev, "UDC already has a gadget driver\n");
3038 return -EBUSY;
3039 }
3040
3041 udc->driver = driver;
3042 udc->gadget.dev.driver = &driver->driver;
3043 udc->enabled = 1;
3044 udc->selfpowered = 1;
3045 udc->vbus = 0;
3046
3047 retval = bind(&udc->gadget);
3048 if (retval) {
3049 dev_err(udc->dev, "bind() returned %d\n", retval);
3050 udc->enabled = 0;
3051 udc->selfpowered = 0;
3052 udc->driver = NULL;
3053 udc->gadget.dev.driver = NULL;
3054 return retval;
3055 }
3056
3057 dev_dbg(udc->dev, "bound to %s\n", driver->driver.name);
3058
3059 /* Force VBUS process once to check for cable insertion */
3060 udc->last_vbus = udc->vbus = 0;
3061 schedule_work(&udc->vbus_job);
3062
3063 /* Do not re-enable ATX IRQ (3) */
3064 for (i = IRQ_USB_LP; i < IRQ_USB_ATX; i++)
3065 enable_irq(udc->udp_irq[i]);
3066
3067 return 0;
3068}
3069
3070static int lpc32xx_stop(struct usb_gadget_driver *driver)
3071{
3072 int i;
3073 struct lpc32xx_udc *udc = &controller;
3074
3075 if (!driver || driver != udc->driver || !driver->unbind)
3076 return -EINVAL;
3077
3078 /* Disable USB pullup */
3079 isp1301_pullup_enable(udc, 0, 1);
3080
3081 for (i = IRQ_USB_LP; i <= IRQ_USB_ATX; i++)
3082 disable_irq(udc->udp_irq[i]);
3083
3084 if (udc->clocked) {
3085
3086 spin_lock(&udc->lock);
3087 stop_activity(udc);
3088 spin_unlock(&udc->lock);
3089
3090 /*
3091 * Wait for all the endpoints to disable,
3092 * before disabling clocks. Don't wait if
3093 * endpoints are not enabled.
3094 */
3095 if (atomic_read(&udc->enabled_ep_cnt))
3096 wait_event_interruptible(udc->ep_disable_wait_queue,
3097 (atomic_read(&udc->enabled_ep_cnt) == 0));
3098
3099 spin_lock(&udc->lock);
3100 udc_clk_set(udc, 0);
3101 spin_unlock(&udc->lock);
3102 }
3103
3104 udc->enabled = 0;
3105 pullup(udc, 0);
3106
3107 driver->unbind(&udc->gadget);
3108 udc->gadget.dev.driver = NULL;
3109 udc->driver = NULL;
3110
3111 dev_dbg(udc->dev, "unbound from %s\n", driver->driver.name);
3112 return 0;
3113}
3114
3115static void lpc32xx_udc_shutdown(struct platform_device *dev)
3116{
3117 /* Force disconnect on reboot */
3118 struct lpc32xx_udc *udc = &controller;
3119
3120 pullup(udc, 0);
3121}
3122
3123/*
3124 * Callbacks to be overridden by options passed via OF (TODO)
3125 */
3126
3127static void lpc32xx_usbd_conn_chg(int conn)
3128{
3129 /* Do nothing, it might be nice to enable an LED
3130 * based on conn state being !0 */
3131}
3132
3133static void lpc32xx_usbd_susp_chg(int susp)
3134{
3135 /* Device suspend if susp != 0 */
3136}
3137
3138static void lpc32xx_rmwkup_chg(int remote_wakup_enable)
3139{
3140 /* Enable or disable USB remote wakeup */
3141}
3142
3143struct lpc32xx_usbd_cfg lpc32xx_usbddata = {
3144 .vbus_drv_pol = 0,
3145 .conn_chgb = &lpc32xx_usbd_conn_chg,
3146 .susp_chgb = &lpc32xx_usbd_susp_chg,
3147 .rmwk_chgb = &lpc32xx_rmwkup_chg,
3148};
3149
3150
3151static u64 lpc32xx_usbd_dmamask = ~(u32) 0x7F;
3152
3153static int __init lpc32xx_udc_probe(struct platform_device *pdev)
3154{
3155 struct device *dev = &pdev->dev;
3156 struct lpc32xx_udc *udc = &controller;
3157 int retval, i;
3158 struct resource *res;
3159 dma_addr_t dma_handle;
3160 struct device_node *isp1301_node;
3161
3162 /* init software state */
3163 udc->gadget.dev.parent = dev;
3164 udc->pdev = pdev;
3165 udc->dev = &pdev->dev;
3166 udc->enabled = 0;
3167
3168 if (pdev->dev.of_node) {
3169 isp1301_node = of_parse_phandle(pdev->dev.of_node,
3170 "transceiver", 0);
3171 } else {
3172 isp1301_node = NULL;
3173 }
3174
3175 udc->isp1301_i2c_client = isp1301_get_client(isp1301_node);
3176 if (!udc->isp1301_i2c_client)
3177 return -EPROBE_DEFER;
3178
3179 dev_info(udc->dev, "ISP1301 I2C device at address 0x%x\n",
3180 udc->isp1301_i2c_client->addr);
3181
3182 pdev->dev.dma_mask = &lpc32xx_usbd_dmamask;
3183 pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
3184
3185 udc->board = &lpc32xx_usbddata;
3186
3187 /*
3188 * Resources are mapped as follows:
3189 * IORESOURCE_MEM, base address and size of USB space
3190 * IORESOURCE_IRQ, USB device low priority interrupt number
3191 * IORESOURCE_IRQ, USB device high priority interrupt number
3192 * IORESOURCE_IRQ, USB device interrupt number
3193 * IORESOURCE_IRQ, USB transceiver interrupt number
3194 */
3195 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3196 if (!res)
3197 return -ENXIO;
3198
3199 spin_lock_init(&udc->lock);
3200
3201 /* Get IRQs */
3202 for (i = 0; i < 4; i++) {
3203 udc->udp_irq[i] = platform_get_irq(pdev, i);
3204 if (udc->udp_irq[i] < 0) {
3205 dev_err(udc->dev,
3206 "irq resource %d not available!\n", i);
3207 return udc->udp_irq[i];
3208 }
3209 }
3210
3211 udc->io_p_start = res->start;
3212 udc->io_p_size = resource_size(res);
3213 if (!request_mem_region(udc->io_p_start, udc->io_p_size, driver_name)) {
3214 dev_err(udc->dev, "someone's using UDC memory\n");
3215 return -EBUSY;
3216 }
3217
3218 udc->udp_baseaddr = ioremap(udc->io_p_start, udc->io_p_size);
3219 if (!udc->udp_baseaddr) {
3220 retval = -ENOMEM;
3221 dev_err(udc->dev, "IO map failure\n");
3222 goto io_map_fail;
3223 }
3224
3225 /* Enable AHB slave USB clock, needed for further USB clock control */
3226 writel(USB_SLAVE_HCLK_EN | (1 << 19), USB_CTRL);
3227
3228 /* Get required clocks */
3229 udc->usb_pll_clk = clk_get(&pdev->dev, "ck_pll5");
3230 if (IS_ERR(udc->usb_pll_clk)) {
3231 dev_err(udc->dev, "failed to acquire USB PLL\n");
3232 retval = PTR_ERR(udc->usb_pll_clk);
3233 goto pll_get_fail;
3234 }
3235 udc->usb_slv_clk = clk_get(&pdev->dev, "ck_usbd");
3236 if (IS_ERR(udc->usb_slv_clk)) {
3237 dev_err(udc->dev, "failed to acquire USB device clock\n");
3238 retval = PTR_ERR(udc->usb_slv_clk);
3239 goto usb_clk_get_fail;
3240 }
3241
3242 /* Setup PLL clock to 48MHz */
3243 retval = clk_enable(udc->usb_pll_clk);
3244 if (retval < 0) {
3245 dev_err(udc->dev, "failed to start USB PLL\n");
3246 goto pll_enable_fail;
3247 }
3248
3249 retval = clk_set_rate(udc->usb_pll_clk, 48000);
3250 if (retval < 0) {
3251 dev_err(udc->dev, "failed to set USB clock rate\n");
3252 goto pll_set_fail;
3253 }
3254
3255 writel(readl(USB_CTRL) | USB_DEV_NEED_CLK_EN, USB_CTRL);
3256
3257 /* Enable USB device clock */
3258 retval = clk_enable(udc->usb_slv_clk);
3259 if (retval < 0) {
3260 dev_err(udc->dev, "failed to start USB device clock\n");
3261 goto usb_clk_enable_fail;
3262 }
3263
3264 /* Set to enable all needed USB OTG clocks */
3265 writel(USB_CLOCK_MASK, USB_OTG_CLK_CTRL(udc));
3266
3267 i = 1000;
3268 while (((readl(USB_OTG_CLK_STAT(udc)) & USB_CLOCK_MASK) !=
3269 USB_CLOCK_MASK) && (i > 0))
3270 i--;
3271 if (!i)
3272 dev_dbg(udc->dev, "USB OTG clocks not correctly enabled\n");
3273
3274 /* Setup deferred workqueue data */
3275 udc->poweron = udc->pullup = 0;
3276 INIT_WORK(&udc->pullup_job, pullup_work);
3277 INIT_WORK(&udc->vbus_job, vbus_work);
3278#ifdef CONFIG_PM
3279 INIT_WORK(&udc->power_job, power_work);
3280#endif
3281
3282 /* All clocks are now on */
3283 udc->clocked = 1;
3284
3285 isp1301_udc_configure(udc);
3286 /* Allocate memory for the UDCA */
3287 udc->udca_v_base = dma_alloc_coherent(&pdev->dev, UDCA_BUFF_SIZE,
3288 &dma_handle,
3289 (GFP_KERNEL | GFP_DMA));
3290 if (!udc->udca_v_base) {
3291 dev_err(udc->dev, "error getting UDCA region\n");
3292 retval = -ENOMEM;
3293 goto i2c_fail;
3294 }
3295 udc->udca_p_base = dma_handle;
3296 dev_dbg(udc->dev, "DMA buffer(0x%x bytes), P:0x%08x, V:0x%p\n",
3297 UDCA_BUFF_SIZE, udc->udca_p_base, udc->udca_v_base);
3298
3299 /* Setup the DD DMA memory pool */
3300 udc->dd_cache = dma_pool_create("udc_dd", udc->dev,
3301 sizeof(struct lpc32xx_usbd_dd_gad),
3302 sizeof(u32), 0);
3303 if (!udc->dd_cache) {
3304 dev_err(udc->dev, "error getting DD DMA region\n");
3305 retval = -ENOMEM;
3306 goto dma_alloc_fail;
3307 }
3308
3309 /* Clear USB peripheral and initialize gadget endpoints */
3310 udc_disable(udc);
3311 udc_reinit(udc);
3312
3313 retval = device_register(&udc->gadget.dev);
3314 if (retval < 0) {
3315 dev_err(udc->dev, "Device registration failure\n");
3316 goto dev_register_fail;
3317 }
3318
3319 /* Request IRQs - low and high priority USB device IRQs are routed to
3320 * the same handler, while the DMA interrupt is routed elsewhere */
3321 retval = request_irq(udc->udp_irq[IRQ_USB_LP], lpc32xx_usb_lp_irq,
3322 0, "udc_lp", udc);
3323 if (retval < 0) {
3324 dev_err(udc->dev, "LP request irq %d failed\n",
3325 udc->udp_irq[IRQ_USB_LP]);
3326 goto irq_lp_fail;
3327 }
3328 retval = request_irq(udc->udp_irq[IRQ_USB_HP], lpc32xx_usb_hp_irq,
3329 0, "udc_hp", udc);
3330 if (retval < 0) {
3331 dev_err(udc->dev, "HP request irq %d failed\n",
3332 udc->udp_irq[IRQ_USB_HP]);
3333 goto irq_hp_fail;
3334 }
3335
3336 retval = request_irq(udc->udp_irq[IRQ_USB_DEVDMA],
3337 lpc32xx_usb_devdma_irq, 0, "udc_dma", udc);
3338 if (retval < 0) {
3339 dev_err(udc->dev, "DEV request irq %d failed\n",
3340 udc->udp_irq[IRQ_USB_DEVDMA]);
3341 goto irq_dev_fail;
3342 }
3343
3344 /* The transceiver interrupt is used for VBUS detection and will
3345 kick off the VBUS handler function */
3346 retval = request_irq(udc->udp_irq[IRQ_USB_ATX], lpc32xx_usb_vbus_irq,
3347 0, "udc_otg", udc);
3348 if (retval < 0) {
3349 dev_err(udc->dev, "VBUS request irq %d failed\n",
3350 udc->udp_irq[IRQ_USB_ATX]);
3351 goto irq_xcvr_fail;
3352 }
3353
3354 /* Initialize wait queue */
3355 init_waitqueue_head(&udc->ep_disable_wait_queue);
3356 atomic_set(&udc->enabled_ep_cnt, 0);
3357
3358 /* Keep all IRQs disabled until GadgetFS starts up */
3359 for (i = IRQ_USB_LP; i <= IRQ_USB_ATX; i++)
3360 disable_irq(udc->udp_irq[i]);
3361
3362 retval = usb_add_gadget_udc(dev, &udc->gadget);
3363 if (retval < 0)
3364 goto add_gadget_fail;
3365
3366 dev_set_drvdata(dev, udc);
3367 device_init_wakeup(dev, 1);
3368 create_debug_file(udc);
3369
3370 /* Disable clocks for now */
3371 udc_clk_set(udc, 0);
3372
3373 dev_info(udc->dev, "%s version %s\n", driver_name, DRIVER_VERSION);
3374 return 0;
3375
3376add_gadget_fail:
3377 free_irq(udc->udp_irq[IRQ_USB_ATX], udc);
3378irq_xcvr_fail:
3379 free_irq(udc->udp_irq[IRQ_USB_DEVDMA], udc);
3380irq_dev_fail:
3381 free_irq(udc->udp_irq[IRQ_USB_HP], udc);
3382irq_hp_fail:
3383 free_irq(udc->udp_irq[IRQ_USB_LP], udc);
3384irq_lp_fail:
3385 device_unregister(&udc->gadget.dev);
3386dev_register_fail:
3387 dma_pool_destroy(udc->dd_cache);
3388dma_alloc_fail:
3389 dma_free_coherent(&pdev->dev, UDCA_BUFF_SIZE,
3390 udc->udca_v_base, udc->udca_p_base);
3391i2c_fail:
3392 clk_disable(udc->usb_slv_clk);
3393usb_clk_enable_fail:
3394pll_set_fail:
3395 clk_disable(udc->usb_pll_clk);
3396pll_enable_fail:
3397 clk_put(udc->usb_slv_clk);
3398usb_clk_get_fail:
3399 clk_put(udc->usb_pll_clk);
3400pll_get_fail:
3401 iounmap(udc->udp_baseaddr);
3402io_map_fail:
3403 release_mem_region(udc->io_p_start, udc->io_p_size);
3404 dev_err(udc->dev, "%s probe failed, %d\n", driver_name, retval);
3405
3406 return retval;
3407}
3408
3409static int __devexit lpc32xx_udc_remove(struct platform_device *pdev)
3410{
3411 struct lpc32xx_udc *udc = platform_get_drvdata(pdev);
3412
3413 usb_del_gadget_udc(&udc->gadget);
3414 if (udc->driver)
3415 return -EBUSY;
3416
3417 udc_clk_set(udc, 1);
3418 udc_disable(udc);
3419 pullup(udc, 0);
3420
3421 free_irq(udc->udp_irq[IRQ_USB_ATX], udc);
3422
3423 device_init_wakeup(&pdev->dev, 0);
3424 remove_debug_file(udc);
3425
3426 dma_pool_destroy(udc->dd_cache);
3427 dma_free_coherent(&pdev->dev, UDCA_BUFF_SIZE,
3428 udc->udca_v_base, udc->udca_p_base);
3429 free_irq(udc->udp_irq[IRQ_USB_DEVDMA], udc);
3430 free_irq(udc->udp_irq[IRQ_USB_HP], udc);
3431 free_irq(udc->udp_irq[IRQ_USB_LP], udc);
3432
3433 device_unregister(&udc->gadget.dev);
3434
3435 clk_disable(udc->usb_slv_clk);
3436 clk_put(udc->usb_slv_clk);
3437 clk_disable(udc->usb_pll_clk);
3438 clk_put(udc->usb_pll_clk);
3439 iounmap(udc->udp_baseaddr);
3440 release_mem_region(udc->io_p_start, udc->io_p_size);
3441
3442 return 0;
3443}
3444
3445#ifdef CONFIG_PM
3446static int lpc32xx_udc_suspend(struct platform_device *pdev, pm_message_t mesg)
3447{
3448 int to = 1000;
3449 struct lpc32xx_udc *udc = platform_get_drvdata(pdev);
3450
3451 if (udc->clocked) {
3452 /* Power down ISP */
3453 udc->poweron = 0;
3454 isp1301_set_powerstate(udc, 0);
3455
3456 /* Disable clocking */
3457 udc_clk_set(udc, 0);
3458
3459 /* Keep clock flag on, so we know to re-enable clocks
3460 on resume */
3461 udc->clocked = 1;
3462
3463 /* Kill OTG and I2C clocks */
3464 writel(0, USB_OTG_CLK_CTRL(udc));
3465 while (((readl(USB_OTG_CLK_STAT(udc)) & OTGOFF_CLK_MASK) !=
3466 OTGOFF_CLK_MASK) && (to > 0))
3467 to--;
3468 if (!to)
3469 dev_dbg(udc->dev,
3470 "USB OTG clocks not correctly enabled\n");
3471
3472 /* Kill global USB clock */
3473 clk_disable(udc->usb_slv_clk);
3474 }
3475
3476 return 0;
3477}
3478
3479static int lpc32xx_udc_resume(struct platform_device *pdev)
3480{
3481 struct lpc32xx_udc *udc = platform_get_drvdata(pdev);
3482
3483 if (udc->clocked) {
3484 /* Enable global USB clock */
3485 clk_enable(udc->usb_slv_clk);
3486
3487 /* Enable clocking */
3488 udc_clk_set(udc, 1);
3489
3490 /* ISP back to normal power mode */
3491 udc->poweron = 1;
3492 isp1301_set_powerstate(udc, 1);
3493 }
3494
3495 return 0;
3496}
3497#else
3498#define lpc32xx_udc_suspend NULL
3499#define lpc32xx_udc_resume NULL
3500#endif
3501
3502#ifdef CONFIG_OF
3503static struct of_device_id lpc32xx_udc_of_match[] = {
3504 { .compatible = "nxp,lpc3220-udc", },
3505 { },
3506};
3507MODULE_DEVICE_TABLE(of, lpc32xx_udc_of_match);
3508#endif
3509
3510static struct platform_driver lpc32xx_udc_driver = {
3511 .remove = __devexit_p(lpc32xx_udc_remove),
3512 .shutdown = lpc32xx_udc_shutdown,
3513 .suspend = lpc32xx_udc_suspend,
3514 .resume = lpc32xx_udc_resume,
3515 .driver = {
3516 .name = (char *) driver_name,
3517 .owner = THIS_MODULE,
3518 .of_match_table = of_match_ptr(lpc32xx_udc_of_match),
3519 },
3520};
3521
3522static int __init udc_init_module(void)
3523{
3524 return platform_driver_probe(&lpc32xx_udc_driver, lpc32xx_udc_probe);
3525}
3526module_init(udc_init_module);
3527
3528static void __exit udc_exit_module(void)
3529{
3530 platform_driver_unregister(&lpc32xx_udc_driver);
3531}
3532module_exit(udc_exit_module);
3533
3534MODULE_DESCRIPTION("LPC32XX udc driver");
3535MODULE_AUTHOR("Kevin Wells <kevin.wells@nxp.com>");
3536MODULE_AUTHOR("Roland Stigge <stigge@antcom.de>");
3537MODULE_LICENSE("GPL");
3538MODULE_ALIAS("platform:lpc32xx_udc");
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-11 02:20:07 -0500