aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/usb/gadget/pch_udc.c
diff options
context:
space:
mode:
authorToshiharu Okada <toshiharu-linux@dsn.okisemi.com>2010-11-11 04:27:57 -0500
committerGreg Kroah-Hartman <gregkh@suse.de>2010-11-16 16:57:25 -0500
commitf646cf94520e22cb11eb5d2e9a35b33bfe4bea1b (patch)
tree877f1f6f98b6f80ad2894d08e492c0d6ca2a1d4b /drivers/usb/gadget/pch_udc.c
parentd8df0b611c66db3b7afd0678213979209616681a (diff)
USB device driver of Topcliff PCH
This patch adds the USB device driver of EG20T(Topcliff) PCH. EG20T PCH is the platform controller hub that is going to be used in Intel's upcoming general embedded platform. All IO peripherals in EG20T PCH are actually devices sitting on AMBA bus. EG20T PCH has USB device I/F. Using this I/F, it is able to access system devices connected to USB device. Signed-off-by: Toshiharu Okada <toshiharu-linux@dsn.okisemi.com> Acked-by: Michał Nazarewicz <m.nazarewicz@samsung.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'drivers/usb/gadget/pch_udc.c')
-rw-r--r--drivers/usb/gadget/pch_udc.c2941
1 files changed, 2941 insertions, 0 deletions
diff --git a/drivers/usb/gadget/pch_udc.c b/drivers/usb/gadget/pch_udc.c
new file mode 100644
index 000000000000..4a5256977d29
--- /dev/null
+++ b/drivers/usb/gadget/pch_udc.c
@@ -0,0 +1,2941 @@
1/*
2 * Copyright (C) 2010 OKI SEMICONDUCTOR CO., LTD.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; version 2 of the License.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
16 */
17#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
18#include <linux/kernel.h>
19#include <linux/module.h>
20#include <linux/pci.h>
21#include <linux/delay.h>
22#include <linux/errno.h>
23#include <linux/list.h>
24#include <linux/interrupt.h>
25#include <linux/usb/ch9.h>
26#include <linux/usb/gadget.h>
27
28/* Address offset of Registers */
29#define UDC_EP_REG_SHIFT 0x20 /* Offset to next EP */
30
31#define UDC_EPCTL_ADDR 0x00 /* Endpoint control */
32#define UDC_EPSTS_ADDR 0x04 /* Endpoint status */
33#define UDC_BUFIN_FRAMENUM_ADDR 0x08 /* buffer size in / frame number out */
34#define UDC_BUFOUT_MAXPKT_ADDR 0x0C /* buffer size out / maxpkt in */
35#define UDC_SUBPTR_ADDR 0x10 /* setup buffer pointer */
36#define UDC_DESPTR_ADDR 0x14 /* Data descriptor pointer */
37#define UDC_CONFIRM_ADDR 0x18 /* Write/Read confirmation */
38
39#define UDC_DEVCFG_ADDR 0x400 /* Device configuration */
40#define UDC_DEVCTL_ADDR 0x404 /* Device control */
41#define UDC_DEVSTS_ADDR 0x408 /* Device status */
42#define UDC_DEVIRQSTS_ADDR 0x40C /* Device irq status */
43#define UDC_DEVIRQMSK_ADDR 0x410 /* Device irq mask */
44#define UDC_EPIRQSTS_ADDR 0x414 /* Endpoint irq status */
45#define UDC_EPIRQMSK_ADDR 0x418 /* Endpoint irq mask */
46#define UDC_DEVLPM_ADDR 0x41C /* LPM control / status */
47#define UDC_CSR_BUSY_ADDR 0x4f0 /* UDC_CSR_BUSY Status register */
48#define UDC_SRST_ADDR 0x4fc /* SOFT RESET register */
49#define UDC_CSR_ADDR 0x500 /* USB_DEVICE endpoint register */
50
51/* Endpoint control register */
52/* Bit position */
53#define UDC_EPCTL_MRXFLUSH (1 << 12)
54#define UDC_EPCTL_RRDY (1 << 9)
55#define UDC_EPCTL_CNAK (1 << 8)
56#define UDC_EPCTL_SNAK (1 << 7)
57#define UDC_EPCTL_NAK (1 << 6)
58#define UDC_EPCTL_P (1 << 3)
59#define UDC_EPCTL_F (1 << 1)
60#define UDC_EPCTL_S (1 << 0)
61#define UDC_EPCTL_ET_SHIFT 4
62/* Mask patern */
63#define UDC_EPCTL_ET_MASK 0x00000030
64/* Value for ET field */
65#define UDC_EPCTL_ET_CONTROL 0
66#define UDC_EPCTL_ET_ISO 1
67#define UDC_EPCTL_ET_BULK 2
68#define UDC_EPCTL_ET_INTERRUPT 3
69
70/* Endpoint status register */
71/* Bit position */
72#define UDC_EPSTS_XFERDONE (1 << 27)
73#define UDC_EPSTS_RSS (1 << 26)
74#define UDC_EPSTS_RCS (1 << 25)
75#define UDC_EPSTS_TXEMPTY (1 << 24)
76#define UDC_EPSTS_TDC (1 << 10)
77#define UDC_EPSTS_HE (1 << 9)
78#define UDC_EPSTS_MRXFIFO_EMP (1 << 8)
79#define UDC_EPSTS_BNA (1 << 7)
80#define UDC_EPSTS_IN (1 << 6)
81#define UDC_EPSTS_OUT_SHIFT 4
82/* Mask patern */
83#define UDC_EPSTS_OUT_MASK 0x00000030
84#define UDC_EPSTS_ALL_CLR_MASK 0x1F0006F0
85/* Value for OUT field */
86#define UDC_EPSTS_OUT_SETUP 2
87#define UDC_EPSTS_OUT_DATA 1
88
89/* Device configuration register */
90/* Bit position */
91#define UDC_DEVCFG_CSR_PRG (1 << 17)
92#define UDC_DEVCFG_SP (1 << 3)
93/* SPD Valee */
94#define UDC_DEVCFG_SPD_HS 0x0
95#define UDC_DEVCFG_SPD_FS 0x1
96#define UDC_DEVCFG_SPD_LS 0x2
97
98/* Device control register */
99/* Bit position */
100#define UDC_DEVCTL_THLEN_SHIFT 24
101#define UDC_DEVCTL_BRLEN_SHIFT 16
102#define UDC_DEVCTL_CSR_DONE (1 << 13)
103#define UDC_DEVCTL_SD (1 << 10)
104#define UDC_DEVCTL_MODE (1 << 9)
105#define UDC_DEVCTL_BREN (1 << 8)
106#define UDC_DEVCTL_THE (1 << 7)
107#define UDC_DEVCTL_DU (1 << 4)
108#define UDC_DEVCTL_TDE (1 << 3)
109#define UDC_DEVCTL_RDE (1 << 2)
110#define UDC_DEVCTL_RES (1 << 0)
111
112/* Device status register */
113/* Bit position */
114#define UDC_DEVSTS_TS_SHIFT 18
115#define UDC_DEVSTS_ENUM_SPEED_SHIFT 13
116#define UDC_DEVSTS_ALT_SHIFT 8
117#define UDC_DEVSTS_INTF_SHIFT 4
118#define UDC_DEVSTS_CFG_SHIFT 0
119/* Mask patern */
120#define UDC_DEVSTS_TS_MASK 0xfffc0000
121#define UDC_DEVSTS_ENUM_SPEED_MASK 0x00006000
122#define UDC_DEVSTS_ALT_MASK 0x00000f00
123#define UDC_DEVSTS_INTF_MASK 0x000000f0
124#define UDC_DEVSTS_CFG_MASK 0x0000000f
125/* value for maximum speed for SPEED field */
126#define UDC_DEVSTS_ENUM_SPEED_FULL 1
127#define UDC_DEVSTS_ENUM_SPEED_HIGH 0
128#define UDC_DEVSTS_ENUM_SPEED_LOW 2
129#define UDC_DEVSTS_ENUM_SPEED_FULLX 3
130
131/* Device irq register */
132/* Bit position */
133#define UDC_DEVINT_RWKP (1 << 7)
134#define UDC_DEVINT_ENUM (1 << 6)
135#define UDC_DEVINT_SOF (1 << 5)
136#define UDC_DEVINT_US (1 << 4)
137#define UDC_DEVINT_UR (1 << 3)
138#define UDC_DEVINT_ES (1 << 2)
139#define UDC_DEVINT_SI (1 << 1)
140#define UDC_DEVINT_SC (1 << 0)
141/* Mask patern */
142#define UDC_DEVINT_MSK 0x7f
143
144/* Endpoint irq register */
145/* Bit position */
146#define UDC_EPINT_IN_SHIFT 0
147#define UDC_EPINT_OUT_SHIFT 16
148#define UDC_EPINT_IN_EP0 (1 << 0)
149#define UDC_EPINT_OUT_EP0 (1 << 16)
150/* Mask patern */
151#define UDC_EPINT_MSK_DISABLE_ALL 0xffffffff
152
153/* UDC_CSR_BUSY Status register */
154/* Bit position */
155#define UDC_CSR_BUSY (1 << 0)
156
157/* SOFT RESET register */
158/* Bit position */
159#define UDC_PSRST (1 << 1)
160#define UDC_SRST (1 << 0)
161
162/* USB_DEVICE endpoint register */
163/* Bit position */
164#define UDC_CSR_NE_NUM_SHIFT 0
165#define UDC_CSR_NE_DIR_SHIFT 4
166#define UDC_CSR_NE_TYPE_SHIFT 5
167#define UDC_CSR_NE_CFG_SHIFT 7
168#define UDC_CSR_NE_INTF_SHIFT 11
169#define UDC_CSR_NE_ALT_SHIFT 15
170#define UDC_CSR_NE_MAX_PKT_SHIFT 19
171/* Mask patern */
172#define UDC_CSR_NE_NUM_MASK 0x0000000f
173#define UDC_CSR_NE_DIR_MASK 0x00000010
174#define UDC_CSR_NE_TYPE_MASK 0x00000060
175#define UDC_CSR_NE_CFG_MASK 0x00000780
176#define UDC_CSR_NE_INTF_MASK 0x00007800
177#define UDC_CSR_NE_ALT_MASK 0x00078000
178#define UDC_CSR_NE_MAX_PKT_MASK 0x3ff80000
179
180#define PCH_UDC_CSR(ep) (UDC_CSR_ADDR + ep*4)
181#define PCH_UDC_EPINT(in, num)\
182 (1 << (num + (in ? UDC_EPINT_IN_SHIFT : UDC_EPINT_OUT_SHIFT)))
183
184/* Index of endpoint */
185#define UDC_EP0IN_IDX 0
186#define UDC_EP0OUT_IDX 1
187#define UDC_EPIN_IDX(ep) (ep * 2)
188#define UDC_EPOUT_IDX(ep) (ep * 2 + 1)
189#define PCH_UDC_EP0 0
190#define PCH_UDC_EP1 1
191#define PCH_UDC_EP2 2
192#define PCH_UDC_EP3 3
193
194/* Number of endpoint */
195#define PCH_UDC_EP_NUM 32 /* Total number of EPs (16 IN,16 OUT) */
196#define PCH_UDC_USED_EP_NUM 4 /* EP number of EP's really used */
197/* Length Value */
198#define PCH_UDC_BRLEN 0x0F /* Burst length */
199#define PCH_UDC_THLEN 0x1F /* Threshold length */
200/* Value of EP Buffer Size */
201#define UDC_EP0IN_BUFF_SIZE 64
202#define UDC_EPIN_BUFF_SIZE 512
203#define UDC_EP0OUT_BUFF_SIZE 64
204#define UDC_EPOUT_BUFF_SIZE 512
205/* Value of EP maximum packet size */
206#define UDC_EP0IN_MAX_PKT_SIZE 64
207#define UDC_EP0OUT_MAX_PKT_SIZE 64
208#define UDC_BULK_MAX_PKT_SIZE 512
209
210/* DMA */
211#define DMA_DIR_RX 1 /* DMA for data receive */
212#define DMA_DIR_TX 2 /* DMA for data transmit */
213#define DMA_ADDR_INVALID (~(dma_addr_t)0)
214#define UDC_DMA_MAXPACKET 65536 /* maximum packet size for DMA */
215
216/**
217 * struct pch_udc_data_dma_desc - Structure to hold DMA descriptor information
218 * for data
219 * @status: Status quadlet
220 * @reserved: Reserved
221 * @dataptr: Buffer descriptor
222 * @next: Next descriptor
223 */
224struct pch_udc_data_dma_desc {
225 u32 status;
226 u32 reserved;
227 u32 dataptr;
228 u32 next;
229};
230
231/**
232 * struct pch_udc_stp_dma_desc - Structure to hold DMA descriptor information
233 * for control data
234 * @status: Status
235 * @reserved: Reserved
236 * @data12: First setup word
237 * @data34: Second setup word
238 */
239struct pch_udc_stp_dma_desc {
240 u32 status;
241 u32 reserved;
242 struct usb_ctrlrequest request;
243} __attribute((packed));
244
245/* DMA status definitions */
246/* Buffer status */
247#define PCH_UDC_BUFF_STS 0xC0000000
248#define PCH_UDC_BS_HST_RDY 0x00000000
249#define PCH_UDC_BS_DMA_BSY 0x40000000
250#define PCH_UDC_BS_DMA_DONE 0x80000000
251#define PCH_UDC_BS_HST_BSY 0xC0000000
252/* Rx/Tx Status */
253#define PCH_UDC_RXTX_STS 0x30000000
254#define PCH_UDC_RTS_SUCC 0x00000000
255#define PCH_UDC_RTS_DESERR 0x10000000
256#define PCH_UDC_RTS_BUFERR 0x30000000
257/* Last Descriptor Indication */
258#define PCH_UDC_DMA_LAST 0x08000000
259/* Number of Rx/Tx Bytes Mask */
260#define PCH_UDC_RXTX_BYTES 0x0000ffff
261
262/**
263 * struct pch_udc_cfg_data - Structure to hold current configuration
264 * and interface information
265 * @cur_cfg: current configuration in use
266 * @cur_intf: current interface in use
267 * @cur_alt: current alt interface in use
268 */
269struct pch_udc_cfg_data {
270 u16 cur_cfg;
271 u16 cur_intf;
272 u16 cur_alt;
273};
274
275/**
276 * struct pch_udc_ep - Structure holding a PCH USB device Endpoint information
277 * @ep: embedded ep request
278 * @td_stp_phys: for setup request
279 * @td_data_phys: for data request
280 * @td_stp: for setup request
281 * @td_data: for data request
282 * @dev: reference to device struct
283 * @offset_addr: offset address of ep register
284 * @desc: for this ep
285 * @queue: queue for requests
286 * @num: endpoint number
287 * @in: endpoint is IN
288 * @halted: endpoint halted?
289 * @epsts: Endpoint status
290 */
291struct pch_udc_ep {
292 struct usb_ep ep;
293 dma_addr_t td_stp_phys;
294 dma_addr_t td_data_phys;
295 struct pch_udc_stp_dma_desc *td_stp;
296 struct pch_udc_data_dma_desc *td_data;
297 struct pch_udc_dev *dev;
298 unsigned long offset_addr;
299 const struct usb_endpoint_descriptor *desc;
300 struct list_head queue;
301 unsigned num:5,
302 in:1,
303 halted:1;
304 unsigned long epsts;
305};
306
307/**
308 * struct pch_udc_dev - Structure holding complete information
309 * of the PCH USB device
310 * @gadget: gadget driver data
311 * @driver: reference to gadget driver bound
312 * @pdev: reference to the PCI device
313 * @ep: array of endpoints
314 * @lock: protects all state
315 * @active: enabled the PCI device
316 * @stall: stall requested
317 * @prot_stall: protcol stall requested
318 * @irq_registered: irq registered with system
319 * @mem_region: device memory mapped
320 * @registered: driver regsitered with system
321 * @suspended: driver in suspended state
322 * @connected: gadget driver associated
323 * @set_cfg_not_acked: pending acknowledgement 4 setup
324 * @waiting_zlp_ack: pending acknowledgement 4 ZLP
325 * @data_requests: DMA pool for data requests
326 * @stp_requests: DMA pool for setup requests
327 * @dma_addr: DMA pool for received
328 * @ep0out_buf: Buffer for DMA
329 * @setup_data: Received setup data
330 * @phys_addr: of device memory
331 * @base_addr: for mapped device memory
332 * @irq: IRQ line for the device
333 * @cfg_data: current cfg, intf, and alt in use
334 */
335struct pch_udc_dev {
336 struct usb_gadget gadget;
337 struct usb_gadget_driver *driver;
338 struct pci_dev *pdev;
339 struct pch_udc_ep ep[PCH_UDC_EP_NUM];
340 spinlock_t lock;
341 unsigned active:1,
342 stall:1,
343 prot_stall:1,
344 irq_registered:1,
345 mem_region:1,
346 registered:1,
347 suspended:1,
348 connected:1,
349 set_cfg_not_acked:1,
350 waiting_zlp_ack:1;
351 struct pci_pool *data_requests;
352 struct pci_pool *stp_requests;
353 dma_addr_t dma_addr;
354 unsigned long ep0out_buf[64];
355 struct usb_ctrlrequest setup_data;
356 unsigned long phys_addr;
357 void __iomem *base_addr;
358 unsigned irq;
359 struct pch_udc_cfg_data cfg_data;
360};
361
362#define PCH_UDC_PCI_BAR 1
363#define PCI_DEVICE_ID_INTEL_EG20T_UDC 0x8808
364
365static const char ep0_string[] = "ep0in";
366static DEFINE_SPINLOCK(udc_stall_spinlock); /* stall spin lock */
367struct pch_udc_dev *pch_udc; /* pointer to device object */
368
369static int speed_fs;
370module_param_named(speed_fs, speed_fs, bool, S_IRUGO);
371MODULE_PARM_DESC(speed_fs, "true for Full speed operation");
372
373/**
374 * struct pch_udc_request - Structure holding a PCH USB device request packet
375 * @req: embedded ep request
376 * @td_data_phys: phys. address
377 * @td_data: first dma desc. of chain
378 * @td_data_last: last dma desc. of chain
379 * @queue: associated queue
380 * @dma_going: DMA in progress for request
381 * @dma_mapped: DMA memory mapped for request
382 * @dma_done: DMA completed for request
383 * @chain_len: chain length
384 */
385struct pch_udc_request {
386 struct usb_request req;
387 dma_addr_t td_data_phys;
388 struct pch_udc_data_dma_desc *td_data;
389 struct pch_udc_data_dma_desc *td_data_last;
390 struct list_head queue;
391 unsigned dma_going:1,
392 dma_mapped:1,
393 dma_done:1;
394 unsigned chain_len;
395};
396
397static inline u32 pch_udc_readl(struct pch_udc_dev *dev, unsigned long reg)
398{
399 return ioread32(dev->base_addr + reg);
400}
401
402static inline void pch_udc_writel(struct pch_udc_dev *dev,
403 unsigned long val, unsigned long reg)
404{
405 iowrite32(val, dev->base_addr + reg);
406}
407
408static inline void pch_udc_bit_set(struct pch_udc_dev *dev,
409 unsigned long reg,
410 unsigned long bitmask)
411{
412 pch_udc_writel(dev, pch_udc_readl(dev, reg) | bitmask, reg);
413}
414
415static inline void pch_udc_bit_clr(struct pch_udc_dev *dev,
416 unsigned long reg,
417 unsigned long bitmask)
418{
419 pch_udc_writel(dev, pch_udc_readl(dev, reg) & ~(bitmask), reg);
420}
421
422static inline u32 pch_udc_ep_readl(struct pch_udc_ep *ep, unsigned long reg)
423{
424 return ioread32(ep->dev->base_addr + ep->offset_addr + reg);
425}
426
427static inline void pch_udc_ep_writel(struct pch_udc_ep *ep,
428 unsigned long val, unsigned long reg)
429{
430 iowrite32(val, ep->dev->base_addr + ep->offset_addr + reg);
431}
432
433static inline void pch_udc_ep_bit_set(struct pch_udc_ep *ep,
434 unsigned long reg,
435 unsigned long bitmask)
436{
437 pch_udc_ep_writel(ep, pch_udc_ep_readl(ep, reg) | bitmask, reg);
438}
439
440static inline void pch_udc_ep_bit_clr(struct pch_udc_ep *ep,
441 unsigned long reg,
442 unsigned long bitmask)
443{
444 pch_udc_ep_writel(ep, pch_udc_ep_readl(ep, reg) & ~(bitmask), reg);
445}
446
447/**
448 * pch_udc_csr_busy() - Wait till idle.
449 * @dev: Reference to pch_udc_dev structure
450 */
451static void pch_udc_csr_busy(struct pch_udc_dev *dev)
452{
453 unsigned int count = 200;
454
455 /* Wait till idle */
456 while ((pch_udc_readl(dev, UDC_CSR_BUSY_ADDR) & UDC_CSR_BUSY)
457 && --count)
458 cpu_relax();
459 if (!count)
460 dev_err(&dev->pdev->dev, "%s: wait error\n", __func__);
461}
462
463/**
464 * pch_udc_write_csr() - Write the command and status registers.
465 * @dev: Reference to pch_udc_dev structure
466 * @val: value to be written to CSR register
467 * @addr: address of CSR register
468 */
469static void pch_udc_write_csr(struct pch_udc_dev *dev, unsigned long val,
470 unsigned int ep)
471{
472 unsigned long reg = PCH_UDC_CSR(ep);
473
474 pch_udc_csr_busy(dev); /* Wait till idle */
475 pch_udc_writel(dev, val, reg);
476 pch_udc_csr_busy(dev); /* Wait till idle */
477}
478
479/**
480 * pch_udc_read_csr() - Read the command and status registers.
481 * @dev: Reference to pch_udc_dev structure
482 * @addr: address of CSR register
483 *
484 * Return codes: content of CSR register
485 */
486static u32 pch_udc_read_csr(struct pch_udc_dev *dev, unsigned int ep)
487{
488 unsigned long reg = PCH_UDC_CSR(ep);
489
490 pch_udc_csr_busy(dev); /* Wait till idle */
491 pch_udc_readl(dev, reg); /* Dummy read */
492 pch_udc_csr_busy(dev); /* Wait till idle */
493 return pch_udc_readl(dev, reg);
494}
495
496/**
497 * pch_udc_rmt_wakeup() - Initiate for remote wakeup
498 * @dev: Reference to pch_udc_dev structure
499 */
500static inline void pch_udc_rmt_wakeup(struct pch_udc_dev *dev)
501{
502 pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RES);
503 mdelay(1);
504 pch_udc_bit_clr(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RES);
505}
506
507/**
508 * pch_udc_get_frame() - Get the current frame from device status register
509 * @dev: Reference to pch_udc_dev structure
510 * Retern current frame
511 */
512static inline int pch_udc_get_frame(struct pch_udc_dev *dev)
513{
514 u32 frame = pch_udc_readl(dev, UDC_DEVSTS_ADDR);
515 return (frame & UDC_DEVSTS_TS_MASK) >> UDC_DEVSTS_TS_SHIFT;
516}
517
518/**
519 * pch_udc_clear_selfpowered() - Clear the self power control
520 * @dev: Reference to pch_udc_regs structure
521 */
522static inline void pch_udc_clear_selfpowered(struct pch_udc_dev *dev)
523{
524 pch_udc_bit_clr(dev, UDC_DEVCFG_ADDR, UDC_DEVCFG_SP);
525}
526
527/**
528 * pch_udc_set_selfpowered() - Set the self power control
529 * @dev: Reference to pch_udc_regs structure
530 */
531static inline void pch_udc_set_selfpowered(struct pch_udc_dev *dev)
532{
533 pch_udc_bit_set(dev, UDC_DEVCFG_ADDR, UDC_DEVCFG_SP);
534}
535
536/**
537 * pch_udc_set_disconnect() - Set the disconnect status.
538 * @dev: Reference to pch_udc_regs structure
539 */
540static inline void pch_udc_set_disconnect(struct pch_udc_dev *dev)
541{
542 pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_SD);
543}
544
545/**
546 * pch_udc_clear_disconnect() - Clear the disconnect status.
547 * @dev: Reference to pch_udc_regs structure
548 */
549static void pch_udc_clear_disconnect(struct pch_udc_dev *dev)
550{
551 /* Clear the disconnect */
552 pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RES);
553 pch_udc_bit_clr(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_SD);
554 mdelay(1);
555 /* Resume USB signalling */
556 pch_udc_bit_clr(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RES);
557}
558
559/**
560 * pch_udc_vbus_session() - set or clearr the disconnect status.
561 * @dev: Reference to pch_udc_regs structure
562 * @is_active: Parameter specifying the action
563 * 0: indicating VBUS power is ending
564 * !0: indicating VBUS power is starting
565 */
566static inline void pch_udc_vbus_session(struct pch_udc_dev *dev,
567 int is_active)
568{
569 if (is_active)
570 pch_udc_clear_disconnect(dev);
571 else
572 pch_udc_set_disconnect(dev);
573}
574
575/**
576 * pch_udc_ep_set_stall() - Set the stall of endpoint
577 * @ep: Reference to structure of type pch_udc_ep_regs
578 */
579static void pch_udc_ep_set_stall(struct pch_udc_ep *ep)
580{
581 if (ep->in) {
582 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_F);
583 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_S);
584 } else {
585 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_S);
586 }
587}
588
589/**
590 * pch_udc_ep_clear_stall() - Clear the stall of endpoint
591 * @ep: Reference to structure of type pch_udc_ep_regs
592 */
593static inline void pch_udc_ep_clear_stall(struct pch_udc_ep *ep)
594{
595 /* Clear the stall */
596 pch_udc_ep_bit_clr(ep, UDC_EPCTL_ADDR, UDC_EPCTL_S);
597 /* Clear NAK by writing CNAK */
598 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_CNAK);
599}
600
601/**
602 * pch_udc_ep_set_trfr_type() - Set the transfer type of endpoint
603 * @ep: Reference to structure of type pch_udc_ep_regs
604 * @type: Type of endpoint
605 */
606static inline void pch_udc_ep_set_trfr_type(struct pch_udc_ep *ep,
607 u8 type)
608{
609 pch_udc_ep_writel(ep, ((type << UDC_EPCTL_ET_SHIFT) &
610 UDC_EPCTL_ET_MASK), UDC_EPCTL_ADDR);
611}
612
613/**
614 * pch_udc_ep_set_bufsz() - Set the maximum packet size for the endpoint
615 * @ep: Reference to structure of type pch_udc_ep_regs
616 * @buf_size: The buffer size
617 */
618static void pch_udc_ep_set_bufsz(struct pch_udc_ep *ep,
619 u32 buf_size, u32 ep_in)
620{
621 u32 data;
622 if (ep_in) {
623 data = pch_udc_ep_readl(ep, UDC_BUFIN_FRAMENUM_ADDR);
624 data = (data & 0xffff0000) | (buf_size & 0xffff);
625 pch_udc_ep_writel(ep, data, UDC_BUFIN_FRAMENUM_ADDR);
626 } else {
627 data = pch_udc_ep_readl(ep, UDC_BUFOUT_MAXPKT_ADDR);
628 data = (buf_size << 16) | (data & 0xffff);
629 pch_udc_ep_writel(ep, data, UDC_BUFOUT_MAXPKT_ADDR);
630 }
631}
632
633/**
634 * pch_udc_ep_set_maxpkt() - Set the Max packet size for the endpoint
635 * @ep: Reference to structure of type pch_udc_ep_regs
636 * @pkt_size: The packet size
637 */
638static void pch_udc_ep_set_maxpkt(struct pch_udc_ep *ep, u32 pkt_size)
639{
640 u32 data = pch_udc_ep_readl(ep, UDC_BUFOUT_MAXPKT_ADDR);
641 data = (data & 0xffff0000) | (pkt_size & 0xffff);
642 pch_udc_ep_writel(ep, data, UDC_BUFOUT_MAXPKT_ADDR);
643}
644
645/**
646 * pch_udc_ep_set_subptr() - Set the Setup buffer pointer for the endpoint
647 * @ep: Reference to structure of type pch_udc_ep_regs
648 * @addr: Address of the register
649 */
650static inline void pch_udc_ep_set_subptr(struct pch_udc_ep *ep, u32 addr)
651{
652 pch_udc_ep_writel(ep, addr, UDC_SUBPTR_ADDR);
653}
654
655/**
656 * pch_udc_ep_set_ddptr() - Set the Data descriptor pointer for the endpoint
657 * @ep: Reference to structure of type pch_udc_ep_regs
658 * @addr: Address of the register
659 */
660static inline void pch_udc_ep_set_ddptr(struct pch_udc_ep *ep, u32 addr)
661{
662 pch_udc_ep_writel(ep, addr, UDC_DESPTR_ADDR);
663}
664
665/**
666 * pch_udc_ep_set_pd() - Set the poll demand bit for the endpoint
667 * @ep: Reference to structure of type pch_udc_ep_regs
668 */
669static inline void pch_udc_ep_set_pd(struct pch_udc_ep *ep)
670{
671 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_P);
672}
673
674/**
675 * pch_udc_ep_set_rrdy() - Set the receive ready bit for the endpoint
676 * @ep: Reference to structure of type pch_udc_ep_regs
677 */
678static inline void pch_udc_ep_set_rrdy(struct pch_udc_ep *ep)
679{
680 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_RRDY);
681}
682
683/**
684 * pch_udc_ep_clear_rrdy() - Clear the receive ready bit for the endpoint
685 * @ep: Reference to structure of type pch_udc_ep_regs
686 */
687static inline void pch_udc_ep_clear_rrdy(struct pch_udc_ep *ep)
688{
689 pch_udc_ep_bit_clr(ep, UDC_EPCTL_ADDR, UDC_EPCTL_RRDY);
690}
691
692/**
693 * pch_udc_set_dma() - Set the 'TDE' or RDE bit of device control
694 * register depending on the direction specified
695 * @dev: Reference to structure of type pch_udc_regs
696 * @dir: whether Tx or Rx
697 * DMA_DIR_RX: Receive
698 * DMA_DIR_TX: Transmit
699 */
700static inline void pch_udc_set_dma(struct pch_udc_dev *dev, int dir)
701{
702 if (dir == DMA_DIR_RX)
703 pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RDE);
704 else if (dir == DMA_DIR_TX)
705 pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_TDE);
706}
707
708/**
709 * pch_udc_clear_dma() - Clear the 'TDE' or RDE bit of device control
710 * register depending on the direction specified
711 * @dev: Reference to structure of type pch_udc_regs
712 * @dir: Whether Tx or Rx
713 * DMA_DIR_RX: Receive
714 * DMA_DIR_TX: Transmit
715 */
716static inline void pch_udc_clear_dma(struct pch_udc_dev *dev, int dir)
717{
718 if (dir == DMA_DIR_RX)
719 pch_udc_bit_clr(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RDE);
720 else if (dir == DMA_DIR_TX)
721 pch_udc_bit_clr(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_TDE);
722}
723
724/**
725 * pch_udc_set_csr_done() - Set the device control register
726 * CSR done field (bit 13)
727 * @dev: reference to structure of type pch_udc_regs
728 */
729static inline void pch_udc_set_csr_done(struct pch_udc_dev *dev)
730{
731 pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_CSR_DONE);
732}
733
734/**
735 * pch_udc_disable_interrupts() - Disables the specified interrupts
736 * @dev: Reference to structure of type pch_udc_regs
737 * @mask: Mask to disable interrupts
738 */
739static inline void pch_udc_disable_interrupts(struct pch_udc_dev *dev,
740 u32 mask)
741{
742 pch_udc_bit_set(dev, UDC_DEVIRQMSK_ADDR, mask);
743}
744
745/**
746 * pch_udc_enable_interrupts() - Enable the specified interrupts
747 * @dev: Reference to structure of type pch_udc_regs
748 * @mask: Mask to enable interrupts
749 */
750static inline void pch_udc_enable_interrupts(struct pch_udc_dev *dev,
751 u32 mask)
752{
753 pch_udc_bit_clr(dev, UDC_DEVIRQMSK_ADDR, mask);
754}
755
756/**
757 * pch_udc_disable_ep_interrupts() - Disable endpoint interrupts
758 * @dev: Reference to structure of type pch_udc_regs
759 * @mask: Mask to disable interrupts
760 */
761static inline void pch_udc_disable_ep_interrupts(struct pch_udc_dev *dev,
762 u32 mask)
763{
764 pch_udc_bit_set(dev, UDC_EPIRQMSK_ADDR, mask);
765}
766
767/**
768 * pch_udc_enable_ep_interrupts() - Enable endpoint interrupts
769 * @dev: Reference to structure of type pch_udc_regs
770 * @mask: Mask to enable interrupts
771 */
772static inline void pch_udc_enable_ep_interrupts(struct pch_udc_dev *dev,
773 u32 mask)
774{
775 pch_udc_bit_clr(dev, UDC_EPIRQMSK_ADDR, mask);
776}
777
778/**
779 * pch_udc_read_device_interrupts() - Read the device interrupts
780 * @dev: Reference to structure of type pch_udc_regs
781 * Retern The device interrupts
782 */
783static inline u32 pch_udc_read_device_interrupts(struct pch_udc_dev *dev)
784{
785 return pch_udc_readl(dev, UDC_DEVIRQSTS_ADDR);
786}
787
788/**
789 * pch_udc_write_device_interrupts() - Write device interrupts
790 * @dev: Reference to structure of type pch_udc_regs
791 * @val: The value to be written to interrupt register
792 */
793static inline void pch_udc_write_device_interrupts(struct pch_udc_dev *dev,
794 u32 val)
795{
796 pch_udc_writel(dev, val, UDC_DEVIRQSTS_ADDR);
797}
798
799/**
800 * pch_udc_read_ep_interrupts() - Read the endpoint interrupts
801 * @dev: Reference to structure of type pch_udc_regs
802 * Retern The endpoint interrupt
803 */
804static inline u32 pch_udc_read_ep_interrupts(struct pch_udc_dev *dev)
805{
806 return pch_udc_readl(dev, UDC_EPIRQSTS_ADDR);
807}
808
809/**
810 * pch_udc_write_ep_interrupts() - Clear endpoint interupts
811 * @dev: Reference to structure of type pch_udc_regs
812 * @val: The value to be written to interrupt register
813 */
814static inline void pch_udc_write_ep_interrupts(struct pch_udc_dev *dev,
815 u32 val)
816{
817 pch_udc_writel(dev, val, UDC_EPIRQSTS_ADDR);
818}
819
820/**
821 * pch_udc_read_device_status() - Read the device status
822 * @dev: Reference to structure of type pch_udc_regs
823 * Retern The device status
824 */
825static inline u32 pch_udc_read_device_status(struct pch_udc_dev *dev)
826{
827 return pch_udc_readl(dev, UDC_DEVSTS_ADDR);
828}
829
830/**
831 * pch_udc_read_ep_control() - Read the endpoint control
832 * @ep: Reference to structure of type pch_udc_ep_regs
833 * Retern The endpoint control register value
834 */
835static inline u32 pch_udc_read_ep_control(struct pch_udc_ep *ep)
836{
837 return pch_udc_ep_readl(ep, UDC_EPCTL_ADDR);
838}
839
840/**
841 * pch_udc_clear_ep_control() - Clear the endpoint control register
842 * @ep: Reference to structure of type pch_udc_ep_regs
843 * Retern The endpoint control register value
844 */
845static inline void pch_udc_clear_ep_control(struct pch_udc_ep *ep)
846{
847 return pch_udc_ep_writel(ep, 0, UDC_EPCTL_ADDR);
848}
849
850/**
851 * pch_udc_read_ep_status() - Read the endpoint status
852 * @ep: Reference to structure of type pch_udc_ep_regs
853 * Retern The endpoint status
854 */
855static inline u32 pch_udc_read_ep_status(struct pch_udc_ep *ep)
856{
857 return pch_udc_ep_readl(ep, UDC_EPSTS_ADDR);
858}
859
860/**
861 * pch_udc_clear_ep_status() - Clear the endpoint status
862 * @ep: Reference to structure of type pch_udc_ep_regs
863 * @stat: Endpoint status
864 */
865static inline void pch_udc_clear_ep_status(struct pch_udc_ep *ep,
866 u32 stat)
867{
868 return pch_udc_ep_writel(ep, stat, UDC_EPSTS_ADDR);
869}
870
871/**
872 * pch_udc_ep_set_nak() - Set the bit 7 (SNAK field)
873 * of the endpoint control register
874 * @ep: Reference to structure of type pch_udc_ep_regs
875 */
876static inline void pch_udc_ep_set_nak(struct pch_udc_ep *ep)
877{
878 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_SNAK);
879}
880
881/**
882 * pch_udc_ep_clear_nak() - Set the bit 8 (CNAK field)
883 * of the endpoint control register
884 * @ep: reference to structure of type pch_udc_ep_regs
885 */
886static void pch_udc_ep_clear_nak(struct pch_udc_ep *ep)
887{
888 unsigned int loopcnt = 0;
889 struct pch_udc_dev *dev = ep->dev;
890
891 if (!(pch_udc_ep_readl(ep, UDC_EPCTL_ADDR) & UDC_EPCTL_NAK))
892 return;
893 if (!ep->in) {
894 loopcnt = 10000;
895 while (!(pch_udc_read_ep_status(ep) & UDC_EPSTS_MRXFIFO_EMP) &&
896 --loopcnt)
897 udelay(5);
898 if (!loopcnt)
899 dev_err(&dev->pdev->dev, "%s: RxFIFO not Empty\n",
900 __func__);
901 }
902 loopcnt = 10000;
903 while ((pch_udc_read_ep_control(ep) & UDC_EPCTL_NAK) && --loopcnt) {
904 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_CNAK);
905 udelay(5);
906 }
907 if (!loopcnt)
908 dev_err(&dev->pdev->dev, "%s: Clear NAK not set for ep%d%s\n",
909 __func__, ep->num, (ep->in ? "in" : "out"));
910}
911
912/**
913 * pch_udc_ep_fifo_flush() - Flush the endpoint fifo
914 * @ep: reference to structure of type pch_udc_ep_regs
915 * @dir: direction of endpoint
916 * 0: endpoint is OUT
917 * !0: endpoint is IN
918 */
919static void pch_udc_ep_fifo_flush(struct pch_udc_ep *ep, int dir)
920{
921 unsigned int loopcnt = 0;
922 struct pch_udc_dev *dev = ep->dev;
923
924 if (dir) { /* IN ep */
925 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_F);
926 return;
927 }
928
929 if (pch_udc_read_ep_status(ep) & UDC_EPSTS_MRXFIFO_EMP)
930 return;
931 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_MRXFLUSH);
932 /* Wait for RxFIFO Empty */
933 loopcnt = 10000;
934 while (!(pch_udc_read_ep_status(ep) & UDC_EPSTS_MRXFIFO_EMP) &&
935 --loopcnt)
936 udelay(5);
937 if (!loopcnt)
938 dev_err(&dev->pdev->dev, "RxFIFO not Empty\n");
939 pch_udc_ep_bit_clr(ep, UDC_EPCTL_ADDR, UDC_EPCTL_MRXFLUSH);
940}
941
942/**
943 * pch_udc_ep_enable() - This api enables endpoint
944 * @regs: Reference to structure pch_udc_ep_regs
945 * @desc: endpoint descriptor
946 */
947static void pch_udc_ep_enable(struct pch_udc_ep *ep,
948 struct pch_udc_cfg_data *cfg,
949 const struct usb_endpoint_descriptor *desc)
950{
951 u32 val = 0;
952 u32 buff_size = 0;
953
954 pch_udc_ep_set_trfr_type(ep, desc->bmAttributes);
955 if (ep->in)
956 buff_size = UDC_EPIN_BUFF_SIZE;
957 else
958 buff_size = UDC_EPOUT_BUFF_SIZE;
959 pch_udc_ep_set_bufsz(ep, buff_size, ep->in);
960 pch_udc_ep_set_maxpkt(ep, le16_to_cpu(desc->wMaxPacketSize));
961 pch_udc_ep_set_nak(ep);
962 pch_udc_ep_fifo_flush(ep, ep->in);
963 /* Configure the endpoint */
964 val = ep->num << UDC_CSR_NE_NUM_SHIFT | ep->in << UDC_CSR_NE_DIR_SHIFT |
965 ((desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) <<
966 UDC_CSR_NE_TYPE_SHIFT) |
967 (cfg->cur_cfg << UDC_CSR_NE_CFG_SHIFT) |
968 (cfg->cur_intf << UDC_CSR_NE_INTF_SHIFT) |
969 (cfg->cur_alt << UDC_CSR_NE_ALT_SHIFT) |
970 le16_to_cpu(desc->wMaxPacketSize) << UDC_CSR_NE_MAX_PKT_SHIFT;
971
972 if (ep->in)
973 pch_udc_write_csr(ep->dev, val, UDC_EPIN_IDX(ep->num));
974 else
975 pch_udc_write_csr(ep->dev, val, UDC_EPOUT_IDX(ep->num));
976}
977
978/**
979 * pch_udc_ep_disable() - This api disables endpoint
980 * @regs: Reference to structure pch_udc_ep_regs
981 */
982static void pch_udc_ep_disable(struct pch_udc_ep *ep)
983{
984 if (ep->in) {
985 /* flush the fifo */
986 pch_udc_ep_writel(ep, UDC_EPCTL_F, UDC_EPCTL_ADDR);
987 /* set NAK */
988 pch_udc_ep_writel(ep, UDC_EPCTL_SNAK, UDC_EPCTL_ADDR);
989 pch_udc_ep_bit_set(ep, UDC_EPSTS_ADDR, UDC_EPSTS_IN);
990 } else {
991 /* set NAK */
992 pch_udc_ep_writel(ep, UDC_EPCTL_SNAK, UDC_EPCTL_ADDR);
993 }
994 /* reset desc pointer */
995 pch_udc_ep_writel(ep, 0, UDC_DESPTR_ADDR);
996}
997
998/**
999 * pch_udc_wait_ep_stall() - Wait EP stall.
1000 * @dev: Reference to pch_udc_dev structure
1001 */
1002static void pch_udc_wait_ep_stall(struct pch_udc_ep *ep)
1003{
1004 unsigned int count = 10000;
1005
1006 /* Wait till idle */
1007 while ((pch_udc_read_ep_control(ep) & UDC_EPCTL_S) && --count)
1008 udelay(5);
1009 if (!count)
1010 dev_err(&ep->dev->pdev->dev, "%s: wait error\n", __func__);
1011}
1012
1013/**
1014 * pch_udc_init() - This API initializes usb device controller
1015 * @dev: Rreference to pch_udc_regs structure
1016 */
1017static void pch_udc_init(struct pch_udc_dev *dev)
1018{
1019 if (NULL == dev) {
1020 pr_err("%s: Invalid address\n", __func__);
1021 return;
1022 }
1023 /* Soft Reset and Reset PHY */
1024 pch_udc_writel(dev, UDC_SRST, UDC_SRST_ADDR);
1025 pch_udc_writel(dev, UDC_SRST | UDC_PSRST, UDC_SRST_ADDR);
1026 mdelay(1);
1027 pch_udc_writel(dev, UDC_SRST, UDC_SRST_ADDR);
1028 pch_udc_writel(dev, 0x00, UDC_SRST_ADDR);
1029 mdelay(1);
1030 /* mask and clear all device interrupts */
1031 pch_udc_bit_set(dev, UDC_DEVIRQMSK_ADDR, UDC_DEVINT_MSK);
1032 pch_udc_bit_set(dev, UDC_DEVIRQSTS_ADDR, UDC_DEVINT_MSK);
1033
1034 /* mask and clear all ep interrupts */
1035 pch_udc_bit_set(dev, UDC_EPIRQMSK_ADDR, UDC_EPINT_MSK_DISABLE_ALL);
1036 pch_udc_bit_set(dev, UDC_EPIRQSTS_ADDR, UDC_EPINT_MSK_DISABLE_ALL);
1037
1038 /* enable dynamic CSR programmingi, self powered and device speed */
1039 if (speed_fs)
1040 pch_udc_bit_set(dev, UDC_DEVCFG_ADDR, UDC_DEVCFG_CSR_PRG |
1041 UDC_DEVCFG_SP | UDC_DEVCFG_SPD_FS);
1042 else /* defaul high speed */
1043 pch_udc_bit_set(dev, UDC_DEVCFG_ADDR, UDC_DEVCFG_CSR_PRG |
1044 UDC_DEVCFG_SP | UDC_DEVCFG_SPD_HS);
1045 pch_udc_bit_set(dev, UDC_DEVCTL_ADDR,
1046 (PCH_UDC_THLEN << UDC_DEVCTL_THLEN_SHIFT) |
1047 (PCH_UDC_BRLEN << UDC_DEVCTL_BRLEN_SHIFT) |
1048 UDC_DEVCTL_MODE | UDC_DEVCTL_BREN |
1049 UDC_DEVCTL_THE);
1050}
1051
1052/**
1053 * pch_udc_exit() - This API exit usb device controller
1054 * @dev: Reference to pch_udc_regs structure
1055 */
1056static void pch_udc_exit(struct pch_udc_dev *dev)
1057{
1058 /* mask all device interrupts */
1059 pch_udc_bit_set(dev, UDC_DEVIRQMSK_ADDR, UDC_DEVINT_MSK);
1060 /* mask all ep interrupts */
1061 pch_udc_bit_set(dev, UDC_EPIRQMSK_ADDR, UDC_EPINT_MSK_DISABLE_ALL);
1062 /* put device in disconnected state */
1063 pch_udc_set_disconnect(dev);
1064}
1065
1066/**
1067 * pch_udc_pcd_get_frame() - This API is invoked to get the current frame number
1068 * @gadget: Reference to the gadget driver
1069 *
1070 * Return codes:
1071 * 0: Success
1072 * -EINVAL: If the gadget passed is NULL
1073 */
1074static int pch_udc_pcd_get_frame(struct usb_gadget *gadget)
1075{
1076 struct pch_udc_dev *dev;
1077
1078 if (!gadget)
1079 return -EINVAL;
1080 dev = container_of(gadget, struct pch_udc_dev, gadget);
1081 return pch_udc_get_frame(dev);
1082}
1083
1084/**
1085 * pch_udc_pcd_wakeup() - This API is invoked to initiate a remote wakeup
1086 * @gadget: Reference to the gadget driver
1087 *
1088 * Return codes:
1089 * 0: Success
1090 * -EINVAL: If the gadget passed is NULL
1091 */
1092static int pch_udc_pcd_wakeup(struct usb_gadget *gadget)
1093{
1094 struct pch_udc_dev *dev;
1095 unsigned long flags;
1096
1097 if (!gadget)
1098 return -EINVAL;
1099 dev = container_of(gadget, struct pch_udc_dev, gadget);
1100 spin_lock_irqsave(&dev->lock, flags);
1101 pch_udc_rmt_wakeup(dev);
1102 spin_unlock_irqrestore(&dev->lock, flags);
1103 return 0;
1104}
1105
1106/**
1107 * pch_udc_pcd_selfpowered() - This API is invoked to specify whether the device
1108 * is self powered or not
1109 * @gadget: Reference to the gadget driver
1110 * @value: Specifies self powered or not
1111 *
1112 * Return codes:
1113 * 0: Success
1114 * -EINVAL: If the gadget passed is NULL
1115 */
1116static int pch_udc_pcd_selfpowered(struct usb_gadget *gadget, int value)
1117{
1118 struct pch_udc_dev *dev;
1119
1120 if (!gadget)
1121 return -EINVAL;
1122 dev = container_of(gadget, struct pch_udc_dev, gadget);
1123 if (value)
1124 pch_udc_set_selfpowered(dev);
1125 else
1126 pch_udc_clear_selfpowered(dev);
1127 return 0;
1128}
1129
1130/**
1131 * pch_udc_pcd_pullup() - This API is invoked to make the device
1132 * visible/invisible to the host
1133 * @gadget: Reference to the gadget driver
1134 * @is_on: Specifies whether the pull up is made active or inactive
1135 *
1136 * Return codes:
1137 * 0: Success
1138 * -EINVAL: If the gadget passed is NULL
1139 */
1140static int pch_udc_pcd_pullup(struct usb_gadget *gadget, int is_on)
1141{
1142 struct pch_udc_dev *dev;
1143
1144 if (!gadget)
1145 return -EINVAL;
1146 dev = container_of(gadget, struct pch_udc_dev, gadget);
1147 pch_udc_vbus_session(dev, is_on);
1148 return 0;
1149}
1150
1151/**
1152 * pch_udc_pcd_vbus_session() - This API is used by a driver for an external
1153 * transceiver (or GPIO) that
1154 * detects a VBUS power session starting/ending
1155 * @gadget: Reference to the gadget driver
1156 * @is_active: specifies whether the session is starting or ending
1157 *
1158 * Return codes:
1159 * 0: Success
1160 * -EINVAL: If the gadget passed is NULL
1161 */
1162static int pch_udc_pcd_vbus_session(struct usb_gadget *gadget, int is_active)
1163{
1164 struct pch_udc_dev *dev;
1165
1166 if (!gadget)
1167 return -EINVAL;
1168 dev = container_of(gadget, struct pch_udc_dev, gadget);
1169 pch_udc_vbus_session(dev, is_active);
1170 return 0;
1171}
1172
1173/**
1174 * pch_udc_pcd_vbus_draw() - This API is used by gadget drivers during
1175 * SET_CONFIGURATION calls to
1176 * specify how much power the device can consume
1177 * @gadget: Reference to the gadget driver
1178 * @mA: specifies the current limit in 2mA unit
1179 *
1180 * Return codes:
1181 * -EINVAL: If the gadget passed is NULL
1182 * -EOPNOTSUPP:
1183 */
1184static int pch_udc_pcd_vbus_draw(struct usb_gadget *gadget, unsigned int mA)
1185{
1186 return -EOPNOTSUPP;
1187}
1188
1189static const struct usb_gadget_ops pch_udc_ops = {
1190 .get_frame = pch_udc_pcd_get_frame,
1191 .wakeup = pch_udc_pcd_wakeup,
1192 .set_selfpowered = pch_udc_pcd_selfpowered,
1193 .pullup = pch_udc_pcd_pullup,
1194 .vbus_session = pch_udc_pcd_vbus_session,
1195 .vbus_draw = pch_udc_pcd_vbus_draw,
1196};
1197
1198/**
1199 * complete_req() - This API is invoked from the driver when processing
1200 * of a request is complete
1201 * @ep: Reference to the endpoint structure
1202 * @req: Reference to the request structure
1203 * @status: Indicates the success/failure of completion
1204 */
1205static void complete_req(struct pch_udc_ep *ep, struct pch_udc_request *req,
1206 int status)
1207{
1208 struct pch_udc_dev *dev;
1209 unsigned halted = ep->halted;
1210
1211 list_del_init(&req->queue);
1212
1213 /* set new status if pending */
1214 if (req->req.status == -EINPROGRESS)
1215 req->req.status = status;
1216 else
1217 status = req->req.status;
1218
1219 dev = ep->dev;
1220 if (req->dma_mapped) {
1221 if (ep->in)
1222 pci_unmap_single(dev->pdev, req->req.dma,
1223 req->req.length, PCI_DMA_TODEVICE);
1224 else
1225 pci_unmap_single(dev->pdev, req->req.dma,
1226 req->req.length, PCI_DMA_FROMDEVICE);
1227 req->dma_mapped = 0;
1228 req->req.dma = DMA_ADDR_INVALID;
1229 }
1230 ep->halted = 1;
1231 spin_unlock(&dev->lock);
1232 if (!ep->in)
1233 pch_udc_ep_clear_rrdy(ep);
1234 req->req.complete(&ep->ep, &req->req);
1235 spin_lock(&dev->lock);
1236 ep->halted = halted;
1237}
1238
1239/**
1240 * empty_req_queue() - This API empties the request queue of an endpoint
1241 * @ep: Reference to the endpoint structure
1242 */
1243static void empty_req_queue(struct pch_udc_ep *ep)
1244{
1245 struct pch_udc_request *req;
1246
1247 ep->halted = 1;
1248 while (!list_empty(&ep->queue)) {
1249 req = list_entry(ep->queue.next, struct pch_udc_request, queue);
1250 complete_req(ep, req, -ESHUTDOWN); /* Remove from list */
1251 }
1252}
1253
1254/**
1255 * pch_udc_free_dma_chain() - This function frees the DMA chain created
1256 * for the request
1257 * @dev Reference to the driver structure
1258 * @req Reference to the request to be freed
1259 *
1260 * Return codes:
1261 * 0: Success
1262 */
1263static void pch_udc_free_dma_chain(struct pch_udc_dev *dev,
1264 struct pch_udc_request *req)
1265{
1266 struct pch_udc_data_dma_desc *td = req->td_data;
1267 unsigned i = req->chain_len;
1268
1269 for (; i > 1; --i) {
1270 dma_addr_t addr = (dma_addr_t)td->next;
1271 /* do not free first desc., will be done by free for request */
1272 td = phys_to_virt(addr);
1273 pci_pool_free(dev->data_requests, td, addr);
1274 }
1275}
1276
1277/**
1278 * pch_udc_create_dma_chain() - This function creates or reinitializes
1279 * a DMA chain
1280 * @ep: Reference to the endpoint structure
1281 * @req: Reference to the request
1282 * @buf_len: The buffer length
1283 * @gfp_flags: Flags to be used while mapping the data buffer
1284 *
1285 * Return codes:
1286 * 0: success,
1287 * -ENOMEM: pci_pool_alloc invocation fails
1288 */
1289static int pch_udc_create_dma_chain(struct pch_udc_ep *ep,
1290 struct pch_udc_request *req,
1291 unsigned long buf_len,
1292 gfp_t gfp_flags)
1293{
1294 struct pch_udc_data_dma_desc *td = req->td_data, *last;
1295 unsigned long bytes = req->req.length, i = 0;
1296 dma_addr_t dma_addr;
1297 unsigned len = 1;
1298
1299 if (req->chain_len > 1)
1300 pch_udc_free_dma_chain(ep->dev, req);
1301
1302 for (; ; bytes -= buf_len, ++len) {
1303 if (ep->in)
1304 td->status = PCH_UDC_BS_HST_BSY | min(buf_len, bytes);
1305 else
1306 td->status = PCH_UDC_BS_HST_BSY;
1307
1308 if (bytes <= buf_len)
1309 break;
1310
1311 last = td;
1312 td = pci_pool_alloc(ep->dev->data_requests, gfp_flags,
1313 &dma_addr);
1314 if (!td)
1315 goto nomem;
1316
1317 i += buf_len;
1318 td->dataptr = req->req.dma + i;
1319 last->next = dma_addr;
1320 }
1321
1322 req->td_data_last = td;
1323 td->status |= PCH_UDC_DMA_LAST;
1324 td->next = req->td_data_phys;
1325 req->chain_len = len;
1326 return 0;
1327
1328nomem:
1329 if (len > 1) {
1330 req->chain_len = len;
1331 pch_udc_free_dma_chain(ep->dev, req);
1332 }
1333 req->chain_len = 1;
1334 return -ENOMEM;
1335}
1336
1337/**
1338 * prepare_dma() - This function creates and initializes the DMA chain
1339 * for the request
1340 * @ep: Reference to the endpoint structure
1341 * @req: Reference to the request
1342 * @gfp: Flag to be used while mapping the data buffer
1343 *
1344 * Return codes:
1345 * 0: Success
1346 * Other 0: linux error number on failure
1347 */
1348static int prepare_dma(struct pch_udc_ep *ep, struct pch_udc_request *req,
1349 gfp_t gfp)
1350{
1351 int retval;
1352
1353 req->td_data->dataptr = req->req.dma;
1354 req->td_data->status |= PCH_UDC_DMA_LAST;
1355 /* Allocate and create a DMA chain */
1356 retval = pch_udc_create_dma_chain(ep, req, ep->ep.maxpacket, gfp);
1357 if (retval) {
1358 pr_err("%s: could not create DMA chain: %d\n",
1359 __func__, retval);
1360 return retval;
1361 }
1362 if (!ep->in)
1363 return 0;
1364 if (req->req.length <= ep->ep.maxpacket)
1365 req->td_data->status = PCH_UDC_DMA_LAST | PCH_UDC_BS_HST_BSY |
1366 req->req.length;
1367 /* if bytes < max packet then tx bytes must
1368 * be written in packet per buffer mode
1369 */
1370 if ((req->req.length < ep->ep.maxpacket) || !ep->num)
1371 req->td_data->status = (req->td_data->status &
1372 ~PCH_UDC_RXTX_BYTES) | req->req.length;
1373 req->td_data->status = (req->td_data->status &
1374 ~PCH_UDC_BUFF_STS) | PCH_UDC_BS_HST_BSY;
1375 return 0;
1376}
1377
1378/**
1379 * process_zlp() - This function process zero length packets
1380 * from the gadget driver
1381 * @ep: Reference to the endpoint structure
1382 * @req: Reference to the request
1383 */
1384static void process_zlp(struct pch_udc_ep *ep, struct pch_udc_request *req)
1385{
1386 struct pch_udc_dev *dev = ep->dev;
1387
1388 /* IN zlp's are handled by hardware */
1389 complete_req(ep, req, 0);
1390
1391 /* if set_config or set_intf is waiting for ack by zlp
1392 * then set CSR_DONE
1393 */
1394 if (dev->set_cfg_not_acked) {
1395 pch_udc_set_csr_done(dev);
1396 dev->set_cfg_not_acked = 0;
1397 }
1398 /* setup command is ACK'ed now by zlp */
1399 if (!dev->stall && dev->waiting_zlp_ack) {
1400 pch_udc_ep_clear_nak(&(dev->ep[UDC_EP0IN_IDX]));
1401 dev->waiting_zlp_ack = 0;
1402 }
1403}
1404
1405/**
1406 * pch_udc_start_rxrequest() - This function starts the receive requirement.
1407 * @ep: Reference to the endpoint structure
1408 * @req: Reference to the request structure
1409 */
1410static void pch_udc_start_rxrequest(struct pch_udc_ep *ep,
1411 struct pch_udc_request *req)
1412{
1413 struct pch_udc_data_dma_desc *td_data;
1414
1415 pch_udc_clear_dma(ep->dev, DMA_DIR_RX);
1416 td_data = req->td_data;
1417 ep->td_data = req->td_data;
1418 /* Set the status bits for all descriptors */
1419 while (1) {
1420 td_data->status = (td_data->status & ~PCH_UDC_BUFF_STS) |
1421 PCH_UDC_BS_HST_RDY;
1422 if ((td_data->status & PCH_UDC_DMA_LAST) == PCH_UDC_DMA_LAST)
1423 break;
1424 td_data = phys_to_virt(td_data->next);
1425 }
1426 /* Write the descriptor pointer */
1427 pch_udc_ep_set_ddptr(ep, req->td_data_phys);
1428 req->dma_going = 1;
1429 pch_udc_enable_ep_interrupts(ep->dev, UDC_EPINT_OUT_EP0 << ep->num);
1430 pch_udc_set_dma(ep->dev, DMA_DIR_RX);
1431 pch_udc_ep_clear_nak(ep);
1432 pch_udc_ep_set_rrdy(ep);
1433}
1434
1435/**
1436 * pch_udc_pcd_ep_enable() - This API enables the endpoint. It is called
1437 * from gadget driver
1438 * @usbep: Reference to the USB endpoint structure
1439 * @desc: Reference to the USB endpoint descriptor structure
1440 *
1441 * Return codes:
1442 * 0: Success
1443 * -EINVAL:
1444 * -ESHUTDOWN:
1445 */
1446static int pch_udc_pcd_ep_enable(struct usb_ep *usbep,
1447 const struct usb_endpoint_descriptor *desc)
1448{
1449 struct pch_udc_ep *ep;
1450 struct pch_udc_dev *dev;
1451 unsigned long iflags;
1452
1453 if (!usbep || (usbep->name == ep0_string) || !desc ||
1454 (desc->bDescriptorType != USB_DT_ENDPOINT) || !desc->wMaxPacketSize)
1455 return -EINVAL;
1456
1457 ep = container_of(usbep, struct pch_udc_ep, ep);
1458 dev = ep->dev;
1459 if (!dev->driver || (dev->gadget.speed == USB_SPEED_UNKNOWN))
1460 return -ESHUTDOWN;
1461 spin_lock_irqsave(&dev->lock, iflags);
1462 ep->desc = desc;
1463 ep->halted = 0;
1464 pch_udc_ep_enable(ep, &ep->dev->cfg_data, desc);
1465 ep->ep.maxpacket = le16_to_cpu(desc->wMaxPacketSize);
1466 pch_udc_enable_ep_interrupts(ep->dev, PCH_UDC_EPINT(ep->in, ep->num));
1467 spin_unlock_irqrestore(&dev->lock, iflags);
1468 return 0;
1469}
1470
1471/**
1472 * pch_udc_pcd_ep_disable() - This API disables endpoint and is called
1473 * from gadget driver
1474 * @usbep Reference to the USB endpoint structure
1475 *
1476 * Return codes:
1477 * 0: Success
1478 * -EINVAL:
1479 */
1480static int pch_udc_pcd_ep_disable(struct usb_ep *usbep)
1481{
1482 struct pch_udc_ep *ep;
1483 struct pch_udc_dev *dev;
1484 unsigned long iflags;
1485
1486 if (!usbep)
1487 return -EINVAL;
1488
1489 ep = container_of(usbep, struct pch_udc_ep, ep);
1490 dev = ep->dev;
1491 if ((usbep->name == ep0_string) || !ep->desc)
1492 return -EINVAL;
1493
1494 spin_lock_irqsave(&ep->dev->lock, iflags);
1495 empty_req_queue(ep);
1496 ep->halted = 1;
1497 pch_udc_ep_disable(ep);
1498 pch_udc_disable_ep_interrupts(ep->dev, PCH_UDC_EPINT(ep->in, ep->num));
1499 ep->desc = NULL;
1500 INIT_LIST_HEAD(&ep->queue);
1501 spin_unlock_irqrestore(&ep->dev->lock, iflags);
1502 return 0;
1503}
1504
1505/**
1506 * pch_udc_alloc_request() - This function allocates request structure.
1507 * It is called by gadget driver
1508 * @usbep: Reference to the USB endpoint structure
1509 * @gfp: Flag to be used while allocating memory
1510 *
1511 * Return codes:
1512 * NULL: Failure
1513 * Allocated address: Success
1514 */
1515static struct usb_request *pch_udc_alloc_request(struct usb_ep *usbep,
1516 gfp_t gfp)
1517{
1518 struct pch_udc_request *req;
1519 struct pch_udc_ep *ep;
1520 struct pch_udc_data_dma_desc *dma_desc;
1521 struct pch_udc_dev *dev;
1522
1523 if (!usbep)
1524 return NULL;
1525 ep = container_of(usbep, struct pch_udc_ep, ep);
1526 dev = ep->dev;
1527 req = kzalloc(sizeof *req, gfp);
1528 if (!req)
1529 return NULL;
1530 req->req.dma = DMA_ADDR_INVALID;
1531 INIT_LIST_HEAD(&req->queue);
1532 if (!ep->dev->dma_addr)
1533 return &req->req;
1534 /* ep0 in requests are allocated from data pool here */
1535 dma_desc = pci_pool_alloc(ep->dev->data_requests, gfp,
1536 &req->td_data_phys);
1537 if (NULL == dma_desc) {
1538 kfree(req);
1539 return NULL;
1540 }
1541 /* prevent from using desc. - set HOST BUSY */
1542 dma_desc->status |= PCH_UDC_BS_HST_BSY;
1543 dma_desc->dataptr = __constant_cpu_to_le32(DMA_ADDR_INVALID);
1544 req->td_data = dma_desc;
1545 req->td_data_last = dma_desc;
1546 req->chain_len = 1;
1547 return &req->req;
1548}
1549
1550/**
1551 * pch_udc_free_request() - This function frees request structure.
1552 * It is called by gadget driver
1553 * @usbep: Reference to the USB endpoint structure
1554 * @usbreq: Reference to the USB request
1555 */
1556static void pch_udc_free_request(struct usb_ep *usbep,
1557 struct usb_request *usbreq)
1558{
1559 struct pch_udc_ep *ep;
1560 struct pch_udc_request *req;
1561 struct pch_udc_dev *dev;
1562
1563 if (!usbep || !usbreq)
1564 return;
1565 ep = container_of(usbep, struct pch_udc_ep, ep);
1566 req = container_of(usbreq, struct pch_udc_request, req);
1567 dev = ep->dev;
1568 if (!list_empty(&req->queue))
1569 dev_err(&dev->pdev->dev, "%s: %s req=0x%p queue not empty\n",
1570 __func__, usbep->name, req);
1571 if (req->td_data != NULL) {
1572 if (req->chain_len > 1)
1573 pch_udc_free_dma_chain(ep->dev, req);
1574 pci_pool_free(ep->dev->data_requests, req->td_data,
1575 req->td_data_phys);
1576 }
1577 kfree(req);
1578}
1579
1580/**
1581 * pch_udc_pcd_queue() - This function queues a request packet. It is called
1582 * by gadget driver
1583 * @usbep: Reference to the USB endpoint structure
1584 * @usbreq: Reference to the USB request
1585 * @gfp: Flag to be used while mapping the data buffer
1586 *
1587 * Return codes:
1588 * 0: Success
1589 * linux error number: Failure
1590 */
1591static int pch_udc_pcd_queue(struct usb_ep *usbep, struct usb_request *usbreq,
1592 gfp_t gfp)
1593{
1594 int retval = 0;
1595 struct pch_udc_ep *ep;
1596 struct pch_udc_dev *dev;
1597 struct pch_udc_request *req;
1598 unsigned long iflags;
1599
1600 if (!usbep || !usbreq || !usbreq->complete || !usbreq->buf)
1601 return -EINVAL;
1602 ep = container_of(usbep, struct pch_udc_ep, ep);
1603 dev = ep->dev;
1604 if (!ep->desc && ep->num)
1605 return -EINVAL;
1606 req = container_of(usbreq, struct pch_udc_request, req);
1607 if (!list_empty(&req->queue))
1608 return -EINVAL;
1609 if (!dev->driver || (dev->gadget.speed == USB_SPEED_UNKNOWN))
1610 return -ESHUTDOWN;
1611 spin_lock_irqsave(&ep->dev->lock, iflags);
1612 /* map the buffer for dma */
1613 if (usbreq->length &&
1614 ((usbreq->dma == DMA_ADDR_INVALID) || !usbreq->dma)) {
1615 if (ep->in)
1616 usbreq->dma = pci_map_single(dev->pdev, usbreq->buf,
1617 usbreq->length, PCI_DMA_TODEVICE);
1618 else
1619 usbreq->dma = pci_map_single(dev->pdev, usbreq->buf,
1620 usbreq->length, PCI_DMA_FROMDEVICE);
1621 req->dma_mapped = 1;
1622 }
1623 if (usbreq->length > 0) {
1624 retval = prepare_dma(ep, req, gfp);
1625 if (retval)
1626 goto probe_end;
1627 }
1628 usbreq->actual = 0;
1629 usbreq->status = -EINPROGRESS;
1630 req->dma_done = 0;
1631 if (list_empty(&ep->queue) && !ep->halted) {
1632 /* no pending transfer, so start this req */
1633 if (!usbreq->length) {
1634 process_zlp(ep, req);
1635 retval = 0;
1636 goto probe_end;
1637 }
1638 if (!ep->in) {
1639 pch_udc_start_rxrequest(ep, req);
1640 } else {
1641 /*
1642 * For IN trfr the descriptors will be programmed and
1643 * P bit will be set when
1644 * we get an IN token
1645 */
1646 pch_udc_wait_ep_stall(ep);
1647 pch_udc_ep_clear_nak(ep);
1648 pch_udc_enable_ep_interrupts(ep->dev, (1 << ep->num));
1649 pch_udc_set_dma(dev, DMA_DIR_TX);
1650 }
1651 }
1652 /* Now add this request to the ep's pending requests */
1653 if (req != NULL)
1654 list_add_tail(&req->queue, &ep->queue);
1655
1656probe_end:
1657 spin_unlock_irqrestore(&dev->lock, iflags);
1658 return retval;
1659}
1660
1661/**
1662 * pch_udc_pcd_dequeue() - This function de-queues a request packet.
1663 * It is called by gadget driver
1664 * @usbep: Reference to the USB endpoint structure
1665 * @usbreq: Reference to the USB request
1666 *
1667 * Return codes:
1668 * 0: Success
1669 * linux error number: Failure
1670 */
1671static int pch_udc_pcd_dequeue(struct usb_ep *usbep,
1672 struct usb_request *usbreq)
1673{
1674 struct pch_udc_ep *ep;
1675 struct pch_udc_request *req;
1676 struct pch_udc_dev *dev;
1677 unsigned long flags;
1678 int ret = -EINVAL;
1679
1680 ep = container_of(usbep, struct pch_udc_ep, ep);
1681 dev = ep->dev;
1682 if (!usbep || !usbreq || (!ep->desc && ep->num))
1683 return ret;
1684 req = container_of(usbreq, struct pch_udc_request, req);
1685 spin_lock_irqsave(&ep->dev->lock, flags);
1686 /* make sure it's still queued on this endpoint */
1687 list_for_each_entry(req, &ep->queue, queue) {
1688 if (&req->req == usbreq) {
1689 pch_udc_ep_set_nak(ep);
1690 if (!list_empty(&req->queue))
1691 complete_req(ep, req, -ECONNRESET);
1692 ret = 0;
1693 break;
1694 }
1695 }
1696 spin_unlock_irqrestore(&ep->dev->lock, flags);
1697 return ret;
1698}
1699
1700/**
1701 * pch_udc_pcd_set_halt() - This function Sets or clear the endpoint halt
1702 * feature
1703 * @usbep: Reference to the USB endpoint structure
1704 * @halt: Specifies whether to set or clear the feature
1705 *
1706 * Return codes:
1707 * 0: Success
1708 * linux error number: Failure
1709 */
1710static int pch_udc_pcd_set_halt(struct usb_ep *usbep, int halt)
1711{
1712 struct pch_udc_ep *ep;
1713 struct pch_udc_dev *dev;
1714 unsigned long iflags;
1715 int ret;
1716
1717 if (!usbep)
1718 return -EINVAL;
1719 ep = container_of(usbep, struct pch_udc_ep, ep);
1720 dev = ep->dev;
1721 if (!ep->desc && !ep->num)
1722 return -EINVAL;
1723 if (!ep->dev->driver || (ep->dev->gadget.speed == USB_SPEED_UNKNOWN))
1724 return -ESHUTDOWN;
1725 spin_lock_irqsave(&udc_stall_spinlock, iflags);
1726 if (list_empty(&ep->queue)) {
1727 if (halt) {
1728 if (ep->num == PCH_UDC_EP0)
1729 ep->dev->stall = 1;
1730 pch_udc_ep_set_stall(ep);
1731 pch_udc_enable_ep_interrupts(ep->dev,
1732 PCH_UDC_EPINT(ep->in,
1733 ep->num));
1734 } else {
1735 pch_udc_ep_clear_stall(ep);
1736 }
1737 ret = 0;
1738 } else {
1739 ret = -EAGAIN;
1740 }
1741 spin_unlock_irqrestore(&udc_stall_spinlock, iflags);
1742 return ret;
1743}
1744
1745/**
1746 * pch_udc_pcd_set_wedge() - This function Sets or clear the endpoint
1747 * halt feature
1748 * @usbep: Reference to the USB endpoint structure
1749 * @halt: Specifies whether to set or clear the feature
1750 *
1751 * Return codes:
1752 * 0: Success
1753 * linux error number: Failure
1754 */
1755static int pch_udc_pcd_set_wedge(struct usb_ep *usbep)
1756{
1757 struct pch_udc_ep *ep;
1758 struct pch_udc_dev *dev;
1759 unsigned long iflags;
1760 int ret;
1761
1762 if (!usbep)
1763 return -EINVAL;
1764 ep = container_of(usbep, struct pch_udc_ep, ep);
1765 dev = ep->dev;
1766 if (!ep->desc && !ep->num)
1767 return -EINVAL;
1768 if (!ep->dev->driver || (ep->dev->gadget.speed == USB_SPEED_UNKNOWN))
1769 return -ESHUTDOWN;
1770 spin_lock_irqsave(&udc_stall_spinlock, iflags);
1771 if (!list_empty(&ep->queue)) {
1772 ret = -EAGAIN;
1773 } else {
1774 if (ep->num == PCH_UDC_EP0)
1775 ep->dev->stall = 1;
1776 pch_udc_ep_set_stall(ep);
1777 pch_udc_enable_ep_interrupts(ep->dev,
1778 PCH_UDC_EPINT(ep->in, ep->num));
1779 ep->dev->prot_stall = 1;
1780 ret = 0;
1781 }
1782 spin_unlock_irqrestore(&udc_stall_spinlock, iflags);
1783 return ret;
1784}
1785
1786/**
1787 * pch_udc_pcd_fifo_flush() - This function Flush the FIFO of specified endpoint
1788 * @usbep: Reference to the USB endpoint structure
1789 */
1790static void pch_udc_pcd_fifo_flush(struct usb_ep *usbep)
1791{
1792 struct pch_udc_ep *ep;
1793
1794 if (!usbep)
1795 return;
1796
1797 ep = container_of(usbep, struct pch_udc_ep, ep);
1798 if (ep->desc || !ep->num)
1799 pch_udc_ep_fifo_flush(ep, ep->in);
1800}
1801
1802static const struct usb_ep_ops pch_udc_ep_ops = {
1803 .enable = pch_udc_pcd_ep_enable,
1804 .disable = pch_udc_pcd_ep_disable,
1805 .alloc_request = pch_udc_alloc_request,
1806 .free_request = pch_udc_free_request,
1807 .queue = pch_udc_pcd_queue,
1808 .dequeue = pch_udc_pcd_dequeue,
1809 .set_halt = pch_udc_pcd_set_halt,
1810 .set_wedge = pch_udc_pcd_set_wedge,
1811 .fifo_status = NULL,
1812 .fifo_flush = pch_udc_pcd_fifo_flush,
1813};
1814
1815/**
1816 * pch_udc_init_setup_buff() - This function initializes the SETUP buffer
1817 * @td_stp: Reference to the SETP buffer structure
1818 */
1819static void pch_udc_init_setup_buff(struct pch_udc_stp_dma_desc *td_stp)
1820{
1821 static u32 pky_marker;
1822
1823 if (!td_stp)
1824 return;
1825 td_stp->reserved = ++pky_marker;
1826 memset(&td_stp->request, 0xFF, sizeof td_stp->request);
1827 td_stp->status = PCH_UDC_BS_HST_RDY;
1828}
1829
1830/**
1831 * pch_udc_start_next_txrequest() - This function starts
1832 * the next transmission requirement
1833 * @ep: Reference to the endpoint structure
1834 */
1835static void pch_udc_start_next_txrequest(struct pch_udc_ep *ep)
1836{
1837 struct pch_udc_request *req;
1838 struct pch_udc_data_dma_desc *td_data;
1839
1840 if (pch_udc_read_ep_control(ep) & UDC_EPCTL_P)
1841 return;
1842
1843 if (list_empty(&ep->queue))
1844 return;
1845
1846 /* next request */
1847 req = list_entry(ep->queue.next, struct pch_udc_request, queue);
1848 if (req->dma_going)
1849 return;
1850 if (!req->td_data)
1851 return;
1852 pch_udc_wait_ep_stall(ep);
1853 req->dma_going = 1;
1854 pch_udc_ep_set_ddptr(ep, 0);
1855 td_data = req->td_data;
1856 while (1) {
1857 td_data->status = (td_data->status & ~PCH_UDC_BUFF_STS) |
1858 PCH_UDC_BS_HST_RDY;
1859 if ((td_data->status & PCH_UDC_DMA_LAST) == PCH_UDC_DMA_LAST)
1860 break;
1861 td_data = phys_to_virt(td_data->next);
1862 }
1863 pch_udc_ep_set_ddptr(ep, req->td_data_phys);
1864 pch_udc_set_dma(ep->dev, DMA_DIR_TX);
1865 pch_udc_ep_set_pd(ep);
1866 pch_udc_enable_ep_interrupts(ep->dev, PCH_UDC_EPINT(ep->in, ep->num));
1867 pch_udc_ep_clear_nak(ep);
1868}
1869
1870/**
1871 * pch_udc_complete_transfer() - This function completes a transfer
1872 * @ep: Reference to the endpoint structure
1873 */
1874static void pch_udc_complete_transfer(struct pch_udc_ep *ep)
1875{
1876 struct pch_udc_request *req;
1877 struct pch_udc_dev *dev = ep->dev;
1878
1879 if (list_empty(&ep->queue))
1880 return;
1881 req = list_entry(ep->queue.next, struct pch_udc_request, queue);
1882 if ((req->td_data_last->status & PCH_UDC_BUFF_STS) !=
1883 PCH_UDC_BS_DMA_DONE)
1884 return;
1885 if ((req->td_data_last->status & PCH_UDC_RXTX_STS) !=
1886 PCH_UDC_RTS_SUCC) {
1887 dev_err(&dev->pdev->dev, "Invalid RXTX status (0x%08x) "
1888 "epstatus=0x%08x\n",
1889 (req->td_data_last->status & PCH_UDC_RXTX_STS),
1890 (int)(ep->epsts));
1891 return;
1892 }
1893
1894 req->req.actual = req->req.length;
1895 req->td_data_last->status = PCH_UDC_BS_HST_BSY | PCH_UDC_DMA_LAST;
1896 req->td_data->status = PCH_UDC_BS_HST_BSY | PCH_UDC_DMA_LAST;
1897 complete_req(ep, req, 0);
1898 req->dma_going = 0;
1899 if (!list_empty(&ep->queue)) {
1900 pch_udc_wait_ep_stall(ep);
1901 pch_udc_ep_clear_nak(ep);
1902 pch_udc_enable_ep_interrupts(ep->dev,
1903 PCH_UDC_EPINT(ep->in, ep->num));
1904 } else {
1905 pch_udc_disable_ep_interrupts(ep->dev,
1906 PCH_UDC_EPINT(ep->in, ep->num));
1907 }
1908}
1909
1910/**
1911 * pch_udc_complete_receiver() - This function completes a receiver
1912 * @ep: Reference to the endpoint structure
1913 */
1914static void pch_udc_complete_receiver(struct pch_udc_ep *ep)
1915{
1916 struct pch_udc_request *req;
1917 struct pch_udc_dev *dev = ep->dev;
1918 unsigned int count;
1919
1920 if (list_empty(&ep->queue))
1921 return;
1922
1923 /* next request */
1924 req = list_entry(ep->queue.next, struct pch_udc_request, queue);
1925 if ((req->td_data_last->status & PCH_UDC_BUFF_STS) !=
1926 PCH_UDC_BS_DMA_DONE)
1927 return;
1928 pch_udc_clear_dma(ep->dev, DMA_DIR_RX);
1929 if ((req->td_data_last->status & PCH_UDC_RXTX_STS) !=
1930 PCH_UDC_RTS_SUCC) {
1931 dev_err(&dev->pdev->dev, "Invalid RXTX status (0x%08x) "
1932 "epstatus=0x%08x\n",
1933 (req->td_data_last->status & PCH_UDC_RXTX_STS),
1934 (int)(ep->epsts));
1935 return;
1936 }
1937 count = req->td_data_last->status & PCH_UDC_RXTX_BYTES;
1938
1939 /* on 64k packets the RXBYTES field is zero */
1940 if (!count && (req->req.length == UDC_DMA_MAXPACKET))
1941 count = UDC_DMA_MAXPACKET;
1942 req->td_data->status |= PCH_UDC_DMA_LAST;
1943 req->td_data_last->status |= PCH_UDC_BS_HST_BSY;
1944
1945 req->dma_going = 0;
1946 req->req.actual = count;
1947 complete_req(ep, req, 0);
1948 /* If there is a new/failed requests try that now */
1949 if (!list_empty(&ep->queue)) {
1950 req = list_entry(ep->queue.next, struct pch_udc_request, queue);
1951 pch_udc_start_rxrequest(ep, req);
1952 }
1953}
1954
1955/**
1956 * pch_udc_svc_data_in() - This function process endpoint interrupts
1957 * for IN endpoints
1958 * @dev: Reference to the device structure
1959 * @ep_num: Endpoint that generated the interrupt
1960 */
1961static void pch_udc_svc_data_in(struct pch_udc_dev *dev, int ep_num)
1962{
1963 u32 epsts;
1964 struct pch_udc_ep *ep;
1965
1966 ep = &dev->ep[2*ep_num];
1967 epsts = ep->epsts;
1968 ep->epsts = 0;
1969
1970 if (!(epsts & (UDC_EPSTS_IN | UDC_EPSTS_BNA | UDC_EPSTS_HE |
1971 UDC_EPSTS_TDC | UDC_EPSTS_RCS | UDC_EPSTS_TXEMPTY |
1972 UDC_EPSTS_RSS | UDC_EPSTS_XFERDONE)))
1973 return;
1974 if ((epsts & UDC_EPSTS_BNA))
1975 return;
1976 if (epsts & UDC_EPSTS_HE)
1977 return;
1978 if (epsts & UDC_EPSTS_RSS) {
1979 pch_udc_ep_set_stall(ep);
1980 pch_udc_enable_ep_interrupts(ep->dev,
1981 PCH_UDC_EPINT(ep->in, ep->num));
1982 }
1983 if (epsts & UDC_EPSTS_RCS)
1984 if (!dev->prot_stall) {
1985 pch_udc_ep_clear_stall(ep);
1986 } else {
1987 pch_udc_ep_set_stall(ep);
1988 pch_udc_enable_ep_interrupts(ep->dev,
1989 PCH_UDC_EPINT(ep->in, ep->num));
1990 }
1991 if (epsts & UDC_EPSTS_TDC)
1992 pch_udc_complete_transfer(ep);
1993 /* On IN interrupt, provide data if we have any */
1994 if ((epsts & UDC_EPSTS_IN) && !(epsts & UDC_EPSTS_RSS) &&
1995 !(epsts & UDC_EPSTS_TDC) && !(epsts & UDC_EPSTS_TXEMPTY))
1996 pch_udc_start_next_txrequest(ep);
1997}
1998
1999/**
2000 * pch_udc_svc_data_out() - Handles interrupts from OUT endpoint
2001 * @dev: Reference to the device structure
2002 * @ep_num: Endpoint that generated the interrupt
2003 */
2004static void pch_udc_svc_data_out(struct pch_udc_dev *dev, int ep_num)
2005{
2006 u32 epsts;
2007 struct pch_udc_ep *ep;
2008 struct pch_udc_request *req = NULL;
2009
2010 ep = &dev->ep[2*ep_num + 1];
2011 epsts = ep->epsts;
2012 ep->epsts = 0;
2013
2014 if ((epsts & UDC_EPSTS_BNA) && (!list_empty(&ep->queue))) {
2015 /* next request */
2016 req = list_entry(ep->queue.next, struct pch_udc_request,
2017 queue);
2018 if ((req->td_data_last->status & PCH_UDC_BUFF_STS) !=
2019 PCH_UDC_BS_DMA_DONE) {
2020 if (!req->dma_going)
2021 pch_udc_start_rxrequest(ep, req);
2022 return;
2023 }
2024 }
2025 if (epsts & UDC_EPSTS_HE)
2026 return;
2027 if (epsts & UDC_EPSTS_RSS)
2028 pch_udc_ep_set_stall(ep);
2029 pch_udc_enable_ep_interrupts(ep->dev,
2030 PCH_UDC_EPINT(ep->in, ep->num));
2031 if (epsts & UDC_EPSTS_RCS)
2032 if (!dev->prot_stall) {
2033 pch_udc_ep_clear_stall(ep);
2034 } else {
2035 pch_udc_ep_set_stall(ep);
2036 pch_udc_enable_ep_interrupts(ep->dev,
2037 PCH_UDC_EPINT(ep->in, ep->num));
2038 }
2039 if (((epsts & UDC_EPSTS_OUT_MASK) >> UDC_EPSTS_OUT_SHIFT) ==
2040 UDC_EPSTS_OUT_DATA) {
2041 if (ep->dev->prot_stall == 1) {
2042 pch_udc_ep_set_stall(ep);
2043 pch_udc_enable_ep_interrupts(ep->dev,
2044 PCH_UDC_EPINT(ep->in, ep->num));
2045 } else {
2046 pch_udc_complete_receiver(ep);
2047 }
2048 }
2049 if (list_empty(&ep->queue))
2050 pch_udc_set_dma(dev, DMA_DIR_RX);
2051}
2052
2053/**
2054 * pch_udc_svc_control_in() - Handle Control IN endpoint interrupts
2055 * @dev: Reference to the device structure
2056 */
2057static void pch_udc_svc_control_in(struct pch_udc_dev *dev)
2058{
2059 u32 epsts;
2060 struct pch_udc_ep *ep;
2061
2062 ep = &dev->ep[UDC_EP0IN_IDX];
2063 epsts = ep->epsts;
2064 ep->epsts = 0;
2065
2066 if (!(epsts & (UDC_EPSTS_IN | UDC_EPSTS_BNA | UDC_EPSTS_HE |
2067 UDC_EPSTS_TDC | UDC_EPSTS_RCS | UDC_EPSTS_TXEMPTY |
2068 UDC_EPSTS_XFERDONE)))
2069 return;
2070 if ((epsts & UDC_EPSTS_BNA))
2071 return;
2072 if (epsts & UDC_EPSTS_HE)
2073 return;
2074 if ((epsts & UDC_EPSTS_TDC) && (!dev->stall))
2075 pch_udc_complete_transfer(ep);
2076 /* On IN interrupt, provide data if we have any */
2077 if ((epsts & UDC_EPSTS_IN) && !(epsts & UDC_EPSTS_TDC) &&
2078 !(epsts & UDC_EPSTS_TXEMPTY))
2079 pch_udc_start_next_txrequest(ep);
2080}
2081
2082/**
2083 * pch_udc_svc_control_out() - Routine that handle Control
2084 * OUT endpoint interrupts
2085 * @dev: Reference to the device structure
2086 */
2087static void pch_udc_svc_control_out(struct pch_udc_dev *dev)
2088{
2089 u32 stat;
2090 int setup_supported;
2091 struct pch_udc_ep *ep;
2092
2093 ep = &dev->ep[UDC_EP0OUT_IDX];
2094 stat = ep->epsts;
2095 ep->epsts = 0;
2096
2097 /* If setup data */
2098 if (((stat & UDC_EPSTS_OUT_MASK) >> UDC_EPSTS_OUT_SHIFT) ==
2099 UDC_EPSTS_OUT_SETUP) {
2100 dev->stall = 0;
2101 dev->ep[UDC_EP0IN_IDX].halted = 0;
2102 dev->ep[UDC_EP0OUT_IDX].halted = 0;
2103 /* In data not ready */
2104 pch_udc_ep_set_nak(&(dev->ep[UDC_EP0IN_IDX]));
2105 dev->setup_data = ep->td_stp->request;
2106 pch_udc_init_setup_buff(ep->td_stp);
2107 pch_udc_clear_dma(dev, DMA_DIR_TX);
2108 pch_udc_ep_fifo_flush(&(dev->ep[UDC_EP0IN_IDX]),
2109 dev->ep[UDC_EP0IN_IDX].in);
2110 if ((dev->setup_data.bRequestType & USB_DIR_IN))
2111 dev->gadget.ep0 = &dev->ep[UDC_EP0IN_IDX].ep;
2112 else /* OUT */
2113 dev->gadget.ep0 = &ep->ep;
2114 spin_unlock(&dev->lock);
2115 /* If Mass storage Reset */
2116 if ((dev->setup_data.bRequestType == 0x21) &&
2117 (dev->setup_data.bRequest == 0xFF))
2118 dev->prot_stall = 0;
2119 /* call gadget with setup data received */
2120 setup_supported = dev->driver->setup(&dev->gadget,
2121 &dev->setup_data);
2122 spin_lock(&dev->lock);
2123 /* ep0 in returns data on IN phase */
2124 if (setup_supported >= 0 && setup_supported <
2125 UDC_EP0IN_MAX_PKT_SIZE) {
2126 pch_udc_ep_clear_nak(&(dev->ep[UDC_EP0IN_IDX]));
2127 /* Gadget would have queued a request when
2128 * we called the setup */
2129 pch_udc_set_dma(dev, DMA_DIR_RX);
2130 pch_udc_ep_clear_nak(ep);
2131 } else if (setup_supported < 0) {
2132 /* if unsupported request, then stall */
2133 pch_udc_ep_set_stall(&(dev->ep[UDC_EP0IN_IDX]));
2134 pch_udc_enable_ep_interrupts(ep->dev,
2135 PCH_UDC_EPINT(ep->in, ep->num));
2136 dev->stall = 0;
2137 pch_udc_set_dma(dev, DMA_DIR_RX);
2138 } else {
2139 dev->waiting_zlp_ack = 1;
2140 }
2141 } else if ((((stat & UDC_EPSTS_OUT_MASK) >> UDC_EPSTS_OUT_SHIFT) ==
2142 UDC_EPSTS_OUT_DATA) && !dev->stall) {
2143 if (list_empty(&ep->queue)) {
2144 dev_err(&dev->pdev->dev, "%s: No request\n", __func__);
2145 ep->td_data->status = (ep->td_data->status &
2146 ~PCH_UDC_BUFF_STS) |
2147 PCH_UDC_BS_HST_RDY;
2148 pch_udc_set_dma(dev, DMA_DIR_RX);
2149 } else {
2150 /* control write */
2151 pch_udc_svc_data_out(dev, UDC_EP0OUT_IDX);
2152 /* re-program desc. pointer for possible ZLPs */
2153 pch_udc_ep_set_ddptr(ep, ep->td_data_phys);
2154 pch_udc_set_dma(dev, DMA_DIR_RX);
2155 }
2156 }
2157 pch_udc_ep_set_rrdy(ep);
2158}
2159
2160
2161/**
2162 * pch_udc_postsvc_epinters() - This function enables end point interrupts
2163 * and clears NAK status
2164 * @dev: Reference to the device structure
2165 * @ep_num: End point number
2166 */
2167static void pch_udc_postsvc_epinters(struct pch_udc_dev *dev, int ep_num)
2168{
2169 struct pch_udc_ep *ep;
2170 struct pch_udc_request *req;
2171
2172 ep = &dev->ep[2*ep_num];
2173 if (!list_empty(&ep->queue)) {
2174 req = list_entry(ep->queue.next, struct pch_udc_request, queue);
2175 pch_udc_enable_ep_interrupts(ep->dev,
2176 PCH_UDC_EPINT(ep->in, ep->num));
2177 pch_udc_ep_clear_nak(ep);
2178 }
2179}
2180
2181/**
2182 * pch_udc_read_all_epstatus() - This function read all endpoint status
2183 * @dev: Reference to the device structure
2184 * @ep_intr: Status of endpoint interrupt
2185 */
2186static void pch_udc_read_all_epstatus(struct pch_udc_dev *dev, u32 ep_intr)
2187{
2188 int i;
2189 struct pch_udc_ep *ep;
2190
2191 for (i = 0; i < PCH_UDC_USED_EP_NUM; i++) {
2192 /* IN */
2193 if (ep_intr & (0x1 << i)) {
2194 ep = &dev->ep[2*i];
2195 ep->epsts = pch_udc_read_ep_status(ep);
2196 pch_udc_clear_ep_status(ep, ep->epsts);
2197 }
2198 /* OUT */
2199 if (ep_intr & (0x10000 << i)) {
2200 ep = &dev->ep[2*i+1];
2201 ep->epsts = pch_udc_read_ep_status(ep);
2202 pch_udc_clear_ep_status(ep, ep->epsts);
2203 }
2204 }
2205}
2206
2207/**
2208 * pch_udc_activate_control_ep() - This function enables the control endpoints
2209 * for traffic after a reset
2210 * @dev: Reference to the device structure
2211 */
2212static void pch_udc_activate_control_ep(struct pch_udc_dev *dev)
2213{
2214 struct pch_udc_ep *ep;
2215 u32 val;
2216
2217 /* Setup the IN endpoint */
2218 ep = &dev->ep[UDC_EP0IN_IDX];
2219 pch_udc_clear_ep_control(ep);
2220 pch_udc_ep_fifo_flush(ep, ep->in);
2221 pch_udc_ep_set_bufsz(ep, UDC_EP0IN_BUFF_SIZE, ep->in);
2222 pch_udc_ep_set_maxpkt(ep, UDC_EP0IN_MAX_PKT_SIZE);
2223 /* Initialize the IN EP Descriptor */
2224 ep->td_data = NULL;
2225 ep->td_stp = NULL;
2226 ep->td_data_phys = 0;
2227 ep->td_stp_phys = 0;
2228
2229 /* Setup the OUT endpoint */
2230 ep = &dev->ep[UDC_EP0OUT_IDX];
2231 pch_udc_clear_ep_control(ep);
2232 pch_udc_ep_fifo_flush(ep, ep->in);
2233 pch_udc_ep_set_bufsz(ep, UDC_EP0OUT_BUFF_SIZE, ep->in);
2234 pch_udc_ep_set_maxpkt(ep, UDC_EP0OUT_MAX_PKT_SIZE);
2235 val = UDC_EP0OUT_MAX_PKT_SIZE << UDC_CSR_NE_MAX_PKT_SHIFT;
2236 pch_udc_write_csr(ep->dev, val, UDC_EP0OUT_IDX);
2237
2238 /* Initialize the SETUP buffer */
2239 pch_udc_init_setup_buff(ep->td_stp);
2240 /* Write the pointer address of dma descriptor */
2241 pch_udc_ep_set_subptr(ep, ep->td_stp_phys);
2242 /* Write the pointer address of Setup descriptor */
2243 pch_udc_ep_set_ddptr(ep, ep->td_data_phys);
2244
2245 /* Initialize the dma descriptor */
2246 ep->td_data->status = PCH_UDC_DMA_LAST;
2247 ep->td_data->dataptr = dev->dma_addr;
2248 ep->td_data->next = ep->td_data_phys;
2249
2250 pch_udc_ep_clear_nak(ep);
2251}
2252
2253
2254/**
2255 * pch_udc_svc_ur_interrupt() - This function handles a USB reset interrupt
2256 * @dev: Reference to driver structure
2257 */
2258static void pch_udc_svc_ur_interrupt(struct pch_udc_dev *dev)
2259{
2260 struct pch_udc_ep *ep;
2261 int i;
2262
2263 pch_udc_clear_dma(dev, DMA_DIR_TX);
2264 pch_udc_clear_dma(dev, DMA_DIR_RX);
2265 /* Mask all endpoint interrupts */
2266 pch_udc_disable_ep_interrupts(dev, UDC_EPINT_MSK_DISABLE_ALL);
2267 /* clear all endpoint interrupts */
2268 pch_udc_write_ep_interrupts(dev, UDC_EPINT_MSK_DISABLE_ALL);
2269
2270 for (i = 0; i < PCH_UDC_EP_NUM; i++) {
2271 ep = &dev->ep[i];
2272 pch_udc_clear_ep_status(ep, UDC_EPSTS_ALL_CLR_MASK);
2273 pch_udc_clear_ep_control(ep);
2274 pch_udc_ep_set_ddptr(ep, 0);
2275 pch_udc_write_csr(ep->dev, 0x00, i);
2276 }
2277 dev->stall = 0;
2278 dev->prot_stall = 0;
2279 dev->waiting_zlp_ack = 0;
2280 dev->set_cfg_not_acked = 0;
2281
2282 /* disable ep to empty req queue. Skip the control EP's */
2283 for (i = 0; i < (PCH_UDC_USED_EP_NUM*2); i++) {
2284 ep = &dev->ep[i];
2285 pch_udc_ep_set_nak(ep);
2286 pch_udc_ep_fifo_flush(ep, ep->in);
2287 /* Complete request queue */
2288 empty_req_queue(ep);
2289 }
2290 if (dev->driver && dev->driver->disconnect)
2291 dev->driver->disconnect(&dev->gadget);
2292}
2293
2294/**
2295 * pch_udc_svc_enum_interrupt() - This function handles a USB speed enumeration
2296 * done interrupt
2297 * @dev: Reference to driver structure
2298 */
2299static void pch_udc_svc_enum_interrupt(struct pch_udc_dev *dev)
2300{
2301 u32 dev_stat, dev_speed;
2302 u32 speed = USB_SPEED_FULL;
2303
2304 dev_stat = pch_udc_read_device_status(dev);
2305 dev_speed = (dev_stat & UDC_DEVSTS_ENUM_SPEED_MASK) >>
2306 UDC_DEVSTS_ENUM_SPEED_SHIFT;
2307 switch (dev_speed) {
2308 case UDC_DEVSTS_ENUM_SPEED_HIGH:
2309 speed = USB_SPEED_HIGH;
2310 break;
2311 case UDC_DEVSTS_ENUM_SPEED_FULL:
2312 speed = USB_SPEED_FULL;
2313 break;
2314 case UDC_DEVSTS_ENUM_SPEED_LOW:
2315 speed = USB_SPEED_LOW;
2316 break;
2317 default:
2318 BUG();
2319 }
2320 dev->gadget.speed = speed;
2321 pch_udc_activate_control_ep(dev);
2322 pch_udc_enable_ep_interrupts(dev, UDC_EPINT_IN_EP0 | UDC_EPINT_OUT_EP0);
2323 pch_udc_set_dma(dev, DMA_DIR_TX);
2324 pch_udc_set_dma(dev, DMA_DIR_RX);
2325 pch_udc_ep_set_rrdy(&(dev->ep[UDC_EP0OUT_IDX]));
2326}
2327
2328/**
2329 * pch_udc_svc_intf_interrupt() - This function handles a set interface
2330 * interrupt
2331 * @dev: Reference to driver structure
2332 */
2333static void pch_udc_svc_intf_interrupt(struct pch_udc_dev *dev)
2334{
2335 u32 reg, dev_stat = 0;
2336 int i, ret;
2337
2338 dev_stat = pch_udc_read_device_status(dev);
2339 dev->cfg_data.cur_intf = (dev_stat & UDC_DEVSTS_INTF_MASK) >>
2340 UDC_DEVSTS_INTF_SHIFT;
2341 dev->cfg_data.cur_alt = (dev_stat & UDC_DEVSTS_ALT_MASK) >>
2342 UDC_DEVSTS_ALT_SHIFT;
2343 dev->set_cfg_not_acked = 1;
2344 /* Construct the usb request for gadget driver and inform it */
2345 memset(&dev->setup_data, 0 , sizeof dev->setup_data);
2346 dev->setup_data.bRequest = USB_REQ_SET_INTERFACE;
2347 dev->setup_data.bRequestType = USB_RECIP_INTERFACE;
2348 dev->setup_data.wValue = cpu_to_le16(dev->cfg_data.cur_alt);
2349 dev->setup_data.wIndex = cpu_to_le16(dev->cfg_data.cur_intf);
2350 /* programm the Endpoint Cfg registers */
2351 /* Only one end point cfg register */
2352 reg = pch_udc_read_csr(dev, UDC_EP0OUT_IDX);
2353 reg = (reg & ~UDC_CSR_NE_INTF_MASK) |
2354 (dev->cfg_data.cur_intf << UDC_CSR_NE_INTF_SHIFT);
2355 reg = (reg & ~UDC_CSR_NE_ALT_MASK) |
2356 (dev->cfg_data.cur_alt << UDC_CSR_NE_ALT_SHIFT);
2357 pch_udc_write_csr(dev, reg, UDC_EP0OUT_IDX);
2358 for (i = 0; i < PCH_UDC_USED_EP_NUM * 2; i++) {
2359 /* clear stall bits */
2360 pch_udc_ep_clear_stall(&(dev->ep[i]));
2361 dev->ep[i].halted = 0;
2362 }
2363 dev->stall = 0;
2364 spin_unlock(&dev->lock);
2365 ret = dev->driver->setup(&dev->gadget, &dev->setup_data);
2366 spin_lock(&dev->lock);
2367}
2368
2369/**
2370 * pch_udc_svc_cfg_interrupt() - This function handles a set configuration
2371 * interrupt
2372 * @dev: Reference to driver structure
2373 */
2374static void pch_udc_svc_cfg_interrupt(struct pch_udc_dev *dev)
2375{
2376 int i, ret;
2377 u32 reg, dev_stat = 0;
2378
2379 dev_stat = pch_udc_read_device_status(dev);
2380 dev->set_cfg_not_acked = 1;
2381 dev->cfg_data.cur_cfg = (dev_stat & UDC_DEVSTS_CFG_MASK) >>
2382 UDC_DEVSTS_CFG_SHIFT;
2383 /* make usb request for gadget driver */
2384 memset(&dev->setup_data, 0 , sizeof dev->setup_data);
2385 dev->setup_data.bRequest = USB_REQ_SET_CONFIGURATION;
2386 dev->setup_data.wValue = cpu_to_le16(dev->cfg_data.cur_cfg);
2387 /* program the NE registers */
2388 /* Only one end point cfg register */
2389 reg = pch_udc_read_csr(dev, UDC_EP0OUT_IDX);
2390 reg = (reg & ~UDC_CSR_NE_CFG_MASK) |
2391 (dev->cfg_data.cur_cfg << UDC_CSR_NE_CFG_SHIFT);
2392 pch_udc_write_csr(dev, reg, UDC_EP0OUT_IDX);
2393 for (i = 0; i < PCH_UDC_USED_EP_NUM * 2; i++) {
2394 /* clear stall bits */
2395 pch_udc_ep_clear_stall(&(dev->ep[i]));
2396 dev->ep[i].halted = 0;
2397 }
2398 dev->stall = 0;
2399
2400 /* call gadget zero with setup data received */
2401 spin_unlock(&dev->lock);
2402 ret = dev->driver->setup(&dev->gadget, &dev->setup_data);
2403 spin_lock(&dev->lock);
2404}
2405
2406/**
2407 * pch_udc_dev_isr() - This function services device interrupts
2408 * by invoking appropriate routines.
2409 * @dev: Reference to the device structure
2410 * @dev_intr: The Device interrupt status.
2411 */
2412static void pch_udc_dev_isr(struct pch_udc_dev *dev, u32 dev_intr)
2413{
2414 /* USB Reset Interrupt */
2415 if (dev_intr & UDC_DEVINT_UR)
2416 pch_udc_svc_ur_interrupt(dev);
2417 /* Enumeration Done Interrupt */
2418 if (dev_intr & UDC_DEVINT_ENUM)
2419 pch_udc_svc_enum_interrupt(dev);
2420 /* Set Interface Interrupt */
2421 if (dev_intr & UDC_DEVINT_SI)
2422 pch_udc_svc_intf_interrupt(dev);
2423 /* Set Config Interrupt */
2424 if (dev_intr & UDC_DEVINT_SC)
2425 pch_udc_svc_cfg_interrupt(dev);
2426 /* USB Suspend interrupt */
2427 if (dev_intr & UDC_DEVINT_US)
2428 dev_dbg(&dev->pdev->dev, "USB_SUSPEND\n");
2429 /* Clear the SOF interrupt, if enabled */
2430 if (dev_intr & UDC_DEVINT_SOF)
2431 dev_dbg(&dev->pdev->dev, "SOF\n");
2432 /* ES interrupt, IDLE > 3ms on the USB */
2433 if (dev_intr & UDC_DEVINT_ES)
2434 dev_dbg(&dev->pdev->dev, "ES\n");
2435 /* RWKP interrupt */
2436 if (dev_intr & UDC_DEVINT_RWKP)
2437 dev_dbg(&dev->pdev->dev, "RWKP\n");
2438}
2439
2440/**
2441 * pch_udc_isr() - This function handles interrupts from the PCH USB Device
2442 * @irq: Interrupt request number
2443 * @dev: Reference to the device structure
2444 */
2445static irqreturn_t pch_udc_isr(int irq, void *pdev)
2446{
2447 struct pch_udc_dev *dev = (struct pch_udc_dev *) pdev;
2448 u32 dev_intr, ep_intr;
2449 int i;
2450
2451 dev_intr = pch_udc_read_device_interrupts(dev);
2452 ep_intr = pch_udc_read_ep_interrupts(dev);
2453
2454 if (dev_intr)
2455 /* Clear device interrupts */
2456 pch_udc_write_device_interrupts(dev, dev_intr);
2457 if (ep_intr)
2458 /* Clear ep interrupts */
2459 pch_udc_write_ep_interrupts(dev, ep_intr);
2460 if (!dev_intr && !ep_intr)
2461 return IRQ_NONE;
2462 spin_lock(&dev->lock);
2463 if (dev_intr)
2464 pch_udc_dev_isr(dev, dev_intr);
2465 if (ep_intr) {
2466 pch_udc_read_all_epstatus(dev, ep_intr);
2467 /* Process Control In interrupts, if present */
2468 if (ep_intr & UDC_EPINT_IN_EP0) {
2469 pch_udc_svc_control_in(dev);
2470 pch_udc_postsvc_epinters(dev, 0);
2471 }
2472 /* Process Control Out interrupts, if present */
2473 if (ep_intr & UDC_EPINT_OUT_EP0)
2474 pch_udc_svc_control_out(dev);
2475 /* Process data in end point interrupts */
2476 for (i = 1; i < PCH_UDC_USED_EP_NUM; i++) {
2477 if (ep_intr & (1 << i)) {
2478 pch_udc_svc_data_in(dev, i);
2479 pch_udc_postsvc_epinters(dev, i);
2480 }
2481 }
2482 /* Process data out end point interrupts */
2483 for (i = UDC_EPINT_OUT_SHIFT + 1; i < (UDC_EPINT_OUT_SHIFT +
2484 PCH_UDC_USED_EP_NUM); i++)
2485 if (ep_intr & (1 << i))
2486 pch_udc_svc_data_out(dev, i -
2487 UDC_EPINT_OUT_SHIFT);
2488 }
2489 spin_unlock(&dev->lock);
2490 return IRQ_HANDLED;
2491}
2492
2493/**
2494 * pch_udc_setup_ep0() - This function enables control endpoint for traffic
2495 * @dev: Reference to the device structure
2496 */
2497static void pch_udc_setup_ep0(struct pch_udc_dev *dev)
2498{
2499 /* enable ep0 interrupts */
2500 pch_udc_enable_ep_interrupts(dev, UDC_EPINT_IN_EP0 |
2501 UDC_EPINT_OUT_EP0);
2502 /* enable device interrupts */
2503 pch_udc_enable_interrupts(dev, UDC_DEVINT_UR | UDC_DEVINT_US |
2504 UDC_DEVINT_ES | UDC_DEVINT_ENUM |
2505 UDC_DEVINT_SI | UDC_DEVINT_SC);
2506}
2507
2508/**
2509 * gadget_release() - Free the gadget driver private data
2510 * @pdev reference to struct pci_dev
2511 */
2512static void gadget_release(struct device *pdev)
2513{
2514 struct pch_udc_dev *dev = dev_get_drvdata(pdev);
2515
2516 kfree(dev);
2517}
2518
2519/**
2520 * pch_udc_pcd_reinit() - This API initializes the endpoint structures
2521 * @dev: Reference to the driver structure
2522 */
2523static void pch_udc_pcd_reinit(struct pch_udc_dev *dev)
2524{
2525 const char *const ep_string[] = {
2526 ep0_string, "ep0out", "ep1in", "ep1out", "ep2in", "ep2out",
2527 "ep3in", "ep3out", "ep4in", "ep4out", "ep5in", "ep5out",
2528 "ep6in", "ep6out", "ep7in", "ep7out", "ep8in", "ep8out",
2529 "ep9in", "ep9out", "ep10in", "ep10out", "ep11in", "ep11out",
2530 "ep12in", "ep12out", "ep13in", "ep13out", "ep14in", "ep14out",
2531 "ep15in", "ep15out",
2532 };
2533 int i;
2534
2535 dev->gadget.speed = USB_SPEED_UNKNOWN;
2536 INIT_LIST_HEAD(&dev->gadget.ep_list);
2537
2538 /* Initialize the endpoints structures */
2539 memset(dev->ep, 0, sizeof dev->ep);
2540 for (i = 0; i < PCH_UDC_EP_NUM; i++) {
2541 struct pch_udc_ep *ep = &dev->ep[i];
2542 ep->dev = dev;
2543 ep->halted = 1;
2544 ep->num = i / 2;
2545 ep->in = ~i & 1;
2546 ep->ep.name = ep_string[i];
2547 ep->ep.ops = &pch_udc_ep_ops;
2548 if (ep->in)
2549 ep->offset_addr = ep->num * UDC_EP_REG_SHIFT;
2550 else
2551 ep->offset_addr = (UDC_EPINT_OUT_SHIFT + ep->num) *
2552 UDC_EP_REG_SHIFT;
2553 /* need to set ep->ep.maxpacket and set Default Configuration?*/
2554 ep->ep.maxpacket = UDC_BULK_MAX_PKT_SIZE;
2555 list_add_tail(&ep->ep.ep_list, &dev->gadget.ep_list);
2556 INIT_LIST_HEAD(&ep->queue);
2557 }
2558 dev->ep[UDC_EP0IN_IDX].ep.maxpacket = UDC_EP0IN_MAX_PKT_SIZE;
2559 dev->ep[UDC_EP0OUT_IDX].ep.maxpacket = UDC_EP0OUT_MAX_PKT_SIZE;
2560
2561 dev->dma_addr = pci_map_single(dev->pdev, dev->ep0out_buf, 256,
2562 PCI_DMA_FROMDEVICE);
2563
2564 /* remove ep0 in and out from the list. They have own pointer */
2565 list_del_init(&dev->ep[UDC_EP0IN_IDX].ep.ep_list);
2566 list_del_init(&dev->ep[UDC_EP0OUT_IDX].ep.ep_list);
2567
2568 dev->gadget.ep0 = &dev->ep[UDC_EP0IN_IDX].ep;
2569 INIT_LIST_HEAD(&dev->gadget.ep0->ep_list);
2570}
2571
2572/**
2573 * pch_udc_pcd_init() - This API initializes the driver structure
2574 * @dev: Reference to the driver structure
2575 *
2576 * Return codes:
2577 * 0: Success
2578 */
2579static int pch_udc_pcd_init(struct pch_udc_dev *dev)
2580{
2581 pch_udc_init(dev);
2582 pch_udc_pcd_reinit(dev);
2583 return 0;
2584}
2585
2586/**
2587 * init_dma_pools() - create dma pools during initialization
2588 * @pdev: reference to struct pci_dev
2589 */
2590static int init_dma_pools(struct pch_udc_dev *dev)
2591{
2592 struct pch_udc_stp_dma_desc *td_stp;
2593 struct pch_udc_data_dma_desc *td_data;
2594
2595 /* DMA setup */
2596 dev->data_requests = pci_pool_create("data_requests", dev->pdev,
2597 sizeof(struct pch_udc_data_dma_desc), 0, 0);
2598 if (!dev->data_requests) {
2599 dev_err(&dev->pdev->dev, "%s: can't get request data pool\n",
2600 __func__);
2601 return -ENOMEM;
2602 }
2603
2604 /* dma desc for setup data */
2605 dev->stp_requests = pci_pool_create("setup requests", dev->pdev,
2606 sizeof(struct pch_udc_stp_dma_desc), 0, 0);
2607 if (!dev->stp_requests) {
2608 dev_err(&dev->pdev->dev, "%s: can't get setup request pool\n",
2609 __func__);
2610 return -ENOMEM;
2611 }
2612 /* setup */
2613 td_stp = pci_pool_alloc(dev->stp_requests, GFP_KERNEL,
2614 &dev->ep[UDC_EP0OUT_IDX].td_stp_phys);
2615 if (!td_stp) {
2616 dev_err(&dev->pdev->dev,
2617 "%s: can't allocate setup dma descriptor\n", __func__);
2618 return -ENOMEM;
2619 }
2620 dev->ep[UDC_EP0OUT_IDX].td_stp = td_stp;
2621
2622 /* data: 0 packets !? */
2623 td_data = pci_pool_alloc(dev->data_requests, GFP_KERNEL,
2624 &dev->ep[UDC_EP0OUT_IDX].td_data_phys);
2625 if (!td_data) {
2626 dev_err(&dev->pdev->dev,
2627 "%s: can't allocate data dma descriptor\n", __func__);
2628 return -ENOMEM;
2629 }
2630 dev->ep[UDC_EP0OUT_IDX].td_data = td_data;
2631 dev->ep[UDC_EP0IN_IDX].td_stp = NULL;
2632 dev->ep[UDC_EP0IN_IDX].td_stp_phys = 0;
2633 dev->ep[UDC_EP0IN_IDX].td_data = NULL;
2634 dev->ep[UDC_EP0IN_IDX].td_data_phys = 0;
2635 return 0;
2636}
2637
2638int usb_gadget_register_driver(struct usb_gadget_driver *driver)
2639{
2640 struct pch_udc_dev *dev = pch_udc;
2641 int retval;
2642
2643 if (!driver || (driver->speed == USB_SPEED_UNKNOWN) || !driver->bind ||
2644 !driver->setup || !driver->unbind || !driver->disconnect) {
2645 dev_err(&dev->pdev->dev,
2646 "%s: invalid driver parameter\n", __func__);
2647 return -EINVAL;
2648 }
2649
2650 if (!dev)
2651 return -ENODEV;
2652
2653 if (dev->driver) {
2654 dev_err(&dev->pdev->dev, "%s: already bound\n", __func__);
2655 return -EBUSY;
2656 }
2657 driver->driver.bus = NULL;
2658 dev->driver = driver;
2659 dev->gadget.dev.driver = &driver->driver;
2660
2661 /* Invoke the bind routine of the gadget driver */
2662 retval = driver->bind(&dev->gadget);
2663
2664 if (retval) {
2665 dev_err(&dev->pdev->dev, "%s: binding to %s returning %d\n",
2666 __func__, driver->driver.name, retval);
2667 dev->driver = NULL;
2668 dev->gadget.dev.driver = NULL;
2669 return retval;
2670 }
2671 /* get ready for ep0 traffic */
2672 pch_udc_setup_ep0(dev);
2673
2674 /* clear SD */
2675 pch_udc_clear_disconnect(dev);
2676
2677 dev->connected = 1;
2678 return 0;
2679}
2680EXPORT_SYMBOL(usb_gadget_register_driver);
2681
2682int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
2683{
2684 struct pch_udc_dev *dev = pch_udc;
2685
2686 if (!dev)
2687 return -ENODEV;
2688
2689 if (!driver || (driver != dev->driver)) {
2690 dev_err(&dev->pdev->dev,
2691 "%s: invalid driver parameter\n", __func__);
2692 return -EINVAL;
2693 }
2694
2695 pch_udc_disable_interrupts(dev, UDC_DEVINT_MSK);
2696
2697 /* Assues that there are no pending requets with this driver */
2698 driver->unbind(&dev->gadget);
2699 dev->gadget.dev.driver = NULL;
2700 dev->driver = NULL;
2701 dev->connected = 0;
2702
2703 /* set SD */
2704 pch_udc_set_disconnect(dev);
2705 return 0;
2706}
2707EXPORT_SYMBOL(usb_gadget_unregister_driver);
2708
2709static void pch_udc_shutdown(struct pci_dev *pdev)
2710{
2711 struct pch_udc_dev *dev = pci_get_drvdata(pdev);
2712
2713 pch_udc_disable_interrupts(dev, UDC_DEVINT_MSK);
2714 pch_udc_disable_ep_interrupts(dev, UDC_EPINT_MSK_DISABLE_ALL);
2715
2716 /* disable the pullup so the host will think we're gone */
2717 pch_udc_set_disconnect(dev);
2718}
2719
2720static void pch_udc_remove(struct pci_dev *pdev)
2721{
2722 struct pch_udc_dev *dev = pci_get_drvdata(pdev);
2723
2724 /* gadget driver must not be registered */
2725 if (dev->driver)
2726 dev_err(&pdev->dev,
2727 "%s: gadget driver still bound!!!\n", __func__);
2728 /* dma pool cleanup */
2729 if (dev->data_requests)
2730 pci_pool_destroy(dev->data_requests);
2731
2732 if (dev->stp_requests) {
2733 /* cleanup DMA desc's for ep0in */
2734 if (dev->ep[UDC_EP0OUT_IDX].td_stp) {
2735 pci_pool_free(dev->stp_requests,
2736 dev->ep[UDC_EP0OUT_IDX].td_stp,
2737 dev->ep[UDC_EP0OUT_IDX].td_stp_phys);
2738 }
2739 if (dev->ep[UDC_EP0OUT_IDX].td_data) {
2740 pci_pool_free(dev->stp_requests,
2741 dev->ep[UDC_EP0OUT_IDX].td_data,
2742 dev->ep[UDC_EP0OUT_IDX].td_data_phys);
2743 }
2744 pci_pool_destroy(dev->stp_requests);
2745 }
2746
2747 pch_udc_exit(dev);
2748
2749 if (dev->irq_registered)
2750 free_irq(pdev->irq, dev);
2751 if (dev->base_addr)
2752 iounmap(dev->base_addr);
2753 if (dev->mem_region)
2754 release_mem_region(dev->phys_addr,
2755 pci_resource_len(pdev, PCH_UDC_PCI_BAR));
2756 if (dev->active)
2757 pci_disable_device(pdev);
2758 if (dev->registered)
2759 device_unregister(&dev->gadget.dev);
2760 kfree(dev);
2761 pci_set_drvdata(pdev, NULL);
2762}
2763
2764#ifdef CONFIG_PM
2765static int pch_udc_suspend(struct pci_dev *pdev, pm_message_t state)
2766{
2767 struct pch_udc_dev *dev = pci_get_drvdata(pdev);
2768
2769 pch_udc_disable_interrupts(dev, UDC_DEVINT_MSK);
2770 pch_udc_disable_ep_interrupts(dev, UDC_EPINT_MSK_DISABLE_ALL);
2771
2772 pci_disable_device(pdev);
2773 pci_enable_wake(pdev, PCI_D3hot, 0);
2774
2775 if (pci_save_state(pdev)) {
2776 dev_err(&pdev->dev,
2777 "%s: could not save PCI config state\n", __func__);
2778 return -ENOMEM;
2779 }
2780 pci_set_power_state(pdev, pci_choose_state(pdev, state));
2781 return 0;
2782}
2783
2784static int pch_udc_resume(struct pci_dev *pdev)
2785{
2786 int ret;
2787
2788 pci_set_power_state(pdev, PCI_D0);
2789 ret = pci_restore_state(pdev);
2790 if (ret) {
2791 dev_err(&pdev->dev, "%s: pci_restore_state failed\n", __func__);
2792 return ret;
2793 }
2794 ret = pci_enable_device(pdev);
2795 if (ret) {
2796 dev_err(&pdev->dev, "%s: pci_enable_device failed\n", __func__);
2797 return ret;
2798 }
2799 pci_enable_wake(pdev, PCI_D3hot, 0);
2800 return 0;
2801}
2802#else
2803#define pch_udc_suspend NULL
2804#define pch_udc_resume NULL
2805#endif /* CONFIG_PM */
2806
2807static int pch_udc_probe(struct pci_dev *pdev,
2808 const struct pci_device_id *id)
2809{
2810 unsigned long resource;
2811 unsigned long len;
2812 int retval;
2813 struct pch_udc_dev *dev;
2814
2815 /* one udc only */
2816 if (pch_udc) {
2817 pr_err("%s: already probed\n", __func__);
2818 return -EBUSY;
2819 }
2820 /* init */
2821 dev = kzalloc(sizeof *dev, GFP_KERNEL);
2822 if (!dev) {
2823 pr_err("%s: no memory for device structure\n", __func__);
2824 return -ENOMEM;
2825 }
2826 /* pci setup */
2827 if (pci_enable_device(pdev) < 0) {
2828 kfree(dev);
2829 pr_err("%s: pci_enable_device failed\n", __func__);
2830 return -ENODEV;
2831 }
2832 dev->active = 1;
2833 pci_set_drvdata(pdev, dev);
2834
2835 /* PCI resource allocation */
2836 resource = pci_resource_start(pdev, 1);
2837 len = pci_resource_len(pdev, 1);
2838
2839 if (!request_mem_region(resource, len, KBUILD_MODNAME)) {
2840 dev_err(&pdev->dev, "%s: pci device used already\n", __func__);
2841 retval = -EBUSY;
2842 goto finished;
2843 }
2844 dev->phys_addr = resource;
2845 dev->mem_region = 1;
2846
2847 dev->base_addr = ioremap_nocache(resource, len);
2848 if (!dev->base_addr) {
2849 pr_err("%s: device memory cannot be mapped\n", __func__);
2850 retval = -ENOMEM;
2851 goto finished;
2852 }
2853 if (!pdev->irq) {
2854 dev_err(&pdev->dev, "%s: irq not set\n", __func__);
2855 retval = -ENODEV;
2856 goto finished;
2857 }
2858 pch_udc = dev;
2859 /* initialize the hardware */
2860 if (pch_udc_pcd_init(dev))
2861 goto finished;
2862 if (request_irq(pdev->irq, pch_udc_isr, IRQF_SHARED, KBUILD_MODNAME,
2863 dev)) {
2864 dev_err(&pdev->dev, "%s: request_irq(%d) fail\n", __func__,
2865 pdev->irq);
2866 retval = -ENODEV;
2867 goto finished;
2868 }
2869 dev->irq = pdev->irq;
2870 dev->irq_registered = 1;
2871
2872 pci_set_master(pdev);
2873 pci_try_set_mwi(pdev);
2874
2875 /* device struct setup */
2876 spin_lock_init(&dev->lock);
2877 dev->pdev = pdev;
2878 dev->gadget.ops = &pch_udc_ops;
2879
2880 retval = init_dma_pools(dev);
2881 if (retval)
2882 goto finished;
2883
2884 dev_set_name(&dev->gadget.dev, "gadget");
2885 dev->gadget.dev.parent = &pdev->dev;
2886 dev->gadget.dev.dma_mask = pdev->dev.dma_mask;
2887 dev->gadget.dev.release = gadget_release;
2888 dev->gadget.name = KBUILD_MODNAME;
2889 dev->gadget.is_dualspeed = 1;
2890
2891 retval = device_register(&dev->gadget.dev);
2892 if (retval)
2893 goto finished;
2894 dev->registered = 1;
2895
2896 /* Put the device in disconnected state till a driver is bound */
2897 pch_udc_set_disconnect(dev);
2898 return 0;
2899
2900finished:
2901 pch_udc_remove(pdev);
2902 return retval;
2903}
2904
2905static const struct pci_device_id pch_udc_pcidev_id[] = {
2906 {
2907 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EG20T_UDC),
2908 .class = (PCI_CLASS_SERIAL_USB << 8) | 0xfe,
2909 .class_mask = 0xffffffff,
2910 },
2911 { 0 },
2912};
2913
2914MODULE_DEVICE_TABLE(pci, pch_udc_pcidev_id);
2915
2916
2917static struct pci_driver pch_udc_driver = {
2918 .name = KBUILD_MODNAME,
2919 .id_table = pch_udc_pcidev_id,
2920 .probe = pch_udc_probe,
2921 .remove = pch_udc_remove,
2922 .suspend = pch_udc_suspend,
2923 .resume = pch_udc_resume,
2924 .shutdown = pch_udc_shutdown,
2925};
2926
2927static int __init pch_udc_pci_init(void)
2928{
2929 return pci_register_driver(&pch_udc_driver);
2930}
2931module_init(pch_udc_pci_init);
2932
2933static void __exit pch_udc_pci_exit(void)
2934{
2935 pci_unregister_driver(&pch_udc_driver);
2936}
2937module_exit(pch_udc_pci_exit);
2938
2939MODULE_DESCRIPTION("Intel EG20T USB Device Controller");
2940MODULE_AUTHOR("OKI SEMICONDUCTOR, <toshiharu-linux@dsn.okisemi.com>");
2941MODULE_LICENSE("GPL");
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-02 11:24:26 -0400