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authorLinus Torvalds <torvalds@linux-foundation.org>2008-07-14 19:06:58 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2008-07-14 19:06:58 -0400
commit85082fd7cbe3173198aac0eb5e85ab1edcc6352c (patch)
treeedbc09b7945994f78668d218fa02e991c3b3b365 /drivers/usb/gadget/omap_udc.h
parent666484f0250db2e016948d63b3ef33e202e3b8d0 (diff)
parent53ffe3b440aa85af6fc4eda09b2d44bcdd312d4d (diff)
Merge branch 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm
* 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm: (241 commits) [ARM] 5171/1: ep93xx: fix compilation of modules using clocks [ARM] 5133/2: at91sam9g20 defconfig file [ARM] 5130/4: Support for the at91sam9g20 [ARM] 5160/1: IOP3XX: gpio/gpiolib support [ARM] at91: Fix NAND FLASH timings for at91sam9x evaluation kits. [ARM] 5084/1: zylonite: Register AC97 device [ARM] 5085/2: PXA: Move AC97 over to the new central device declaration model [ARM] 5120/1: pxa: correct platform driver names for PXA25x and PXA27x UDC drivers [ARM] 5147/1: pxaficp_ir: drop pxa_gpio_mode calls, as pin setting [ARM] 5145/1: PXA2xx: provide api to control IrDA pins state [ARM] 5144/1: pxaficp_ir: cleanup includes [ARM] pxa: remove pxa_set_cken() [ARM] pxa: allow clk aliases [ARM] Feroceon: don't disable BPU on boot [ARM] Orion: LED support for HP mv2120 [ARM] Orion: add RD88F5181L-FXO support [ARM] Orion: add RD88F5181L-GE support [ARM] Orion: add Netgear WNR854T support [ARM] s3c2410_defconfig: update for current build [ARM] Acer n30: Minor style and indentation fixes. ...
Diffstat (limited to 'drivers/usb/gadget/omap_udc.h')
-rw-r--r--drivers/usb/gadget/omap_udc.h61
1 files changed, 30 insertions, 31 deletions
diff --git a/drivers/usb/gadget/omap_udc.h b/drivers/usb/gadget/omap_udc.h
index c6b9cbc7230a..8522bbb12278 100644
--- a/drivers/usb/gadget/omap_udc.h
+++ b/drivers/usb/gadget/omap_udc.h
@@ -8,23 +8,22 @@
8/* 8/*
9 * USB device/endpoint management registers 9 * USB device/endpoint management registers
10 */ 10 */
11#define UDC_REG(offset) __REG16(UDC_BASE + (offset))
12 11
13#define UDC_REV_REG UDC_REG(0x0) /* Revision */ 12#define UDC_REV (UDC_BASE + 0x0) /* Revision */
14#define UDC_EP_NUM_REG UDC_REG(0x4) /* Which endpoint */ 13#define UDC_EP_NUM (UDC_BASE + 0x4) /* Which endpoint */
15# define UDC_SETUP_SEL (1 << 6) 14# define UDC_SETUP_SEL (1 << 6)
16# define UDC_EP_SEL (1 << 5) 15# define UDC_EP_SEL (1 << 5)
17# define UDC_EP_DIR (1 << 4) 16# define UDC_EP_DIR (1 << 4)
18 /* low 4 bits for endpoint number */ 17 /* low 4 bits for endpoint number */
19#define UDC_DATA_REG UDC_REG(0x08) /* Endpoint FIFO */ 18#define UDC_DATA (UDC_BASE + 0x08) /* Endpoint FIFO */
20#define UDC_CTRL_REG UDC_REG(0x0C) /* Endpoint control */ 19#define UDC_CTRL (UDC_BASE + 0x0C) /* Endpoint control */
21# define UDC_CLR_HALT (1 << 7) 20# define UDC_CLR_HALT (1 << 7)
22# define UDC_SET_HALT (1 << 6) 21# define UDC_SET_HALT (1 << 6)
23# define UDC_CLRDATA_TOGGLE (1 << 3) 22# define UDC_CLRDATA_TOGGLE (1 << 3)
24# define UDC_SET_FIFO_EN (1 << 2) 23# define UDC_SET_FIFO_EN (1 << 2)
25# define UDC_CLR_EP (1 << 1) 24# define UDC_CLR_EP (1 << 1)
26# define UDC_RESET_EP (1 << 0) 25# define UDC_RESET_EP (1 << 0)
27#define UDC_STAT_FLG_REG UDC_REG(0x10) /* Endpoint status */ 26#define UDC_STAT_FLG (UDC_BASE + 0x10) /* Endpoint status */
28# define UDC_NO_RXPACKET (1 << 15) 27# define UDC_NO_RXPACKET (1 << 15)
29# define UDC_MISS_IN (1 << 14) 28# define UDC_MISS_IN (1 << 14)
30# define UDC_DATA_FLUSH (1 << 13) 29# define UDC_DATA_FLUSH (1 << 13)
@@ -38,8 +37,8 @@
38# define UDC_FIFO_EN (1 << 2) 37# define UDC_FIFO_EN (1 << 2)
39# define UDC_NON_ISO_FIFO_EMPTY (1 << 1) 38# define UDC_NON_ISO_FIFO_EMPTY (1 << 1)
40# define UDC_NON_ISO_FIFO_FULL (1 << 0) 39# define UDC_NON_ISO_FIFO_FULL (1 << 0)
41#define UDC_RXFSTAT_REG UDC_REG(0x14) /* OUT bytecount */ 40#define UDC_RXFSTAT (UDC_BASE + 0x14) /* OUT bytecount */
42#define UDC_SYSCON1_REG UDC_REG(0x18) /* System config 1 */ 41#define UDC_SYSCON1 (UDC_BASE + 0x18) /* System config 1 */
43# define UDC_CFG_LOCK (1 << 8) 42# define UDC_CFG_LOCK (1 << 8)
44# define UDC_DATA_ENDIAN (1 << 7) 43# define UDC_DATA_ENDIAN (1 << 7)
45# define UDC_DMA_ENDIAN (1 << 6) 44# define UDC_DMA_ENDIAN (1 << 6)
@@ -48,12 +47,12 @@
48# define UDC_SELF_PWR (1 << 2) 47# define UDC_SELF_PWR (1 << 2)
49# define UDC_SOFF_DIS (1 << 1) 48# define UDC_SOFF_DIS (1 << 1)
50# define UDC_PULLUP_EN (1 << 0) 49# define UDC_PULLUP_EN (1 << 0)
51#define UDC_SYSCON2_REG UDC_REG(0x1C) /* System config 2 */ 50#define UDC_SYSCON2 (UDC_BASE + 0x1C) /* System config 2 */
52# define UDC_RMT_WKP (1 << 6) 51# define UDC_RMT_WKP (1 << 6)
53# define UDC_STALL_CMD (1 << 5) 52# define UDC_STALL_CMD (1 << 5)
54# define UDC_DEV_CFG (1 << 3) 53# define UDC_DEV_CFG (1 << 3)
55# define UDC_CLR_CFG (1 << 2) 54# define UDC_CLR_CFG (1 << 2)
56#define UDC_DEVSTAT_REG UDC_REG(0x20) /* Device status */ 55#define UDC_DEVSTAT (UDC_BASE + 0x20) /* Device status */
57# define UDC_B_HNP_ENABLE (1 << 9) 56# define UDC_B_HNP_ENABLE (1 << 9)
58# define UDC_A_HNP_SUPPORT (1 << 8) 57# define UDC_A_HNP_SUPPORT (1 << 8)
59# define UDC_A_ALT_HNP_SUPPORT (1 << 7) 58# define UDC_A_ALT_HNP_SUPPORT (1 << 7)
@@ -64,26 +63,26 @@
64# define UDC_ADD (1 << 2) 63# define UDC_ADD (1 << 2)
65# define UDC_DEF (1 << 1) 64# define UDC_DEF (1 << 1)
66# define UDC_ATT (1 << 0) 65# define UDC_ATT (1 << 0)
67#define UDC_SOF_REG UDC_REG(0x24) /* Start of frame */ 66#define UDC_SOF (UDC_BASE + 0x24) /* Start of frame */
68# define UDC_FT_LOCK (1 << 12) 67# define UDC_FT_LOCK (1 << 12)
69# define UDC_TS_OK (1 << 11) 68# define UDC_TS_OK (1 << 11)
70# define UDC_TS 0x03ff 69# define UDC_TS 0x03ff
71#define UDC_IRQ_EN_REG UDC_REG(0x28) /* Interrupt enable */ 70#define UDC_IRQ_EN (UDC_BASE + 0x28) /* Interrupt enable */
72# define UDC_SOF_IE (1 << 7) 71# define UDC_SOF_IE (1 << 7)
73# define UDC_EPN_RX_IE (1 << 5) 72# define UDC_EPN_RX_IE (1 << 5)
74# define UDC_EPN_TX_IE (1 << 4) 73# define UDC_EPN_TX_IE (1 << 4)
75# define UDC_DS_CHG_IE (1 << 3) 74# define UDC_DS_CHG_IE (1 << 3)
76# define UDC_EP0_IE (1 << 0) 75# define UDC_EP0_IE (1 << 0)
77#define UDC_DMA_IRQ_EN_REG UDC_REG(0x2C) /* DMA irq enable */ 76#define UDC_DMA_IRQ_EN (UDC_BASE + 0x2C) /* DMA irq enable */
78 /* rx/tx dma channels numbered 1-3 not 0-2 */ 77 /* rx/tx dma channels numbered 1-3 not 0-2 */
79# define UDC_TX_DONE_IE(n) (1 << (4 * (n) - 2)) 78# define UDC_TX_DONE_IE(n) (1 << (4 * (n) - 2))
80# define UDC_RX_CNT_IE(n) (1 << (4 * (n) - 3)) 79# define UDC_RX_CNT_IE(n) (1 << (4 * (n) - 3))
81# define UDC_RX_EOT_IE(n) (1 << (4 * (n) - 4)) 80# define UDC_RX_EOT_IE(n) (1 << (4 * (n) - 4))
82#define UDC_IRQ_SRC_REG UDC_REG(0x30) /* Interrupt source */ 81#define UDC_IRQ_SRC (UDC_BASE + 0x30) /* Interrupt source */
83# define UDC_TXN_DONE (1 << 10) 82# define UDC_TXN_DONE (1 << 10)
84# define UDC_RXN_CNT (1 << 9) 83# define UDC_RXN_CNT (1 << 9)
85# define UDC_RXN_EOT (1 << 8) 84# define UDC_RXN_EOT (1 << 8)
86# define UDC_SOF (1 << 7) 85# define UDC_IRQ_SOF (1 << 7)
87# define UDC_EPN_RX (1 << 5) 86# define UDC_EPN_RX (1 << 5)
88# define UDC_EPN_TX (1 << 4) 87# define UDC_EPN_TX (1 << 4)
89# define UDC_DS_CHG (1 << 3) 88# define UDC_DS_CHG (1 << 3)
@@ -91,41 +90,41 @@
91# define UDC_EP0_RX (1 << 1) 90# define UDC_EP0_RX (1 << 1)
92# define UDC_EP0_TX (1 << 0) 91# define UDC_EP0_TX (1 << 0)
93# define UDC_IRQ_SRC_MASK 0x7bf 92# define UDC_IRQ_SRC_MASK 0x7bf
94#define UDC_EPN_STAT_REG UDC_REG(0x34) /* EP irq status */ 93#define UDC_EPN_STAT (UDC_BASE + 0x34) /* EP irq status */
95#define UDC_DMAN_STAT_REG UDC_REG(0x38) /* DMA irq status */ 94#define UDC_DMAN_STAT (UDC_BASE + 0x38) /* DMA irq status */
96# define UDC_DMA_RX_SB (1 << 12) 95# define UDC_DMA_RX_SB (1 << 12)
97# define UDC_DMA_RX_SRC(x) (((x)>>8) & 0xf) 96# define UDC_DMA_RX_SRC(x) (((x)>>8) & 0xf)
98# define UDC_DMA_TX_SRC(x) (((x)>>0) & 0xf) 97# define UDC_DMA_TX_SRC(x) (((x)>>0) & 0xf)
99 98
100 99
101/* DMA configuration registers: up to three channels in each direction. */ 100/* DMA configuration registers: up to three channels in each direction. */
102#define UDC_RXDMA_CFG_REG UDC_REG(0x40) /* 3 eps for RX DMA */ 101#define UDC_RXDMA_CFG (UDC_BASE + 0x40) /* 3 eps for RX DMA */
103# define UDC_DMA_REQ (1 << 12) 102# define UDC_DMA_REQ (1 << 12)
104#define UDC_TXDMA_CFG_REG UDC_REG(0x44) /* 3 eps for TX DMA */ 103#define UDC_TXDMA_CFG (UDC_BASE + 0x44) /* 3 eps for TX DMA */
105#define UDC_DATA_DMA_REG UDC_REG(0x48) /* rx/tx fifo addr */ 104#define UDC_DATA_DMA (UDC_BASE + 0x48) /* rx/tx fifo addr */
106 105
107/* rx/tx dma control, numbering channels 1-3 not 0-2 */ 106/* rx/tx dma control, numbering channels 1-3 not 0-2 */
108#define UDC_TXDMA_REG(chan) UDC_REG(0x50 - 4 + 4 * (chan)) 107#define UDC_TXDMA(chan) (UDC_BASE + 0x50 - 4 + 4 * (chan))
109# define UDC_TXN_EOT (1 << 15) /* bytes vs packets */ 108# define UDC_TXN_EOT (1 << 15) /* bytes vs packets */
110# define UDC_TXN_START (1 << 14) /* start transfer */ 109# define UDC_TXN_START (1 << 14) /* start transfer */
111# define UDC_TXN_TSC 0x03ff /* units in xfer */ 110# define UDC_TXN_TSC 0x03ff /* units in xfer */
112#define UDC_RXDMA_REG(chan) UDC_REG(0x60 - 4 + 4 * (chan)) 111#define UDC_RXDMA(chan) (UDC_BASE + 0x60 - 4 + 4 * (chan))
113# define UDC_RXN_STOP (1 << 15) /* enable EOT irq */ 112# define UDC_RXN_STOP (1 << 15) /* enable EOT irq */
114# define UDC_RXN_TC 0x00ff /* packets in xfer */ 113# define UDC_RXN_TC 0x00ff /* packets in xfer */
115 114
116 115
117/* 116/*
118 * Endpoint configuration registers (used before CFG_LOCK is set) 117 * Endpoint configuration registers (used before CFG_LOCK is set)
119 * UDC_EP_TX_REG(0) is unused 118 * UDC_EP_TX(0) is unused
120 */ 119 */
121#define UDC_EP_RX_REG(endpoint) UDC_REG(0x80 + (endpoint)*4) 120#define UDC_EP_RX(endpoint) (UDC_BASE + 0x80 + (endpoint)*4)
122# define UDC_EPN_RX_VALID (1 << 15) 121# define UDC_EPN_RX_VALID (1 << 15)
123# define UDC_EPN_RX_DB (1 << 14) 122# define UDC_EPN_RX_DB (1 << 14)
124 /* buffer size in bits 13, 12 */ 123 /* buffer size in bits 13, 12 */
125# define UDC_EPN_RX_ISO (1 << 11) 124# define UDC_EPN_RX_ISO (1 << 11)
126 /* buffer pointer in low 11 bits */ 125 /* buffer pointer in low 11 bits */
127#define UDC_EP_TX_REG(endpoint) UDC_REG(0xc0 + (endpoint)*4) 126#define UDC_EP_TX(endpoint) (UDC_BASE + 0xc0 + (endpoint)*4)
128 /* same bitfields as in RX_REG */ 127 /* same bitfields as in RX */
129 128
130/*-------------------------------------------------------------------------*/ 129/*-------------------------------------------------------------------------*/
131 130
@@ -195,14 +194,14 @@ struct omap_udc {
195 194
196/*-------------------------------------------------------------------------*/ 195/*-------------------------------------------------------------------------*/
197 196
198#define MOD_CONF_CTRL_0_REG __REG32(MOD_CONF_CTRL_0) 197/* MOD_CONF_CTRL_0 */
199#define VBUS_W2FC_1510 (1 << 17) /* 0 gpio0, 1 dvdd2 pin */ 198#define VBUS_W2FC_1510 (1 << 17) /* 0 gpio0, 1 dvdd2 pin */
200 199
201#define FUNC_MUX_CTRL_0_REG __REG32(FUNC_MUX_CTRL_0) 200/* FUNC_MUX_CTRL_0 */
202#define VBUS_CTRL_1510 (1 << 19) /* 1 connected (software) */ 201#define VBUS_CTRL_1510 (1 << 19) /* 1 connected (software) */
203#define VBUS_MODE_1510 (1 << 18) /* 0 hardware, 1 software */ 202#define VBUS_MODE_1510 (1 << 18) /* 0 hardware, 1 software */
204 203
205#define HMC_1510 ((MOD_CONF_CTRL_0_REG >> 1) & 0x3f) 204#define HMC_1510 ((omap_readl(MOD_CONF_CTRL_0) >> 1) & 0x3f)
206#define HMC_1610 (OTG_SYSCON_2_REG & 0x3f) 205#define HMC_1610 (omap_readl(OTG_SYSCON_2) & 0x3f)
207#define HMC (cpu_is_omap15xx() ? HMC_1510 : HMC_1610) 206#define HMC (cpu_is_omap15xx() ? HMC_1510 : HMC_1610)
208 207
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