diff options
author | Tony Lindgren <tony@atomide.com> | 2008-07-03 05:24:43 -0400 |
---|---|---|
committer | Tony Lindgren <tony@atomide.com> | 2008-07-03 05:24:43 -0400 |
commit | f35ae6346850f6c192269b09088b20261760f0e0 (patch) | |
tree | 3ec954ee3aa2d37a34f00a88d25260685d1f2db6 /drivers/usb/gadget/omap_udc.c | |
parent | 030b15457d8069a6255579a28db196e002cb9c86 (diff) |
ARM: OMAP: USB: Change omap USB code to use omap_read/write instead of __REG
Change omap USB code to use omap_read/write instead of __REG for multi-omap
Cc: David Brownell <david-b@pacbell.net>
Cc: linux-usb@vger.kernel.org
Cc: i2c@lm-sensors.org
Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'drivers/usb/gadget/omap_udc.c')
-rw-r--r-- | drivers/usb/gadget/omap_udc.c | 468 |
1 files changed, 261 insertions, 207 deletions
diff --git a/drivers/usb/gadget/omap_udc.c b/drivers/usb/gadget/omap_udc.c index 86c029a8d998..03a7f49d207d 100644 --- a/drivers/usb/gadget/omap_udc.c +++ b/drivers/usb/gadget/omap_udc.c | |||
@@ -135,13 +135,17 @@ static void use_ep(struct omap_ep *ep, u16 select) | |||
135 | 135 | ||
136 | if (ep->bEndpointAddress & USB_DIR_IN) | 136 | if (ep->bEndpointAddress & USB_DIR_IN) |
137 | num |= UDC_EP_DIR; | 137 | num |= UDC_EP_DIR; |
138 | UDC_EP_NUM_REG = num | select; | 138 | omap_writew(num | select, UDC_EP_NUM); |
139 | /* when select, MUST deselect later !! */ | 139 | /* when select, MUST deselect later !! */ |
140 | } | 140 | } |
141 | 141 | ||
142 | static inline void deselect_ep(void) | 142 | static inline void deselect_ep(void) |
143 | { | 143 | { |
144 | UDC_EP_NUM_REG &= ~UDC_EP_SEL; | 144 | u16 w; |
145 | |||
146 | w = omap_readw(UDC_EP_NUM); | ||
147 | w &= ~UDC_EP_SEL; | ||
148 | omap_writew(w, UDC_EP_NUM); | ||
145 | /* 6 wait states before TX will happen */ | 149 | /* 6 wait states before TX will happen */ |
146 | } | 150 | } |
147 | 151 | ||
@@ -216,7 +220,7 @@ static int omap_ep_enable(struct usb_ep *_ep, | |||
216 | ep->has_dma = 0; | 220 | ep->has_dma = 0; |
217 | ep->lch = -1; | 221 | ep->lch = -1; |
218 | use_ep(ep, UDC_EP_SEL); | 222 | use_ep(ep, UDC_EP_SEL); |
219 | UDC_CTRL_REG = udc->clr_halt; | 223 | omap_writew(udc->clr_halt, UDC_CTRL); |
220 | ep->ackwait = 0; | 224 | ep->ackwait = 0; |
221 | deselect_ep(); | 225 | deselect_ep(); |
222 | 226 | ||
@@ -232,7 +236,7 @@ static int omap_ep_enable(struct usb_ep *_ep, | |||
232 | if (desc->bmAttributes != USB_ENDPOINT_XFER_ISOC | 236 | if (desc->bmAttributes != USB_ENDPOINT_XFER_ISOC |
233 | && !ep->has_dma | 237 | && !ep->has_dma |
234 | && !(ep->bEndpointAddress & USB_DIR_IN)) { | 238 | && !(ep->bEndpointAddress & USB_DIR_IN)) { |
235 | UDC_CTRL_REG = UDC_SET_FIFO_EN; | 239 | omap_writew(UDC_SET_FIFO_EN, UDC_CTRL); |
236 | ep->ackwait = 1 + ep->double_buf; | 240 | ep->ackwait = 1 + ep->double_buf; |
237 | } | 241 | } |
238 | 242 | ||
@@ -259,7 +263,7 @@ static int omap_ep_disable(struct usb_ep *_ep) | |||
259 | nuke (ep, -ESHUTDOWN); | 263 | nuke (ep, -ESHUTDOWN); |
260 | ep->ep.maxpacket = ep->maxpacket; | 264 | ep->ep.maxpacket = ep->maxpacket; |
261 | ep->has_dma = 0; | 265 | ep->has_dma = 0; |
262 | UDC_CTRL_REG = UDC_SET_HALT; | 266 | omap_writew(UDC_SET_HALT, UDC_CTRL); |
263 | list_del_init(&ep->iso); | 267 | list_del_init(&ep->iso); |
264 | del_timer(&ep->timer); | 268 | del_timer(&ep->timer); |
265 | 269 | ||
@@ -360,13 +364,13 @@ write_packet(u8 *buf, struct omap_req *req, unsigned max) | |||
360 | if (likely((((int)buf) & 1) == 0)) { | 364 | if (likely((((int)buf) & 1) == 0)) { |
361 | wp = (u16 *)buf; | 365 | wp = (u16 *)buf; |
362 | while (max >= 2) { | 366 | while (max >= 2) { |
363 | UDC_DATA_REG = *wp++; | 367 | omap_writew(*wp++, UDC_DATA); |
364 | max -= 2; | 368 | max -= 2; |
365 | } | 369 | } |
366 | buf = (u8 *)wp; | 370 | buf = (u8 *)wp; |
367 | } | 371 | } |
368 | while (max--) | 372 | while (max--) |
369 | *(volatile u8 *)&UDC_DATA_REG = *buf++; | 373 | omap_writeb(*buf++, UDC_DATA); |
370 | return len; | 374 | return len; |
371 | } | 375 | } |
372 | 376 | ||
@@ -385,13 +389,13 @@ static int write_fifo(struct omap_ep *ep, struct omap_req *req) | |||
385 | prefetch(buf); | 389 | prefetch(buf); |
386 | 390 | ||
387 | /* PIO-IN isn't double buffered except for iso */ | 391 | /* PIO-IN isn't double buffered except for iso */ |
388 | ep_stat = UDC_STAT_FLG_REG; | 392 | ep_stat = omap_readw(UDC_STAT_FLG); |
389 | if (ep_stat & UDC_FIFO_UNWRITABLE) | 393 | if (ep_stat & UDC_FIFO_UNWRITABLE) |
390 | return 0; | 394 | return 0; |
391 | 395 | ||
392 | count = ep->ep.maxpacket; | 396 | count = ep->ep.maxpacket; |
393 | count = write_packet(buf, req, count); | 397 | count = write_packet(buf, req, count); |
394 | UDC_CTRL_REG = UDC_SET_FIFO_EN; | 398 | omap_writew(UDC_SET_FIFO_EN, UDC_CTRL); |
395 | ep->ackwait = 1; | 399 | ep->ackwait = 1; |
396 | 400 | ||
397 | /* last packet is often short (sometimes a zlp) */ | 401 | /* last packet is often short (sometimes a zlp) */ |
@@ -425,13 +429,13 @@ read_packet(u8 *buf, struct omap_req *req, unsigned avail) | |||
425 | if (likely((((int)buf) & 1) == 0)) { | 429 | if (likely((((int)buf) & 1) == 0)) { |
426 | wp = (u16 *)buf; | 430 | wp = (u16 *)buf; |
427 | while (avail >= 2) { | 431 | while (avail >= 2) { |
428 | *wp++ = UDC_DATA_REG; | 432 | *wp++ = omap_readw(UDC_DATA); |
429 | avail -= 2; | 433 | avail -= 2; |
430 | } | 434 | } |
431 | buf = (u8 *)wp; | 435 | buf = (u8 *)wp; |
432 | } | 436 | } |
433 | while (avail--) | 437 | while (avail--) |
434 | *buf++ = *(volatile u8 *)&UDC_DATA_REG; | 438 | *buf++ = omap_readb(UDC_DATA); |
435 | return len; | 439 | return len; |
436 | } | 440 | } |
437 | 441 | ||
@@ -446,7 +450,7 @@ static int read_fifo(struct omap_ep *ep, struct omap_req *req) | |||
446 | prefetchw(buf); | 450 | prefetchw(buf); |
447 | 451 | ||
448 | for (;;) { | 452 | for (;;) { |
449 | u16 ep_stat = UDC_STAT_FLG_REG; | 453 | u16 ep_stat = omap_readw(UDC_STAT_FLG); |
450 | 454 | ||
451 | is_last = 0; | 455 | is_last = 0; |
452 | if (ep_stat & FIFO_EMPTY) { | 456 | if (ep_stat & FIFO_EMPTY) { |
@@ -460,7 +464,7 @@ static int read_fifo(struct omap_ep *ep, struct omap_req *req) | |||
460 | if (ep_stat & UDC_FIFO_FULL) | 464 | if (ep_stat & UDC_FIFO_FULL) |
461 | avail = ep->ep.maxpacket; | 465 | avail = ep->ep.maxpacket; |
462 | else { | 466 | else { |
463 | avail = UDC_RXFSTAT_REG; | 467 | avail = omap_readw(UDC_RXFSTAT); |
464 | ep->fnf = ep->double_buf; | 468 | ep->fnf = ep->double_buf; |
465 | } | 469 | } |
466 | count = read_packet(buf, req, avail); | 470 | count = read_packet(buf, req, avail); |
@@ -473,7 +477,7 @@ static int read_fifo(struct omap_ep *ep, struct omap_req *req) | |||
473 | req->req.status = -EOVERFLOW; | 477 | req->req.status = -EOVERFLOW; |
474 | avail -= count; | 478 | avail -= count; |
475 | while (avail--) | 479 | while (avail--) |
476 | (void) *(volatile u8 *)&UDC_DATA_REG; | 480 | omap_readw(UDC_DATA); |
477 | } | 481 | } |
478 | } else if (req->req.length == req->req.actual) | 482 | } else if (req->req.length == req->req.actual) |
479 | is_last = 1; | 483 | is_last = 1; |
@@ -535,7 +539,7 @@ static u16 dma_dest_len(struct omap_ep *ep, dma_addr_t start) | |||
535 | 539 | ||
536 | static void next_in_dma(struct omap_ep *ep, struct omap_req *req) | 540 | static void next_in_dma(struct omap_ep *ep, struct omap_req *req) |
537 | { | 541 | { |
538 | u16 txdma_ctrl; | 542 | u16 txdma_ctrl, w; |
539 | unsigned length = req->req.length - req->req.actual; | 543 | unsigned length = req->req.length - req->req.actual; |
540 | const int sync_mode = cpu_is_omap15xx() | 544 | const int sync_mode = cpu_is_omap15xx() |
541 | ? OMAP_DMA_SYNC_FRAME | 545 | ? OMAP_DMA_SYNC_FRAME |
@@ -567,13 +571,17 @@ static void next_in_dma(struct omap_ep *ep, struct omap_req *req) | |||
567 | 571 | ||
568 | omap_start_dma(ep->lch); | 572 | omap_start_dma(ep->lch); |
569 | ep->dma_counter = omap_get_dma_src_pos(ep->lch); | 573 | ep->dma_counter = omap_get_dma_src_pos(ep->lch); |
570 | UDC_DMA_IRQ_EN_REG |= UDC_TX_DONE_IE(ep->dma_channel); | 574 | w = omap_readw(UDC_DMA_IRQ_EN); |
571 | UDC_TXDMA_REG(ep->dma_channel) = UDC_TXN_START | txdma_ctrl; | 575 | w |= UDC_TX_DONE_IE(ep->dma_channel); |
576 | omap_writew(w, UDC_DMA_IRQ_EN); | ||
577 | omap_writew(UDC_TXN_START | txdma_ctrl, UDC_TXDMA(ep->dma_channel)); | ||
572 | req->dma_bytes = length; | 578 | req->dma_bytes = length; |
573 | } | 579 | } |
574 | 580 | ||
575 | static void finish_in_dma(struct omap_ep *ep, struct omap_req *req, int status) | 581 | static void finish_in_dma(struct omap_ep *ep, struct omap_req *req, int status) |
576 | { | 582 | { |
583 | u16 w; | ||
584 | |||
577 | if (status == 0) { | 585 | if (status == 0) { |
578 | req->req.actual += req->dma_bytes; | 586 | req->req.actual += req->dma_bytes; |
579 | 587 | ||
@@ -590,7 +598,9 @@ static void finish_in_dma(struct omap_ep *ep, struct omap_req *req, int status) | |||
590 | 598 | ||
591 | /* tx completion */ | 599 | /* tx completion */ |
592 | omap_stop_dma(ep->lch); | 600 | omap_stop_dma(ep->lch); |
593 | UDC_DMA_IRQ_EN_REG &= ~UDC_TX_DONE_IE(ep->dma_channel); | 601 | w = omap_readw(UDC_DMA_IRQ_EN); |
602 | w &= ~UDC_TX_DONE_IE(ep->dma_channel); | ||
603 | omap_writew(w, UDC_DMA_IRQ_EN); | ||
594 | done(ep, req, status); | 604 | done(ep, req, status); |
595 | } | 605 | } |
596 | 606 | ||
@@ -598,6 +608,7 @@ static void next_out_dma(struct omap_ep *ep, struct omap_req *req) | |||
598 | { | 608 | { |
599 | unsigned packets = req->req.length - req->req.actual; | 609 | unsigned packets = req->req.length - req->req.actual; |
600 | int dma_trigger = 0; | 610 | int dma_trigger = 0; |
611 | u16 w; | ||
601 | 612 | ||
602 | if (cpu_is_omap24xx()) | 613 | if (cpu_is_omap24xx()) |
603 | dma_trigger = OMAP24XX_DMA(USB_W2FC_RX0, ep->dma_channel); | 614 | dma_trigger = OMAP24XX_DMA(USB_W2FC_RX0, ep->dma_channel); |
@@ -626,10 +637,12 @@ static void next_out_dma(struct omap_ep *ep, struct omap_req *req) | |||
626 | 0, 0); | 637 | 0, 0); |
627 | ep->dma_counter = omap_get_dma_dst_pos(ep->lch); | 638 | ep->dma_counter = omap_get_dma_dst_pos(ep->lch); |
628 | 639 | ||
629 | UDC_RXDMA_REG(ep->dma_channel) = UDC_RXN_STOP | (packets - 1); | 640 | omap_writew(UDC_RXN_STOP | (packets - 1), UDC_RXDMA(ep->dma_channel)); |
630 | UDC_DMA_IRQ_EN_REG |= UDC_RX_EOT_IE(ep->dma_channel); | 641 | w = omap_readw(UDC_DMA_IRQ_EN); |
631 | UDC_EP_NUM_REG = (ep->bEndpointAddress & 0xf); | 642 | w |= UDC_RX_EOT_IE(ep->dma_channel); |
632 | UDC_CTRL_REG = UDC_SET_FIFO_EN; | 643 | omap_writew(w, UDC_DMA_IRQ_EN); |
644 | omap_writew(ep->bEndpointAddress & 0xf, UDC_EP_NUM); | ||
645 | omap_writew(UDC_SET_FIFO_EN, UDC_CTRL); | ||
633 | 646 | ||
634 | omap_start_dma(ep->lch); | 647 | omap_start_dma(ep->lch); |
635 | } | 648 | } |
@@ -637,7 +650,7 @@ static void next_out_dma(struct omap_ep *ep, struct omap_req *req) | |||
637 | static void | 650 | static void |
638 | finish_out_dma(struct omap_ep *ep, struct omap_req *req, int status, int one) | 651 | finish_out_dma(struct omap_ep *ep, struct omap_req *req, int status, int one) |
639 | { | 652 | { |
640 | u16 count; | 653 | u16 count, w; |
641 | 654 | ||
642 | if (status == 0) | 655 | if (status == 0) |
643 | ep->dma_counter = (u16) (req->req.dma + req->req.actual); | 656 | ep->dma_counter = (u16) (req->req.dma + req->req.actual); |
@@ -656,13 +669,15 @@ finish_out_dma(struct omap_ep *ep, struct omap_req *req, int status, int one) | |||
656 | return; | 669 | return; |
657 | 670 | ||
658 | /* rx completion */ | 671 | /* rx completion */ |
659 | UDC_DMA_IRQ_EN_REG &= ~UDC_RX_EOT_IE(ep->dma_channel); | 672 | w = omap_readw(UDC_DMA_IRQ_EN); |
673 | w &= ~UDC_RX_EOT_IE(ep->dma_channel); | ||
674 | omap_writew(w, UDC_DMA_IRQ_EN); | ||
660 | done(ep, req, status); | 675 | done(ep, req, status); |
661 | } | 676 | } |
662 | 677 | ||
663 | static void dma_irq(struct omap_udc *udc, u16 irq_src) | 678 | static void dma_irq(struct omap_udc *udc, u16 irq_src) |
664 | { | 679 | { |
665 | u16 dman_stat = UDC_DMAN_STAT_REG; | 680 | u16 dman_stat = omap_readw(UDC_DMAN_STAT); |
666 | struct omap_ep *ep; | 681 | struct omap_ep *ep; |
667 | struct omap_req *req; | 682 | struct omap_req *req; |
668 | 683 | ||
@@ -676,7 +691,7 @@ static void dma_irq(struct omap_udc *udc, u16 irq_src) | |||
676 | struct omap_req, queue); | 691 | struct omap_req, queue); |
677 | finish_in_dma(ep, req, 0); | 692 | finish_in_dma(ep, req, 0); |
678 | } | 693 | } |
679 | UDC_IRQ_SRC_REG = UDC_TXN_DONE; | 694 | omap_writew(UDC_TXN_DONE, UDC_IRQ_SRC); |
680 | 695 | ||
681 | if (!list_empty (&ep->queue)) { | 696 | if (!list_empty (&ep->queue)) { |
682 | req = container_of(ep->queue.next, | 697 | req = container_of(ep->queue.next, |
@@ -695,7 +710,7 @@ static void dma_irq(struct omap_udc *udc, u16 irq_src) | |||
695 | struct omap_req, queue); | 710 | struct omap_req, queue); |
696 | finish_out_dma(ep, req, 0, dman_stat & UDC_DMA_RX_SB); | 711 | finish_out_dma(ep, req, 0, dman_stat & UDC_DMA_RX_SB); |
697 | } | 712 | } |
698 | UDC_IRQ_SRC_REG = UDC_RXN_EOT; | 713 | omap_writew(UDC_RXN_EOT, UDC_IRQ_SRC); |
699 | 714 | ||
700 | if (!list_empty (&ep->queue)) { | 715 | if (!list_empty (&ep->queue)) { |
701 | req = container_of(ep->queue.next, | 716 | req = container_of(ep->queue.next, |
@@ -709,7 +724,7 @@ static void dma_irq(struct omap_udc *udc, u16 irq_src) | |||
709 | ep->irqs++; | 724 | ep->irqs++; |
710 | /* omap15xx does this unasked... */ | 725 | /* omap15xx does this unasked... */ |
711 | VDBG("%s, RX_CNT irq?\n", ep->ep.name); | 726 | VDBG("%s, RX_CNT irq?\n", ep->ep.name); |
712 | UDC_IRQ_SRC_REG = UDC_RXN_CNT; | 727 | omap_writew(UDC_RXN_CNT, UDC_IRQ_SRC); |
713 | } | 728 | } |
714 | } | 729 | } |
715 | 730 | ||
@@ -732,9 +747,9 @@ static void dma_channel_claim(struct omap_ep *ep, unsigned channel) | |||
732 | 747 | ||
733 | is_in = ep->bEndpointAddress & USB_DIR_IN; | 748 | is_in = ep->bEndpointAddress & USB_DIR_IN; |
734 | if (is_in) | 749 | if (is_in) |
735 | reg = UDC_TXDMA_CFG_REG; | 750 | reg = omap_readw(UDC_TXDMA_CFG); |
736 | else | 751 | else |
737 | reg = UDC_RXDMA_CFG_REG; | 752 | reg = omap_readw(UDC_RXDMA_CFG); |
738 | reg |= UDC_DMA_REQ; /* "pulse" activated */ | 753 | reg |= UDC_DMA_REQ; /* "pulse" activated */ |
739 | 754 | ||
740 | ep->dma_channel = 0; | 755 | ep->dma_channel = 0; |
@@ -762,7 +777,7 @@ static void dma_channel_claim(struct omap_ep *ep, unsigned channel) | |||
762 | status = omap_request_dma(dma_channel, | 777 | status = omap_request_dma(dma_channel, |
763 | ep->ep.name, dma_error, ep, &ep->lch); | 778 | ep->ep.name, dma_error, ep, &ep->lch); |
764 | if (status == 0) { | 779 | if (status == 0) { |
765 | UDC_TXDMA_CFG_REG = reg; | 780 | omap_writew(reg, UDC_TXDMA_CFG); |
766 | /* EMIFF or SDRC */ | 781 | /* EMIFF or SDRC */ |
767 | omap_set_dma_src_burst_mode(ep->lch, | 782 | omap_set_dma_src_burst_mode(ep->lch, |
768 | OMAP_DMA_DATA_BURST_4); | 783 | OMAP_DMA_DATA_BURST_4); |
@@ -771,7 +786,7 @@ static void dma_channel_claim(struct omap_ep *ep, unsigned channel) | |||
771 | omap_set_dma_dest_params(ep->lch, | 786 | omap_set_dma_dest_params(ep->lch, |
772 | OMAP_DMA_PORT_TIPB, | 787 | OMAP_DMA_PORT_TIPB, |
773 | OMAP_DMA_AMODE_CONSTANT, | 788 | OMAP_DMA_AMODE_CONSTANT, |
774 | (unsigned long) io_v2p((u32)&UDC_DATA_DMA_REG), | 789 | (unsigned long) io_v2p(UDC_DATA_DMA), |
775 | 0, 0); | 790 | 0, 0); |
776 | } | 791 | } |
777 | } else { | 792 | } else { |
@@ -783,12 +798,12 @@ static void dma_channel_claim(struct omap_ep *ep, unsigned channel) | |||
783 | status = omap_request_dma(dma_channel, | 798 | status = omap_request_dma(dma_channel, |
784 | ep->ep.name, dma_error, ep, &ep->lch); | 799 | ep->ep.name, dma_error, ep, &ep->lch); |
785 | if (status == 0) { | 800 | if (status == 0) { |
786 | UDC_RXDMA_CFG_REG = reg; | 801 | omap_writew(reg, UDC_RXDMA_CFG); |
787 | /* TIPB */ | 802 | /* TIPB */ |
788 | omap_set_dma_src_params(ep->lch, | 803 | omap_set_dma_src_params(ep->lch, |
789 | OMAP_DMA_PORT_TIPB, | 804 | OMAP_DMA_PORT_TIPB, |
790 | OMAP_DMA_AMODE_CONSTANT, | 805 | OMAP_DMA_AMODE_CONSTANT, |
791 | (unsigned long) io_v2p((u32)&UDC_DATA_DMA_REG), | 806 | (unsigned long) io_v2p(UDC_DATA_DMA), |
792 | 0, 0); | 807 | 0, 0); |
793 | /* EMIFF or SDRC */ | 808 | /* EMIFF or SDRC */ |
794 | omap_set_dma_dest_burst_mode(ep->lch, | 809 | omap_set_dma_dest_burst_mode(ep->lch, |
@@ -830,7 +845,7 @@ just_restart: | |||
830 | (is_in ? write_fifo : read_fifo)(ep, req); | 845 | (is_in ? write_fifo : read_fifo)(ep, req); |
831 | deselect_ep(); | 846 | deselect_ep(); |
832 | if (!is_in) { | 847 | if (!is_in) { |
833 | UDC_CTRL_REG = UDC_SET_FIFO_EN; | 848 | omap_writew(UDC_SET_FIFO_EN, UDC_CTRL); |
834 | ep->ackwait = 1 + ep->double_buf; | 849 | ep->ackwait = 1 + ep->double_buf; |
835 | } | 850 | } |
836 | /* IN: 6 wait states before it'll tx */ | 851 | /* IN: 6 wait states before it'll tx */ |
@@ -864,23 +879,25 @@ static void dma_channel_release(struct omap_ep *ep) | |||
864 | 879 | ||
865 | /* wait till current packet DMA finishes, and fifo empties */ | 880 | /* wait till current packet DMA finishes, and fifo empties */ |
866 | if (ep->bEndpointAddress & USB_DIR_IN) { | 881 | if (ep->bEndpointAddress & USB_DIR_IN) { |
867 | UDC_TXDMA_CFG_REG = (UDC_TXDMA_CFG_REG & ~mask) | UDC_DMA_REQ; | 882 | omap_writew((omap_readw(UDC_TXDMA_CFG) & ~mask) | UDC_DMA_REQ, |
883 | UDC_TXDMA_CFG); | ||
868 | 884 | ||
869 | if (req) { | 885 | if (req) { |
870 | finish_in_dma(ep, req, -ECONNRESET); | 886 | finish_in_dma(ep, req, -ECONNRESET); |
871 | 887 | ||
872 | /* clear FIFO; hosts probably won't empty it */ | 888 | /* clear FIFO; hosts probably won't empty it */ |
873 | use_ep(ep, UDC_EP_SEL); | 889 | use_ep(ep, UDC_EP_SEL); |
874 | UDC_CTRL_REG = UDC_CLR_EP; | 890 | omap_writew(UDC_CLR_EP, UDC_CTRL); |
875 | deselect_ep(); | 891 | deselect_ep(); |
876 | } | 892 | } |
877 | while (UDC_TXDMA_CFG_REG & mask) | 893 | while (omap_readw(UDC_TXDMA_CFG) & mask) |
878 | udelay(10); | 894 | udelay(10); |
879 | } else { | 895 | } else { |
880 | UDC_RXDMA_CFG_REG = (UDC_RXDMA_CFG_REG & ~mask) | UDC_DMA_REQ; | 896 | omap_writew((omap_readw(UDC_RXDMA_CFG) & ~mask) | UDC_DMA_REQ, |
897 | UDC_RXDMA_CFG); | ||
881 | 898 | ||
882 | /* dma empties the fifo */ | 899 | /* dma empties the fifo */ |
883 | while (UDC_RXDMA_CFG_REG & mask) | 900 | while (omap_readw(UDC_RXDMA_CFG) & mask) |
884 | udelay(10); | 901 | udelay(10); |
885 | if (req) | 902 | if (req) |
886 | finish_out_dma(ep, req, -ECONNRESET, 0); | 903 | finish_out_dma(ep, req, -ECONNRESET, 0); |
@@ -967,9 +984,13 @@ omap_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags) | |||
967 | req->req.actual = 0; | 984 | req->req.actual = 0; |
968 | 985 | ||
969 | /* maybe kickstart non-iso i/o queues */ | 986 | /* maybe kickstart non-iso i/o queues */ |
970 | if (is_iso) | 987 | if (is_iso) { |
971 | UDC_IRQ_EN_REG |= UDC_SOF_IE; | 988 | u16 w; |
972 | else if (list_empty(&ep->queue) && !ep->stopped && !ep->ackwait) { | 989 | |
990 | w = omap_readw(UDC_IRQ_EN); | ||
991 | w |= UDC_SOF_IE; | ||
992 | omap_writew(w, UDC_IRQ_EN); | ||
993 | } else if (list_empty(&ep->queue) && !ep->stopped && !ep->ackwait) { | ||
973 | int is_in; | 994 | int is_in; |
974 | 995 | ||
975 | if (ep->bEndpointAddress == 0) { | 996 | if (ep->bEndpointAddress == 0) { |
@@ -987,23 +1008,23 @@ omap_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags) | |||
987 | * requests to non-control endpoints | 1008 | * requests to non-control endpoints |
988 | */ | 1009 | */ |
989 | if (udc->ep0_set_config) { | 1010 | if (udc->ep0_set_config) { |
990 | u16 irq_en = UDC_IRQ_EN_REG; | 1011 | u16 irq_en = omap_readw(UDC_IRQ_EN); |
991 | 1012 | ||
992 | irq_en |= UDC_DS_CHG_IE | UDC_EP0_IE; | 1013 | irq_en |= UDC_DS_CHG_IE | UDC_EP0_IE; |
993 | if (!udc->ep0_reset_config) | 1014 | if (!udc->ep0_reset_config) |
994 | irq_en |= UDC_EPN_RX_IE | 1015 | irq_en |= UDC_EPN_RX_IE |
995 | | UDC_EPN_TX_IE; | 1016 | | UDC_EPN_TX_IE; |
996 | UDC_IRQ_EN_REG = irq_en; | 1017 | omap_writew(irq_en, UDC_IRQ_EN); |
997 | } | 1018 | } |
998 | 1019 | ||
999 | /* STATUS for zero length DATA stages is | 1020 | /* STATUS for zero length DATA stages is |
1000 | * always an IN ... even for IN transfers, | 1021 | * always an IN ... even for IN transfers, |
1001 | * a weird case which seem to stall OMAP. | 1022 | * a weird case which seem to stall OMAP. |
1002 | */ | 1023 | */ |
1003 | UDC_EP_NUM_REG = (UDC_EP_SEL|UDC_EP_DIR); | 1024 | omap_writew(UDC_EP_SEL | UDC_EP_DIR, UDC_EP_NUM); |
1004 | UDC_CTRL_REG = UDC_CLR_EP; | 1025 | omap_writew(UDC_CLR_EP, UDC_CTRL); |
1005 | UDC_CTRL_REG = UDC_SET_FIFO_EN; | 1026 | omap_writew(UDC_SET_FIFO_EN, UDC_CTRL); |
1006 | UDC_EP_NUM_REG = UDC_EP_DIR; | 1027 | omap_writew(UDC_EP_DIR, UDC_EP_NUM); |
1007 | 1028 | ||
1008 | /* cleanup */ | 1029 | /* cleanup */ |
1009 | udc->ep0_pending = 0; | 1030 | udc->ep0_pending = 0; |
@@ -1012,11 +1033,11 @@ omap_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags) | |||
1012 | 1033 | ||
1013 | /* non-empty DATA stage */ | 1034 | /* non-empty DATA stage */ |
1014 | } else if (is_in) { | 1035 | } else if (is_in) { |
1015 | UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR; | 1036 | omap_writew(UDC_EP_SEL | UDC_EP_DIR, UDC_EP_NUM); |
1016 | } else { | 1037 | } else { |
1017 | if (udc->ep0_setup) | 1038 | if (udc->ep0_setup) |
1018 | goto irq_wait; | 1039 | goto irq_wait; |
1019 | UDC_EP_NUM_REG = UDC_EP_SEL; | 1040 | omap_writew(UDC_EP_SEL, UDC_EP_NUM); |
1020 | } | 1041 | } |
1021 | } else { | 1042 | } else { |
1022 | is_in = ep->bEndpointAddress & USB_DIR_IN; | 1043 | is_in = ep->bEndpointAddress & USB_DIR_IN; |
@@ -1032,7 +1053,7 @@ omap_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags) | |||
1032 | req = NULL; | 1053 | req = NULL; |
1033 | deselect_ep(); | 1054 | deselect_ep(); |
1034 | if (!is_in) { | 1055 | if (!is_in) { |
1035 | UDC_CTRL_REG = UDC_SET_FIFO_EN; | 1056 | omap_writew(UDC_SET_FIFO_EN, UDC_CTRL); |
1036 | ep->ackwait = 1 + ep->double_buf; | 1057 | ep->ackwait = 1 + ep->double_buf; |
1037 | } | 1058 | } |
1038 | /* IN: 6 wait states before it'll tx */ | 1059 | /* IN: 6 wait states before it'll tx */ |
@@ -1100,9 +1121,9 @@ static int omap_ep_set_halt(struct usb_ep *_ep, int value) | |||
1100 | else if (value) { | 1121 | else if (value) { |
1101 | if (ep->udc->ep0_set_config) { | 1122 | if (ep->udc->ep0_set_config) { |
1102 | WARN("error changing config?\n"); | 1123 | WARN("error changing config?\n"); |
1103 | UDC_SYSCON2_REG = UDC_CLR_CFG; | 1124 | omap_writew(UDC_CLR_CFG, UDC_SYSCON2); |
1104 | } | 1125 | } |
1105 | UDC_SYSCON2_REG = UDC_STALL_CMD; | 1126 | omap_writew(UDC_STALL_CMD, UDC_SYSCON2); |
1106 | ep->udc->ep0_pending = 0; | 1127 | ep->udc->ep0_pending = 0; |
1107 | status = 0; | 1128 | status = 0; |
1108 | } else /* NOP */ | 1129 | } else /* NOP */ |
@@ -1129,8 +1150,8 @@ static int omap_ep_set_halt(struct usb_ep *_ep, int value) | |||
1129 | channel = 0; | 1150 | channel = 0; |
1130 | 1151 | ||
1131 | use_ep(ep, UDC_EP_SEL); | 1152 | use_ep(ep, UDC_EP_SEL); |
1132 | if (UDC_STAT_FLG_REG & UDC_NON_ISO_FIFO_EMPTY) { | 1153 | if (omap_readw(UDC_STAT_FLG) & UDC_NON_ISO_FIFO_EMPTY) { |
1133 | UDC_CTRL_REG = UDC_SET_HALT; | 1154 | omap_writew(UDC_SET_HALT, UDC_CTRL); |
1134 | status = 0; | 1155 | status = 0; |
1135 | } else | 1156 | } else |
1136 | status = -EAGAIN; | 1157 | status = -EAGAIN; |
@@ -1140,10 +1161,10 @@ static int omap_ep_set_halt(struct usb_ep *_ep, int value) | |||
1140 | dma_channel_claim(ep, channel); | 1161 | dma_channel_claim(ep, channel); |
1141 | } else { | 1162 | } else { |
1142 | use_ep(ep, 0); | 1163 | use_ep(ep, 0); |
1143 | UDC_CTRL_REG = ep->udc->clr_halt; | 1164 | omap_writew(ep->udc->clr_halt, UDC_CTRL); |
1144 | ep->ackwait = 0; | 1165 | ep->ackwait = 0; |
1145 | if (!(ep->bEndpointAddress & USB_DIR_IN)) { | 1166 | if (!(ep->bEndpointAddress & USB_DIR_IN)) { |
1146 | UDC_CTRL_REG = UDC_SET_FIFO_EN; | 1167 | omap_writew(UDC_SET_FIFO_EN, UDC_CTRL); |
1147 | ep->ackwait = 1 + ep->double_buf; | 1168 | ep->ackwait = 1 + ep->double_buf; |
1148 | } | 1169 | } |
1149 | } | 1170 | } |
@@ -1175,7 +1196,7 @@ static struct usb_ep_ops omap_ep_ops = { | |||
1175 | 1196 | ||
1176 | static int omap_get_frame(struct usb_gadget *gadget) | 1197 | static int omap_get_frame(struct usb_gadget *gadget) |
1177 | { | 1198 | { |
1178 | u16 sof = UDC_SOF_REG; | 1199 | u16 sof = omap_readw(UDC_SOF); |
1179 | return (sof & UDC_TS_OK) ? (sof & UDC_TS) : -EL2NSYNC; | 1200 | return (sof & UDC_TS_OK) ? (sof & UDC_TS) : -EL2NSYNC; |
1180 | } | 1201 | } |
1181 | 1202 | ||
@@ -1194,7 +1215,7 @@ static int omap_wakeup(struct usb_gadget *gadget) | |||
1194 | */ | 1215 | */ |
1195 | if (udc->devstat & (UDC_B_HNP_ENABLE|UDC_R_WK_OK)) { | 1216 | if (udc->devstat & (UDC_B_HNP_ENABLE|UDC_R_WK_OK)) { |
1196 | DBG("remote wakeup...\n"); | 1217 | DBG("remote wakeup...\n"); |
1197 | UDC_SYSCON2_REG = UDC_RMT_WKP; | 1218 | omap_writew(UDC_RMT_WKP, UDC_SYSCON2); |
1198 | retval = 0; | 1219 | retval = 0; |
1199 | } | 1220 | } |
1200 | 1221 | ||
@@ -1217,12 +1238,12 @@ omap_set_selfpowered(struct usb_gadget *gadget, int is_selfpowered) | |||
1217 | 1238 | ||
1218 | udc = container_of(gadget, struct omap_udc, gadget); | 1239 | udc = container_of(gadget, struct omap_udc, gadget); |
1219 | spin_lock_irqsave(&udc->lock, flags); | 1240 | spin_lock_irqsave(&udc->lock, flags); |
1220 | syscon1 = UDC_SYSCON1_REG; | 1241 | syscon1 = omap_readw(UDC_SYSCON1); |
1221 | if (is_selfpowered) | 1242 | if (is_selfpowered) |
1222 | syscon1 |= UDC_SELF_PWR; | 1243 | syscon1 |= UDC_SELF_PWR; |
1223 | else | 1244 | else |
1224 | syscon1 &= ~UDC_SELF_PWR; | 1245 | syscon1 &= ~UDC_SELF_PWR; |
1225 | UDC_SYSCON1_REG = syscon1; | 1246 | omap_writew(syscon1, UDC_SYSCON1); |
1226 | spin_unlock_irqrestore(&udc->lock, flags); | 1247 | spin_unlock_irqrestore(&udc->lock, flags); |
1227 | 1248 | ||
1228 | return 0; | 1249 | return 0; |
@@ -1235,18 +1256,36 @@ static int can_pullup(struct omap_udc *udc) | |||
1235 | 1256 | ||
1236 | static void pullup_enable(struct omap_udc *udc) | 1257 | static void pullup_enable(struct omap_udc *udc) |
1237 | { | 1258 | { |
1238 | UDC_SYSCON1_REG |= UDC_PULLUP_EN; | 1259 | u16 w; |
1239 | if (!gadget_is_otg(&udc->gadget) && !cpu_is_omap15xx()) | 1260 | |
1240 | OTG_CTRL_REG |= OTG_BSESSVLD; | 1261 | w = omap_readw(UDC_SYSCON1); |
1241 | UDC_IRQ_EN_REG = UDC_DS_CHG_IE; | 1262 | w |= UDC_PULLUP_EN; |
1263 | omap_writew(w, UDC_SYSCON1); | ||
1264 | if (!gadget_is_otg(&udc->gadget) && !cpu_is_omap15xx()) { | ||
1265 | u32 l; | ||
1266 | |||
1267 | l = omap_readl(OTG_CTRL); | ||
1268 | l |= OTG_BSESSVLD; | ||
1269 | omap_writel(l, OTG_CTRL); | ||
1270 | } | ||
1271 | omap_writew(UDC_DS_CHG_IE, UDC_IRQ_EN); | ||
1242 | } | 1272 | } |
1243 | 1273 | ||
1244 | static void pullup_disable(struct omap_udc *udc) | 1274 | static void pullup_disable(struct omap_udc *udc) |
1245 | { | 1275 | { |
1246 | if (!gadget_is_otg(&udc->gadget) && !cpu_is_omap15xx()) | 1276 | u16 w; |
1247 | OTG_CTRL_REG &= ~OTG_BSESSVLD; | 1277 | |
1248 | UDC_IRQ_EN_REG = UDC_DS_CHG_IE; | 1278 | if (!gadget_is_otg(&udc->gadget) && !cpu_is_omap15xx()) { |
1249 | UDC_SYSCON1_REG &= ~UDC_PULLUP_EN; | 1279 | u32 l; |
1280 | |||
1281 | l = omap_readl(OTG_CTRL); | ||
1282 | l &= ~OTG_BSESSVLD; | ||
1283 | omap_writel(l, OTG_CTRL); | ||
1284 | } | ||
1285 | omap_writew(UDC_DS_CHG_IE, UDC_IRQ_EN); | ||
1286 | w = omap_readw(UDC_SYSCON1); | ||
1287 | w &= ~UDC_PULLUP_EN; | ||
1288 | omap_writew(w, UDC_SYSCON1); | ||
1250 | } | 1289 | } |
1251 | 1290 | ||
1252 | static struct omap_udc *udc; | 1291 | static struct omap_udc *udc; |
@@ -1274,6 +1313,7 @@ static int omap_vbus_session(struct usb_gadget *gadget, int is_active) | |||
1274 | { | 1313 | { |
1275 | struct omap_udc *udc; | 1314 | struct omap_udc *udc; |
1276 | unsigned long flags; | 1315 | unsigned long flags; |
1316 | u32 l; | ||
1277 | 1317 | ||
1278 | udc = container_of(gadget, struct omap_udc, gadget); | 1318 | udc = container_of(gadget, struct omap_udc, gadget); |
1279 | spin_lock_irqsave(&udc->lock, flags); | 1319 | spin_lock_irqsave(&udc->lock, flags); |
@@ -1281,10 +1321,12 @@ static int omap_vbus_session(struct usb_gadget *gadget, int is_active) | |||
1281 | udc->vbus_active = (is_active != 0); | 1321 | udc->vbus_active = (is_active != 0); |
1282 | if (cpu_is_omap15xx()) { | 1322 | if (cpu_is_omap15xx()) { |
1283 | /* "software" detect, ignored if !VBUS_MODE_1510 */ | 1323 | /* "software" detect, ignored if !VBUS_MODE_1510 */ |
1324 | l = omap_readl(FUNC_MUX_CTRL_0); | ||
1284 | if (is_active) | 1325 | if (is_active) |
1285 | FUNC_MUX_CTRL_0_REG |= VBUS_CTRL_1510; | 1326 | l |= VBUS_CTRL_1510; |
1286 | else | 1327 | else |
1287 | FUNC_MUX_CTRL_0_REG &= ~VBUS_CTRL_1510; | 1328 | l &= ~VBUS_CTRL_1510; |
1329 | omap_writel(l, FUNC_MUX_CTRL_0); | ||
1288 | } | 1330 | } |
1289 | if (udc->dc_clk != NULL && is_active) { | 1331 | if (udc->dc_clk != NULL && is_active) { |
1290 | if (!udc->clk_requested) { | 1332 | if (!udc->clk_requested) { |
@@ -1354,9 +1396,9 @@ static void nuke(struct omap_ep *ep, int status) | |||
1354 | dma_channel_release(ep); | 1396 | dma_channel_release(ep); |
1355 | 1397 | ||
1356 | use_ep(ep, 0); | 1398 | use_ep(ep, 0); |
1357 | UDC_CTRL_REG = UDC_CLR_EP; | 1399 | omap_writew(UDC_CLR_EP, UDC_CTRL); |
1358 | if (ep->bEndpointAddress && ep->bmAttributes != USB_ENDPOINT_XFER_ISOC) | 1400 | if (ep->bEndpointAddress && ep->bmAttributes != USB_ENDPOINT_XFER_ISOC) |
1359 | UDC_CTRL_REG = UDC_SET_HALT; | 1401 | omap_writew(UDC_SET_HALT, UDC_CTRL); |
1360 | 1402 | ||
1361 | while (!list_empty(&ep->queue)) { | 1403 | while (!list_empty(&ep->queue)) { |
1362 | req = list_entry(ep->queue.next, struct omap_req, queue); | 1404 | req = list_entry(ep->queue.next, struct omap_req, queue); |
@@ -1384,8 +1426,8 @@ static void update_otg(struct omap_udc *udc) | |||
1384 | if (!gadget_is_otg(&udc->gadget)) | 1426 | if (!gadget_is_otg(&udc->gadget)) |
1385 | return; | 1427 | return; |
1386 | 1428 | ||
1387 | if (OTG_CTRL_REG & OTG_ID) | 1429 | if (omap_readl(OTG_CTRL) & OTG_ID) |
1388 | devstat = UDC_DEVSTAT_REG; | 1430 | devstat = omap_readw(UDC_DEVSTAT); |
1389 | else | 1431 | else |
1390 | devstat = 0; | 1432 | devstat = 0; |
1391 | 1433 | ||
@@ -1396,9 +1438,14 @@ static void update_otg(struct omap_udc *udc) | |||
1396 | /* Enable HNP early, avoiding races on suspend irq path. | 1438 | /* Enable HNP early, avoiding races on suspend irq path. |
1397 | * ASSUMES OTG state machine B_BUS_REQ input is true. | 1439 | * ASSUMES OTG state machine B_BUS_REQ input is true. |
1398 | */ | 1440 | */ |
1399 | if (udc->gadget.b_hnp_enable) | 1441 | if (udc->gadget.b_hnp_enable) { |
1400 | OTG_CTRL_REG = (OTG_CTRL_REG | OTG_B_HNPEN | OTG_B_BUSREQ) | 1442 | u32 l; |
1401 | & ~OTG_PULLUP; | 1443 | |
1444 | l = omap_readl(OTG_CTRL); | ||
1445 | l |= OTG_B_HNPEN | OTG_B_BUSREQ; | ||
1446 | l &= ~OTG_PULLUP; | ||
1447 | omap_writel(l, OTG_CTRL); | ||
1448 | } | ||
1402 | } | 1449 | } |
1403 | 1450 | ||
1404 | static void ep0_irq(struct omap_udc *udc, u16 irq_src) | 1451 | static void ep0_irq(struct omap_udc *udc, u16 irq_src) |
@@ -1416,7 +1463,7 @@ static void ep0_irq(struct omap_udc *udc, u16 irq_src) | |||
1416 | 1463 | ||
1417 | nuke(ep0, 0); | 1464 | nuke(ep0, 0); |
1418 | if (ack) { | 1465 | if (ack) { |
1419 | UDC_IRQ_SRC_REG = ack; | 1466 | omap_writew(ack, UDC_IRQ_SRC); |
1420 | irq_src = UDC_SETUP; | 1467 | irq_src = UDC_SETUP; |
1421 | } | 1468 | } |
1422 | } | 1469 | } |
@@ -1436,9 +1483,9 @@ static void ep0_irq(struct omap_udc *udc, u16 irq_src) | |||
1436 | if (irq_src & UDC_EP0_TX) { | 1483 | if (irq_src & UDC_EP0_TX) { |
1437 | int stat; | 1484 | int stat; |
1438 | 1485 | ||
1439 | UDC_IRQ_SRC_REG = UDC_EP0_TX; | 1486 | omap_writew(UDC_EP0_TX, UDC_IRQ_SRC); |
1440 | UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR; | 1487 | omap_writew(UDC_EP_SEL|UDC_EP_DIR, UDC_EP_NUM); |
1441 | stat = UDC_STAT_FLG_REG; | 1488 | stat = omap_readw(UDC_STAT_FLG); |
1442 | if (stat & UDC_ACK) { | 1489 | if (stat & UDC_ACK) { |
1443 | if (udc->ep0_in) { | 1490 | if (udc->ep0_in) { |
1444 | /* write next IN packet from response, | 1491 | /* write next IN packet from response, |
@@ -1446,26 +1493,26 @@ static void ep0_irq(struct omap_udc *udc, u16 irq_src) | |||
1446 | */ | 1493 | */ |
1447 | if (req) | 1494 | if (req) |
1448 | stat = write_fifo(ep0, req); | 1495 | stat = write_fifo(ep0, req); |
1449 | UDC_EP_NUM_REG = UDC_EP_DIR; | 1496 | omap_writew(UDC_EP_DIR, UDC_EP_NUM); |
1450 | if (!req && udc->ep0_pending) { | 1497 | if (!req && udc->ep0_pending) { |
1451 | UDC_EP_NUM_REG = UDC_EP_SEL; | 1498 | omap_writew(UDC_EP_SEL, UDC_EP_NUM); |
1452 | UDC_CTRL_REG = UDC_CLR_EP; | 1499 | omap_writew(UDC_CLR_EP, UDC_CTRL); |
1453 | UDC_CTRL_REG = UDC_SET_FIFO_EN; | 1500 | omap_writew(UDC_SET_FIFO_EN, UDC_CTRL); |
1454 | UDC_EP_NUM_REG = 0; | 1501 | omap_writew(0, UDC_EP_NUM); |
1455 | udc->ep0_pending = 0; | 1502 | udc->ep0_pending = 0; |
1456 | } /* else: 6 wait states before it'll tx */ | 1503 | } /* else: 6 wait states before it'll tx */ |
1457 | } else { | 1504 | } else { |
1458 | /* ack status stage of OUT transfer */ | 1505 | /* ack status stage of OUT transfer */ |
1459 | UDC_EP_NUM_REG = UDC_EP_DIR; | 1506 | omap_writew(UDC_EP_DIR, UDC_EP_NUM); |
1460 | if (req) | 1507 | if (req) |
1461 | done(ep0, req, 0); | 1508 | done(ep0, req, 0); |
1462 | } | 1509 | } |
1463 | req = NULL; | 1510 | req = NULL; |
1464 | } else if (stat & UDC_STALL) { | 1511 | } else if (stat & UDC_STALL) { |
1465 | UDC_CTRL_REG = UDC_CLR_HALT; | 1512 | omap_writew(UDC_CLR_HALT, UDC_CTRL); |
1466 | UDC_EP_NUM_REG = UDC_EP_DIR; | 1513 | omap_writew(UDC_EP_DIR, UDC_EP_NUM); |
1467 | } else { | 1514 | } else { |
1468 | UDC_EP_NUM_REG = UDC_EP_DIR; | 1515 | omap_writew(UDC_EP_DIR, UDC_EP_NUM); |
1469 | } | 1516 | } |
1470 | } | 1517 | } |
1471 | 1518 | ||
@@ -1473,9 +1520,9 @@ static void ep0_irq(struct omap_udc *udc, u16 irq_src) | |||
1473 | if (irq_src & UDC_EP0_RX) { | 1520 | if (irq_src & UDC_EP0_RX) { |
1474 | int stat; | 1521 | int stat; |
1475 | 1522 | ||
1476 | UDC_IRQ_SRC_REG = UDC_EP0_RX; | 1523 | omap_writew(UDC_EP0_RX, UDC_IRQ_SRC); |
1477 | UDC_EP_NUM_REG = UDC_EP_SEL; | 1524 | omap_writew(UDC_EP_SEL, UDC_EP_NUM); |
1478 | stat = UDC_STAT_FLG_REG; | 1525 | stat = omap_readw(UDC_STAT_FLG); |
1479 | if (stat & UDC_ACK) { | 1526 | if (stat & UDC_ACK) { |
1480 | if (!udc->ep0_in) { | 1527 | if (!udc->ep0_in) { |
1481 | stat = 0; | 1528 | stat = 0; |
@@ -1483,34 +1530,35 @@ static void ep0_irq(struct omap_udc *udc, u16 irq_src) | |||
1483 | * reactiviting the fifo; stall on errors. | 1530 | * reactiviting the fifo; stall on errors. |
1484 | */ | 1531 | */ |
1485 | if (!req || (stat = read_fifo(ep0, req)) < 0) { | 1532 | if (!req || (stat = read_fifo(ep0, req)) < 0) { |
1486 | UDC_SYSCON2_REG = UDC_STALL_CMD; | 1533 | omap_writew(UDC_STALL_CMD, UDC_SYSCON2); |
1487 | udc->ep0_pending = 0; | 1534 | udc->ep0_pending = 0; |
1488 | stat = 0; | 1535 | stat = 0; |
1489 | } else if (stat == 0) | 1536 | } else if (stat == 0) |
1490 | UDC_CTRL_REG = UDC_SET_FIFO_EN; | 1537 | omap_writew(UDC_SET_FIFO_EN, UDC_CTRL); |
1491 | UDC_EP_NUM_REG = 0; | 1538 | omap_writew(0, UDC_EP_NUM); |
1492 | 1539 | ||
1493 | /* activate status stage */ | 1540 | /* activate status stage */ |
1494 | if (stat == 1) { | 1541 | if (stat == 1) { |
1495 | done(ep0, req, 0); | 1542 | done(ep0, req, 0); |
1496 | /* that may have STALLed ep0... */ | 1543 | /* that may have STALLed ep0... */ |
1497 | UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR; | 1544 | omap_writew(UDC_EP_SEL | UDC_EP_DIR, |
1498 | UDC_CTRL_REG = UDC_CLR_EP; | 1545 | UDC_EP_NUM); |
1499 | UDC_CTRL_REG = UDC_SET_FIFO_EN; | 1546 | omap_writew(UDC_CLR_EP, UDC_CTRL); |
1500 | UDC_EP_NUM_REG = UDC_EP_DIR; | 1547 | omap_writew(UDC_SET_FIFO_EN, UDC_CTRL); |
1548 | omap_writew(UDC_EP_DIR, UDC_EP_NUM); | ||
1501 | udc->ep0_pending = 0; | 1549 | udc->ep0_pending = 0; |
1502 | } | 1550 | } |
1503 | } else { | 1551 | } else { |
1504 | /* ack status stage of IN transfer */ | 1552 | /* ack status stage of IN transfer */ |
1505 | UDC_EP_NUM_REG = 0; | 1553 | omap_writew(0, UDC_EP_NUM); |
1506 | if (req) | 1554 | if (req) |
1507 | done(ep0, req, 0); | 1555 | done(ep0, req, 0); |
1508 | } | 1556 | } |
1509 | } else if (stat & UDC_STALL) { | 1557 | } else if (stat & UDC_STALL) { |
1510 | UDC_CTRL_REG = UDC_CLR_HALT; | 1558 | omap_writew(UDC_CLR_HALT, UDC_CTRL); |
1511 | UDC_EP_NUM_REG = 0; | 1559 | omap_writew(0, UDC_EP_NUM); |
1512 | } else { | 1560 | } else { |
1513 | UDC_EP_NUM_REG = 0; | 1561 | omap_writew(0, UDC_EP_NUM); |
1514 | } | 1562 | } |
1515 | } | 1563 | } |
1516 | 1564 | ||
@@ -1525,14 +1573,14 @@ static void ep0_irq(struct omap_udc *udc, u16 irq_src) | |||
1525 | 1573 | ||
1526 | /* read the (latest) SETUP message */ | 1574 | /* read the (latest) SETUP message */ |
1527 | do { | 1575 | do { |
1528 | UDC_EP_NUM_REG = UDC_SETUP_SEL; | 1576 | omap_writew(UDC_SETUP_SEL, UDC_EP_NUM); |
1529 | /* two bytes at a time */ | 1577 | /* two bytes at a time */ |
1530 | u.word[0] = UDC_DATA_REG; | 1578 | u.word[0] = omap_readw(UDC_DATA); |
1531 | u.word[1] = UDC_DATA_REG; | 1579 | u.word[1] = omap_readw(UDC_DATA); |
1532 | u.word[2] = UDC_DATA_REG; | 1580 | u.word[2] = omap_readw(UDC_DATA); |
1533 | u.word[3] = UDC_DATA_REG; | 1581 | u.word[3] = omap_readw(UDC_DATA); |
1534 | UDC_EP_NUM_REG = 0; | 1582 | omap_writew(0, UDC_EP_NUM); |
1535 | } while (UDC_IRQ_SRC_REG & UDC_SETUP); | 1583 | } while (omap_readw(UDC_IRQ_SRC) & UDC_SETUP); |
1536 | 1584 | ||
1537 | #define w_value le16_to_cpu(u.r.wValue) | 1585 | #define w_value le16_to_cpu(u.r.wValue) |
1538 | #define w_index le16_to_cpu(u.r.wIndex) | 1586 | #define w_index le16_to_cpu(u.r.wIndex) |
@@ -1563,9 +1611,9 @@ static void ep0_irq(struct omap_udc *udc, u16 irq_src) | |||
1563 | * later if it fails the request. | 1611 | * later if it fails the request. |
1564 | */ | 1612 | */ |
1565 | if (udc->ep0_reset_config) | 1613 | if (udc->ep0_reset_config) |
1566 | UDC_SYSCON2_REG = UDC_CLR_CFG; | 1614 | omap_writew(UDC_CLR_CFG, UDC_SYSCON2); |
1567 | else | 1615 | else |
1568 | UDC_SYSCON2_REG = UDC_DEV_CFG; | 1616 | omap_writew(UDC_DEV_CFG, UDC_SYSCON2); |
1569 | update_otg(udc); | 1617 | update_otg(udc); |
1570 | goto delegate; | 1618 | goto delegate; |
1571 | case USB_REQ_CLEAR_FEATURE: | 1619 | case USB_REQ_CLEAR_FEATURE: |
@@ -1583,10 +1631,10 @@ static void ep0_irq(struct omap_udc *udc, u16 irq_src) | |||
1583 | || !ep->desc) | 1631 | || !ep->desc) |
1584 | goto do_stall; | 1632 | goto do_stall; |
1585 | use_ep(ep, 0); | 1633 | use_ep(ep, 0); |
1586 | UDC_CTRL_REG = udc->clr_halt; | 1634 | omap_writew(udc->clr_halt, UDC_CTRL); |
1587 | ep->ackwait = 0; | 1635 | ep->ackwait = 0; |
1588 | if (!(ep->bEndpointAddress & USB_DIR_IN)) { | 1636 | if (!(ep->bEndpointAddress & USB_DIR_IN)) { |
1589 | UDC_CTRL_REG = UDC_SET_FIFO_EN; | 1637 | omap_writew(UDC_SET_FIFO_EN, UDC_CTRL); |
1590 | ep->ackwait = 1 + ep->double_buf; | 1638 | ep->ackwait = 1 + ep->double_buf; |
1591 | } | 1639 | } |
1592 | /* NOTE: assumes the host behaves sanely, | 1640 | /* NOTE: assumes the host behaves sanely, |
@@ -1619,15 +1667,15 @@ static void ep0_irq(struct omap_udc *udc, u16 irq_src) | |||
1619 | } | 1667 | } |
1620 | use_ep(ep, 0); | 1668 | use_ep(ep, 0); |
1621 | /* can't halt if fifo isn't empty... */ | 1669 | /* can't halt if fifo isn't empty... */ |
1622 | UDC_CTRL_REG = UDC_CLR_EP; | 1670 | omap_writew(UDC_CLR_EP, UDC_CTRL); |
1623 | UDC_CTRL_REG = UDC_SET_HALT; | 1671 | omap_writew(UDC_SET_HALT, UDC_CTRL); |
1624 | VDBG("%s halted by host\n", ep->name); | 1672 | VDBG("%s halted by host\n", ep->name); |
1625 | ep0out_status_stage: | 1673 | ep0out_status_stage: |
1626 | status = 0; | 1674 | status = 0; |
1627 | UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR; | 1675 | omap_writew(UDC_EP_SEL|UDC_EP_DIR, UDC_EP_NUM); |
1628 | UDC_CTRL_REG = UDC_CLR_EP; | 1676 | omap_writew(UDC_CLR_EP, UDC_CTRL); |
1629 | UDC_CTRL_REG = UDC_SET_FIFO_EN; | 1677 | omap_writew(UDC_SET_FIFO_EN, UDC_CTRL); |
1630 | UDC_EP_NUM_REG = UDC_EP_DIR; | 1678 | omap_writew(UDC_EP_DIR, UDC_EP_NUM); |
1631 | udc->ep0_pending = 0; | 1679 | udc->ep0_pending = 0; |
1632 | break; | 1680 | break; |
1633 | case USB_REQ_GET_STATUS: | 1681 | case USB_REQ_GET_STATUS: |
@@ -1664,10 +1712,10 @@ intf_status: | |||
1664 | 1712 | ||
1665 | zero_status: | 1713 | zero_status: |
1666 | /* return two zero bytes */ | 1714 | /* return two zero bytes */ |
1667 | UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR; | 1715 | omap_writew(UDC_EP_SEL|UDC_EP_DIR, UDC_EP_NUM); |
1668 | UDC_DATA_REG = 0; | 1716 | omap_writew(0, UDC_DATA); |
1669 | UDC_CTRL_REG = UDC_SET_FIFO_EN; | 1717 | omap_writew(UDC_SET_FIFO_EN, UDC_CTRL); |
1670 | UDC_EP_NUM_REG = UDC_EP_DIR; | 1718 | omap_writew(UDC_EP_DIR, UDC_EP_NUM); |
1671 | status = 0; | 1719 | status = 0; |
1672 | VDBG("GET_STATUS, interface %d\n", w_index); | 1720 | VDBG("GET_STATUS, interface %d\n", w_index); |
1673 | /* next, status stage */ | 1721 | /* next, status stage */ |
@@ -1676,8 +1724,8 @@ zero_status: | |||
1676 | delegate: | 1724 | delegate: |
1677 | /* activate the ep0out fifo right away */ | 1725 | /* activate the ep0out fifo right away */ |
1678 | if (!udc->ep0_in && w_length) { | 1726 | if (!udc->ep0_in && w_length) { |
1679 | UDC_EP_NUM_REG = 0; | 1727 | omap_writew(0, UDC_EP_NUM); |
1680 | UDC_CTRL_REG = UDC_SET_FIFO_EN; | 1728 | omap_writew(UDC_SET_FIFO_EN, UDC_CTRL); |
1681 | } | 1729 | } |
1682 | 1730 | ||
1683 | /* gadget drivers see class/vendor specific requests, | 1731 | /* gadget drivers see class/vendor specific requests, |
@@ -1718,9 +1766,9 @@ do_stall: | |||
1718 | if (udc->ep0_reset_config) | 1766 | if (udc->ep0_reset_config) |
1719 | WARN("error resetting config?\n"); | 1767 | WARN("error resetting config?\n"); |
1720 | else | 1768 | else |
1721 | UDC_SYSCON2_REG = UDC_CLR_CFG; | 1769 | omap_writew(UDC_CLR_CFG, UDC_SYSCON2); |
1722 | } | 1770 | } |
1723 | UDC_SYSCON2_REG = UDC_STALL_CMD; | 1771 | omap_writew(UDC_STALL_CMD, UDC_SYSCON2); |
1724 | udc->ep0_pending = 0; | 1772 | udc->ep0_pending = 0; |
1725 | } | 1773 | } |
1726 | } | 1774 | } |
@@ -1734,7 +1782,7 @@ static void devstate_irq(struct omap_udc *udc, u16 irq_src) | |||
1734 | { | 1782 | { |
1735 | u16 devstat, change; | 1783 | u16 devstat, change; |
1736 | 1784 | ||
1737 | devstat = UDC_DEVSTAT_REG; | 1785 | devstat = omap_readw(UDC_DEVSTAT); |
1738 | change = devstat ^ udc->devstat; | 1786 | change = devstat ^ udc->devstat; |
1739 | udc->devstat = devstat; | 1787 | udc->devstat = devstat; |
1740 | 1788 | ||
@@ -1774,7 +1822,8 @@ static void devstate_irq(struct omap_udc *udc, u16 irq_src) | |||
1774 | INFO("USB reset done, gadget %s\n", | 1822 | INFO("USB reset done, gadget %s\n", |
1775 | udc->driver->driver.name); | 1823 | udc->driver->driver.name); |
1776 | /* ep0 traffic is legal from now on */ | 1824 | /* ep0 traffic is legal from now on */ |
1777 | UDC_IRQ_EN_REG = UDC_DS_CHG_IE | UDC_EP0_IE; | 1825 | omap_writew(UDC_DS_CHG_IE | UDC_EP0_IE, |
1826 | UDC_IRQ_EN); | ||
1778 | } | 1827 | } |
1779 | change &= ~UDC_USB_RESET; | 1828 | change &= ~UDC_USB_RESET; |
1780 | } | 1829 | } |
@@ -1818,7 +1867,7 @@ static void devstate_irq(struct omap_udc *udc, u16 irq_src) | |||
1818 | VDBG("devstat %03x, ignore change %03x\n", | 1867 | VDBG("devstat %03x, ignore change %03x\n", |
1819 | devstat, change); | 1868 | devstat, change); |
1820 | 1869 | ||
1821 | UDC_IRQ_SRC_REG = UDC_DS_CHG; | 1870 | omap_writew(UDC_DS_CHG, UDC_IRQ_SRC); |
1822 | } | 1871 | } |
1823 | 1872 | ||
1824 | static irqreturn_t omap_udc_irq(int irq, void *_udc) | 1873 | static irqreturn_t omap_udc_irq(int irq, void *_udc) |
@@ -1829,7 +1878,7 @@ static irqreturn_t omap_udc_irq(int irq, void *_udc) | |||
1829 | unsigned long flags; | 1878 | unsigned long flags; |
1830 | 1879 | ||
1831 | spin_lock_irqsave(&udc->lock, flags); | 1880 | spin_lock_irqsave(&udc->lock, flags); |
1832 | irq_src = UDC_IRQ_SRC_REG; | 1881 | irq_src = omap_readw(UDC_IRQ_SRC); |
1833 | 1882 | ||
1834 | /* Device state change (usb ch9 stuff) */ | 1883 | /* Device state change (usb ch9 stuff) */ |
1835 | if (irq_src & UDC_DS_CHG) { | 1884 | if (irq_src & UDC_DS_CHG) { |
@@ -1852,7 +1901,7 @@ static irqreturn_t omap_udc_irq(int irq, void *_udc) | |||
1852 | irq_src &= ~(UDC_TXN_DONE|UDC_RXN_CNT|UDC_RXN_EOT); | 1901 | irq_src &= ~(UDC_TXN_DONE|UDC_RXN_CNT|UDC_RXN_EOT); |
1853 | } | 1902 | } |
1854 | 1903 | ||
1855 | irq_src &= ~(UDC_SOF|UDC_EPN_TX|UDC_EPN_RX); | 1904 | irq_src &= ~(UDC_IRQ_SOF | UDC_EPN_TX|UDC_EPN_RX); |
1856 | if (irq_src) | 1905 | if (irq_src) |
1857 | DBG("udc_irq, unhandled %03x\n", irq_src); | 1906 | DBG("udc_irq, unhandled %03x\n", irq_src); |
1858 | spin_unlock_irqrestore(&udc->lock, flags); | 1907 | spin_unlock_irqrestore(&udc->lock, flags); |
@@ -1873,7 +1922,7 @@ static void pio_out_timer(unsigned long _ep) | |||
1873 | spin_lock_irqsave(&ep->udc->lock, flags); | 1922 | spin_lock_irqsave(&ep->udc->lock, flags); |
1874 | if (!list_empty(&ep->queue) && ep->ackwait) { | 1923 | if (!list_empty(&ep->queue) && ep->ackwait) { |
1875 | use_ep(ep, UDC_EP_SEL); | 1924 | use_ep(ep, UDC_EP_SEL); |
1876 | stat_flg = UDC_STAT_FLG_REG; | 1925 | stat_flg = omap_readw(UDC_STAT_FLG); |
1877 | 1926 | ||
1878 | if ((stat_flg & UDC_ACK) && (!(stat_flg & UDC_FIFO_EN) | 1927 | if ((stat_flg & UDC_ACK) && (!(stat_flg & UDC_FIFO_EN) |
1879 | || (ep->double_buf && HALF_FULL(stat_flg)))) { | 1928 | || (ep->double_buf && HALF_FULL(stat_flg)))) { |
@@ -1883,8 +1932,8 @@ static void pio_out_timer(unsigned long _ep) | |||
1883 | req = container_of(ep->queue.next, | 1932 | req = container_of(ep->queue.next, |
1884 | struct omap_req, queue); | 1933 | struct omap_req, queue); |
1885 | (void) read_fifo(ep, req); | 1934 | (void) read_fifo(ep, req); |
1886 | UDC_EP_NUM_REG = ep->bEndpointAddress; | 1935 | omap_writew(ep->bEndpointAddress, UDC_EP_NUM); |
1887 | UDC_CTRL_REG = UDC_SET_FIFO_EN; | 1936 | omap_writew(UDC_SET_FIFO_EN, UDC_CTRL); |
1888 | ep->ackwait = 1 + ep->double_buf; | 1937 | ep->ackwait = 1 + ep->double_buf; |
1889 | } else | 1938 | } else |
1890 | deselect_ep(); | 1939 | deselect_ep(); |
@@ -1904,20 +1953,20 @@ static irqreturn_t omap_udc_pio_irq(int irq, void *_dev) | |||
1904 | unsigned long flags; | 1953 | unsigned long flags; |
1905 | 1954 | ||
1906 | spin_lock_irqsave(&udc->lock, flags); | 1955 | spin_lock_irqsave(&udc->lock, flags); |
1907 | epn_stat = UDC_EPN_STAT_REG; | 1956 | epn_stat = omap_readw(UDC_EPN_STAT); |
1908 | irq_src = UDC_IRQ_SRC_REG; | 1957 | irq_src = omap_readw(UDC_IRQ_SRC); |
1909 | 1958 | ||
1910 | /* handle OUT first, to avoid some wasteful NAKs */ | 1959 | /* handle OUT first, to avoid some wasteful NAKs */ |
1911 | if (irq_src & UDC_EPN_RX) { | 1960 | if (irq_src & UDC_EPN_RX) { |
1912 | epnum = (epn_stat >> 8) & 0x0f; | 1961 | epnum = (epn_stat >> 8) & 0x0f; |
1913 | UDC_IRQ_SRC_REG = UDC_EPN_RX; | 1962 | omap_writew(UDC_EPN_RX, UDC_IRQ_SRC); |
1914 | status = IRQ_HANDLED; | 1963 | status = IRQ_HANDLED; |
1915 | ep = &udc->ep[epnum]; | 1964 | ep = &udc->ep[epnum]; |
1916 | ep->irqs++; | 1965 | ep->irqs++; |
1917 | 1966 | ||
1918 | UDC_EP_NUM_REG = epnum | UDC_EP_SEL; | 1967 | omap_writew(epnum | UDC_EP_SEL, UDC_EP_NUM); |
1919 | ep->fnf = 0; | 1968 | ep->fnf = 0; |
1920 | if ((UDC_STAT_FLG_REG & UDC_ACK)) { | 1969 | if (omap_readw(UDC_STAT_FLG) & UDC_ACK) { |
1921 | ep->ackwait--; | 1970 | ep->ackwait--; |
1922 | if (!list_empty(&ep->queue)) { | 1971 | if (!list_empty(&ep->queue)) { |
1923 | int stat; | 1972 | int stat; |
@@ -1929,15 +1978,15 @@ static irqreturn_t omap_udc_pio_irq(int irq, void *_dev) | |||
1929 | } | 1978 | } |
1930 | } | 1979 | } |
1931 | /* min 6 clock delay before clearing EP_SEL ... */ | 1980 | /* min 6 clock delay before clearing EP_SEL ... */ |
1932 | epn_stat = UDC_EPN_STAT_REG; | 1981 | epn_stat = omap_readw(UDC_EPN_STAT); |
1933 | epn_stat = UDC_EPN_STAT_REG; | 1982 | epn_stat = omap_readw(UDC_EPN_STAT); |
1934 | UDC_EP_NUM_REG = epnum; | 1983 | omap_writew(epnum, UDC_EP_NUM); |
1935 | 1984 | ||
1936 | /* enabling fifo _after_ clearing ACK, contrary to docs, | 1985 | /* enabling fifo _after_ clearing ACK, contrary to docs, |
1937 | * reduces lossage; timer still needed though (sigh). | 1986 | * reduces lossage; timer still needed though (sigh). |
1938 | */ | 1987 | */ |
1939 | if (ep->fnf) { | 1988 | if (ep->fnf) { |
1940 | UDC_CTRL_REG = UDC_SET_FIFO_EN; | 1989 | omap_writew(UDC_SET_FIFO_EN, UDC_CTRL); |
1941 | ep->ackwait = 1 + ep->double_buf; | 1990 | ep->ackwait = 1 + ep->double_buf; |
1942 | } | 1991 | } |
1943 | mod_timer(&ep->timer, PIO_OUT_TIMEOUT); | 1992 | mod_timer(&ep->timer, PIO_OUT_TIMEOUT); |
@@ -1946,13 +1995,13 @@ static irqreturn_t omap_udc_pio_irq(int irq, void *_dev) | |||
1946 | /* then IN transfers */ | 1995 | /* then IN transfers */ |
1947 | else if (irq_src & UDC_EPN_TX) { | 1996 | else if (irq_src & UDC_EPN_TX) { |
1948 | epnum = epn_stat & 0x0f; | 1997 | epnum = epn_stat & 0x0f; |
1949 | UDC_IRQ_SRC_REG = UDC_EPN_TX; | 1998 | omap_writew(UDC_EPN_TX, UDC_IRQ_SRC); |
1950 | status = IRQ_HANDLED; | 1999 | status = IRQ_HANDLED; |
1951 | ep = &udc->ep[16 + epnum]; | 2000 | ep = &udc->ep[16 + epnum]; |
1952 | ep->irqs++; | 2001 | ep->irqs++; |
1953 | 2002 | ||
1954 | UDC_EP_NUM_REG = epnum | UDC_EP_DIR | UDC_EP_SEL; | 2003 | omap_writew(epnum | UDC_EP_DIR | UDC_EP_SEL, UDC_EP_NUM); |
1955 | if ((UDC_STAT_FLG_REG & UDC_ACK)) { | 2004 | if (omap_readw(UDC_STAT_FLG) & UDC_ACK) { |
1956 | ep->ackwait = 0; | 2005 | ep->ackwait = 0; |
1957 | if (!list_empty(&ep->queue)) { | 2006 | if (!list_empty(&ep->queue)) { |
1958 | req = container_of(ep->queue.next, | 2007 | req = container_of(ep->queue.next, |
@@ -1961,9 +2010,9 @@ static irqreturn_t omap_udc_pio_irq(int irq, void *_dev) | |||
1961 | } | 2010 | } |
1962 | } | 2011 | } |
1963 | /* min 6 clock delay before clearing EP_SEL ... */ | 2012 | /* min 6 clock delay before clearing EP_SEL ... */ |
1964 | epn_stat = UDC_EPN_STAT_REG; | 2013 | epn_stat = omap_readw(UDC_EPN_STAT); |
1965 | epn_stat = UDC_EPN_STAT_REG; | 2014 | epn_stat = omap_readw(UDC_EPN_STAT); |
1966 | UDC_EP_NUM_REG = epnum | UDC_EP_DIR; | 2015 | omap_writew(epnum | UDC_EP_DIR, UDC_EP_NUM); |
1967 | /* then 6 clocks before it'd tx */ | 2016 | /* then 6 clocks before it'd tx */ |
1968 | } | 2017 | } |
1969 | 2018 | ||
@@ -1991,7 +2040,7 @@ static irqreturn_t omap_udc_iso_irq(int irq, void *_dev) | |||
1991 | req = list_entry(ep->queue.next, struct omap_req, queue); | 2040 | req = list_entry(ep->queue.next, struct omap_req, queue); |
1992 | 2041 | ||
1993 | use_ep(ep, UDC_EP_SEL); | 2042 | use_ep(ep, UDC_EP_SEL); |
1994 | stat = UDC_STAT_FLG_REG; | 2043 | stat = omap_readw(UDC_STAT_FLG); |
1995 | 2044 | ||
1996 | /* NOTE: like the other controller drivers, this isn't | 2045 | /* NOTE: like the other controller drivers, this isn't |
1997 | * currently reporting lost or damaged frames. | 2046 | * currently reporting lost or damaged frames. |
@@ -2023,9 +2072,14 @@ static irqreturn_t omap_udc_iso_irq(int irq, void *_dev) | |||
2023 | if (!list_empty(&ep->queue)) | 2072 | if (!list_empty(&ep->queue)) |
2024 | pending = 1; | 2073 | pending = 1; |
2025 | } | 2074 | } |
2026 | if (!pending) | 2075 | if (!pending) { |
2027 | UDC_IRQ_EN_REG &= ~UDC_SOF_IE; | 2076 | u16 w; |
2028 | UDC_IRQ_SRC_REG = UDC_SOF; | 2077 | |
2078 | w = omap_readw(UDC_IRQ_EN); | ||
2079 | w &= ~UDC_SOF_IE; | ||
2080 | omap_writew(w, UDC_IRQ_EN); | ||
2081 | } | ||
2082 | omap_writew(UDC_IRQ_SOF, UDC_IRQ_SRC); | ||
2029 | 2083 | ||
2030 | spin_unlock_irqrestore(&udc->lock, flags); | 2084 | spin_unlock_irqrestore(&udc->lock, flags); |
2031 | return IRQ_HANDLED; | 2085 | return IRQ_HANDLED; |
@@ -2074,7 +2128,7 @@ int usb_gadget_register_driver (struct usb_gadget_driver *driver) | |||
2074 | if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) | 2128 | if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) |
2075 | continue; | 2129 | continue; |
2076 | use_ep(ep, 0); | 2130 | use_ep(ep, 0); |
2077 | UDC_CTRL_REG = UDC_SET_HALT; | 2131 | omap_writew(UDC_SET_HALT, UDC_CTRL); |
2078 | } | 2132 | } |
2079 | udc->ep0_pending = 0; | 2133 | udc->ep0_pending = 0; |
2080 | udc->ep[0].irqs = 0; | 2134 | udc->ep[0].irqs = 0; |
@@ -2098,7 +2152,7 @@ int usb_gadget_register_driver (struct usb_gadget_driver *driver) | |||
2098 | } | 2152 | } |
2099 | DBG("bound to driver %s\n", driver->driver.name); | 2153 | DBG("bound to driver %s\n", driver->driver.name); |
2100 | 2154 | ||
2101 | UDC_IRQ_SRC_REG = UDC_IRQ_SRC_MASK; | 2155 | omap_writew(UDC_IRQ_SRC_MASK, UDC_IRQ_SRC); |
2102 | 2156 | ||
2103 | /* connect to bus through transceiver */ | 2157 | /* connect to bus through transceiver */ |
2104 | if (udc->transceiver) { | 2158 | if (udc->transceiver) { |
@@ -2195,7 +2249,7 @@ static void proc_ep_show(struct seq_file *s, struct omap_ep *ep) | |||
2195 | else | 2249 | else |
2196 | buf[0] = 0; | 2250 | buf[0] = 0; |
2197 | 2251 | ||
2198 | stat_flg = UDC_STAT_FLG_REG; | 2252 | stat_flg = omap_readw(UDC_STAT_FLG); |
2199 | seq_printf(s, | 2253 | seq_printf(s, |
2200 | "\n%s %s%s%sirqs %ld stat %04x " EIGHTBITS FOURBITS "%s\n", | 2254 | "\n%s %s%s%sirqs %ld stat %04x " EIGHTBITS FOURBITS "%s\n", |
2201 | ep->name, buf, | 2255 | ep->name, buf, |
@@ -2262,11 +2316,11 @@ static int proc_otg_show(struct seq_file *s) | |||
2262 | trans = CONTROL_DEVCONF_REG; | 2316 | trans = CONTROL_DEVCONF_REG; |
2263 | } else { | 2317 | } else { |
2264 | ctrl_name = "tranceiver_ctrl"; | 2318 | ctrl_name = "tranceiver_ctrl"; |
2265 | trans = USB_TRANSCEIVER_CTRL_REG; | 2319 | trans = omap_readw(USB_TRANSCEIVER_CTRL); |
2266 | } | 2320 | } |
2267 | seq_printf(s, "\nOTG rev %d.%d, %s %05x\n", | 2321 | seq_printf(s, "\nOTG rev %d.%d, %s %05x\n", |
2268 | tmp >> 4, tmp & 0xf, ctrl_name, trans); | 2322 | tmp >> 4, tmp & 0xf, ctrl_name, trans); |
2269 | tmp = OTG_SYSCON_1_REG; | 2323 | tmp = omap_readw(OTG_SYSCON_1); |
2270 | seq_printf(s, "otg_syscon1 %08x usb2 %s, usb1 %s, usb0 %s," | 2324 | seq_printf(s, "otg_syscon1 %08x usb2 %s, usb1 %s, usb0 %s," |
2271 | FOURBITS "\n", tmp, | 2325 | FOURBITS "\n", tmp, |
2272 | trx_mode(USB2_TRX_MODE(tmp), trans & CONF_USB2_UNI_R), | 2326 | trx_mode(USB2_TRX_MODE(tmp), trans & CONF_USB2_UNI_R), |
@@ -2278,7 +2332,7 @@ static int proc_otg_show(struct seq_file *s) | |||
2278 | (tmp & HST_IDLE_EN) ? " !host" : "", | 2332 | (tmp & HST_IDLE_EN) ? " !host" : "", |
2279 | (tmp & DEV_IDLE_EN) ? " !dev" : "", | 2333 | (tmp & DEV_IDLE_EN) ? " !dev" : "", |
2280 | (tmp & OTG_RESET_DONE) ? " reset_done" : " reset_active"); | 2334 | (tmp & OTG_RESET_DONE) ? " reset_done" : " reset_active"); |
2281 | tmp = OTG_SYSCON_2_REG; | 2335 | tmp = omap_readl(OTG_SYSCON_2); |
2282 | seq_printf(s, "otg_syscon2 %08x%s" EIGHTBITS | 2336 | seq_printf(s, "otg_syscon2 %08x%s" EIGHTBITS |
2283 | " b_ase_brst=%d hmc=%d\n", tmp, | 2337 | " b_ase_brst=%d hmc=%d\n", tmp, |
2284 | (tmp & OTG_EN) ? " otg_en" : "", | 2338 | (tmp & OTG_EN) ? " otg_en" : "", |
@@ -2293,7 +2347,7 @@ static int proc_otg_show(struct seq_file *s) | |||
2293 | (tmp & HMC_TLLATTACH) ? " tllattach" : "", | 2347 | (tmp & HMC_TLLATTACH) ? " tllattach" : "", |
2294 | B_ASE_BRST(tmp), | 2348 | B_ASE_BRST(tmp), |
2295 | OTG_HMC(tmp)); | 2349 | OTG_HMC(tmp)); |
2296 | tmp = OTG_CTRL_REG; | 2350 | tmp = omap_readl(OTG_CTRL); |
2297 | seq_printf(s, "otg_ctrl %06x" EIGHTBITS EIGHTBITS "%s\n", tmp, | 2351 | seq_printf(s, "otg_ctrl %06x" EIGHTBITS EIGHTBITS "%s\n", tmp, |
2298 | (tmp & OTG_ASESSVLD) ? " asess" : "", | 2352 | (tmp & OTG_ASESSVLD) ? " asess" : "", |
2299 | (tmp & OTG_BSESSEND) ? " bsess_end" : "", | 2353 | (tmp & OTG_BSESSEND) ? " bsess_end" : "", |
@@ -2313,13 +2367,13 @@ static int proc_otg_show(struct seq_file *s) | |||
2313 | (tmp & OTG_PU_VBUS) ? " pu_vb" : "", | 2367 | (tmp & OTG_PU_VBUS) ? " pu_vb" : "", |
2314 | (tmp & OTG_PU_ID) ? " pu_id" : "" | 2368 | (tmp & OTG_PU_ID) ? " pu_id" : "" |
2315 | ); | 2369 | ); |
2316 | tmp = OTG_IRQ_EN_REG; | 2370 | tmp = omap_readw(OTG_IRQ_EN); |
2317 | seq_printf(s, "otg_irq_en %04x" "\n", tmp); | 2371 | seq_printf(s, "otg_irq_en %04x" "\n", tmp); |
2318 | tmp = OTG_IRQ_SRC_REG; | 2372 | tmp = omap_readw(OTG_IRQ_SRC); |
2319 | seq_printf(s, "otg_irq_src %04x" "\n", tmp); | 2373 | seq_printf(s, "otg_irq_src %04x" "\n", tmp); |
2320 | tmp = OTG_OUTCTRL_REG; | 2374 | tmp = omap_readw(OTG_OUTCTRL); |
2321 | seq_printf(s, "otg_outctrl %04x" "\n", tmp); | 2375 | seq_printf(s, "otg_outctrl %04x" "\n", tmp); |
2322 | tmp = OTG_TEST_REG; | 2376 | tmp = omap_readw(OTG_TEST); |
2323 | seq_printf(s, "otg_test %04x" "\n", tmp); | 2377 | seq_printf(s, "otg_test %04x" "\n", tmp); |
2324 | return 0; | 2378 | return 0; |
2325 | } | 2379 | } |
@@ -2340,7 +2394,7 @@ static int proc_udc_show(struct seq_file *s, void *_) | |||
2340 | driver_desc, | 2394 | driver_desc, |
2341 | use_dma ? " (dma)" : ""); | 2395 | use_dma ? " (dma)" : ""); |
2342 | 2396 | ||
2343 | tmp = UDC_REV_REG & 0xff; | 2397 | tmp = omap_readw(UDC_REV) & 0xff; |
2344 | seq_printf(s, | 2398 | seq_printf(s, |
2345 | "UDC rev %d.%d, fifo mode %d, gadget %s\n" | 2399 | "UDC rev %d.%d, fifo mode %d, gadget %s\n" |
2346 | "hmc %d, transceiver %s\n", | 2400 | "hmc %d, transceiver %s\n", |
@@ -2354,16 +2408,16 @@ static int proc_udc_show(struct seq_file *s, void *_) | |||
2354 | ? "external" : "(none)")); | 2408 | ? "external" : "(none)")); |
2355 | if (cpu_class_is_omap1()) { | 2409 | if (cpu_class_is_omap1()) { |
2356 | seq_printf(s, "ULPD control %04x req %04x status %04x\n", | 2410 | seq_printf(s, "ULPD control %04x req %04x status %04x\n", |
2357 | __REG16(ULPD_CLOCK_CTRL), | 2411 | omap_readw(ULPD_CLOCK_CTRL), |
2358 | __REG16(ULPD_SOFT_REQ), | 2412 | omap_readw(ULPD_SOFT_REQ), |
2359 | __REG16(ULPD_STATUS_REQ)); | 2413 | omap_readw(ULPD_STATUS_REQ)); |
2360 | } | 2414 | } |
2361 | 2415 | ||
2362 | /* OTG controller registers */ | 2416 | /* OTG controller registers */ |
2363 | if (!cpu_is_omap15xx()) | 2417 | if (!cpu_is_omap15xx()) |
2364 | proc_otg_show(s); | 2418 | proc_otg_show(s); |
2365 | 2419 | ||
2366 | tmp = UDC_SYSCON1_REG; | 2420 | tmp = omap_readw(UDC_SYSCON1); |
2367 | seq_printf(s, "\nsyscon1 %04x" EIGHTBITS "\n", tmp, | 2421 | seq_printf(s, "\nsyscon1 %04x" EIGHTBITS "\n", tmp, |
2368 | (tmp & UDC_CFG_LOCK) ? " cfg_lock" : "", | 2422 | (tmp & UDC_CFG_LOCK) ? " cfg_lock" : "", |
2369 | (tmp & UDC_DATA_ENDIAN) ? " data_endian" : "", | 2423 | (tmp & UDC_DATA_ENDIAN) ? " data_endian" : "", |
@@ -2382,7 +2436,7 @@ static int proc_udc_show(struct seq_file *s, void *_) | |||
2382 | return 0; | 2436 | return 0; |
2383 | } | 2437 | } |
2384 | 2438 | ||
2385 | tmp = UDC_DEVSTAT_REG; | 2439 | tmp = omap_readw(UDC_DEVSTAT); |
2386 | seq_printf(s, "devstat %04x" EIGHTBITS "%s%s\n", tmp, | 2440 | seq_printf(s, "devstat %04x" EIGHTBITS "%s%s\n", tmp, |
2387 | (tmp & UDC_B_HNP_ENABLE) ? " b_hnp" : "", | 2441 | (tmp & UDC_B_HNP_ENABLE) ? " b_hnp" : "", |
2388 | (tmp & UDC_A_HNP_SUPPORT) ? " a_hnp" : "", | 2442 | (tmp & UDC_A_HNP_SUPPORT) ? " a_hnp" : "", |
@@ -2394,20 +2448,20 @@ static int proc_udc_show(struct seq_file *s, void *_) | |||
2394 | (tmp & UDC_ADD) ? " ADD" : "", | 2448 | (tmp & UDC_ADD) ? " ADD" : "", |
2395 | (tmp & UDC_DEF) ? " DEF" : "", | 2449 | (tmp & UDC_DEF) ? " DEF" : "", |
2396 | (tmp & UDC_ATT) ? " ATT" : ""); | 2450 | (tmp & UDC_ATT) ? " ATT" : ""); |
2397 | seq_printf(s, "sof %04x\n", UDC_SOF_REG); | 2451 | seq_printf(s, "sof %04x\n", omap_readw(UDC_SOF)); |
2398 | tmp = UDC_IRQ_EN_REG; | 2452 | tmp = omap_readw(UDC_IRQ_EN); |
2399 | seq_printf(s, "irq_en %04x" FOURBITS "%s\n", tmp, | 2453 | seq_printf(s, "irq_en %04x" FOURBITS "%s\n", tmp, |
2400 | (tmp & UDC_SOF_IE) ? " sof" : "", | 2454 | (tmp & UDC_SOF_IE) ? " sof" : "", |
2401 | (tmp & UDC_EPN_RX_IE) ? " epn_rx" : "", | 2455 | (tmp & UDC_EPN_RX_IE) ? " epn_rx" : "", |
2402 | (tmp & UDC_EPN_TX_IE) ? " epn_tx" : "", | 2456 | (tmp & UDC_EPN_TX_IE) ? " epn_tx" : "", |
2403 | (tmp & UDC_DS_CHG_IE) ? " ds_chg" : "", | 2457 | (tmp & UDC_DS_CHG_IE) ? " ds_chg" : "", |
2404 | (tmp & UDC_EP0_IE) ? " ep0" : ""); | 2458 | (tmp & UDC_EP0_IE) ? " ep0" : ""); |
2405 | tmp = UDC_IRQ_SRC_REG; | 2459 | tmp = omap_readw(UDC_IRQ_SRC); |
2406 | seq_printf(s, "irq_src %04x" EIGHTBITS "%s%s\n", tmp, | 2460 | seq_printf(s, "irq_src %04x" EIGHTBITS "%s%s\n", tmp, |
2407 | (tmp & UDC_TXN_DONE) ? " txn_done" : "", | 2461 | (tmp & UDC_TXN_DONE) ? " txn_done" : "", |
2408 | (tmp & UDC_RXN_CNT) ? " rxn_cnt" : "", | 2462 | (tmp & UDC_RXN_CNT) ? " rxn_cnt" : "", |
2409 | (tmp & UDC_RXN_EOT) ? " rxn_eot" : "", | 2463 | (tmp & UDC_RXN_EOT) ? " rxn_eot" : "", |
2410 | (tmp & UDC_SOF) ? " sof" : "", | 2464 | (tmp & UDC_IRQ_SOF) ? " sof" : "", |
2411 | (tmp & UDC_EPN_RX) ? " epn_rx" : "", | 2465 | (tmp & UDC_EPN_RX) ? " epn_rx" : "", |
2412 | (tmp & UDC_EPN_TX) ? " epn_tx" : "", | 2466 | (tmp & UDC_EPN_TX) ? " epn_tx" : "", |
2413 | (tmp & UDC_DS_CHG) ? " ds_chg" : "", | 2467 | (tmp & UDC_DS_CHG) ? " ds_chg" : "", |
@@ -2417,7 +2471,7 @@ static int proc_udc_show(struct seq_file *s, void *_) | |||
2417 | if (use_dma) { | 2471 | if (use_dma) { |
2418 | unsigned i; | 2472 | unsigned i; |
2419 | 2473 | ||
2420 | tmp = UDC_DMA_IRQ_EN_REG; | 2474 | tmp = omap_readw(UDC_DMA_IRQ_EN); |
2421 | seq_printf(s, "dma_irq_en %04x%s" EIGHTBITS "\n", tmp, | 2475 | seq_printf(s, "dma_irq_en %04x%s" EIGHTBITS "\n", tmp, |
2422 | (tmp & UDC_TX_DONE_IE(3)) ? " tx2_done" : "", | 2476 | (tmp & UDC_TX_DONE_IE(3)) ? " tx2_done" : "", |
2423 | (tmp & UDC_RX_CNT_IE(3)) ? " rx2_cnt" : "", | 2477 | (tmp & UDC_RX_CNT_IE(3)) ? " rx2_cnt" : "", |
@@ -2431,29 +2485,29 @@ static int proc_udc_show(struct seq_file *s, void *_) | |||
2431 | (tmp & UDC_RX_CNT_IE(1)) ? " rx0_cnt" : "", | 2485 | (tmp & UDC_RX_CNT_IE(1)) ? " rx0_cnt" : "", |
2432 | (tmp & UDC_RX_EOT_IE(1)) ? " rx0_eot" : ""); | 2486 | (tmp & UDC_RX_EOT_IE(1)) ? " rx0_eot" : ""); |
2433 | 2487 | ||
2434 | tmp = UDC_RXDMA_CFG_REG; | 2488 | tmp = omap_readw(UDC_RXDMA_CFG); |
2435 | seq_printf(s, "rxdma_cfg %04x\n", tmp); | 2489 | seq_printf(s, "rxdma_cfg %04x\n", tmp); |
2436 | if (tmp) { | 2490 | if (tmp) { |
2437 | for (i = 0; i < 3; i++) { | 2491 | for (i = 0; i < 3; i++) { |
2438 | if ((tmp & (0x0f << (i * 4))) == 0) | 2492 | if ((tmp & (0x0f << (i * 4))) == 0) |
2439 | continue; | 2493 | continue; |
2440 | seq_printf(s, "rxdma[%d] %04x\n", i, | 2494 | seq_printf(s, "rxdma[%d] %04x\n", i, |
2441 | UDC_RXDMA_REG(i + 1)); | 2495 | omap_readw(UDC_RXDMA(i + 1))); |
2442 | } | 2496 | } |
2443 | } | 2497 | } |
2444 | tmp = UDC_TXDMA_CFG_REG; | 2498 | tmp = omap_readw(UDC_TXDMA_CFG); |
2445 | seq_printf(s, "txdma_cfg %04x\n", tmp); | 2499 | seq_printf(s, "txdma_cfg %04x\n", tmp); |
2446 | if (tmp) { | 2500 | if (tmp) { |
2447 | for (i = 0; i < 3; i++) { | 2501 | for (i = 0; i < 3; i++) { |
2448 | if (!(tmp & (0x0f << (i * 4)))) | 2502 | if (!(tmp & (0x0f << (i * 4)))) |
2449 | continue; | 2503 | continue; |
2450 | seq_printf(s, "txdma[%d] %04x\n", i, | 2504 | seq_printf(s, "txdma[%d] %04x\n", i, |
2451 | UDC_TXDMA_REG(i + 1)); | 2505 | omap_readw(UDC_TXDMA(i + 1))); |
2452 | } | 2506 | } |
2453 | } | 2507 | } |
2454 | } | 2508 | } |
2455 | 2509 | ||
2456 | tmp = UDC_DEVSTAT_REG; | 2510 | tmp = omap_readw(UDC_DEVSTAT); |
2457 | if (tmp & UDC_ATT) { | 2511 | if (tmp & UDC_ATT) { |
2458 | proc_ep_show(s, &udc->ep[0]); | 2512 | proc_ep_show(s, &udc->ep[0]); |
2459 | if (tmp & UDC_ADD) { | 2513 | if (tmp & UDC_ADD) { |
@@ -2505,7 +2559,7 @@ static inline void remove_proc_file(void) {} | |||
2505 | * buffer space among the endpoints we'll be operating. | 2559 | * buffer space among the endpoints we'll be operating. |
2506 | * | 2560 | * |
2507 | * NOTE: as of OMAP 1710 ES2.0, writing a new endpoint config when | 2561 | * NOTE: as of OMAP 1710 ES2.0, writing a new endpoint config when |
2508 | * UDC_SYSCON_1_REG.CFG_LOCK is set can now work. We won't use that | 2562 | * UDC_SYSCON_1.CFG_LOCK is set can now work. We won't use that |
2509 | * capability yet though. | 2563 | * capability yet though. |
2510 | */ | 2564 | */ |
2511 | static unsigned __init | 2565 | static unsigned __init |
@@ -2567,9 +2621,9 @@ omap_ep_setup(char *name, u8 addr, u8 type, | |||
2567 | name, addr, epn_rxtx, maxp, dbuf ? "x2" : "", buf); | 2621 | name, addr, epn_rxtx, maxp, dbuf ? "x2" : "", buf); |
2568 | 2622 | ||
2569 | if (addr & USB_DIR_IN) | 2623 | if (addr & USB_DIR_IN) |
2570 | UDC_EP_TX_REG(addr & 0xf) = epn_rxtx; | 2624 | omap_writew(epn_rxtx, UDC_EP_TX(addr & 0xf)); |
2571 | else | 2625 | else |
2572 | UDC_EP_RX_REG(addr) = epn_rxtx; | 2626 | omap_writew(epn_rxtx, UDC_EP_RX(addr)); |
2573 | 2627 | ||
2574 | /* next endpoint's buffer starts after this one's */ | 2628 | /* next endpoint's buffer starts after this one's */ |
2575 | buf += maxp; | 2629 | buf += maxp; |
@@ -2608,15 +2662,15 @@ omap_udc_setup(struct platform_device *odev, struct otg_transceiver *xceiv) | |||
2608 | unsigned tmp, buf; | 2662 | unsigned tmp, buf; |
2609 | 2663 | ||
2610 | /* abolish any previous hardware state */ | 2664 | /* abolish any previous hardware state */ |
2611 | UDC_SYSCON1_REG = 0; | 2665 | omap_writew(0, UDC_SYSCON1); |
2612 | UDC_IRQ_EN_REG = 0; | 2666 | omap_writew(0, UDC_IRQ_EN); |
2613 | UDC_IRQ_SRC_REG = UDC_IRQ_SRC_MASK; | 2667 | omap_writew(UDC_IRQ_SRC_MASK, UDC_IRQ_SRC); |
2614 | UDC_DMA_IRQ_EN_REG = 0; | 2668 | omap_writew(0, UDC_DMA_IRQ_EN); |
2615 | UDC_RXDMA_CFG_REG = 0; | 2669 | omap_writew(0, UDC_RXDMA_CFG); |
2616 | UDC_TXDMA_CFG_REG = 0; | 2670 | omap_writew(0, UDC_TXDMA_CFG); |
2617 | 2671 | ||
2618 | /* UDC_PULLUP_EN gates the chip clock */ | 2672 | /* UDC_PULLUP_EN gates the chip clock */ |
2619 | // OTG_SYSCON_1_REG |= DEV_IDLE_EN; | 2673 | // OTG_SYSCON_1 |= DEV_IDLE_EN; |
2620 | 2674 | ||
2621 | udc = kzalloc(sizeof(*udc), GFP_KERNEL); | 2675 | udc = kzalloc(sizeof(*udc), GFP_KERNEL); |
2622 | if (!udc) | 2676 | if (!udc) |
@@ -2647,8 +2701,8 @@ omap_udc_setup(struct platform_device *odev, struct otg_transceiver *xceiv) | |||
2647 | 2701 | ||
2648 | /* initially disable all non-ep0 endpoints */ | 2702 | /* initially disable all non-ep0 endpoints */ |
2649 | for (tmp = 1; tmp < 15; tmp++) { | 2703 | for (tmp = 1; tmp < 15; tmp++) { |
2650 | UDC_EP_RX_REG(tmp) = 0; | 2704 | omap_writew(0, UDC_EP_RX(tmp)); |
2651 | UDC_EP_TX_REG(tmp) = 0; | 2705 | omap_writew(0, UDC_EP_TX(tmp)); |
2652 | } | 2706 | } |
2653 | 2707 | ||
2654 | #define OMAP_BULK_EP(name,addr) \ | 2708 | #define OMAP_BULK_EP(name,addr) \ |
@@ -2733,7 +2787,7 @@ omap_udc_setup(struct platform_device *odev, struct otg_transceiver *xceiv) | |||
2733 | ERR("unsupported fifo_mode #%d\n", fifo_mode); | 2787 | ERR("unsupported fifo_mode #%d\n", fifo_mode); |
2734 | return -ENODEV; | 2788 | return -ENODEV; |
2735 | } | 2789 | } |
2736 | UDC_SYSCON1_REG = UDC_CFG_LOCK|UDC_SELF_PWR; | 2790 | omap_writew(UDC_CFG_LOCK|UDC_SELF_PWR, UDC_SYSCON1); |
2737 | INFO("fifo mode %d, %d bytes not used\n", fifo_mode, 2048 - buf); | 2791 | INFO("fifo mode %d, %d bytes not used\n", fifo_mode, 2048 - buf); |
2738 | return 0; | 2792 | return 0; |
2739 | } | 2793 | } |
@@ -2777,7 +2831,7 @@ static int __init omap_udc_probe(struct platform_device *pdev) | |||
2777 | } | 2831 | } |
2778 | 2832 | ||
2779 | INFO("OMAP UDC rev %d.%d%s\n", | 2833 | INFO("OMAP UDC rev %d.%d%s\n", |
2780 | UDC_REV_REG >> 4, UDC_REV_REG & 0xf, | 2834 | omap_readw(UDC_REV) >> 4, omap_readw(UDC_REV) & 0xf, |
2781 | config->otg ? ", Mini-AB" : ""); | 2835 | config->otg ? ", Mini-AB" : ""); |
2782 | 2836 | ||
2783 | /* use the mode given to us by board init code */ | 2837 | /* use the mode given to us by board init code */ |
@@ -2792,12 +2846,12 @@ static int __init omap_udc_probe(struct platform_device *pdev) | |||
2792 | * know when to turn PULLUP_EN on/off; and that | 2846 | * know when to turn PULLUP_EN on/off; and that |
2793 | * means we always "need" the 48MHz clock. | 2847 | * means we always "need" the 48MHz clock. |
2794 | */ | 2848 | */ |
2795 | u32 tmp = FUNC_MUX_CTRL_0_REG; | 2849 | u32 tmp = omap_readl(FUNC_MUX_CTRL_0); |
2796 | 2850 | tmp &= ~VBUS_CTRL_1510; | |
2797 | FUNC_MUX_CTRL_0_REG &= ~VBUS_CTRL_1510; | 2851 | omap_writel(tmp, FUNC_MUX_CTRL_0); |
2798 | tmp |= VBUS_MODE_1510; | 2852 | tmp |= VBUS_MODE_1510; |
2799 | tmp &= ~VBUS_CTRL_1510; | 2853 | tmp &= ~VBUS_CTRL_1510; |
2800 | FUNC_MUX_CTRL_0_REG = tmp; | 2854 | omap_writel(tmp, FUNC_MUX_CTRL_0); |
2801 | } | 2855 | } |
2802 | } else { | 2856 | } else { |
2803 | /* The transceiver may package some GPIO logic or handle | 2857 | /* The transceiver may package some GPIO logic or handle |
@@ -2877,7 +2931,7 @@ known: | |||
2877 | #endif | 2931 | #endif |
2878 | 2932 | ||
2879 | /* starting with omap1710 es2.0, clear toggle is a separate bit */ | 2933 | /* starting with omap1710 es2.0, clear toggle is a separate bit */ |
2880 | if (UDC_REV_REG >= 0x61) | 2934 | if (omap_readw(UDC_REV) >= 0x61) |
2881 | udc->clr_halt = UDC_RESET_EP | UDC_CLRDATA_TOGGLE; | 2935 | udc->clr_halt = UDC_RESET_EP | UDC_CLRDATA_TOGGLE; |
2882 | else | 2936 | else |
2883 | udc->clr_halt = UDC_RESET_EP; | 2937 | udc->clr_halt = UDC_RESET_EP; |
@@ -2975,7 +3029,7 @@ static int __exit omap_udc_remove(struct platform_device *pdev) | |||
2975 | put_device(udc->transceiver->dev); | 3029 | put_device(udc->transceiver->dev); |
2976 | udc->transceiver = NULL; | 3030 | udc->transceiver = NULL; |
2977 | } | 3031 | } |
2978 | UDC_SYSCON1_REG = 0; | 3032 | omap_writew(0, UDC_SYSCON1); |
2979 | 3033 | ||
2980 | remove_proc_file(); | 3034 | remove_proc_file(); |
2981 | 3035 | ||
@@ -3006,7 +3060,7 @@ static int __exit omap_udc_remove(struct platform_device *pdev) | |||
3006 | * | 3060 | * |
3007 | * REVISIT we should probably reject suspend requests when there's a host | 3061 | * REVISIT we should probably reject suspend requests when there's a host |
3008 | * session active, rather than disconnecting, at least on boards that can | 3062 | * session active, rather than disconnecting, at least on boards that can |
3009 | * report VBUS irqs (UDC_DEVSTAT_REG.UDC_ATT). And in any case, we need to | 3063 | * report VBUS irqs (UDC_DEVSTAT.UDC_ATT). And in any case, we need to |
3010 | * make host resumes and VBUS detection trigger OMAP wakeup events; that | 3064 | * make host resumes and VBUS detection trigger OMAP wakeup events; that |
3011 | * may involve talking to an external transceiver (e.g. isp1301). | 3065 | * may involve talking to an external transceiver (e.g. isp1301). |
3012 | */ | 3066 | */ |
@@ -3015,7 +3069,7 @@ static int omap_udc_suspend(struct platform_device *dev, pm_message_t message) | |||
3015 | { | 3069 | { |
3016 | u32 devstat; | 3070 | u32 devstat; |
3017 | 3071 | ||
3018 | devstat = UDC_DEVSTAT_REG; | 3072 | devstat = omap_readw(UDC_DEVSTAT); |
3019 | 3073 | ||
3020 | /* we're requesting 48 MHz clock if the pullup is enabled | 3074 | /* we're requesting 48 MHz clock if the pullup is enabled |
3021 | * (== we're attached to the host) and we're not suspended, | 3075 | * (== we're attached to the host) and we're not suspended, |