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authorYoshihiro Shimoda <shimoda.yoshihiro@renesas.com>2007-11-22 07:00:30 -0500
committerGreg Kroah-Hartman <gregkh@suse.de>2008-02-01 17:34:48 -0500
commit8c73aff6d3b772e5f373d78bc34fd47b10b35fef (patch)
treec6829760527dd59c27acf86b3f935b3659b2c6fa /drivers/usb/gadget/m66592-udc.h
parent9da0068a4964540d8d1caa8455fe193b544d846d (diff)
USB: m66592-udc: Add support for SH7722 USBF
Add support for SuperH SH7722 USB Function. M66592 is similar to SH7722 USBF. It can support SH7722 USBF by changing several M66592 code. Signed-off-by: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> Acked-by: David Brownell <david-b@pacbell.net> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'drivers/usb/gadget/m66592-udc.h')
-rw-r--r--drivers/usb/gadget/m66592-udc.h54
1 files changed, 54 insertions, 0 deletions
diff --git a/drivers/usb/gadget/m66592-udc.h b/drivers/usb/gadget/m66592-udc.h
index bfa0c645f229..17b792b7f6bf 100644
--- a/drivers/usb/gadget/m66592-udc.h
+++ b/drivers/usb/gadget/m66592-udc.h
@@ -72,6 +72,11 @@
72#define M66592_P_TST_J 0x0001 /* PERI TEST J */ 72#define M66592_P_TST_J 0x0001 /* PERI TEST J */
73#define M66592_P_TST_NORMAL 0x0000 /* PERI Normal Mode */ 73#define M66592_P_TST_NORMAL 0x0000 /* PERI Normal Mode */
74 74
75#if defined(CONFIG_SUPERH_BUILT_IN_M66592)
76#define M66592_CFBCFG 0x0A
77#define M66592_D0FBCFG 0x0C
78#define M66592_LITTLE 0x0100 /* b8: Little endian mode */
79#else
75#define M66592_PINCFG 0x0A 80#define M66592_PINCFG 0x0A
76#define M66592_LDRV 0x8000 /* b15: Drive Current Adjust */ 81#define M66592_LDRV 0x8000 /* b15: Drive Current Adjust */
77#define M66592_BIGEND 0x0100 /* b8: Big endian mode */ 82#define M66592_BIGEND 0x0100 /* b8: Big endian mode */
@@ -91,6 +96,7 @@
91#define M66592_PKTM 0x0020 /* b5: Packet mode */ 96#define M66592_PKTM 0x0020 /* b5: Packet mode */
92#define M66592_DENDE 0x0010 /* b4: Dend enable */ 97#define M66592_DENDE 0x0010 /* b4: Dend enable */
93#define M66592_OBUS 0x0004 /* b2: OUTbus mode */ 98#define M66592_OBUS 0x0004 /* b2: OUTbus mode */
99#endif /* #if defined(CONFIG_SUPERH_BUILT_IN_M66592) */
94 100
95#define M66592_CFIFO 0x10 101#define M66592_CFIFO 0x10
96#define M66592_D0FIFO 0x14 102#define M66592_D0FIFO 0x14
@@ -103,9 +109,13 @@
103#define M66592_REW 0x4000 /* b14: Buffer rewind */ 109#define M66592_REW 0x4000 /* b14: Buffer rewind */
104#define M66592_DCLRM 0x2000 /* b13: DMA buffer clear mode */ 110#define M66592_DCLRM 0x2000 /* b13: DMA buffer clear mode */
105#define M66592_DREQE 0x1000 /* b12: DREQ output enable */ 111#define M66592_DREQE 0x1000 /* b12: DREQ output enable */
112#if defined(CONFIG_SUPERH_BUILT_IN_M66592)
113#define M66592_MBW 0x0800 /* b11: Maximum bit width for FIFO */
114#else
106#define M66592_MBW 0x0400 /* b10: Maximum bit width for FIFO */ 115#define M66592_MBW 0x0400 /* b10: Maximum bit width for FIFO */
107#define M66592_MBW_8 0x0000 /* 8bit */ 116#define M66592_MBW_8 0x0000 /* 8bit */
108#define M66592_MBW_16 0x0400 /* 16bit */ 117#define M66592_MBW_16 0x0400 /* 16bit */
118#endif /* #if defined(CONFIG_SUPERH_BUILT_IN_M66592) */
109#define M66592_TRENB 0x0200 /* b9: Transaction counter enable */ 119#define M66592_TRENB 0x0200 /* b9: Transaction counter enable */
110#define M66592_TRCLR 0x0100 /* b8: Transaction counter clear */ 120#define M66592_TRCLR 0x0100 /* b8: Transaction counter clear */
111#define M66592_DEZPM 0x0080 /* b7: Zero-length packet mode */ 121#define M66592_DEZPM 0x0080 /* b7: Zero-length packet mode */
@@ -530,8 +540,13 @@ static inline void m66592_read_fifo(struct m66592 *m66592,
530{ 540{
531 unsigned long fifoaddr = (unsigned long)m66592->reg + offset; 541 unsigned long fifoaddr = (unsigned long)m66592->reg + offset;
532 542
543#if defined(CONFIG_SUPERH_BUILT_IN_M66592)
544 len = (len + 3) / 4;
545 insl(fifoaddr, buf, len);
546#else
533 len = (len + 1) / 2; 547 len = (len + 1) / 2;
534 insw(fifoaddr, buf, len); 548 insw(fifoaddr, buf, len);
549#endif
535} 550}
536 551
537static inline void m66592_write(struct m66592 *m66592, u16 val, 552static inline void m66592_write(struct m66592 *m66592, u16 val,
@@ -545,6 +560,24 @@ static inline void m66592_write_fifo(struct m66592 *m66592,
545 void *buf, unsigned long len) 560 void *buf, unsigned long len)
546{ 561{
547 unsigned long fifoaddr = (unsigned long)m66592->reg + offset; 562 unsigned long fifoaddr = (unsigned long)m66592->reg + offset;
563#if defined(CONFIG_SUPERH_BUILT_IN_M66592)
564 unsigned long count;
565 unsigned char *pb;
566 int i;
567
568 count = len / 4;
569 outsl(fifoaddr, buf, count);
570
571 if (len & 0x00000003) {
572 pb = buf + count * 4;
573 for (i = 0; i < (len & 0x00000003); i++) {
574 if (m66592_read(m66592, M66592_CFBCFG)) /* little */
575 outb(pb[i], fifoaddr + (3 - i));
576 else
577 outb(pb[i], fifoaddr + i);
578 }
579 }
580#else
548 unsigned long odd = len & 0x0001; 581 unsigned long odd = len & 0x0001;
549 582
550 len = len / 2; 583 len = len / 2;
@@ -553,6 +586,7 @@ static inline void m66592_write_fifo(struct m66592 *m66592,
553 unsigned char *p = buf + len*2; 586 unsigned char *p = buf + len*2;
554 outb(*p, fifoaddr); 587 outb(*p, fifoaddr);
555 } 588 }
589#endif /* #if defined(CONFIG_SUPERH_BUILT_IN_M66592) */
556} 590}
557 591
558static inline void m66592_mdfy(struct m66592 *m66592, u16 val, u16 pat, 592static inline void m66592_mdfy(struct m66592 *m66592, u16 val, u16 pat,
@@ -570,6 +604,26 @@ static inline void m66592_mdfy(struct m66592 *m66592, u16 val, u16 pat,
570#define m66592_bset(m66592, val, offset) \ 604#define m66592_bset(m66592, val, offset) \
571 m66592_mdfy(m66592, val, 0, offset) 605 m66592_mdfy(m66592, val, 0, offset)
572 606
607#if defined(CONFIG_SUPERH_BUILT_IN_M66592)
608#include <asm/io.h>
609#define MSTPCR2 0xA4150038 /* for SH7722 */
610#define MSTPCR2_USB 0x00000800
611
612static inline void usbf_start_clock(void)
613{
614 ctrl_outl(ctrl_inl(MSTPCR2) & ~MSTPCR2_USB, MSTPCR2);
615}
616
617static inline void usbf_stop_clock(void)
618{
619 ctrl_outl(ctrl_inl(MSTPCR2) | MSTPCR2_USB, MSTPCR2);
620}
621
622#else
623#define usbf_start_clock(x)
624#define usbf_stop_clock(x)
625#endif /* if defined(CONFIG_SUPERH_BUILT_IN_M66592) */
626
573#endif /* ifndef __M66592_UDC_H__ */ 627#endif /* ifndef __M66592_UDC_H__ */
574 628
575 629