diff options
author | Gerard CAUVY <g-cauvy1@ti.com> | 2012-05-24 05:47:36 -0400 |
---|---|---|
committer | Felipe Balbi <balbi@ti.com> | 2012-06-03 16:08:26 -0400 |
commit | 5cbe8c220c1e126dd0855ad57fe4491b267132b9 (patch) | |
tree | f1d1a6993993f79b8561d8648ea3e9dae83c0972 /drivers/usb/dwc3 | |
parent | c4430a26948b84c0d820e83f8c640229f960d3b6 (diff) |
usb: dwc3: gadget: move AcceptU1Ena and AcceptU2Ena to Reset IRQ
According to the databook, the DWC3 Core will
reset those bits to 0 on USB Bus Reset. This
means we must re-enable those bits on every
reset interrupt.
Because we will always get a Reset interrupt
after loading a gadget driver, we can, instead
of re-enabling something that was just lost,
move the handling of those bits to the Reset
Interrupt.
This patch fixes USB30CV U1/U2 Test.
Signed-off-by: Gerard CAUVY <g-cauvy1@ti.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>
Diffstat (limited to 'drivers/usb/dwc3')
-rw-r--r-- | drivers/usb/dwc3/gadget.c | 5 |
1 files changed, 1 insertions, 4 deletions
diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c index 054ee5ec5c13..a9fc7c4a5a20 100644 --- a/drivers/usb/dwc3/gadget.c +++ b/drivers/usb/dwc3/gadget.c | |||
@@ -2006,6 +2006,7 @@ static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc) | |||
2006 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | 2006 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); |
2007 | reg &= ~DWC3_DCTL_TSTCTRL_MASK; | 2007 | reg &= ~DWC3_DCTL_TSTCTRL_MASK; |
2008 | reg &= ~(DWC3_DCTL_INITU1ENA | DWC3_DCTL_INITU2ENA); | 2008 | reg &= ~(DWC3_DCTL_INITU1ENA | DWC3_DCTL_INITU2ENA); |
2009 | reg |= (DWC3_DCTL_ACCEPTU1ENA | DWC3_DCTL_ACCEPTU2ENA); | ||
2009 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | 2010 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); |
2010 | dwc->test_mode = false; | 2011 | dwc->test_mode = false; |
2011 | 2012 | ||
@@ -2410,10 +2411,6 @@ int __devinit dwc3_gadget_init(struct dwc3 *dwc) | |||
2410 | reg |= DWC3_DCFG_LPM_CAP; | 2411 | reg |= DWC3_DCFG_LPM_CAP; |
2411 | dwc3_writel(dwc->regs, DWC3_DCFG, reg); | 2412 | dwc3_writel(dwc->regs, DWC3_DCFG, reg); |
2412 | 2413 | ||
2413 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | ||
2414 | reg |= DWC3_DCTL_ACCEPTU1ENA | DWC3_DCTL_ACCEPTU2ENA; | ||
2415 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | ||
2416 | |||
2417 | /* Enable all but Start and End of Frame IRQs */ | 2414 | /* Enable all but Start and End of Frame IRQs */ |
2418 | reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN | | 2415 | reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN | |
2419 | DWC3_DEVTEN_EVNTOVERFLOWEN | | 2416 | DWC3_DEVTEN_EVNTOVERFLOWEN | |