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authorDmitry Torokhov <dmitry.torokhov@gmail.com>2011-11-29 04:51:07 -0500
committerDmitry Torokhov <dmitry.torokhov@gmail.com>2011-11-29 04:51:07 -0500
commit0d2cd91bf7b1a7cc1d638296111fcc2bcf5c0bb4 (patch)
treed2ca69347816c27f9dc352581f5d0fe76811cd49 /drivers/usb/dwc3
parent3d95fd6ad8d3cf582a70ed65660017114b6e4065 (diff)
parentcaca6a03d365883564885f2c1da3e88dcf65d139 (diff)
Merge commit 'v3.2-rc3' into next
Diffstat (limited to 'drivers/usb/dwc3')
-rw-r--r--drivers/usb/dwc3/Kconfig25
-rw-r--r--drivers/usb/dwc3/Makefile36
-rw-r--r--drivers/usb/dwc3/core.c484
-rw-r--r--drivers/usb/dwc3/core.h768
-rw-r--r--drivers/usb/dwc3/debug.h50
-rw-r--r--drivers/usb/dwc3/debugfs.c441
-rw-r--r--drivers/usb/dwc3/dwc3-omap.c401
-rw-r--r--drivers/usb/dwc3/dwc3-pci.c219
-rw-r--r--drivers/usb/dwc3/ep0.c804
-rw-r--r--drivers/usb/dwc3/gadget.c2105
-rw-r--r--drivers/usb/dwc3/gadget.h211
-rw-r--r--drivers/usb/dwc3/io.h54
12 files changed, 5598 insertions, 0 deletions
diff --git a/drivers/usb/dwc3/Kconfig b/drivers/usb/dwc3/Kconfig
new file mode 100644
index 000000000000..3c1d67d324fd
--- /dev/null
+++ b/drivers/usb/dwc3/Kconfig
@@ -0,0 +1,25 @@
1config USB_DWC3
2 tristate "DesignWare USB3 DRD Core Support"
3 depends on (USB || USB_GADGET)
4 select USB_OTG_UTILS
5 help
6 Say Y or M here if your system has a Dual Role SuperSpeed
7 USB controller based on the DesignWare USB3 IP Core.
8
9 If you choose to build this driver is a dynamically linked
10 module, the module will be called dwc3.ko.
11
12if USB_DWC3
13
14config USB_DWC3_DEBUG
15 bool "Enable Debugging Messages"
16 help
17 Say Y here to enable debugging messages on DWC3 Driver.
18
19config USB_DWC3_VERBOSE
20 bool "Enable Verbose Debugging Messages"
21 depends on USB_DWC3_DEBUG
22 help
23 Say Y here to enable verbose debugging messages on DWC3 Driver.
24
25endif
diff --git a/drivers/usb/dwc3/Makefile b/drivers/usb/dwc3/Makefile
new file mode 100644
index 000000000000..593d1dbc465b
--- /dev/null
+++ b/drivers/usb/dwc3/Makefile
@@ -0,0 +1,36 @@
1ccflags-$(CONFIG_USB_DWC3_DEBUG) := -DDEBUG
2ccflags-$(CONFIG_USB_DWC3_VERBOSE) += -DVERBOSE_DEBUG
3
4obj-$(CONFIG_USB_DWC3) += dwc3.o
5
6dwc3-y := core.o
7
8ifneq ($(CONFIG_USB_GADGET_DWC3),)
9 dwc3-y += gadget.o ep0.o
10endif
11
12ifneq ($(CONFIG_DEBUG_FS),)
13 dwc3-y += debugfs.o
14endif
15
16##
17# Platform-specific glue layers go here
18#
19# NOTICE: Make sure your glue layer doesn't depend on anything
20# which is arch-specific and that it compiles on all situations.
21#
22# We want to keep this requirement in order to be able to compile
23# the entire driver (with all its glue layers) on several architectures
24# and make sure it compiles fine. This will also help with allmodconfig
25# and allyesconfig builds.
26#
27# The only exception is the PCI glue layer, but that's only because
28# PCI doesn't provide nops if CONFIG_PCI isn't enabled.
29##
30
31obj-$(CONFIG_USB_DWC3) += dwc3-omap.o
32
33ifneq ($(CONFIG_PCI),)
34 obj-$(CONFIG_USB_DWC3) += dwc3-pci.o
35endif
36
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
new file mode 100644
index 000000000000..717ebc9ff941
--- /dev/null
+++ b/drivers/usb/dwc3/core.c
@@ -0,0 +1,484 @@
1/**
2 * core.c - DesignWare USB3 DRD Controller Core file
3 *
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
5 *
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions, and the following disclaimer,
14 * without modification.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. The names of the above-listed copyright holders may not be used
19 * to endorse or promote products derived from this software without
20 * specific prior written permission.
21 *
22 * ALTERNATIVELY, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2, as published by the Free
24 * Software Foundation.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
27 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
28 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
30 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
31 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
32 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
33 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
34 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
35 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
36 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 */
38
39#include <linux/module.h>
40#include <linux/kernel.h>
41#include <linux/slab.h>
42#include <linux/spinlock.h>
43#include <linux/platform_device.h>
44#include <linux/pm_runtime.h>
45#include <linux/interrupt.h>
46#include <linux/ioport.h>
47#include <linux/io.h>
48#include <linux/list.h>
49#include <linux/delay.h>
50#include <linux/dma-mapping.h>
51
52#include <linux/usb/ch9.h>
53#include <linux/usb/gadget.h>
54#include <linux/module.h>
55
56#include "core.h"
57#include "gadget.h"
58#include "io.h"
59
60#include "debug.h"
61
62/**
63 * dwc3_core_soft_reset - Issues core soft reset and PHY reset
64 * @dwc: pointer to our context structure
65 */
66static void dwc3_core_soft_reset(struct dwc3 *dwc)
67{
68 u32 reg;
69
70 /* Before Resetting PHY, put Core in Reset */
71 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
72 reg |= DWC3_GCTL_CORESOFTRESET;
73 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
74
75 /* Assert USB3 PHY reset */
76 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
77 reg |= DWC3_GUSB3PIPECTL_PHYSOFTRST;
78 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
79
80 /* Assert USB2 PHY reset */
81 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
82 reg |= DWC3_GUSB2PHYCFG_PHYSOFTRST;
83 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
84
85 mdelay(100);
86
87 /* Clear USB3 PHY reset */
88 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
89 reg &= ~DWC3_GUSB3PIPECTL_PHYSOFTRST;
90 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
91
92 /* Clear USB2 PHY reset */
93 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
94 reg &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST;
95 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
96
97 /* After PHYs are stable we can take Core out of reset state */
98 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
99 reg &= ~DWC3_GCTL_CORESOFTRESET;
100 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
101}
102
103/**
104 * dwc3_free_one_event_buffer - Frees one event buffer
105 * @dwc: Pointer to our controller context structure
106 * @evt: Pointer to event buffer to be freed
107 */
108static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
109 struct dwc3_event_buffer *evt)
110{
111 dma_free_coherent(dwc->dev, evt->length, evt->buf, evt->dma);
112 kfree(evt);
113}
114
115/**
116 * dwc3_alloc_one_event_buffer - Allocated one event buffer structure
117 * @dwc: Pointer to our controller context structure
118 * @length: size of the event buffer
119 *
120 * Returns a pointer to the allocated event buffer structure on succes
121 * otherwise ERR_PTR(errno).
122 */
123static struct dwc3_event_buffer *__devinit
124dwc3_alloc_one_event_buffer(struct dwc3 *dwc, unsigned length)
125{
126 struct dwc3_event_buffer *evt;
127
128 evt = kzalloc(sizeof(*evt), GFP_KERNEL);
129 if (!evt)
130 return ERR_PTR(-ENOMEM);
131
132 evt->dwc = dwc;
133 evt->length = length;
134 evt->buf = dma_alloc_coherent(dwc->dev, length,
135 &evt->dma, GFP_KERNEL);
136 if (!evt->buf) {
137 kfree(evt);
138 return ERR_PTR(-ENOMEM);
139 }
140
141 return evt;
142}
143
144/**
145 * dwc3_free_event_buffers - frees all allocated event buffers
146 * @dwc: Pointer to our controller context structure
147 */
148static void dwc3_free_event_buffers(struct dwc3 *dwc)
149{
150 struct dwc3_event_buffer *evt;
151 int i;
152
153 for (i = 0; i < DWC3_EVENT_BUFFERS_NUM; i++) {
154 evt = dwc->ev_buffs[i];
155 if (evt) {
156 dwc3_free_one_event_buffer(dwc, evt);
157 dwc->ev_buffs[i] = NULL;
158 }
159 }
160}
161
162/**
163 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
164 * @dwc: Pointer to out controller context structure
165 * @num: number of event buffers to allocate
166 * @length: size of event buffer
167 *
168 * Returns 0 on success otherwise negative errno. In error the case, dwc
169 * may contain some buffers allocated but not all which were requested.
170 */
171static int __devinit dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned num,
172 unsigned length)
173{
174 int i;
175
176 for (i = 0; i < num; i++) {
177 struct dwc3_event_buffer *evt;
178
179 evt = dwc3_alloc_one_event_buffer(dwc, length);
180 if (IS_ERR(evt)) {
181 dev_err(dwc->dev, "can't allocate event buffer\n");
182 return PTR_ERR(evt);
183 }
184 dwc->ev_buffs[i] = evt;
185 }
186
187 return 0;
188}
189
190/**
191 * dwc3_event_buffers_setup - setup our allocated event buffers
192 * @dwc: Pointer to out controller context structure
193 *
194 * Returns 0 on success otherwise negative errno.
195 */
196static int __devinit dwc3_event_buffers_setup(struct dwc3 *dwc)
197{
198 struct dwc3_event_buffer *evt;
199 int n;
200
201 for (n = 0; n < DWC3_EVENT_BUFFERS_NUM; n++) {
202 evt = dwc->ev_buffs[n];
203 dev_dbg(dwc->dev, "Event buf %p dma %08llx length %d\n",
204 evt->buf, (unsigned long long) evt->dma,
205 evt->length);
206
207 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n),
208 lower_32_bits(evt->dma));
209 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n),
210 upper_32_bits(evt->dma));
211 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n),
212 evt->length & 0xffff);
213 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
214 }
215
216 return 0;
217}
218
219static void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
220{
221 struct dwc3_event_buffer *evt;
222 int n;
223
224 for (n = 0; n < DWC3_EVENT_BUFFERS_NUM; n++) {
225 evt = dwc->ev_buffs[n];
226 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), 0);
227 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), 0);
228 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), 0);
229 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
230 }
231}
232
233static void __devinit dwc3_cache_hwparams(struct dwc3 *dwc)
234{
235 struct dwc3_hwparams *parms = &dwc->hwparams;
236
237 parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
238 parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
239 parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
240 parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
241 parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
242 parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
243 parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
244 parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
245 parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
246}
247
248/**
249 * dwc3_core_init - Low-level initialization of DWC3 Core
250 * @dwc: Pointer to our controller context structure
251 *
252 * Returns 0 on success otherwise negative errno.
253 */
254static int __devinit dwc3_core_init(struct dwc3 *dwc)
255{
256 unsigned long timeout;
257 u32 reg;
258 int ret;
259
260 reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
261 /* This should read as U3 followed by revision number */
262 if ((reg & DWC3_GSNPSID_MASK) != 0x55330000) {
263 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
264 ret = -ENODEV;
265 goto err0;
266 }
267 dwc->revision = reg & DWC3_GSNPSREV_MASK;
268
269 dwc3_core_soft_reset(dwc);
270
271 /* issue device SoftReset too */
272 timeout = jiffies + msecs_to_jiffies(500);
273 dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST);
274 do {
275 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
276 if (!(reg & DWC3_DCTL_CSFTRST))
277 break;
278
279 if (time_after(jiffies, timeout)) {
280 dev_err(dwc->dev, "Reset Timed Out\n");
281 ret = -ETIMEDOUT;
282 goto err0;
283 }
284
285 cpu_relax();
286 } while (true);
287
288 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_NUM,
289 DWC3_EVENT_BUFFERS_SIZE);
290 if (ret) {
291 dev_err(dwc->dev, "failed to allocate event buffers\n");
292 ret = -ENOMEM;
293 goto err1;
294 }
295
296 ret = dwc3_event_buffers_setup(dwc);
297 if (ret) {
298 dev_err(dwc->dev, "failed to setup event buffers\n");
299 goto err1;
300 }
301
302 dwc3_cache_hwparams(dwc);
303
304 return 0;
305
306err1:
307 dwc3_free_event_buffers(dwc);
308
309err0:
310 return ret;
311}
312
313static void dwc3_core_exit(struct dwc3 *dwc)
314{
315 dwc3_event_buffers_cleanup(dwc);
316 dwc3_free_event_buffers(dwc);
317}
318
319#define DWC3_ALIGN_MASK (16 - 1)
320
321static int __devinit dwc3_probe(struct platform_device *pdev)
322{
323 const struct platform_device_id *id = platform_get_device_id(pdev);
324 struct resource *res;
325 struct dwc3 *dwc;
326 void __iomem *regs;
327 unsigned int features = id->driver_data;
328 int ret = -ENOMEM;
329 int irq;
330 void *mem;
331
332 mem = kzalloc(sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL);
333 if (!mem) {
334 dev_err(&pdev->dev, "not enough memory\n");
335 goto err0;
336 }
337 dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1);
338 dwc->mem = mem;
339
340 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
341 if (!res) {
342 dev_err(&pdev->dev, "missing resource\n");
343 goto err1;
344 }
345
346 res = request_mem_region(res->start, resource_size(res),
347 dev_name(&pdev->dev));
348 if (!res) {
349 dev_err(&pdev->dev, "can't request mem region\n");
350 goto err1;
351 }
352
353 regs = ioremap(res->start, resource_size(res));
354 if (!regs) {
355 dev_err(&pdev->dev, "ioremap failed\n");
356 goto err2;
357 }
358
359 irq = platform_get_irq(pdev, 0);
360 if (irq < 0) {
361 dev_err(&pdev->dev, "missing IRQ\n");
362 goto err3;
363 }
364
365 spin_lock_init(&dwc->lock);
366 platform_set_drvdata(pdev, dwc);
367
368 dwc->regs = regs;
369 dwc->regs_size = resource_size(res);
370 dwc->dev = &pdev->dev;
371 dwc->irq = irq;
372
373 pm_runtime_enable(&pdev->dev);
374 pm_runtime_get_sync(&pdev->dev);
375 pm_runtime_forbid(&pdev->dev);
376
377 ret = dwc3_core_init(dwc);
378 if (ret) {
379 dev_err(&pdev->dev, "failed to initialize core\n");
380 goto err3;
381 }
382
383 if (features & DWC3_HAS_PERIPHERAL) {
384 ret = dwc3_gadget_init(dwc);
385 if (ret) {
386 dev_err(&pdev->dev, "failed to initialized gadget\n");
387 goto err4;
388 }
389 }
390
391 ret = dwc3_debugfs_init(dwc);
392 if (ret) {
393 dev_err(&pdev->dev, "failed to initialize debugfs\n");
394 goto err5;
395 }
396
397 pm_runtime_allow(&pdev->dev);
398
399 return 0;
400
401err5:
402 if (features & DWC3_HAS_PERIPHERAL)
403 dwc3_gadget_exit(dwc);
404
405err4:
406 dwc3_core_exit(dwc);
407
408err3:
409 iounmap(regs);
410
411err2:
412 release_mem_region(res->start, resource_size(res));
413
414err1:
415 kfree(dwc->mem);
416
417err0:
418 return ret;
419}
420
421static int __devexit dwc3_remove(struct platform_device *pdev)
422{
423 const struct platform_device_id *id = platform_get_device_id(pdev);
424 struct dwc3 *dwc = platform_get_drvdata(pdev);
425 struct resource *res;
426 unsigned int features = id->driver_data;
427
428 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
429
430 pm_runtime_put(&pdev->dev);
431 pm_runtime_disable(&pdev->dev);
432
433 dwc3_debugfs_exit(dwc);
434
435 if (features & DWC3_HAS_PERIPHERAL)
436 dwc3_gadget_exit(dwc);
437
438 dwc3_core_exit(dwc);
439 release_mem_region(res->start, resource_size(res));
440 iounmap(dwc->regs);
441 kfree(dwc->mem);
442
443 return 0;
444}
445
446static const struct platform_device_id dwc3_id_table[] __devinitconst = {
447 {
448 .name = "dwc3-omap",
449 .driver_data = (DWC3_HAS_PERIPHERAL
450 | DWC3_HAS_XHCI
451 | DWC3_HAS_OTG),
452 },
453 {
454 .name = "dwc3-pci",
455 .driver_data = DWC3_HAS_PERIPHERAL,
456 },
457 { }, /* Terminating Entry */
458};
459MODULE_DEVICE_TABLE(platform, dwc3_id_table);
460
461static struct platform_driver dwc3_driver = {
462 .probe = dwc3_probe,
463 .remove = __devexit_p(dwc3_remove),
464 .driver = {
465 .name = "dwc3",
466 },
467 .id_table = dwc3_id_table,
468};
469
470MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
471MODULE_LICENSE("Dual BSD/GPL");
472MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");
473
474static int __devinit dwc3_init(void)
475{
476 return platform_driver_register(&dwc3_driver);
477}
478module_init(dwc3_init);
479
480static void __exit dwc3_exit(void)
481{
482 platform_driver_unregister(&dwc3_driver);
483}
484module_exit(dwc3_exit);
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
new file mode 100644
index 000000000000..29a8e1679e12
--- /dev/null
+++ b/drivers/usb/dwc3/core.h
@@ -0,0 +1,768 @@
1/**
2 * core.h - DesignWare USB3 DRD Core Header
3 *
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
5 *
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions, and the following disclaimer,
14 * without modification.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. The names of the above-listed copyright holders may not be used
19 * to endorse or promote products derived from this software without
20 * specific prior written permission.
21 *
22 * ALTERNATIVELY, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2, as published by the Free
24 * Software Foundation.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
27 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
28 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
30 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
31 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
32 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
33 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
34 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
35 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
36 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 */
38
39#ifndef __DRIVERS_USB_DWC3_CORE_H
40#define __DRIVERS_USB_DWC3_CORE_H
41
42#include <linux/device.h>
43#include <linux/spinlock.h>
44#include <linux/list.h>
45#include <linux/dma-mapping.h>
46#include <linux/mm.h>
47#include <linux/debugfs.h>
48
49#include <linux/usb/ch9.h>
50#include <linux/usb/gadget.h>
51
52/* Global constants */
53#define DWC3_ENDPOINTS_NUM 32
54
55#define DWC3_EVENT_BUFFERS_NUM 2
56#define DWC3_EVENT_BUFFERS_SIZE PAGE_SIZE
57#define DWC3_EVENT_TYPE_MASK 0xfe
58
59#define DWC3_EVENT_TYPE_DEV 0
60#define DWC3_EVENT_TYPE_CARKIT 3
61#define DWC3_EVENT_TYPE_I2C 4
62
63#define DWC3_DEVICE_EVENT_DISCONNECT 0
64#define DWC3_DEVICE_EVENT_RESET 1
65#define DWC3_DEVICE_EVENT_CONNECT_DONE 2
66#define DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE 3
67#define DWC3_DEVICE_EVENT_WAKEUP 4
68#define DWC3_DEVICE_EVENT_EOPF 6
69#define DWC3_DEVICE_EVENT_SOF 7
70#define DWC3_DEVICE_EVENT_ERRATIC_ERROR 9
71#define DWC3_DEVICE_EVENT_CMD_CMPL 10
72#define DWC3_DEVICE_EVENT_OVERFLOW 11
73
74#define DWC3_GEVNTCOUNT_MASK 0xfffc
75#define DWC3_GSNPSID_MASK 0xffff0000
76#define DWC3_GSNPSREV_MASK 0xffff
77
78/* Global Registers */
79#define DWC3_GSBUSCFG0 0xc100
80#define DWC3_GSBUSCFG1 0xc104
81#define DWC3_GTXTHRCFG 0xc108
82#define DWC3_GRXTHRCFG 0xc10c
83#define DWC3_GCTL 0xc110
84#define DWC3_GEVTEN 0xc114
85#define DWC3_GSTS 0xc118
86#define DWC3_GSNPSID 0xc120
87#define DWC3_GGPIO 0xc124
88#define DWC3_GUID 0xc128
89#define DWC3_GUCTL 0xc12c
90#define DWC3_GBUSERRADDR0 0xc130
91#define DWC3_GBUSERRADDR1 0xc134
92#define DWC3_GPRTBIMAP0 0xc138
93#define DWC3_GPRTBIMAP1 0xc13c
94#define DWC3_GHWPARAMS0 0xc140
95#define DWC3_GHWPARAMS1 0xc144
96#define DWC3_GHWPARAMS2 0xc148
97#define DWC3_GHWPARAMS3 0xc14c
98#define DWC3_GHWPARAMS4 0xc150
99#define DWC3_GHWPARAMS5 0xc154
100#define DWC3_GHWPARAMS6 0xc158
101#define DWC3_GHWPARAMS7 0xc15c
102#define DWC3_GDBGFIFOSPACE 0xc160
103#define DWC3_GDBGLTSSM 0xc164
104#define DWC3_GPRTBIMAP_HS0 0xc180
105#define DWC3_GPRTBIMAP_HS1 0xc184
106#define DWC3_GPRTBIMAP_FS0 0xc188
107#define DWC3_GPRTBIMAP_FS1 0xc18c
108
109#define DWC3_GUSB2PHYCFG(n) (0xc200 + (n * 0x04))
110#define DWC3_GUSB2I2CCTL(n) (0xc240 + (n * 0x04))
111
112#define DWC3_GUSB2PHYACC(n) (0xc280 + (n * 0x04))
113
114#define DWC3_GUSB3PIPECTL(n) (0xc2c0 + (n * 0x04))
115
116#define DWC3_GTXFIFOSIZ(n) (0xc300 + (n * 0x04))
117#define DWC3_GRXFIFOSIZ(n) (0xc380 + (n * 0x04))
118
119#define DWC3_GEVNTADRLO(n) (0xc400 + (n * 0x10))
120#define DWC3_GEVNTADRHI(n) (0xc404 + (n * 0x10))
121#define DWC3_GEVNTSIZ(n) (0xc408 + (n * 0x10))
122#define DWC3_GEVNTCOUNT(n) (0xc40c + (n * 0x10))
123
124#define DWC3_GHWPARAMS8 0xc600
125
126/* Device Registers */
127#define DWC3_DCFG 0xc700
128#define DWC3_DCTL 0xc704
129#define DWC3_DEVTEN 0xc708
130#define DWC3_DSTS 0xc70c
131#define DWC3_DGCMDPAR 0xc710
132#define DWC3_DGCMD 0xc714
133#define DWC3_DALEPENA 0xc720
134#define DWC3_DEPCMDPAR2(n) (0xc800 + (n * 0x10))
135#define DWC3_DEPCMDPAR1(n) (0xc804 + (n * 0x10))
136#define DWC3_DEPCMDPAR0(n) (0xc808 + (n * 0x10))
137#define DWC3_DEPCMD(n) (0xc80c + (n * 0x10))
138
139/* OTG Registers */
140#define DWC3_OCFG 0xcc00
141#define DWC3_OCTL 0xcc04
142#define DWC3_OEVTEN 0xcc08
143#define DWC3_OSTS 0xcc0C
144
145/* Bit fields */
146
147/* Global Configuration Register */
148#define DWC3_GCTL_PWRDNSCALE(n) (n << 19)
149#define DWC3_GCTL_U2RSTECN (1 << 16)
150#define DWC3_GCTL_RAMCLKSEL(x) ((x & DWC3_GCTL_CLK_MASK) << 6)
151#define DWC3_GCTL_CLK_BUS (0)
152#define DWC3_GCTL_CLK_PIPE (1)
153#define DWC3_GCTL_CLK_PIPEHALF (2)
154#define DWC3_GCTL_CLK_MASK (3)
155
156#define DWC3_GCTL_PRTCAPDIR(n) (n << 12)
157#define DWC3_GCTL_PRTCAP_HOST 1
158#define DWC3_GCTL_PRTCAP_DEVICE 2
159#define DWC3_GCTL_PRTCAP_OTG 3
160
161#define DWC3_GCTL_CORESOFTRESET (1 << 11)
162#define DWC3_GCTL_SCALEDOWN(n) (n << 4)
163#define DWC3_GCTL_DISSCRAMBLE (1 << 3)
164#define DWC3_GCTL_DSBLCLKGTNG (1 << 0)
165
166/* Global USB2 PHY Configuration Register */
167#define DWC3_GUSB2PHYCFG_PHYSOFTRST (1 << 31)
168#define DWC3_GUSB2PHYCFG_SUSPHY (1 << 6)
169
170/* Global USB3 PIPE Control Register */
171#define DWC3_GUSB3PIPECTL_PHYSOFTRST (1 << 31)
172#define DWC3_GUSB3PIPECTL_SUSPHY (1 << 17)
173
174/* Global HWPARAMS1 Register */
175#define DWC3_GHWPARAMS1_EN_PWROPT(n) ((n & (3 << 24)) >> 24)
176#define DWC3_GHWPARAMS1_EN_PWROPT_NO 0
177#define DWC3_GHWPARAMS1_EN_PWROPT_CLK 1
178
179/* Device Configuration Register */
180#define DWC3_DCFG_DEVADDR(addr) ((addr) << 3)
181#define DWC3_DCFG_DEVADDR_MASK DWC3_DCFG_DEVADDR(0x7f)
182
183#define DWC3_DCFG_SPEED_MASK (7 << 0)
184#define DWC3_DCFG_SUPERSPEED (4 << 0)
185#define DWC3_DCFG_HIGHSPEED (0 << 0)
186#define DWC3_DCFG_FULLSPEED2 (1 << 0)
187#define DWC3_DCFG_LOWSPEED (2 << 0)
188#define DWC3_DCFG_FULLSPEED1 (3 << 0)
189
190/* Device Control Register */
191#define DWC3_DCTL_RUN_STOP (1 << 31)
192#define DWC3_DCTL_CSFTRST (1 << 30)
193#define DWC3_DCTL_LSFTRST (1 << 29)
194
195#define DWC3_DCTL_HIRD_THRES_MASK (0x1f << 24)
196#define DWC3_DCTL_HIRD_THRES(n) (((n) & DWC3_DCTL_HIRD_THRES_MASK) >> 24)
197
198#define DWC3_DCTL_APPL1RES (1 << 23)
199
200#define DWC3_DCTL_INITU2ENA (1 << 12)
201#define DWC3_DCTL_ACCEPTU2ENA (1 << 11)
202#define DWC3_DCTL_INITU1ENA (1 << 10)
203#define DWC3_DCTL_ACCEPTU1ENA (1 << 9)
204#define DWC3_DCTL_TSTCTRL_MASK (0xf << 1)
205
206#define DWC3_DCTL_ULSTCHNGREQ_MASK (0x0f << 5)
207#define DWC3_DCTL_ULSTCHNGREQ(n) (((n) << 5) & DWC3_DCTL_ULSTCHNGREQ_MASK)
208
209#define DWC3_DCTL_ULSTCHNG_NO_ACTION (DWC3_DCTL_ULSTCHNGREQ(0))
210#define DWC3_DCTL_ULSTCHNG_SS_DISABLED (DWC3_DCTL_ULSTCHNGREQ(4))
211#define DWC3_DCTL_ULSTCHNG_RX_DETECT (DWC3_DCTL_ULSTCHNGREQ(5))
212#define DWC3_DCTL_ULSTCHNG_SS_INACTIVE (DWC3_DCTL_ULSTCHNGREQ(6))
213#define DWC3_DCTL_ULSTCHNG_RECOVERY (DWC3_DCTL_ULSTCHNGREQ(8))
214#define DWC3_DCTL_ULSTCHNG_COMPLIANCE (DWC3_DCTL_ULSTCHNGREQ(10))
215#define DWC3_DCTL_ULSTCHNG_LOOPBACK (DWC3_DCTL_ULSTCHNGREQ(11))
216
217/* Device Event Enable Register */
218#define DWC3_DEVTEN_VNDRDEVTSTRCVEDEN (1 << 12)
219#define DWC3_DEVTEN_EVNTOVERFLOWEN (1 << 11)
220#define DWC3_DEVTEN_CMDCMPLTEN (1 << 10)
221#define DWC3_DEVTEN_ERRTICERREN (1 << 9)
222#define DWC3_DEVTEN_SOFEN (1 << 7)
223#define DWC3_DEVTEN_EOPFEN (1 << 6)
224#define DWC3_DEVTEN_WKUPEVTEN (1 << 4)
225#define DWC3_DEVTEN_ULSTCNGEN (1 << 3)
226#define DWC3_DEVTEN_CONNECTDONEEN (1 << 2)
227#define DWC3_DEVTEN_USBRSTEN (1 << 1)
228#define DWC3_DEVTEN_DISCONNEVTEN (1 << 0)
229
230/* Device Status Register */
231#define DWC3_DSTS_PWRUPREQ (1 << 24)
232#define DWC3_DSTS_COREIDLE (1 << 23)
233#define DWC3_DSTS_DEVCTRLHLT (1 << 22)
234
235#define DWC3_DSTS_USBLNKST_MASK (0x0f << 18)
236#define DWC3_DSTS_USBLNKST(n) (((n) & DWC3_DSTS_USBLNKST_MASK) >> 18)
237
238#define DWC3_DSTS_RXFIFOEMPTY (1 << 17)
239
240#define DWC3_DSTS_SOFFN_MASK (0x3ff << 3)
241#define DWC3_DSTS_SOFFN(n) (((n) & DWC3_DSTS_SOFFN_MASK) >> 3)
242
243#define DWC3_DSTS_CONNECTSPD (7 << 0)
244
245#define DWC3_DSTS_SUPERSPEED (4 << 0)
246#define DWC3_DSTS_HIGHSPEED (0 << 0)
247#define DWC3_DSTS_FULLSPEED2 (1 << 0)
248#define DWC3_DSTS_LOWSPEED (2 << 0)
249#define DWC3_DSTS_FULLSPEED1 (3 << 0)
250
251/* Device Generic Command Register */
252#define DWC3_DGCMD_SET_LMP 0x01
253#define DWC3_DGCMD_SET_PERIODIC_PAR 0x02
254#define DWC3_DGCMD_XMIT_FUNCTION 0x03
255#define DWC3_DGCMD_SELECTED_FIFO_FLUSH 0x09
256#define DWC3_DGCMD_ALL_FIFO_FLUSH 0x0a
257#define DWC3_DGCMD_SET_ENDPOINT_NRDY 0x0c
258#define DWC3_DGCMD_RUN_SOC_BUS_LOOPBACK 0x10
259
260/* Device Endpoint Command Register */
261#define DWC3_DEPCMD_PARAM_SHIFT 16
262#define DWC3_DEPCMD_PARAM(x) (x << DWC3_DEPCMD_PARAM_SHIFT)
263#define DWC3_DEPCMD_GET_RSC_IDX(x) ((x >> DWC3_DEPCMD_PARAM_SHIFT) & 0x7f)
264#define DWC3_DEPCMD_STATUS_MASK (0x0f << 12)
265#define DWC3_DEPCMD_STATUS(x) ((x & DWC3_DEPCMD_STATUS_MASK) >> 12)
266#define DWC3_DEPCMD_HIPRI_FORCERM (1 << 11)
267#define DWC3_DEPCMD_CMDACT (1 << 10)
268#define DWC3_DEPCMD_CMDIOC (1 << 8)
269
270#define DWC3_DEPCMD_DEPSTARTCFG (0x09 << 0)
271#define DWC3_DEPCMD_ENDTRANSFER (0x08 << 0)
272#define DWC3_DEPCMD_UPDATETRANSFER (0x07 << 0)
273#define DWC3_DEPCMD_STARTTRANSFER (0x06 << 0)
274#define DWC3_DEPCMD_CLEARSTALL (0x05 << 0)
275#define DWC3_DEPCMD_SETSTALL (0x04 << 0)
276#define DWC3_DEPCMD_GETSEQNUMBER (0x03 << 0)
277#define DWC3_DEPCMD_SETTRANSFRESOURCE (0x02 << 0)
278#define DWC3_DEPCMD_SETEPCONFIG (0x01 << 0)
279
280/* The EP number goes 0..31 so ep0 is always out and ep1 is always in */
281#define DWC3_DALEPENA_EP(n) (1 << n)
282
283#define DWC3_DEPCMD_TYPE_CONTROL 0
284#define DWC3_DEPCMD_TYPE_ISOC 1
285#define DWC3_DEPCMD_TYPE_BULK 2
286#define DWC3_DEPCMD_TYPE_INTR 3
287
288/* Structures */
289
290struct dwc3_trb_hw;
291
292/**
293 * struct dwc3_event_buffer - Software event buffer representation
294 * @list: a list of event buffers
295 * @buf: _THE_ buffer
296 * @length: size of this buffer
297 * @dma: dma_addr_t
298 * @dwc: pointer to DWC controller
299 */
300struct dwc3_event_buffer {
301 void *buf;
302 unsigned length;
303 unsigned int lpos;
304
305 dma_addr_t dma;
306
307 struct dwc3 *dwc;
308};
309
310#define DWC3_EP_FLAG_STALLED (1 << 0)
311#define DWC3_EP_FLAG_WEDGED (1 << 1)
312
313#define DWC3_EP_DIRECTION_TX true
314#define DWC3_EP_DIRECTION_RX false
315
316#define DWC3_TRB_NUM 32
317#define DWC3_TRB_MASK (DWC3_TRB_NUM - 1)
318
319/**
320 * struct dwc3_ep - device side endpoint representation
321 * @endpoint: usb endpoint
322 * @request_list: list of requests for this endpoint
323 * @req_queued: list of requests on this ep which have TRBs setup
324 * @trb_pool: array of transaction buffers
325 * @trb_pool_dma: dma address of @trb_pool
326 * @free_slot: next slot which is going to be used
327 * @busy_slot: first slot which is owned by HW
328 * @desc: usb_endpoint_descriptor pointer
329 * @dwc: pointer to DWC controller
330 * @flags: endpoint flags (wedged, stalled, ...)
331 * @current_trb: index of current used trb
332 * @number: endpoint number (1 - 15)
333 * @type: set to bmAttributes & USB_ENDPOINT_XFERTYPE_MASK
334 * @res_trans_idx: Resource transfer index
335 * @interval: the intervall on which the ISOC transfer is started
336 * @name: a human readable name e.g. ep1out-bulk
337 * @direction: true for TX, false for RX
338 * @stream_capable: true when streams are enabled
339 */
340struct dwc3_ep {
341 struct usb_ep endpoint;
342 struct list_head request_list;
343 struct list_head req_queued;
344
345 struct dwc3_trb_hw *trb_pool;
346 dma_addr_t trb_pool_dma;
347 u32 free_slot;
348 u32 busy_slot;
349 const struct usb_endpoint_descriptor *desc;
350 struct dwc3 *dwc;
351
352 unsigned flags;
353#define DWC3_EP_ENABLED (1 << 0)
354#define DWC3_EP_STALL (1 << 1)
355#define DWC3_EP_WEDGE (1 << 2)
356#define DWC3_EP_BUSY (1 << 4)
357#define DWC3_EP_PENDING_REQUEST (1 << 5)
358
359 /* This last one is specific to EP0 */
360#define DWC3_EP0_DIR_IN (1 << 31)
361
362 unsigned current_trb;
363
364 u8 number;
365 u8 type;
366 u8 res_trans_idx;
367 u32 interval;
368
369 char name[20];
370
371 unsigned direction:1;
372 unsigned stream_capable:1;
373};
374
375enum dwc3_phy {
376 DWC3_PHY_UNKNOWN = 0,
377 DWC3_PHY_USB3,
378 DWC3_PHY_USB2,
379};
380
381enum dwc3_ep0_next {
382 DWC3_EP0_UNKNOWN = 0,
383 DWC3_EP0_COMPLETE,
384 DWC3_EP0_NRDY_SETUP,
385 DWC3_EP0_NRDY_DATA,
386 DWC3_EP0_NRDY_STATUS,
387};
388
389enum dwc3_ep0_state {
390 EP0_UNCONNECTED = 0,
391 EP0_SETUP_PHASE,
392 EP0_DATA_PHASE,
393 EP0_STATUS_PHASE,
394};
395
396enum dwc3_link_state {
397 /* In SuperSpeed */
398 DWC3_LINK_STATE_U0 = 0x00, /* in HS, means ON */
399 DWC3_LINK_STATE_U1 = 0x01,
400 DWC3_LINK_STATE_U2 = 0x02, /* in HS, means SLEEP */
401 DWC3_LINK_STATE_U3 = 0x03, /* in HS, means SUSPEND */
402 DWC3_LINK_STATE_SS_DIS = 0x04,
403 DWC3_LINK_STATE_RX_DET = 0x05, /* in HS, means Early Suspend */
404 DWC3_LINK_STATE_SS_INACT = 0x06,
405 DWC3_LINK_STATE_POLL = 0x07,
406 DWC3_LINK_STATE_RECOV = 0x08,
407 DWC3_LINK_STATE_HRESET = 0x09,
408 DWC3_LINK_STATE_CMPLY = 0x0a,
409 DWC3_LINK_STATE_LPBK = 0x0b,
410 DWC3_LINK_STATE_MASK = 0x0f,
411};
412
413enum dwc3_device_state {
414 DWC3_DEFAULT_STATE,
415 DWC3_ADDRESS_STATE,
416 DWC3_CONFIGURED_STATE,
417};
418
419/**
420 * struct dwc3_trb - transfer request block
421 * @bpl: lower 32bit of the buffer
422 * @bph: higher 32bit of the buffer
423 * @length: buffer size (up to 16mb - 1)
424 * @pcm1: packet count m1
425 * @trbsts: trb status
426 * 0 = ok
427 * 1 = missed isoc
428 * 2 = setup pending
429 * @hwo: hardware owner of descriptor
430 * @lst: last trb
431 * @chn: chain buffers
432 * @csp: continue on short packets (only supported on isoc eps)
433 * @trbctl: trb control
434 * 1 = normal
435 * 2 = control-setup
436 * 3 = control-status-2
437 * 4 = control-status-3
438 * 5 = control-data (first trb of data stage)
439 * 6 = isochronous-first (first trb of service interval)
440 * 7 = isochronous
441 * 8 = link trb
442 * others = reserved
443 * @isp_imi: interrupt on short packet / interrupt on missed isoc
444 * @ioc: interrupt on complete
445 * @sid_sofn: Stream ID / SOF Number
446 */
447struct dwc3_trb {
448 u64 bplh;
449
450 union {
451 struct {
452 u32 length:24;
453 u32 pcm1:2;
454 u32 reserved27_26:2;
455 u32 trbsts:4;
456#define DWC3_TRB_STS_OKAY 0
457#define DWC3_TRB_STS_MISSED_ISOC 1
458#define DWC3_TRB_STS_SETUP_PENDING 2
459 };
460 u32 len_pcm;
461 };
462
463 union {
464 struct {
465 u32 hwo:1;
466 u32 lst:1;
467 u32 chn:1;
468 u32 csp:1;
469 u32 trbctl:6;
470 u32 isp_imi:1;
471 u32 ioc:1;
472 u32 reserved13_12:2;
473 u32 sid_sofn:16;
474 u32 reserved31_30:2;
475 };
476 u32 control;
477 };
478} __packed;
479
480/**
481 * struct dwc3_trb_hw - transfer request block (hw format)
482 * @bpl: DW0-3
483 * @bph: DW4-7
484 * @size: DW8-B
485 * @trl: DWC-F
486 */
487struct dwc3_trb_hw {
488 __le32 bpl;
489 __le32 bph;
490 __le32 size;
491 __le32 ctrl;
492} __packed;
493
494static inline void dwc3_trb_to_hw(struct dwc3_trb *nat, struct dwc3_trb_hw *hw)
495{
496 hw->bpl = cpu_to_le32(lower_32_bits(nat->bplh));
497 hw->bph = cpu_to_le32(upper_32_bits(nat->bplh));
498 hw->size = cpu_to_le32p(&nat->len_pcm);
499 /* HWO is written last */
500 hw->ctrl = cpu_to_le32p(&nat->control);
501}
502
503static inline void dwc3_trb_to_nat(struct dwc3_trb_hw *hw, struct dwc3_trb *nat)
504{
505 u64 bplh;
506
507 bplh = le32_to_cpup(&hw->bpl);
508 bplh |= (u64) le32_to_cpup(&hw->bph) << 32;
509 nat->bplh = bplh;
510
511 nat->len_pcm = le32_to_cpup(&hw->size);
512 nat->control = le32_to_cpup(&hw->ctrl);
513}
514
515/**
516 * dwc3_hwparams - copy of HWPARAMS registers
517 * @hwparams0 - GHWPARAMS0
518 * @hwparams1 - GHWPARAMS1
519 * @hwparams2 - GHWPARAMS2
520 * @hwparams3 - GHWPARAMS3
521 * @hwparams4 - GHWPARAMS4
522 * @hwparams5 - GHWPARAMS5
523 * @hwparams6 - GHWPARAMS6
524 * @hwparams7 - GHWPARAMS7
525 * @hwparams8 - GHWPARAMS8
526 */
527struct dwc3_hwparams {
528 u32 hwparams0;
529 u32 hwparams1;
530 u32 hwparams2;
531 u32 hwparams3;
532 u32 hwparams4;
533 u32 hwparams5;
534 u32 hwparams6;
535 u32 hwparams7;
536 u32 hwparams8;
537};
538
539/**
540 * struct dwc3 - representation of our controller
541 * @ctrl_req: usb control request which is used for ep0
542 * @ep0_trb: trb which is used for the ctrl_req
543 * @ep0_bounce: bounce buffer for ep0
544 * @setup_buf: used while precessing STD USB requests
545 * @ctrl_req_addr: dma address of ctrl_req
546 * @ep0_trb: dma address of ep0_trb
547 * @ep0_usb_req: dummy req used while handling STD USB requests
548 * @setup_buf_addr: dma address of setup_buf
549 * @ep0_bounce_addr: dma address of ep0_bounce
550 * @lock: for synchronizing
551 * @dev: pointer to our struct device
552 * @event_buffer_list: a list of event buffers
553 * @gadget: device side representation of the peripheral controller
554 * @gadget_driver: pointer to the gadget driver
555 * @regs: base address for our registers
556 * @regs_size: address space size
557 * @irq: IRQ number
558 * @revision: revision register contents
559 * @is_selfpowered: true when we are selfpowered
560 * @three_stage_setup: set if we perform a three phase setup
561 * @ep0_status_pending: ep0 status response without a req is pending
562 * @ep0_bounced: true when we used bounce buffer
563 * @ep0_expect_in: true when we expect a DATA IN transfer
564 * @start_config_issued: true when StartConfig command has been issued
565 * @ep0_next_event: hold the next expected event
566 * @ep0state: state of endpoint zero
567 * @link_state: link state
568 * @speed: device speed (super, high, full, low)
569 * @mem: points to start of memory which is used for this struct.
570 * @hwparams: copy of hwparams registers
571 * @root: debugfs root folder pointer
572 */
573struct dwc3 {
574 struct usb_ctrlrequest *ctrl_req;
575 struct dwc3_trb_hw *ep0_trb;
576 void *ep0_bounce;
577 u8 *setup_buf;
578 dma_addr_t ctrl_req_addr;
579 dma_addr_t ep0_trb_addr;
580 dma_addr_t setup_buf_addr;
581 dma_addr_t ep0_bounce_addr;
582 struct usb_request ep0_usb_req;
583 /* device lock */
584 spinlock_t lock;
585 struct device *dev;
586
587 struct dwc3_event_buffer *ev_buffs[DWC3_EVENT_BUFFERS_NUM];
588 struct dwc3_ep *eps[DWC3_ENDPOINTS_NUM];
589
590 struct usb_gadget gadget;
591 struct usb_gadget_driver *gadget_driver;
592
593 void __iomem *regs;
594 size_t regs_size;
595
596 int irq;
597
598 u32 revision;
599
600#define DWC3_REVISION_173A 0x5533173a
601#define DWC3_REVISION_175A 0x5533175a
602#define DWC3_REVISION_180A 0x5533180a
603#define DWC3_REVISION_183A 0x5533183a
604#define DWC3_REVISION_185A 0x5533185a
605#define DWC3_REVISION_188A 0x5533188a
606#define DWC3_REVISION_190A 0x5533190a
607
608 unsigned is_selfpowered:1;
609 unsigned three_stage_setup:1;
610 unsigned ep0_status_pending:1;
611 unsigned ep0_bounced:1;
612 unsigned ep0_expect_in:1;
613 unsigned start_config_issued:1;
614
615 enum dwc3_ep0_next ep0_next_event;
616 enum dwc3_ep0_state ep0state;
617 enum dwc3_link_state link_state;
618 enum dwc3_device_state dev_state;
619
620 u8 speed;
621 void *mem;
622
623 struct dwc3_hwparams hwparams;
624 struct dentry *root;
625};
626
627/* -------------------------------------------------------------------------- */
628
629#define DWC3_TRBSTS_OK 0
630#define DWC3_TRBSTS_MISSED_ISOC 1
631#define DWC3_TRBSTS_SETUP_PENDING 2
632
633#define DWC3_TRBCTL_NORMAL 1
634#define DWC3_TRBCTL_CONTROL_SETUP 2
635#define DWC3_TRBCTL_CONTROL_STATUS2 3
636#define DWC3_TRBCTL_CONTROL_STATUS3 4
637#define DWC3_TRBCTL_CONTROL_DATA 5
638#define DWC3_TRBCTL_ISOCHRONOUS_FIRST 6
639#define DWC3_TRBCTL_ISOCHRONOUS 7
640#define DWC3_TRBCTL_LINK_TRB 8
641
642/* -------------------------------------------------------------------------- */
643
644struct dwc3_event_type {
645 u32 is_devspec:1;
646 u32 type:6;
647 u32 reserved8_31:25;
648} __packed;
649
650#define DWC3_DEPEVT_XFERCOMPLETE 0x01
651#define DWC3_DEPEVT_XFERINPROGRESS 0x02
652#define DWC3_DEPEVT_XFERNOTREADY 0x03
653#define DWC3_DEPEVT_RXTXFIFOEVT 0x04
654#define DWC3_DEPEVT_STREAMEVT 0x06
655#define DWC3_DEPEVT_EPCMDCMPLT 0x07
656
657/**
658 * struct dwc3_event_depvt - Device Endpoint Events
659 * @one_bit: indicates this is an endpoint event (not used)
660 * @endpoint_number: number of the endpoint
661 * @endpoint_event: The event we have:
662 * 0x00 - Reserved
663 * 0x01 - XferComplete
664 * 0x02 - XferInProgress
665 * 0x03 - XferNotReady
666 * 0x04 - RxTxFifoEvt (IN->Underrun, OUT->Overrun)
667 * 0x05 - Reserved
668 * 0x06 - StreamEvt
669 * 0x07 - EPCmdCmplt
670 * @reserved11_10: Reserved, don't use.
671 * @status: Indicates the status of the event. Refer to databook for
672 * more information.
673 * @parameters: Parameters of the current event. Refer to databook for
674 * more information.
675 */
676struct dwc3_event_depevt {
677 u32 one_bit:1;
678 u32 endpoint_number:5;
679 u32 endpoint_event:4;
680 u32 reserved11_10:2;
681 u32 status:4;
682#define DEPEVT_STATUS_BUSERR (1 << 0)
683#define DEPEVT_STATUS_SHORT (1 << 1)
684#define DEPEVT_STATUS_IOC (1 << 2)
685#define DEPEVT_STATUS_LST (1 << 3)
686
687/* Stream event only */
688#define DEPEVT_STREAMEVT_FOUND 1
689#define DEPEVT_STREAMEVT_NOTFOUND 2
690
691/* Control-only Status */
692#define DEPEVT_STATUS_CONTROL_SETUP 0
693#define DEPEVT_STATUS_CONTROL_DATA 1
694#define DEPEVT_STATUS_CONTROL_STATUS 2
695
696 u32 parameters:16;
697} __packed;
698
699/**
700 * struct dwc3_event_devt - Device Events
701 * @one_bit: indicates this is a non-endpoint event (not used)
702 * @device_event: indicates it's a device event. Should read as 0x00
703 * @type: indicates the type of device event.
704 * 0 - DisconnEvt
705 * 1 - USBRst
706 * 2 - ConnectDone
707 * 3 - ULStChng
708 * 4 - WkUpEvt
709 * 5 - Reserved
710 * 6 - EOPF
711 * 7 - SOF
712 * 8 - Reserved
713 * 9 - ErrticErr
714 * 10 - CmdCmplt
715 * 11 - EvntOverflow
716 * 12 - VndrDevTstRcved
717 * @reserved15_12: Reserved, not used
718 * @event_info: Information about this event
719 * @reserved31_24: Reserved, not used
720 */
721struct dwc3_event_devt {
722 u32 one_bit:1;
723 u32 device_event:7;
724 u32 type:4;
725 u32 reserved15_12:4;
726 u32 event_info:8;
727 u32 reserved31_24:8;
728} __packed;
729
730/**
731 * struct dwc3_event_gevt - Other Core Events
732 * @one_bit: indicates this is a non-endpoint event (not used)
733 * @device_event: indicates it's (0x03) Carkit or (0x04) I2C event.
734 * @phy_port_number: self-explanatory
735 * @reserved31_12: Reserved, not used.
736 */
737struct dwc3_event_gevt {
738 u32 one_bit:1;
739 u32 device_event:7;
740 u32 phy_port_number:4;
741 u32 reserved31_12:20;
742} __packed;
743
744/**
745 * union dwc3_event - representation of Event Buffer contents
746 * @raw: raw 32-bit event
747 * @type: the type of the event
748 * @depevt: Device Endpoint Event
749 * @devt: Device Event
750 * @gevt: Global Event
751 */
752union dwc3_event {
753 u32 raw;
754 struct dwc3_event_type type;
755 struct dwc3_event_depevt depevt;
756 struct dwc3_event_devt devt;
757 struct dwc3_event_gevt gevt;
758};
759
760/*
761 * DWC3 Features to be used as Driver Data
762 */
763
764#define DWC3_HAS_PERIPHERAL BIT(0)
765#define DWC3_HAS_XHCI BIT(1)
766#define DWC3_HAS_OTG BIT(3)
767
768#endif /* __DRIVERS_USB_DWC3_CORE_H */
diff --git a/drivers/usb/dwc3/debug.h b/drivers/usb/dwc3/debug.h
new file mode 100644
index 000000000000..5894ee8222af
--- /dev/null
+++ b/drivers/usb/dwc3/debug.h
@@ -0,0 +1,50 @@
1/**
2 * debug.h - DesignWare USB3 DRD Controller Debug Header
3 *
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
5 *
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions, and the following disclaimer,
14 * without modification.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. The names of the above-listed copyright holders may not be used
19 * to endorse or promote products derived from this software without
20 * specific prior written permission.
21 *
22 * ALTERNATIVELY, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2, as published by the Free
24 * Software Foundation.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
27 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
28 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
30 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
31 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
32 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
33 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
34 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
35 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
36 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 */
38
39#include "core.h"
40
41#ifdef CONFIG_DEBUG_FS
42extern int dwc3_debugfs_init(struct dwc3 *);
43extern void dwc3_debugfs_exit(struct dwc3 *);
44#else
45static inline int dwc3_debugfs_init(struct dwc3 *d)
46{ return 0; }
47static inline void dwc3_debugfs_exit(struct dwc3 *d)
48{ }
49#endif
50
diff --git a/drivers/usb/dwc3/debugfs.c b/drivers/usb/dwc3/debugfs.c
new file mode 100644
index 000000000000..da1ad77d8d51
--- /dev/null
+++ b/drivers/usb/dwc3/debugfs.c
@@ -0,0 +1,441 @@
1/**
2 * debugfs.c - DesignWare USB3 DRD Controller DebugFS file
3 *
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
5 *
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions, and the following disclaimer,
14 * without modification.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. The names of the above-listed copyright holders may not be used
19 * to endorse or promote products derived from this software without
20 * specific prior written permission.
21 *
22 * ALTERNATIVELY, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2, as published by the Free
24 * Software Foundation.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
27 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
28 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
30 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
31 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
32 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
33 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
34 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
35 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
36 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 */
38
39#include <linux/kernel.h>
40#include <linux/slab.h>
41#include <linux/ptrace.h>
42#include <linux/types.h>
43#include <linux/spinlock.h>
44#include <linux/debugfs.h>
45#include <linux/seq_file.h>
46#include <linux/delay.h>
47
48#include <asm/uaccess.h>
49
50#include "core.h"
51#include "gadget.h"
52#include "io.h"
53
54struct dwc3_register {
55 const char *name;
56 u32 offset;
57};
58
59#define dump_register(nm) \
60{ \
61 .name = __stringify(nm), \
62 .offset = DWC3_ ##nm, \
63}
64
65static const struct dwc3_register dwc3_regs[] = {
66 dump_register(GSBUSCFG0),
67 dump_register(GSBUSCFG1),
68 dump_register(GTXTHRCFG),
69 dump_register(GRXTHRCFG),
70 dump_register(GCTL),
71 dump_register(GEVTEN),
72 dump_register(GSTS),
73 dump_register(GSNPSID),
74 dump_register(GGPIO),
75 dump_register(GUID),
76 dump_register(GUCTL),
77 dump_register(GBUSERRADDR0),
78 dump_register(GBUSERRADDR1),
79 dump_register(GPRTBIMAP0),
80 dump_register(GPRTBIMAP1),
81 dump_register(GHWPARAMS0),
82 dump_register(GHWPARAMS1),
83 dump_register(GHWPARAMS2),
84 dump_register(GHWPARAMS3),
85 dump_register(GHWPARAMS4),
86 dump_register(GHWPARAMS5),
87 dump_register(GHWPARAMS6),
88 dump_register(GHWPARAMS7),
89 dump_register(GDBGFIFOSPACE),
90 dump_register(GDBGLTSSM),
91 dump_register(GPRTBIMAP_HS0),
92 dump_register(GPRTBIMAP_HS1),
93 dump_register(GPRTBIMAP_FS0),
94 dump_register(GPRTBIMAP_FS1),
95
96 dump_register(GUSB2PHYCFG(0)),
97 dump_register(GUSB2PHYCFG(1)),
98 dump_register(GUSB2PHYCFG(2)),
99 dump_register(GUSB2PHYCFG(3)),
100 dump_register(GUSB2PHYCFG(4)),
101 dump_register(GUSB2PHYCFG(5)),
102 dump_register(GUSB2PHYCFG(6)),
103 dump_register(GUSB2PHYCFG(7)),
104 dump_register(GUSB2PHYCFG(8)),
105 dump_register(GUSB2PHYCFG(9)),
106 dump_register(GUSB2PHYCFG(10)),
107 dump_register(GUSB2PHYCFG(11)),
108 dump_register(GUSB2PHYCFG(12)),
109 dump_register(GUSB2PHYCFG(13)),
110 dump_register(GUSB2PHYCFG(14)),
111 dump_register(GUSB2PHYCFG(15)),
112
113 dump_register(GUSB2I2CCTL(0)),
114 dump_register(GUSB2I2CCTL(1)),
115 dump_register(GUSB2I2CCTL(2)),
116 dump_register(GUSB2I2CCTL(3)),
117 dump_register(GUSB2I2CCTL(4)),
118 dump_register(GUSB2I2CCTL(5)),
119 dump_register(GUSB2I2CCTL(6)),
120 dump_register(GUSB2I2CCTL(7)),
121 dump_register(GUSB2I2CCTL(8)),
122 dump_register(GUSB2I2CCTL(9)),
123 dump_register(GUSB2I2CCTL(10)),
124 dump_register(GUSB2I2CCTL(11)),
125 dump_register(GUSB2I2CCTL(12)),
126 dump_register(GUSB2I2CCTL(13)),
127 dump_register(GUSB2I2CCTL(14)),
128 dump_register(GUSB2I2CCTL(15)),
129
130 dump_register(GUSB2PHYACC(0)),
131 dump_register(GUSB2PHYACC(1)),
132 dump_register(GUSB2PHYACC(2)),
133 dump_register(GUSB2PHYACC(3)),
134 dump_register(GUSB2PHYACC(4)),
135 dump_register(GUSB2PHYACC(5)),
136 dump_register(GUSB2PHYACC(6)),
137 dump_register(GUSB2PHYACC(7)),
138 dump_register(GUSB2PHYACC(8)),
139 dump_register(GUSB2PHYACC(9)),
140 dump_register(GUSB2PHYACC(10)),
141 dump_register(GUSB2PHYACC(11)),
142 dump_register(GUSB2PHYACC(12)),
143 dump_register(GUSB2PHYACC(13)),
144 dump_register(GUSB2PHYACC(14)),
145 dump_register(GUSB2PHYACC(15)),
146
147 dump_register(GUSB3PIPECTL(0)),
148 dump_register(GUSB3PIPECTL(1)),
149 dump_register(GUSB3PIPECTL(2)),
150 dump_register(GUSB3PIPECTL(3)),
151 dump_register(GUSB3PIPECTL(4)),
152 dump_register(GUSB3PIPECTL(5)),
153 dump_register(GUSB3PIPECTL(6)),
154 dump_register(GUSB3PIPECTL(7)),
155 dump_register(GUSB3PIPECTL(8)),
156 dump_register(GUSB3PIPECTL(9)),
157 dump_register(GUSB3PIPECTL(10)),
158 dump_register(GUSB3PIPECTL(11)),
159 dump_register(GUSB3PIPECTL(12)),
160 dump_register(GUSB3PIPECTL(13)),
161 dump_register(GUSB3PIPECTL(14)),
162 dump_register(GUSB3PIPECTL(15)),
163
164 dump_register(GTXFIFOSIZ(0)),
165 dump_register(GTXFIFOSIZ(1)),
166 dump_register(GTXFIFOSIZ(2)),
167 dump_register(GTXFIFOSIZ(3)),
168 dump_register(GTXFIFOSIZ(4)),
169 dump_register(GTXFIFOSIZ(5)),
170 dump_register(GTXFIFOSIZ(6)),
171 dump_register(GTXFIFOSIZ(7)),
172 dump_register(GTXFIFOSIZ(8)),
173 dump_register(GTXFIFOSIZ(9)),
174 dump_register(GTXFIFOSIZ(10)),
175 dump_register(GTXFIFOSIZ(11)),
176 dump_register(GTXFIFOSIZ(12)),
177 dump_register(GTXFIFOSIZ(13)),
178 dump_register(GTXFIFOSIZ(14)),
179 dump_register(GTXFIFOSIZ(15)),
180 dump_register(GTXFIFOSIZ(16)),
181 dump_register(GTXFIFOSIZ(17)),
182 dump_register(GTXFIFOSIZ(18)),
183 dump_register(GTXFIFOSIZ(19)),
184 dump_register(GTXFIFOSIZ(20)),
185 dump_register(GTXFIFOSIZ(21)),
186 dump_register(GTXFIFOSIZ(22)),
187 dump_register(GTXFIFOSIZ(23)),
188 dump_register(GTXFIFOSIZ(24)),
189 dump_register(GTXFIFOSIZ(25)),
190 dump_register(GTXFIFOSIZ(26)),
191 dump_register(GTXFIFOSIZ(27)),
192 dump_register(GTXFIFOSIZ(28)),
193 dump_register(GTXFIFOSIZ(29)),
194 dump_register(GTXFIFOSIZ(30)),
195 dump_register(GTXFIFOSIZ(31)),
196
197 dump_register(GRXFIFOSIZ(0)),
198 dump_register(GRXFIFOSIZ(1)),
199 dump_register(GRXFIFOSIZ(2)),
200 dump_register(GRXFIFOSIZ(3)),
201 dump_register(GRXFIFOSIZ(4)),
202 dump_register(GRXFIFOSIZ(5)),
203 dump_register(GRXFIFOSIZ(6)),
204 dump_register(GRXFIFOSIZ(7)),
205 dump_register(GRXFIFOSIZ(8)),
206 dump_register(GRXFIFOSIZ(9)),
207 dump_register(GRXFIFOSIZ(10)),
208 dump_register(GRXFIFOSIZ(11)),
209 dump_register(GRXFIFOSIZ(12)),
210 dump_register(GRXFIFOSIZ(13)),
211 dump_register(GRXFIFOSIZ(14)),
212 dump_register(GRXFIFOSIZ(15)),
213 dump_register(GRXFIFOSIZ(16)),
214 dump_register(GRXFIFOSIZ(17)),
215 dump_register(GRXFIFOSIZ(18)),
216 dump_register(GRXFIFOSIZ(19)),
217 dump_register(GRXFIFOSIZ(20)),
218 dump_register(GRXFIFOSIZ(21)),
219 dump_register(GRXFIFOSIZ(22)),
220 dump_register(GRXFIFOSIZ(23)),
221 dump_register(GRXFIFOSIZ(24)),
222 dump_register(GRXFIFOSIZ(25)),
223 dump_register(GRXFIFOSIZ(26)),
224 dump_register(GRXFIFOSIZ(27)),
225 dump_register(GRXFIFOSIZ(28)),
226 dump_register(GRXFIFOSIZ(29)),
227 dump_register(GRXFIFOSIZ(30)),
228 dump_register(GRXFIFOSIZ(31)),
229
230 dump_register(GEVNTADRLO(0)),
231 dump_register(GEVNTADRHI(0)),
232 dump_register(GEVNTSIZ(0)),
233 dump_register(GEVNTCOUNT(0)),
234
235 dump_register(GHWPARAMS8),
236 dump_register(DCFG),
237 dump_register(DCTL),
238 dump_register(DEVTEN),
239 dump_register(DSTS),
240 dump_register(DGCMDPAR),
241 dump_register(DGCMD),
242 dump_register(DALEPENA),
243
244 dump_register(DEPCMDPAR2(0)),
245 dump_register(DEPCMDPAR2(1)),
246 dump_register(DEPCMDPAR2(2)),
247 dump_register(DEPCMDPAR2(3)),
248 dump_register(DEPCMDPAR2(4)),
249 dump_register(DEPCMDPAR2(5)),
250 dump_register(DEPCMDPAR2(6)),
251 dump_register(DEPCMDPAR2(7)),
252 dump_register(DEPCMDPAR2(8)),
253 dump_register(DEPCMDPAR2(9)),
254 dump_register(DEPCMDPAR2(10)),
255 dump_register(DEPCMDPAR2(11)),
256 dump_register(DEPCMDPAR2(12)),
257 dump_register(DEPCMDPAR2(13)),
258 dump_register(DEPCMDPAR2(14)),
259 dump_register(DEPCMDPAR2(15)),
260 dump_register(DEPCMDPAR2(16)),
261 dump_register(DEPCMDPAR2(17)),
262 dump_register(DEPCMDPAR2(18)),
263 dump_register(DEPCMDPAR2(19)),
264 dump_register(DEPCMDPAR2(20)),
265 dump_register(DEPCMDPAR2(21)),
266 dump_register(DEPCMDPAR2(22)),
267 dump_register(DEPCMDPAR2(23)),
268 dump_register(DEPCMDPAR2(24)),
269 dump_register(DEPCMDPAR2(25)),
270 dump_register(DEPCMDPAR2(26)),
271 dump_register(DEPCMDPAR2(27)),
272 dump_register(DEPCMDPAR2(28)),
273 dump_register(DEPCMDPAR2(29)),
274 dump_register(DEPCMDPAR2(30)),
275 dump_register(DEPCMDPAR2(31)),
276
277 dump_register(DEPCMDPAR1(0)),
278 dump_register(DEPCMDPAR1(1)),
279 dump_register(DEPCMDPAR1(2)),
280 dump_register(DEPCMDPAR1(3)),
281 dump_register(DEPCMDPAR1(4)),
282 dump_register(DEPCMDPAR1(5)),
283 dump_register(DEPCMDPAR1(6)),
284 dump_register(DEPCMDPAR1(7)),
285 dump_register(DEPCMDPAR1(8)),
286 dump_register(DEPCMDPAR1(9)),
287 dump_register(DEPCMDPAR1(10)),
288 dump_register(DEPCMDPAR1(11)),
289 dump_register(DEPCMDPAR1(12)),
290 dump_register(DEPCMDPAR1(13)),
291 dump_register(DEPCMDPAR1(14)),
292 dump_register(DEPCMDPAR1(15)),
293 dump_register(DEPCMDPAR1(16)),
294 dump_register(DEPCMDPAR1(17)),
295 dump_register(DEPCMDPAR1(18)),
296 dump_register(DEPCMDPAR1(19)),
297 dump_register(DEPCMDPAR1(20)),
298 dump_register(DEPCMDPAR1(21)),
299 dump_register(DEPCMDPAR1(22)),
300 dump_register(DEPCMDPAR1(23)),
301 dump_register(DEPCMDPAR1(24)),
302 dump_register(DEPCMDPAR1(25)),
303 dump_register(DEPCMDPAR1(26)),
304 dump_register(DEPCMDPAR1(27)),
305 dump_register(DEPCMDPAR1(28)),
306 dump_register(DEPCMDPAR1(29)),
307 dump_register(DEPCMDPAR1(30)),
308 dump_register(DEPCMDPAR1(31)),
309
310 dump_register(DEPCMDPAR0(0)),
311 dump_register(DEPCMDPAR0(1)),
312 dump_register(DEPCMDPAR0(2)),
313 dump_register(DEPCMDPAR0(3)),
314 dump_register(DEPCMDPAR0(4)),
315 dump_register(DEPCMDPAR0(5)),
316 dump_register(DEPCMDPAR0(6)),
317 dump_register(DEPCMDPAR0(7)),
318 dump_register(DEPCMDPAR0(8)),
319 dump_register(DEPCMDPAR0(9)),
320 dump_register(DEPCMDPAR0(10)),
321 dump_register(DEPCMDPAR0(11)),
322 dump_register(DEPCMDPAR0(12)),
323 dump_register(DEPCMDPAR0(13)),
324 dump_register(DEPCMDPAR0(14)),
325 dump_register(DEPCMDPAR0(15)),
326 dump_register(DEPCMDPAR0(16)),
327 dump_register(DEPCMDPAR0(17)),
328 dump_register(DEPCMDPAR0(18)),
329 dump_register(DEPCMDPAR0(19)),
330 dump_register(DEPCMDPAR0(20)),
331 dump_register(DEPCMDPAR0(21)),
332 dump_register(DEPCMDPAR0(22)),
333 dump_register(DEPCMDPAR0(23)),
334 dump_register(DEPCMDPAR0(24)),
335 dump_register(DEPCMDPAR0(25)),
336 dump_register(DEPCMDPAR0(26)),
337 dump_register(DEPCMDPAR0(27)),
338 dump_register(DEPCMDPAR0(28)),
339 dump_register(DEPCMDPAR0(29)),
340 dump_register(DEPCMDPAR0(30)),
341 dump_register(DEPCMDPAR0(31)),
342
343 dump_register(DEPCMD(0)),
344 dump_register(DEPCMD(1)),
345 dump_register(DEPCMD(2)),
346 dump_register(DEPCMD(3)),
347 dump_register(DEPCMD(4)),
348 dump_register(DEPCMD(5)),
349 dump_register(DEPCMD(6)),
350 dump_register(DEPCMD(7)),
351 dump_register(DEPCMD(8)),
352 dump_register(DEPCMD(9)),
353 dump_register(DEPCMD(10)),
354 dump_register(DEPCMD(11)),
355 dump_register(DEPCMD(12)),
356 dump_register(DEPCMD(13)),
357 dump_register(DEPCMD(14)),
358 dump_register(DEPCMD(15)),
359 dump_register(DEPCMD(16)),
360 dump_register(DEPCMD(17)),
361 dump_register(DEPCMD(18)),
362 dump_register(DEPCMD(19)),
363 dump_register(DEPCMD(20)),
364 dump_register(DEPCMD(21)),
365 dump_register(DEPCMD(22)),
366 dump_register(DEPCMD(23)),
367 dump_register(DEPCMD(24)),
368 dump_register(DEPCMD(25)),
369 dump_register(DEPCMD(26)),
370 dump_register(DEPCMD(27)),
371 dump_register(DEPCMD(28)),
372 dump_register(DEPCMD(29)),
373 dump_register(DEPCMD(30)),
374 dump_register(DEPCMD(31)),
375
376 dump_register(OCFG),
377 dump_register(OCTL),
378 dump_register(OEVTEN),
379 dump_register(OSTS),
380};
381
382static int dwc3_regdump_show(struct seq_file *s, void *unused)
383{
384 struct dwc3 *dwc = s->private;
385 int i;
386
387 seq_printf(s, "DesignWare USB3 Core Register Dump\n");
388
389 for (i = 0; i < ARRAY_SIZE(dwc3_regs); i++) {
390 seq_printf(s, "%-20s : %08x\n", dwc3_regs[i].name,
391 dwc3_readl(dwc->regs, dwc3_regs[i].offset));
392 }
393
394 return 0;
395}
396
397static int dwc3_regdump_open(struct inode *inode, struct file *file)
398{
399 return single_open(file, dwc3_regdump_show, inode->i_private);
400}
401
402static const struct file_operations dwc3_regdump_fops = {
403 .open = dwc3_regdump_open,
404 .read = seq_read,
405 .release = single_release,
406};
407
408int __devinit dwc3_debugfs_init(struct dwc3 *dwc)
409{
410 struct dentry *root;
411 struct dentry *file;
412 int ret;
413
414 root = debugfs_create_dir(dev_name(dwc->dev), NULL);
415 if (IS_ERR(root)){
416 ret = PTR_ERR(root);
417 goto err0;
418 }
419
420 dwc->root = root;
421
422 file = debugfs_create_file("regdump", S_IRUGO, root, dwc,
423 &dwc3_regdump_fops);
424 if (IS_ERR(file)) {
425 ret = PTR_ERR(file);
426 goto err1;
427 }
428 return 0;
429
430err1:
431 debugfs_remove_recursive(root);
432
433err0:
434 return ret;
435}
436
437void __devexit dwc3_debugfs_exit(struct dwc3 *dwc)
438{
439 debugfs_remove_recursive(dwc->root);
440 dwc->root = NULL;
441}
diff --git a/drivers/usb/dwc3/dwc3-omap.c b/drivers/usb/dwc3/dwc3-omap.c
new file mode 100644
index 000000000000..062552b5fc8a
--- /dev/null
+++ b/drivers/usb/dwc3/dwc3-omap.c
@@ -0,0 +1,401 @@
1/**
2 * dwc3-omap.c - OMAP Specific Glue layer
3 *
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
5 *
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions, and the following disclaimer,
14 * without modification.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. The names of the above-listed copyright holders may not be used
19 * to endorse or promote products derived from this software without
20 * specific prior written permission.
21 *
22 * ALTERNATIVELY, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2, as published by the Free
24 * Software Foundation.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
27 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
28 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
30 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
31 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
32 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
33 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
34 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
35 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
36 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 */
38
39#include <linux/module.h>
40#include <linux/kernel.h>
41#include <linux/slab.h>
42#include <linux/interrupt.h>
43#include <linux/spinlock.h>
44#include <linux/platform_device.h>
45#include <linux/platform_data/dwc3-omap.h>
46#include <linux/dma-mapping.h>
47#include <linux/ioport.h>
48#include <linux/io.h>
49#include <linux/module.h>
50
51#include "io.h"
52
53/*
54 * All these registers belong to OMAP's Wrapper around the
55 * DesignWare USB3 Core.
56 */
57
58#define USBOTGSS_REVISION 0x0000
59#define USBOTGSS_SYSCONFIG 0x0010
60#define USBOTGSS_IRQ_EOI 0x0020
61#define USBOTGSS_IRQSTATUS_RAW_0 0x0024
62#define USBOTGSS_IRQSTATUS_0 0x0028
63#define USBOTGSS_IRQENABLE_SET_0 0x002c
64#define USBOTGSS_IRQENABLE_CLR_0 0x0030
65#define USBOTGSS_IRQSTATUS_RAW_1 0x0034
66#define USBOTGSS_IRQSTATUS_1 0x0038
67#define USBOTGSS_IRQENABLE_SET_1 0x003c
68#define USBOTGSS_IRQENABLE_CLR_1 0x0040
69#define USBOTGSS_UTMI_OTG_CTRL 0x0080
70#define USBOTGSS_UTMI_OTG_STATUS 0x0084
71#define USBOTGSS_MMRAM_OFFSET 0x0100
72#define USBOTGSS_FLADJ 0x0104
73#define USBOTGSS_DEBUG_CFG 0x0108
74#define USBOTGSS_DEBUG_DATA 0x010c
75
76/* SYSCONFIG REGISTER */
77#define USBOTGSS_SYSCONFIG_DMADISABLE (1 << 16)
78#define USBOTGSS_SYSCONFIG_STANDBYMODE(x) ((x) << 4)
79
80#define USBOTGSS_STANDBYMODE_FORCE_STANDBY 0
81#define USBOTGSS_STANDBYMODE_NO_STANDBY 1
82#define USBOTGSS_STANDBYMODE_SMART_STANDBY 2
83#define USBOTGSS_STANDBYMODE_SMART_WAKEUP 3
84
85#define USBOTGSS_STANDBYMODE_MASK (0x03 << 4)
86
87#define USBOTGSS_SYSCONFIG_IDLEMODE(x) ((x) << 2)
88
89#define USBOTGSS_IDLEMODE_FORCE_IDLE 0
90#define USBOTGSS_IDLEMODE_NO_IDLE 1
91#define USBOTGSS_IDLEMODE_SMART_IDLE 2
92#define USBOTGSS_IDLEMODE_SMART_WAKEUP 3
93
94#define USBOTGSS_IDLEMODE_MASK (0x03 << 2)
95
96/* IRQ_EOI REGISTER */
97#define USBOTGSS_IRQ_EOI_LINE_NUMBER (1 << 0)
98
99/* IRQS0 BITS */
100#define USBOTGSS_IRQO_COREIRQ_ST (1 << 0)
101
102/* IRQ1 BITS */
103#define USBOTGSS_IRQ1_DMADISABLECLR (1 << 17)
104#define USBOTGSS_IRQ1_OEVT (1 << 16)
105#define USBOTGSS_IRQ1_DRVVBUS_RISE (1 << 13)
106#define USBOTGSS_IRQ1_CHRGVBUS_RISE (1 << 12)
107#define USBOTGSS_IRQ1_DISCHRGVBUS_RISE (1 << 11)
108#define USBOTGSS_IRQ1_IDPULLUP_RISE (1 << 8)
109#define USBOTGSS_IRQ1_DRVVBUS_FALL (1 << 5)
110#define USBOTGSS_IRQ1_CHRGVBUS_FALL (1 << 4)
111#define USBOTGSS_IRQ1_DISCHRGVBUS_FALL (1 << 3)
112#define USBOTGSS_IRQ1_IDPULLUP_FALL (1 << 0)
113
114/* UTMI_OTG_CTRL REGISTER */
115#define USBOTGSS_UTMI_OTG_CTRL_DRVVBUS (1 << 5)
116#define USBOTGSS_UTMI_OTG_CTRL_CHRGVBUS (1 << 4)
117#define USBOTGSS_UTMI_OTG_CTRL_DISCHRGVBUS (1 << 3)
118#define USBOTGSS_UTMI_OTG_CTRL_IDPULLUP (1 << 0)
119
120/* UTMI_OTG_STATUS REGISTER */
121#define USBOTGSS_UTMI_OTG_STATUS_SW_MODE (1 << 31)
122#define USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT (1 << 9)
123#define USBOTGSS_UTMI_OTG_STATUS_TXBITSTUFFENABLE (1 << 8)
124#define USBOTGSS_UTMI_OTG_STATUS_IDDIG (1 << 4)
125#define USBOTGSS_UTMI_OTG_STATUS_SESSEND (1 << 3)
126#define USBOTGSS_UTMI_OTG_STATUS_SESSVALID (1 << 2)
127#define USBOTGSS_UTMI_OTG_STATUS_VBUSVALID (1 << 1)
128
129struct dwc3_omap {
130 /* device lock */
131 spinlock_t lock;
132
133 struct platform_device *dwc3;
134 struct device *dev;
135
136 int irq;
137 void __iomem *base;
138
139 void *context;
140 u32 resource_size;
141
142 u32 dma_status:1;
143};
144
145static irqreturn_t dwc3_omap_interrupt(int irq, void *_omap)
146{
147 struct dwc3_omap *omap = _omap;
148 u32 reg;
149
150 spin_lock(&omap->lock);
151
152 reg = dwc3_readl(omap->base, USBOTGSS_IRQSTATUS_1);
153
154 if (reg & USBOTGSS_IRQ1_DMADISABLECLR) {
155 dev_dbg(omap->dev, "DMA Disable was Cleared\n");
156 omap->dma_status = false;
157 }
158
159 if (reg & USBOTGSS_IRQ1_OEVT)
160 dev_dbg(omap->dev, "OTG Event\n");
161
162 if (reg & USBOTGSS_IRQ1_DRVVBUS_RISE)
163 dev_dbg(omap->dev, "DRVVBUS Rise\n");
164
165 if (reg & USBOTGSS_IRQ1_CHRGVBUS_RISE)
166 dev_dbg(omap->dev, "CHRGVBUS Rise\n");
167
168 if (reg & USBOTGSS_IRQ1_DISCHRGVBUS_RISE)
169 dev_dbg(omap->dev, "DISCHRGVBUS Rise\n");
170
171 if (reg & USBOTGSS_IRQ1_IDPULLUP_RISE)
172 dev_dbg(omap->dev, "IDPULLUP Rise\n");
173
174 if (reg & USBOTGSS_IRQ1_DRVVBUS_FALL)
175 dev_dbg(omap->dev, "DRVVBUS Fall\n");
176
177 if (reg & USBOTGSS_IRQ1_CHRGVBUS_FALL)
178 dev_dbg(omap->dev, "CHRGVBUS Fall\n");
179
180 if (reg & USBOTGSS_IRQ1_DISCHRGVBUS_FALL)
181 dev_dbg(omap->dev, "DISCHRGVBUS Fall\n");
182
183 if (reg & USBOTGSS_IRQ1_IDPULLUP_FALL)
184 dev_dbg(omap->dev, "IDPULLUP Fall\n");
185
186 dwc3_writel(omap->base, USBOTGSS_IRQSTATUS_1, reg);
187
188 reg = dwc3_readl(omap->base, USBOTGSS_IRQSTATUS_0);
189 dwc3_writel(omap->base, USBOTGSS_IRQSTATUS_0, reg);
190
191 spin_unlock(&omap->lock);
192
193 return IRQ_HANDLED;
194}
195
196static int __devinit dwc3_omap_probe(struct platform_device *pdev)
197{
198 struct dwc3_omap_data *pdata = pdev->dev.platform_data;
199 struct platform_device *dwc3;
200 struct dwc3_omap *omap;
201 struct resource *res;
202
203 int ret = -ENOMEM;
204 int irq;
205
206 u32 reg;
207
208 void __iomem *base;
209 void *context;
210
211 omap = kzalloc(sizeof(*omap), GFP_KERNEL);
212 if (!omap) {
213 dev_err(&pdev->dev, "not enough memory\n");
214 goto err0;
215 }
216
217 platform_set_drvdata(pdev, omap);
218
219 irq = platform_get_irq(pdev, 1);
220 if (irq < 0) {
221 dev_err(&pdev->dev, "missing IRQ resource\n");
222 ret = -EINVAL;
223 goto err1;
224 }
225
226 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
227 if (!res) {
228 dev_err(&pdev->dev, "missing memory base resource\n");
229 ret = -EINVAL;
230 goto err1;
231 }
232
233 base = ioremap_nocache(res->start, resource_size(res));
234 if (!base) {
235 dev_err(&pdev->dev, "ioremap failed\n");
236 goto err1;
237 }
238
239 dwc3 = platform_device_alloc("dwc3-omap", -1);
240 if (!dwc3) {
241 dev_err(&pdev->dev, "couldn't allocate dwc3 device\n");
242 goto err2;
243 }
244
245 context = kzalloc(resource_size(res), GFP_KERNEL);
246 if (!context) {
247 dev_err(&pdev->dev, "couldn't allocate dwc3 context memory\n");
248 goto err3;
249 }
250
251 spin_lock_init(&omap->lock);
252 dma_set_coherent_mask(&dwc3->dev, pdev->dev.coherent_dma_mask);
253
254 dwc3->dev.parent = &pdev->dev;
255 dwc3->dev.dma_mask = pdev->dev.dma_mask;
256 dwc3->dev.dma_parms = pdev->dev.dma_parms;
257 omap->resource_size = resource_size(res);
258 omap->context = context;
259 omap->dev = &pdev->dev;
260 omap->irq = irq;
261 omap->base = base;
262 omap->dwc3 = dwc3;
263
264 reg = dwc3_readl(omap->base, USBOTGSS_UTMI_OTG_STATUS);
265
266 if (!pdata) {
267 dev_dbg(&pdev->dev, "missing platform data\n");
268 } else {
269 switch (pdata->utmi_mode) {
270 case DWC3_OMAP_UTMI_MODE_SW:
271 reg |= USBOTGSS_UTMI_OTG_STATUS_SW_MODE;
272 break;
273 case DWC3_OMAP_UTMI_MODE_HW:
274 reg &= ~USBOTGSS_UTMI_OTG_STATUS_SW_MODE;
275 break;
276 default:
277 dev_dbg(&pdev->dev, "UNKNOWN utmi mode %d\n",
278 pdata->utmi_mode);
279 }
280 }
281
282 dwc3_writel(omap->base, USBOTGSS_UTMI_OTG_STATUS, reg);
283
284 /* check the DMA Status */
285 reg = dwc3_readl(omap->base, USBOTGSS_SYSCONFIG);
286 omap->dma_status = !!(reg & USBOTGSS_SYSCONFIG_DMADISABLE);
287
288 /* Set No-Idle and No-Standby */
289 reg &= ~(USBOTGSS_STANDBYMODE_MASK
290 | USBOTGSS_IDLEMODE_MASK);
291
292 reg |= (USBOTGSS_SYSCONFIG_STANDBYMODE(USBOTGSS_STANDBYMODE_NO_STANDBY)
293 | USBOTGSS_SYSCONFIG_IDLEMODE(USBOTGSS_IDLEMODE_NO_IDLE));
294
295 dwc3_writel(omap->base, USBOTGSS_SYSCONFIG, reg);
296
297 ret = request_irq(omap->irq, dwc3_omap_interrupt, 0,
298 "dwc3-omap", omap);
299 if (ret) {
300 dev_err(&pdev->dev, "failed to request IRQ #%d --> %d\n",
301 omap->irq, ret);
302 goto err4;
303 }
304
305 /* enable all IRQs */
306 reg = USBOTGSS_IRQO_COREIRQ_ST;
307 dwc3_writel(omap->base, USBOTGSS_IRQENABLE_SET_0, reg);
308
309 reg = (USBOTGSS_IRQ1_OEVT |
310 USBOTGSS_IRQ1_DRVVBUS_RISE |
311 USBOTGSS_IRQ1_CHRGVBUS_RISE |
312 USBOTGSS_IRQ1_DISCHRGVBUS_RISE |
313 USBOTGSS_IRQ1_IDPULLUP_RISE |
314 USBOTGSS_IRQ1_DRVVBUS_FALL |
315 USBOTGSS_IRQ1_CHRGVBUS_FALL |
316 USBOTGSS_IRQ1_DISCHRGVBUS_FALL |
317 USBOTGSS_IRQ1_IDPULLUP_FALL);
318
319 dwc3_writel(omap->base, USBOTGSS_IRQENABLE_SET_1, reg);
320
321 ret = platform_device_add_resources(dwc3, pdev->resource,
322 pdev->num_resources);
323 if (ret) {
324 dev_err(&pdev->dev, "couldn't add resources to dwc3 device\n");
325 goto err5;
326 }
327
328 ret = platform_device_add(dwc3);
329 if (ret) {
330 dev_err(&pdev->dev, "failed to register dwc3 device\n");
331 goto err5;
332 }
333
334 return 0;
335
336err5:
337 free_irq(omap->irq, omap);
338
339err4:
340 kfree(omap->context);
341
342err3:
343 platform_device_put(dwc3);
344
345err2:
346 iounmap(base);
347
348err1:
349 kfree(omap);
350
351err0:
352 return ret;
353}
354
355static int __devexit dwc3_omap_remove(struct platform_device *pdev)
356{
357 struct dwc3_omap *omap = platform_get_drvdata(pdev);
358
359 platform_device_unregister(omap->dwc3);
360
361 free_irq(omap->irq, omap);
362 iounmap(omap->base);
363
364 kfree(omap->context);
365 kfree(omap);
366
367 return 0;
368}
369
370static const struct of_device_id of_dwc3_matach[] = {
371 {
372 "ti,dwc3",
373 },
374 { },
375};
376MODULE_DEVICE_TABLE(of, of_dwc3_matach);
377
378static struct platform_driver dwc3_omap_driver = {
379 .probe = dwc3_omap_probe,
380 .remove = __devexit_p(dwc3_omap_remove),
381 .driver = {
382 .name = "omap-dwc3",
383 .of_match_table = of_dwc3_matach,
384 },
385};
386
387MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
388MODULE_LICENSE("Dual BSD/GPL");
389MODULE_DESCRIPTION("DesignWare USB3 OMAP Glue Layer");
390
391static int __devinit dwc3_omap_init(void)
392{
393 return platform_driver_register(&dwc3_omap_driver);
394}
395module_init(dwc3_omap_init);
396
397static void __exit dwc3_omap_exit(void)
398{
399 platform_driver_unregister(&dwc3_omap_driver);
400}
401module_exit(dwc3_omap_exit);
diff --git a/drivers/usb/dwc3/dwc3-pci.c b/drivers/usb/dwc3/dwc3-pci.c
new file mode 100644
index 000000000000..f77c00042685
--- /dev/null
+++ b/drivers/usb/dwc3/dwc3-pci.c
@@ -0,0 +1,219 @@
1/**
2 * dwc3-pci.c - PCI Specific glue layer
3 *
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
5 *
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions, and the following disclaimer,
14 * without modification.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. The names of the above-listed copyright holders may not be used
19 * to endorse or promote products derived from this software without
20 * specific prior written permission.
21 *
22 * ALTERNATIVELY, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2, as published by the Free
24 * Software Foundation.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
27 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
28 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
30 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
31 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
32 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
33 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
34 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
35 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
36 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 */
38
39#include <linux/kernel.h>
40#include <linux/module.h>
41#include <linux/slab.h>
42#include <linux/pci.h>
43#include <linux/platform_device.h>
44
45/* FIXME define these in <linux/pci_ids.h> */
46#define PCI_VENDOR_ID_SYNOPSYS 0x16c3
47#define PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3 0xabcd
48
49#define DWC3_PCI_DEVS_POSSIBLE 32
50
51struct dwc3_pci {
52 struct device *dev;
53 struct platform_device *dwc3;
54};
55
56static DECLARE_BITMAP(dwc3_pci_devs, DWC3_PCI_DEVS_POSSIBLE);
57
58static int dwc3_pci_get_device_id(struct dwc3_pci *glue)
59{
60 int id;
61
62again:
63 id = find_first_zero_bit(dwc3_pci_devs, DWC3_PCI_DEVS_POSSIBLE);
64 if (id < DWC3_PCI_DEVS_POSSIBLE) {
65 int old;
66
67 old = test_and_set_bit(id, dwc3_pci_devs);
68 if (old)
69 goto again;
70 } else {
71 dev_err(glue->dev, "no space for new device\n");
72 id = -ENOMEM;
73 }
74
75 return 0;
76}
77
78static void dwc3_pci_put_device_id(struct dwc3_pci *glue, int id)
79{
80 int ret;
81
82 if (id < 0)
83 return;
84
85 ret = test_bit(id, dwc3_pci_devs);
86 WARN(!ret, "Device: %s\nID %d not in use\n",
87 dev_driver_string(glue->dev), id);
88 clear_bit(id, dwc3_pci_devs);
89}
90
91static int __devinit dwc3_pci_probe(struct pci_dev *pci,
92 const struct pci_device_id *id)
93{
94 struct resource res[2];
95 struct platform_device *dwc3;
96 struct dwc3_pci *glue;
97 int ret = -ENOMEM;
98 int devid;
99
100 glue = kzalloc(sizeof(*glue), GFP_KERNEL);
101 if (!glue) {
102 dev_err(&pci->dev, "not enough memory\n");
103 goto err0;
104 }
105
106 glue->dev = &pci->dev;
107
108 ret = pci_enable_device(pci);
109 if (ret) {
110 dev_err(&pci->dev, "failed to enable pci device\n");
111 goto err1;
112 }
113
114 pci_set_power_state(pci, PCI_D0);
115 pci_set_master(pci);
116
117 devid = dwc3_pci_get_device_id(glue);
118 if (devid < 0)
119 goto err2;
120
121 dwc3 = platform_device_alloc("dwc3-pci", devid);
122 if (!dwc3) {
123 dev_err(&pci->dev, "couldn't allocate dwc3 device\n");
124 goto err3;
125 }
126
127 memset(res, 0x00, sizeof(struct resource) * ARRAY_SIZE(res));
128
129 res[0].start = pci_resource_start(pci, 0);
130 res[0].end = pci_resource_end(pci, 0);
131 res[0].name = "dwc_usb3";
132 res[0].flags = IORESOURCE_MEM;
133
134 res[1].start = pci->irq;
135 res[1].name = "dwc_usb3";
136 res[1].flags = IORESOURCE_IRQ;
137
138 ret = platform_device_add_resources(dwc3, res, ARRAY_SIZE(res));
139 if (ret) {
140 dev_err(&pci->dev, "couldn't add resources to dwc3 device\n");
141 goto err4;
142 }
143
144 pci_set_drvdata(pci, glue);
145
146 dma_set_coherent_mask(&dwc3->dev, pci->dev.coherent_dma_mask);
147
148 dwc3->dev.dma_mask = pci->dev.dma_mask;
149 dwc3->dev.dma_parms = pci->dev.dma_parms;
150 dwc3->dev.parent = &pci->dev;
151 glue->dwc3 = dwc3;
152
153 ret = platform_device_add(dwc3);
154 if (ret) {
155 dev_err(&pci->dev, "failed to register dwc3 device\n");
156 goto err4;
157 }
158
159 return 0;
160
161err4:
162 pci_set_drvdata(pci, NULL);
163 platform_device_put(dwc3);
164
165err3:
166 dwc3_pci_put_device_id(glue, devid);
167
168err2:
169 pci_disable_device(pci);
170
171err1:
172 kfree(pci);
173
174err0:
175 return ret;
176}
177
178static void __devexit dwc3_pci_remove(struct pci_dev *pci)
179{
180 struct dwc3_pci *glue = pci_get_drvdata(pci);
181
182 dwc3_pci_put_device_id(glue, glue->dwc3->id);
183 platform_device_unregister(glue->dwc3);
184 pci_set_drvdata(pci, NULL);
185 pci_disable_device(pci);
186 kfree(glue);
187}
188
189static DEFINE_PCI_DEVICE_TABLE(dwc3_pci_id_table) = {
190 {
191 PCI_DEVICE(PCI_VENDOR_ID_SYNOPSYS,
192 PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3),
193 },
194 { } /* Terminating Entry */
195};
196MODULE_DEVICE_TABLE(pci, dwc3_pci_id_table);
197
198static struct pci_driver dwc3_pci_driver = {
199 .name = "pci-dwc3",
200 .id_table = dwc3_pci_id_table,
201 .probe = dwc3_pci_probe,
202 .remove = __devexit_p(dwc3_pci_remove),
203};
204
205MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
206MODULE_LICENSE("Dual BSD/GPL");
207MODULE_DESCRIPTION("DesignWare USB3 PCI Glue Layer");
208
209static int __devinit dwc3_pci_init(void)
210{
211 return pci_register_driver(&dwc3_pci_driver);
212}
213module_init(dwc3_pci_init);
214
215static void __exit dwc3_pci_exit(void)
216{
217 pci_unregister_driver(&dwc3_pci_driver);
218}
219module_exit(dwc3_pci_exit);
diff --git a/drivers/usb/dwc3/ep0.c b/drivers/usb/dwc3/ep0.c
new file mode 100644
index 000000000000..69a4e43ddf59
--- /dev/null
+++ b/drivers/usb/dwc3/ep0.c
@@ -0,0 +1,804 @@
1/**
2 * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling
3 *
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
5 *
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions, and the following disclaimer,
14 * without modification.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. The names of the above-listed copyright holders may not be used
19 * to endorse or promote products derived from this software without
20 * specific prior written permission.
21 *
22 * ALTERNATIVELY, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2, as published by the Free
24 * Software Foundation.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
27 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
28 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
30 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
31 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
32 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
33 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
34 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
35 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
36 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 */
38
39#include <linux/kernel.h>
40#include <linux/slab.h>
41#include <linux/spinlock.h>
42#include <linux/platform_device.h>
43#include <linux/pm_runtime.h>
44#include <linux/interrupt.h>
45#include <linux/io.h>
46#include <linux/list.h>
47#include <linux/dma-mapping.h>
48
49#include <linux/usb/ch9.h>
50#include <linux/usb/gadget.h>
51
52#include "core.h"
53#include "gadget.h"
54#include "io.h"
55
56static void dwc3_ep0_inspect_setup(struct dwc3 *dwc,
57 const struct dwc3_event_depevt *event);
58
59static const char *dwc3_ep0_state_string(enum dwc3_ep0_state state)
60{
61 switch (state) {
62 case EP0_UNCONNECTED:
63 return "Unconnected";
64 case EP0_SETUP_PHASE:
65 return "Setup Phase";
66 case EP0_DATA_PHASE:
67 return "Data Phase";
68 case EP0_STATUS_PHASE:
69 return "Status Phase";
70 default:
71 return "UNKNOWN";
72 }
73}
74
75static int dwc3_ep0_start_trans(struct dwc3 *dwc, u8 epnum, dma_addr_t buf_dma,
76 u32 len, u32 type)
77{
78 struct dwc3_gadget_ep_cmd_params params;
79 struct dwc3_trb_hw *trb_hw;
80 struct dwc3_trb trb;
81 struct dwc3_ep *dep;
82
83 int ret;
84
85 dep = dwc->eps[epnum];
86 if (dep->flags & DWC3_EP_BUSY) {
87 dev_vdbg(dwc->dev, "%s: still busy\n", dep->name);
88 return 0;
89 }
90
91 trb_hw = dwc->ep0_trb;
92 memset(&trb, 0, sizeof(trb));
93
94 trb.trbctl = type;
95 trb.bplh = buf_dma;
96 trb.length = len;
97
98 trb.hwo = 1;
99 trb.lst = 1;
100 trb.ioc = 1;
101 trb.isp_imi = 1;
102
103 dwc3_trb_to_hw(&trb, trb_hw);
104
105 memset(&params, 0, sizeof(params));
106 params.param0 = upper_32_bits(dwc->ep0_trb_addr);
107 params.param1 = lower_32_bits(dwc->ep0_trb_addr);
108
109 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
110 DWC3_DEPCMD_STARTTRANSFER, &params);
111 if (ret < 0) {
112 dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n");
113 return ret;
114 }
115
116 dep->flags |= DWC3_EP_BUSY;
117 dep->res_trans_idx = dwc3_gadget_ep_get_transfer_index(dwc,
118 dep->number);
119
120 dwc->ep0_next_event = DWC3_EP0_COMPLETE;
121
122 return 0;
123}
124
125static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep,
126 struct dwc3_request *req)
127{
128 int ret = 0;
129
130 req->request.actual = 0;
131 req->request.status = -EINPROGRESS;
132 req->epnum = dep->number;
133
134 list_add_tail(&req->list, &dep->request_list);
135
136 /*
137 * Gadget driver might not be quick enough to queue a request
138 * before we get a Transfer Not Ready event on this endpoint.
139 *
140 * In that case, we will set DWC3_EP_PENDING_REQUEST. When that
141 * flag is set, it's telling us that as soon as Gadget queues the
142 * required request, we should kick the transfer here because the
143 * IRQ we were waiting for is long gone.
144 */
145 if (dep->flags & DWC3_EP_PENDING_REQUEST) {
146 struct dwc3 *dwc = dep->dwc;
147 unsigned direction;
148 u32 type;
149
150 direction = !!(dep->flags & DWC3_EP0_DIR_IN);
151
152 if (dwc->ep0state == EP0_STATUS_PHASE) {
153 type = dwc->three_stage_setup
154 ? DWC3_TRBCTL_CONTROL_STATUS3
155 : DWC3_TRBCTL_CONTROL_STATUS2;
156 } else if (dwc->ep0state == EP0_DATA_PHASE) {
157 type = DWC3_TRBCTL_CONTROL_DATA;
158 } else {
159 /* should never happen */
160 WARN_ON(1);
161 return 0;
162 }
163
164 ret = dwc3_ep0_start_trans(dwc, direction,
165 req->request.dma, req->request.length, type);
166 dep->flags &= ~(DWC3_EP_PENDING_REQUEST |
167 DWC3_EP0_DIR_IN);
168 }
169
170 return ret;
171}
172
173int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request,
174 gfp_t gfp_flags)
175{
176 struct dwc3_request *req = to_dwc3_request(request);
177 struct dwc3_ep *dep = to_dwc3_ep(ep);
178 struct dwc3 *dwc = dep->dwc;
179
180 unsigned long flags;
181
182 int ret;
183
184 spin_lock_irqsave(&dwc->lock, flags);
185 if (!dep->desc) {
186 dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n",
187 request, dep->name);
188 ret = -ESHUTDOWN;
189 goto out;
190 }
191
192 /* we share one TRB for ep0/1 */
193 if (!list_empty(&dwc->eps[0]->request_list) ||
194 !list_empty(&dwc->eps[1]->request_list) ||
195 dwc->ep0_status_pending) {
196 ret = -EBUSY;
197 goto out;
198 }
199
200 dev_vdbg(dwc->dev, "queueing request %p to %s length %d, state '%s'\n",
201 request, dep->name, request->length,
202 dwc3_ep0_state_string(dwc->ep0state));
203
204 ret = __dwc3_gadget_ep0_queue(dep, req);
205
206out:
207 spin_unlock_irqrestore(&dwc->lock, flags);
208
209 return ret;
210}
211
212static void dwc3_ep0_stall_and_restart(struct dwc3 *dwc)
213{
214 struct dwc3_ep *dep = dwc->eps[0];
215
216 /* stall is always issued on EP0 */
217 __dwc3_gadget_ep_set_halt(dwc->eps[0], 1);
218 dwc->eps[0]->flags = DWC3_EP_ENABLED;
219
220 if (!list_empty(&dep->request_list)) {
221 struct dwc3_request *req;
222
223 req = next_request(&dep->request_list);
224 dwc3_gadget_giveback(dep, req, -ECONNRESET);
225 }
226
227 dwc->ep0state = EP0_SETUP_PHASE;
228 dwc3_ep0_out_start(dwc);
229}
230
231void dwc3_ep0_out_start(struct dwc3 *dwc)
232{
233 int ret;
234
235 ret = dwc3_ep0_start_trans(dwc, 0, dwc->ctrl_req_addr, 8,
236 DWC3_TRBCTL_CONTROL_SETUP);
237 WARN_ON(ret < 0);
238}
239
240static struct dwc3_ep *dwc3_wIndex_to_dep(struct dwc3 *dwc, __le16 wIndex_le)
241{
242 struct dwc3_ep *dep;
243 u32 windex = le16_to_cpu(wIndex_le);
244 u32 epnum;
245
246 epnum = (windex & USB_ENDPOINT_NUMBER_MASK) << 1;
247 if ((windex & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN)
248 epnum |= 1;
249
250 dep = dwc->eps[epnum];
251 if (dep->flags & DWC3_EP_ENABLED)
252 return dep;
253
254 return NULL;
255}
256
257static void dwc3_ep0_send_status_response(struct dwc3 *dwc)
258{
259 dwc3_ep0_start_trans(dwc, 1, dwc->setup_buf_addr,
260 dwc->ep0_usb_req.length,
261 DWC3_TRBCTL_CONTROL_DATA);
262}
263
264/*
265 * ch 9.4.5
266 */
267static int dwc3_ep0_handle_status(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
268{
269 struct dwc3_ep *dep;
270 u32 recip;
271 u16 usb_status = 0;
272 __le16 *response_pkt;
273
274 recip = ctrl->bRequestType & USB_RECIP_MASK;
275 switch (recip) {
276 case USB_RECIP_DEVICE:
277 /*
278 * We are self-powered. U1/U2/LTM will be set later
279 * once we handle this states. RemoteWakeup is 0 on SS
280 */
281 usb_status |= dwc->is_selfpowered << USB_DEVICE_SELF_POWERED;
282 break;
283
284 case USB_RECIP_INTERFACE:
285 /*
286 * Function Remote Wake Capable D0
287 * Function Remote Wakeup D1
288 */
289 break;
290
291 case USB_RECIP_ENDPOINT:
292 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
293 if (!dep)
294 return -EINVAL;
295
296 if (dep->flags & DWC3_EP_STALL)
297 usb_status = 1 << USB_ENDPOINT_HALT;
298 break;
299 default:
300 return -EINVAL;
301 };
302
303 response_pkt = (__le16 *) dwc->setup_buf;
304 *response_pkt = cpu_to_le16(usb_status);
305 dwc->ep0_usb_req.length = sizeof(*response_pkt);
306 dwc->ep0_status_pending = 1;
307
308 return 0;
309}
310
311static int dwc3_ep0_handle_feature(struct dwc3 *dwc,
312 struct usb_ctrlrequest *ctrl, int set)
313{
314 struct dwc3_ep *dep;
315 u32 recip;
316 u32 wValue;
317 u32 wIndex;
318 u32 reg;
319 int ret;
320 u32 mode;
321
322 wValue = le16_to_cpu(ctrl->wValue);
323 wIndex = le16_to_cpu(ctrl->wIndex);
324 recip = ctrl->bRequestType & USB_RECIP_MASK;
325 switch (recip) {
326 case USB_RECIP_DEVICE:
327
328 /*
329 * 9.4.1 says only only for SS, in AddressState only for
330 * default control pipe
331 */
332 switch (wValue) {
333 case USB_DEVICE_U1_ENABLE:
334 case USB_DEVICE_U2_ENABLE:
335 case USB_DEVICE_LTM_ENABLE:
336 if (dwc->dev_state != DWC3_CONFIGURED_STATE)
337 return -EINVAL;
338 if (dwc->speed != DWC3_DSTS_SUPERSPEED)
339 return -EINVAL;
340 }
341
342 /* XXX add U[12] & LTM */
343 switch (wValue) {
344 case USB_DEVICE_REMOTE_WAKEUP:
345 break;
346 case USB_DEVICE_U1_ENABLE:
347 break;
348 case USB_DEVICE_U2_ENABLE:
349 break;
350 case USB_DEVICE_LTM_ENABLE:
351 break;
352
353 case USB_DEVICE_TEST_MODE:
354 if ((wIndex & 0xff) != 0)
355 return -EINVAL;
356 if (!set)
357 return -EINVAL;
358
359 mode = wIndex >> 8;
360 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
361 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
362
363 switch (mode) {
364 case TEST_J:
365 case TEST_K:
366 case TEST_SE0_NAK:
367 case TEST_PACKET:
368 case TEST_FORCE_EN:
369 reg |= mode << 1;
370 break;
371 default:
372 return -EINVAL;
373 }
374 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
375 break;
376 default:
377 return -EINVAL;
378 }
379 break;
380
381 case USB_RECIP_INTERFACE:
382 switch (wValue) {
383 case USB_INTRF_FUNC_SUSPEND:
384 if (wIndex & USB_INTRF_FUNC_SUSPEND_LP)
385 /* XXX enable Low power suspend */
386 ;
387 if (wIndex & USB_INTRF_FUNC_SUSPEND_RW)
388 /* XXX enable remote wakeup */
389 ;
390 break;
391 default:
392 return -EINVAL;
393 }
394 break;
395
396 case USB_RECIP_ENDPOINT:
397 switch (wValue) {
398 case USB_ENDPOINT_HALT:
399
400 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
401 if (!dep)
402 return -EINVAL;
403 ret = __dwc3_gadget_ep_set_halt(dep, set);
404 if (ret)
405 return -EINVAL;
406 break;
407 default:
408 return -EINVAL;
409 }
410 break;
411
412 default:
413 return -EINVAL;
414 };
415
416 return 0;
417}
418
419static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
420{
421 u32 addr;
422 u32 reg;
423
424 addr = le16_to_cpu(ctrl->wValue);
425 if (addr > 127)
426 return -EINVAL;
427
428 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
429 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
430 reg |= DWC3_DCFG_DEVADDR(addr);
431 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
432
433 if (addr)
434 dwc->dev_state = DWC3_ADDRESS_STATE;
435 else
436 dwc->dev_state = DWC3_DEFAULT_STATE;
437
438 return 0;
439}
440
441static int dwc3_ep0_delegate_req(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
442{
443 int ret;
444
445 spin_unlock(&dwc->lock);
446 ret = dwc->gadget_driver->setup(&dwc->gadget, ctrl);
447 spin_lock(&dwc->lock);
448 return ret;
449}
450
451static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
452{
453 u32 cfg;
454 int ret;
455
456 dwc->start_config_issued = false;
457 cfg = le16_to_cpu(ctrl->wValue);
458
459 switch (dwc->dev_state) {
460 case DWC3_DEFAULT_STATE:
461 return -EINVAL;
462 break;
463
464 case DWC3_ADDRESS_STATE:
465 ret = dwc3_ep0_delegate_req(dwc, ctrl);
466 /* if the cfg matches and the cfg is non zero */
467 if (!ret && cfg)
468 dwc->dev_state = DWC3_CONFIGURED_STATE;
469 break;
470
471 case DWC3_CONFIGURED_STATE:
472 ret = dwc3_ep0_delegate_req(dwc, ctrl);
473 if (!cfg)
474 dwc->dev_state = DWC3_ADDRESS_STATE;
475 break;
476 }
477 return 0;
478}
479
480static int dwc3_ep0_std_request(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
481{
482 int ret;
483
484 switch (ctrl->bRequest) {
485 case USB_REQ_GET_STATUS:
486 dev_vdbg(dwc->dev, "USB_REQ_GET_STATUS\n");
487 ret = dwc3_ep0_handle_status(dwc, ctrl);
488 break;
489 case USB_REQ_CLEAR_FEATURE:
490 dev_vdbg(dwc->dev, "USB_REQ_CLEAR_FEATURE\n");
491 ret = dwc3_ep0_handle_feature(dwc, ctrl, 0);
492 break;
493 case USB_REQ_SET_FEATURE:
494 dev_vdbg(dwc->dev, "USB_REQ_SET_FEATURE\n");
495 ret = dwc3_ep0_handle_feature(dwc, ctrl, 1);
496 break;
497 case USB_REQ_SET_ADDRESS:
498 dev_vdbg(dwc->dev, "USB_REQ_SET_ADDRESS\n");
499 ret = dwc3_ep0_set_address(dwc, ctrl);
500 break;
501 case USB_REQ_SET_CONFIGURATION:
502 dev_vdbg(dwc->dev, "USB_REQ_SET_CONFIGURATION\n");
503 ret = dwc3_ep0_set_config(dwc, ctrl);
504 break;
505 default:
506 dev_vdbg(dwc->dev, "Forwarding to gadget driver\n");
507 ret = dwc3_ep0_delegate_req(dwc, ctrl);
508 break;
509 };
510
511 return ret;
512}
513
514static void dwc3_ep0_inspect_setup(struct dwc3 *dwc,
515 const struct dwc3_event_depevt *event)
516{
517 struct usb_ctrlrequest *ctrl = dwc->ctrl_req;
518 int ret;
519 u32 len;
520
521 if (!dwc->gadget_driver)
522 goto err;
523
524 len = le16_to_cpu(ctrl->wLength);
525 if (!len) {
526 dwc->three_stage_setup = false;
527 dwc->ep0_expect_in = false;
528 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
529 } else {
530 dwc->three_stage_setup = true;
531 dwc->ep0_expect_in = !!(ctrl->bRequestType & USB_DIR_IN);
532 dwc->ep0_next_event = DWC3_EP0_NRDY_DATA;
533 }
534
535 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD)
536 ret = dwc3_ep0_std_request(dwc, ctrl);
537 else
538 ret = dwc3_ep0_delegate_req(dwc, ctrl);
539
540 if (ret >= 0)
541 return;
542
543err:
544 dwc3_ep0_stall_and_restart(dwc);
545}
546
547static void dwc3_ep0_complete_data(struct dwc3 *dwc,
548 const struct dwc3_event_depevt *event)
549{
550 struct dwc3_request *r = NULL;
551 struct usb_request *ur;
552 struct dwc3_trb trb;
553 struct dwc3_ep *dep;
554 u32 transferred;
555 u8 epnum;
556
557 epnum = event->endpoint_number;
558 dep = dwc->eps[epnum];
559
560 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
561
562 if (!dwc->ep0_status_pending) {
563 r = next_request(&dwc->eps[0]->request_list);
564 ur = &r->request;
565 } else {
566 ur = &dwc->ep0_usb_req;
567 dwc->ep0_status_pending = 0;
568 }
569
570 dwc3_trb_to_nat(dwc->ep0_trb, &trb);
571
572 if (dwc->ep0_bounced) {
573 struct dwc3_ep *ep0 = dwc->eps[0];
574
575 transferred = min_t(u32, ur->length,
576 ep0->endpoint.maxpacket - trb.length);
577 memcpy(ur->buf, dwc->ep0_bounce, transferred);
578 dwc->ep0_bounced = false;
579 } else {
580 transferred = ur->length - trb.length;
581 ur->actual += transferred;
582 }
583
584 if ((epnum & 1) && ur->actual < ur->length) {
585 /* for some reason we did not get everything out */
586
587 dwc3_ep0_stall_and_restart(dwc);
588 } else {
589 /*
590 * handle the case where we have to send a zero packet. This
591 * seems to be case when req.length > maxpacket. Could it be?
592 */
593 if (r)
594 dwc3_gadget_giveback(dep, r, 0);
595 }
596}
597
598static void dwc3_ep0_complete_req(struct dwc3 *dwc,
599 const struct dwc3_event_depevt *event)
600{
601 struct dwc3_request *r;
602 struct dwc3_ep *dep;
603
604 dep = dwc->eps[0];
605
606 if (!list_empty(&dep->request_list)) {
607 r = next_request(&dep->request_list);
608
609 dwc3_gadget_giveback(dep, r, 0);
610 }
611
612 dwc->ep0state = EP0_SETUP_PHASE;
613 dwc3_ep0_out_start(dwc);
614}
615
616static void dwc3_ep0_xfer_complete(struct dwc3 *dwc,
617 const struct dwc3_event_depevt *event)
618{
619 struct dwc3_ep *dep = dwc->eps[event->endpoint_number];
620
621 dep->flags &= ~DWC3_EP_BUSY;
622
623 switch (dwc->ep0state) {
624 case EP0_SETUP_PHASE:
625 dev_vdbg(dwc->dev, "Inspecting Setup Bytes\n");
626 dwc3_ep0_inspect_setup(dwc, event);
627 break;
628
629 case EP0_DATA_PHASE:
630 dev_vdbg(dwc->dev, "Data Phase\n");
631 dwc3_ep0_complete_data(dwc, event);
632 break;
633
634 case EP0_STATUS_PHASE:
635 dev_vdbg(dwc->dev, "Status Phase\n");
636 dwc3_ep0_complete_req(dwc, event);
637 break;
638 default:
639 WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state);
640 }
641}
642
643static void dwc3_ep0_do_control_setup(struct dwc3 *dwc,
644 const struct dwc3_event_depevt *event)
645{
646 dwc->ep0state = EP0_SETUP_PHASE;
647 dwc3_ep0_out_start(dwc);
648}
649
650static void dwc3_ep0_do_control_data(struct dwc3 *dwc,
651 const struct dwc3_event_depevt *event)
652{
653 struct dwc3_ep *dep;
654 struct dwc3_request *req;
655 int ret;
656
657 dep = dwc->eps[0];
658 dwc->ep0state = EP0_DATA_PHASE;
659
660 if (dwc->ep0_status_pending) {
661 dwc3_ep0_send_status_response(dwc);
662 return;
663 }
664
665 if (list_empty(&dep->request_list)) {
666 dev_vdbg(dwc->dev, "pending request for EP0 Data phase\n");
667 dep->flags |= DWC3_EP_PENDING_REQUEST;
668
669 if (event->endpoint_number)
670 dep->flags |= DWC3_EP0_DIR_IN;
671 return;
672 }
673
674 req = next_request(&dep->request_list);
675 req->direction = !!event->endpoint_number;
676
677 dwc->ep0state = EP0_DATA_PHASE;
678 if (req->request.length == 0) {
679 ret = dwc3_ep0_start_trans(dwc, event->endpoint_number,
680 dwc->ctrl_req_addr, 0,
681 DWC3_TRBCTL_CONTROL_DATA);
682 } else if ((req->request.length % dep->endpoint.maxpacket)
683 && (event->endpoint_number == 0)) {
684 dwc3_map_buffer_to_dma(req);
685
686 WARN_ON(req->request.length > dep->endpoint.maxpacket);
687
688 dwc->ep0_bounced = true;
689
690 /*
691 * REVISIT in case request length is bigger than EP0
692 * wMaxPacketSize, we will need two chained TRBs to handle
693 * the transfer.
694 */
695 ret = dwc3_ep0_start_trans(dwc, event->endpoint_number,
696 dwc->ep0_bounce_addr, dep->endpoint.maxpacket,
697 DWC3_TRBCTL_CONTROL_DATA);
698 } else {
699 dwc3_map_buffer_to_dma(req);
700
701 ret = dwc3_ep0_start_trans(dwc, event->endpoint_number,
702 req->request.dma, req->request.length,
703 DWC3_TRBCTL_CONTROL_DATA);
704 }
705
706 WARN_ON(ret < 0);
707}
708
709static void dwc3_ep0_do_control_status(struct dwc3 *dwc,
710 const struct dwc3_event_depevt *event)
711{
712 u32 type;
713 int ret;
714
715 dwc->ep0state = EP0_STATUS_PHASE;
716
717 type = dwc->three_stage_setup ? DWC3_TRBCTL_CONTROL_STATUS3
718 : DWC3_TRBCTL_CONTROL_STATUS2;
719
720 ret = dwc3_ep0_start_trans(dwc, event->endpoint_number,
721 dwc->ctrl_req_addr, 0, type);
722
723 WARN_ON(ret < 0);
724}
725
726static void dwc3_ep0_xfernotready(struct dwc3 *dwc,
727 const struct dwc3_event_depevt *event)
728{
729 switch (event->status) {
730 case DEPEVT_STATUS_CONTROL_SETUP:
731 dev_vdbg(dwc->dev, "Control Setup\n");
732 dwc3_ep0_do_control_setup(dwc, event);
733 break;
734
735 case DEPEVT_STATUS_CONTROL_DATA:
736 dev_vdbg(dwc->dev, "Control Data\n");
737
738 if (dwc->ep0_next_event != DWC3_EP0_NRDY_DATA) {
739 dev_vdbg(dwc->dev, "Expected %d got %d\n",
740 dwc->ep0_next_event,
741 DWC3_EP0_NRDY_DATA);
742
743 dwc3_ep0_stall_and_restart(dwc);
744 return;
745 }
746
747 /*
748 * One of the possible error cases is when Host _does_
749 * request for Data Phase, but it does so on the wrong
750 * direction.
751 *
752 * Here, we already know ep0_next_event is DATA (see above),
753 * so we only need to check for direction.
754 */
755 if (dwc->ep0_expect_in != event->endpoint_number) {
756 dev_vdbg(dwc->dev, "Wrong direction for Data phase\n");
757 dwc3_ep0_stall_and_restart(dwc);
758 return;
759 }
760
761 dwc3_ep0_do_control_data(dwc, event);
762 break;
763
764 case DEPEVT_STATUS_CONTROL_STATUS:
765 dev_vdbg(dwc->dev, "Control Status\n");
766
767 if (dwc->ep0_next_event != DWC3_EP0_NRDY_STATUS) {
768 dev_vdbg(dwc->dev, "Expected %d got %d\n",
769 dwc->ep0_next_event,
770 DWC3_EP0_NRDY_STATUS);
771
772 dwc3_ep0_stall_and_restart(dwc);
773 return;
774 }
775 dwc3_ep0_do_control_status(dwc, event);
776 }
777}
778
779void dwc3_ep0_interrupt(struct dwc3 *dwc,
780 const const struct dwc3_event_depevt *event)
781{
782 u8 epnum = event->endpoint_number;
783
784 dev_dbg(dwc->dev, "%s while ep%d%s in state '%s'\n",
785 dwc3_ep_event_string(event->endpoint_event),
786 epnum >> 1, (epnum & 1) ? "in" : "out",
787 dwc3_ep0_state_string(dwc->ep0state));
788
789 switch (event->endpoint_event) {
790 case DWC3_DEPEVT_XFERCOMPLETE:
791 dwc3_ep0_xfer_complete(dwc, event);
792 break;
793
794 case DWC3_DEPEVT_XFERNOTREADY:
795 dwc3_ep0_xfernotready(dwc, event);
796 break;
797
798 case DWC3_DEPEVT_XFERINPROGRESS:
799 case DWC3_DEPEVT_RXTXFIFOEVT:
800 case DWC3_DEPEVT_STREAMEVT:
801 case DWC3_DEPEVT_EPCMDCMPLT:
802 break;
803 }
804}
diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c
new file mode 100644
index 000000000000..25dbd8614e72
--- /dev/null
+++ b/drivers/usb/dwc3/gadget.c
@@ -0,0 +1,2105 @@
1/**
2 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
3 *
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
5 *
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions, and the following disclaimer,
14 * without modification.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. The names of the above-listed copyright holders may not be used
19 * to endorse or promote products derived from this software without
20 * specific prior written permission.
21 *
22 * ALTERNATIVELY, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2, as published by the Free
24 * Software Foundation.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
27 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
28 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
30 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
31 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
32 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
33 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
34 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
35 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
36 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 */
38
39#include <linux/kernel.h>
40#include <linux/delay.h>
41#include <linux/slab.h>
42#include <linux/spinlock.h>
43#include <linux/platform_device.h>
44#include <linux/pm_runtime.h>
45#include <linux/interrupt.h>
46#include <linux/io.h>
47#include <linux/list.h>
48#include <linux/dma-mapping.h>
49
50#include <linux/usb/ch9.h>
51#include <linux/usb/gadget.h>
52
53#include "core.h"
54#include "gadget.h"
55#include "io.h"
56
57#define DMA_ADDR_INVALID (~(dma_addr_t)0)
58
59void dwc3_map_buffer_to_dma(struct dwc3_request *req)
60{
61 struct dwc3 *dwc = req->dep->dwc;
62
63 if (req->request.length == 0) {
64 /* req->request.dma = dwc->setup_buf_addr; */
65 return;
66 }
67
68 if (req->request.dma == DMA_ADDR_INVALID) {
69 req->request.dma = dma_map_single(dwc->dev, req->request.buf,
70 req->request.length, req->direction
71 ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
72 req->mapped = true;
73 }
74}
75
76void dwc3_unmap_buffer_from_dma(struct dwc3_request *req)
77{
78 struct dwc3 *dwc = req->dep->dwc;
79
80 if (req->request.length == 0) {
81 req->request.dma = DMA_ADDR_INVALID;
82 return;
83 }
84
85 if (req->mapped) {
86 dma_unmap_single(dwc->dev, req->request.dma,
87 req->request.length, req->direction
88 ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
89 req->mapped = 0;
90 req->request.dma = DMA_ADDR_INVALID;
91 }
92}
93
94void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
95 int status)
96{
97 struct dwc3 *dwc = dep->dwc;
98
99 if (req->queued) {
100 dep->busy_slot++;
101 /*
102 * Skip LINK TRB. We can't use req->trb and check for
103 * DWC3_TRBCTL_LINK_TRB because it points the TRB we just
104 * completed (not the LINK TRB).
105 */
106 if (((dep->busy_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) &&
107 usb_endpoint_xfer_isoc(dep->desc))
108 dep->busy_slot++;
109 }
110 list_del(&req->list);
111
112 if (req->request.status == -EINPROGRESS)
113 req->request.status = status;
114
115 dwc3_unmap_buffer_from_dma(req);
116
117 dev_dbg(dwc->dev, "request %p from %s completed %d/%d ===> %d\n",
118 req, dep->name, req->request.actual,
119 req->request.length, status);
120
121 spin_unlock(&dwc->lock);
122 req->request.complete(&req->dep->endpoint, &req->request);
123 spin_lock(&dwc->lock);
124}
125
126static const char *dwc3_gadget_ep_cmd_string(u8 cmd)
127{
128 switch (cmd) {
129 case DWC3_DEPCMD_DEPSTARTCFG:
130 return "Start New Configuration";
131 case DWC3_DEPCMD_ENDTRANSFER:
132 return "End Transfer";
133 case DWC3_DEPCMD_UPDATETRANSFER:
134 return "Update Transfer";
135 case DWC3_DEPCMD_STARTTRANSFER:
136 return "Start Transfer";
137 case DWC3_DEPCMD_CLEARSTALL:
138 return "Clear Stall";
139 case DWC3_DEPCMD_SETSTALL:
140 return "Set Stall";
141 case DWC3_DEPCMD_GETSEQNUMBER:
142 return "Get Data Sequence Number";
143 case DWC3_DEPCMD_SETTRANSFRESOURCE:
144 return "Set Endpoint Transfer Resource";
145 case DWC3_DEPCMD_SETEPCONFIG:
146 return "Set Endpoint Configuration";
147 default:
148 return "UNKNOWN command";
149 }
150}
151
152int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep,
153 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params)
154{
155 struct dwc3_ep *dep = dwc->eps[ep];
156 u32 timeout = 500;
157 u32 reg;
158
159 dev_vdbg(dwc->dev, "%s: cmd '%s' params %08x %08x %08x\n",
160 dep->name,
161 dwc3_gadget_ep_cmd_string(cmd), params->param0,
162 params->param1, params->param2);
163
164 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR0(ep), params->param0);
165 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR1(ep), params->param1);
166 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR2(ep), params->param2);
167
168 dwc3_writel(dwc->regs, DWC3_DEPCMD(ep), cmd | DWC3_DEPCMD_CMDACT);
169 do {
170 reg = dwc3_readl(dwc->regs, DWC3_DEPCMD(ep));
171 if (!(reg & DWC3_DEPCMD_CMDACT)) {
172 dev_vdbg(dwc->dev, "Command Complete --> %d\n",
173 DWC3_DEPCMD_STATUS(reg));
174 return 0;
175 }
176
177 /*
178 * We can't sleep here, because it is also called from
179 * interrupt context.
180 */
181 timeout--;
182 if (!timeout)
183 return -ETIMEDOUT;
184
185 udelay(1);
186 } while (1);
187}
188
189static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
190 struct dwc3_trb_hw *trb)
191{
192 u32 offset = (char *) trb - (char *) dep->trb_pool;
193
194 return dep->trb_pool_dma + offset;
195}
196
197static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
198{
199 struct dwc3 *dwc = dep->dwc;
200
201 if (dep->trb_pool)
202 return 0;
203
204 if (dep->number == 0 || dep->number == 1)
205 return 0;
206
207 dep->trb_pool = dma_alloc_coherent(dwc->dev,
208 sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
209 &dep->trb_pool_dma, GFP_KERNEL);
210 if (!dep->trb_pool) {
211 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
212 dep->name);
213 return -ENOMEM;
214 }
215
216 return 0;
217}
218
219static void dwc3_free_trb_pool(struct dwc3_ep *dep)
220{
221 struct dwc3 *dwc = dep->dwc;
222
223 dma_free_coherent(dwc->dev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
224 dep->trb_pool, dep->trb_pool_dma);
225
226 dep->trb_pool = NULL;
227 dep->trb_pool_dma = 0;
228}
229
230static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep)
231{
232 struct dwc3_gadget_ep_cmd_params params;
233 u32 cmd;
234
235 memset(&params, 0x00, sizeof(params));
236
237 if (dep->number != 1) {
238 cmd = DWC3_DEPCMD_DEPSTARTCFG;
239 /* XferRscIdx == 0 for ep0 and 2 for the remaining */
240 if (dep->number > 1) {
241 if (dwc->start_config_issued)
242 return 0;
243 dwc->start_config_issued = true;
244 cmd |= DWC3_DEPCMD_PARAM(2);
245 }
246
247 return dwc3_send_gadget_ep_cmd(dwc, 0, cmd, &params);
248 }
249
250 return 0;
251}
252
253static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep,
254 const struct usb_endpoint_descriptor *desc)
255{
256 struct dwc3_gadget_ep_cmd_params params;
257
258 memset(&params, 0x00, sizeof(params));
259
260 params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
261 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc))
262 | DWC3_DEPCFG_BURST_SIZE(dep->endpoint.maxburst);
263
264 params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN
265 | DWC3_DEPCFG_XFER_NOT_READY_EN;
266
267 if (usb_endpoint_xfer_bulk(desc) && dep->endpoint.max_streams) {
268 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
269 | DWC3_DEPCFG_STREAM_EVENT_EN;
270 dep->stream_capable = true;
271 }
272
273 if (usb_endpoint_xfer_isoc(desc))
274 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
275
276 /*
277 * We are doing 1:1 mapping for endpoints, meaning
278 * Physical Endpoints 2 maps to Logical Endpoint 2 and
279 * so on. We consider the direction bit as part of the physical
280 * endpoint number. So USB endpoint 0x81 is 0x03.
281 */
282 params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
283
284 /*
285 * We must use the lower 16 TX FIFOs even though
286 * HW might have more
287 */
288 if (dep->direction)
289 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
290
291 if (desc->bInterval) {
292 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1);
293 dep->interval = 1 << (desc->bInterval - 1);
294 }
295
296 return dwc3_send_gadget_ep_cmd(dwc, dep->number,
297 DWC3_DEPCMD_SETEPCONFIG, &params);
298}
299
300static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep)
301{
302 struct dwc3_gadget_ep_cmd_params params;
303
304 memset(&params, 0x00, sizeof(params));
305
306 params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
307
308 return dwc3_send_gadget_ep_cmd(dwc, dep->number,
309 DWC3_DEPCMD_SETTRANSFRESOURCE, &params);
310}
311
312/**
313 * __dwc3_gadget_ep_enable - Initializes a HW endpoint
314 * @dep: endpoint to be initialized
315 * @desc: USB Endpoint Descriptor
316 *
317 * Caller should take care of locking
318 */
319static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep,
320 const struct usb_endpoint_descriptor *desc)
321{
322 struct dwc3 *dwc = dep->dwc;
323 u32 reg;
324 int ret = -ENOMEM;
325
326 if (!(dep->flags & DWC3_EP_ENABLED)) {
327 ret = dwc3_gadget_start_config(dwc, dep);
328 if (ret)
329 return ret;
330 }
331
332 ret = dwc3_gadget_set_ep_config(dwc, dep, desc);
333 if (ret)
334 return ret;
335
336 if (!(dep->flags & DWC3_EP_ENABLED)) {
337 struct dwc3_trb_hw *trb_st_hw;
338 struct dwc3_trb_hw *trb_link_hw;
339 struct dwc3_trb trb_link;
340
341 ret = dwc3_gadget_set_xfer_resource(dwc, dep);
342 if (ret)
343 return ret;
344
345 dep->desc = desc;
346 dep->type = usb_endpoint_type(desc);
347 dep->flags |= DWC3_EP_ENABLED;
348
349 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
350 reg |= DWC3_DALEPENA_EP(dep->number);
351 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
352
353 if (!usb_endpoint_xfer_isoc(desc))
354 return 0;
355
356 memset(&trb_link, 0, sizeof(trb_link));
357
358 /* Link TRB for ISOC. The HWO but is never reset */
359 trb_st_hw = &dep->trb_pool[0];
360
361 trb_link.bplh = dwc3_trb_dma_offset(dep, trb_st_hw);
362 trb_link.trbctl = DWC3_TRBCTL_LINK_TRB;
363 trb_link.hwo = true;
364
365 trb_link_hw = &dep->trb_pool[DWC3_TRB_NUM - 1];
366 dwc3_trb_to_hw(&trb_link, trb_link_hw);
367 }
368
369 return 0;
370}
371
372static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum);
373static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
374{
375 struct dwc3_request *req;
376
377 if (!list_empty(&dep->req_queued))
378 dwc3_stop_active_transfer(dwc, dep->number);
379
380 while (!list_empty(&dep->request_list)) {
381 req = next_request(&dep->request_list);
382
383 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
384 }
385}
386
387/**
388 * __dwc3_gadget_ep_disable - Disables a HW endpoint
389 * @dep: the endpoint to disable
390 *
391 * This function also removes requests which are currently processed ny the
392 * hardware and those which are not yet scheduled.
393 * Caller should take care of locking.
394 */
395static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
396{
397 struct dwc3 *dwc = dep->dwc;
398 u32 reg;
399
400 dwc3_remove_requests(dwc, dep);
401
402 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
403 reg &= ~DWC3_DALEPENA_EP(dep->number);
404 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
405
406 dep->stream_capable = false;
407 dep->desc = NULL;
408 dep->type = 0;
409 dep->flags = 0;
410
411 return 0;
412}
413
414/* -------------------------------------------------------------------------- */
415
416static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
417 const struct usb_endpoint_descriptor *desc)
418{
419 return -EINVAL;
420}
421
422static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
423{
424 return -EINVAL;
425}
426
427/* -------------------------------------------------------------------------- */
428
429static int dwc3_gadget_ep_enable(struct usb_ep *ep,
430 const struct usb_endpoint_descriptor *desc)
431{
432 struct dwc3_ep *dep;
433 struct dwc3 *dwc;
434 unsigned long flags;
435 int ret;
436
437 if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
438 pr_debug("dwc3: invalid parameters\n");
439 return -EINVAL;
440 }
441
442 if (!desc->wMaxPacketSize) {
443 pr_debug("dwc3: missing wMaxPacketSize\n");
444 return -EINVAL;
445 }
446
447 dep = to_dwc3_ep(ep);
448 dwc = dep->dwc;
449
450 switch (usb_endpoint_type(desc)) {
451 case USB_ENDPOINT_XFER_CONTROL:
452 strncat(dep->name, "-control", sizeof(dep->name));
453 break;
454 case USB_ENDPOINT_XFER_ISOC:
455 strncat(dep->name, "-isoc", sizeof(dep->name));
456 break;
457 case USB_ENDPOINT_XFER_BULK:
458 strncat(dep->name, "-bulk", sizeof(dep->name));
459 break;
460 case USB_ENDPOINT_XFER_INT:
461 strncat(dep->name, "-int", sizeof(dep->name));
462 break;
463 default:
464 dev_err(dwc->dev, "invalid endpoint transfer type\n");
465 }
466
467 if (dep->flags & DWC3_EP_ENABLED) {
468 dev_WARN_ONCE(dwc->dev, true, "%s is already enabled\n",
469 dep->name);
470 return 0;
471 }
472
473 dev_vdbg(dwc->dev, "Enabling %s\n", dep->name);
474
475 spin_lock_irqsave(&dwc->lock, flags);
476 ret = __dwc3_gadget_ep_enable(dep, desc);
477 spin_unlock_irqrestore(&dwc->lock, flags);
478
479 return ret;
480}
481
482static int dwc3_gadget_ep_disable(struct usb_ep *ep)
483{
484 struct dwc3_ep *dep;
485 struct dwc3 *dwc;
486 unsigned long flags;
487 int ret;
488
489 if (!ep) {
490 pr_debug("dwc3: invalid parameters\n");
491 return -EINVAL;
492 }
493
494 dep = to_dwc3_ep(ep);
495 dwc = dep->dwc;
496
497 if (!(dep->flags & DWC3_EP_ENABLED)) {
498 dev_WARN_ONCE(dwc->dev, true, "%s is already disabled\n",
499 dep->name);
500 return 0;
501 }
502
503 snprintf(dep->name, sizeof(dep->name), "ep%d%s",
504 dep->number >> 1,
505 (dep->number & 1) ? "in" : "out");
506
507 spin_lock_irqsave(&dwc->lock, flags);
508 ret = __dwc3_gadget_ep_disable(dep);
509 spin_unlock_irqrestore(&dwc->lock, flags);
510
511 return ret;
512}
513
514static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
515 gfp_t gfp_flags)
516{
517 struct dwc3_request *req;
518 struct dwc3_ep *dep = to_dwc3_ep(ep);
519 struct dwc3 *dwc = dep->dwc;
520
521 req = kzalloc(sizeof(*req), gfp_flags);
522 if (!req) {
523 dev_err(dwc->dev, "not enough memory\n");
524 return NULL;
525 }
526
527 req->epnum = dep->number;
528 req->dep = dep;
529 req->request.dma = DMA_ADDR_INVALID;
530
531 return &req->request;
532}
533
534static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
535 struct usb_request *request)
536{
537 struct dwc3_request *req = to_dwc3_request(request);
538
539 kfree(req);
540}
541
542/*
543 * dwc3_prepare_trbs - setup TRBs from requests
544 * @dep: endpoint for which requests are being prepared
545 * @starting: true if the endpoint is idle and no requests are queued.
546 *
547 * The functions goes through the requests list and setups TRBs for the
548 * transfers. The functions returns once there are not more TRBs available or
549 * it run out of requests.
550 */
551static struct dwc3_request *dwc3_prepare_trbs(struct dwc3_ep *dep,
552 bool starting)
553{
554 struct dwc3_request *req, *n, *ret = NULL;
555 struct dwc3_trb_hw *trb_hw;
556 struct dwc3_trb trb;
557 u32 trbs_left;
558
559 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
560
561 /* the first request must not be queued */
562 trbs_left = (dep->busy_slot - dep->free_slot) & DWC3_TRB_MASK;
563 /*
564 * if busy & slot are equal than it is either full or empty. If we are
565 * starting to proceed requests then we are empty. Otherwise we ar
566 * full and don't do anything
567 */
568 if (!trbs_left) {
569 if (!starting)
570 return NULL;
571 trbs_left = DWC3_TRB_NUM;
572 /*
573 * In case we start from scratch, we queue the ISOC requests
574 * starting from slot 1. This is done because we use ring
575 * buffer and have no LST bit to stop us. Instead, we place
576 * IOC bit TRB_NUM/4. We try to avoid to having an interrupt
577 * after the first request so we start at slot 1 and have
578 * 7 requests proceed before we hit the first IOC.
579 * Other transfer types don't use the ring buffer and are
580 * processed from the first TRB until the last one. Since we
581 * don't wrap around we have to start at the beginning.
582 */
583 if (usb_endpoint_xfer_isoc(dep->desc)) {
584 dep->busy_slot = 1;
585 dep->free_slot = 1;
586 } else {
587 dep->busy_slot = 0;
588 dep->free_slot = 0;
589 }
590 }
591
592 /* The last TRB is a link TRB, not used for xfer */
593 if ((trbs_left <= 1) && usb_endpoint_xfer_isoc(dep->desc))
594 return NULL;
595
596 list_for_each_entry_safe(req, n, &dep->request_list, list) {
597 unsigned int last_one = 0;
598 unsigned int cur_slot;
599
600 trb_hw = &dep->trb_pool[dep->free_slot & DWC3_TRB_MASK];
601 cur_slot = dep->free_slot;
602 dep->free_slot++;
603
604 /* Skip the LINK-TRB on ISOC */
605 if (((cur_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) &&
606 usb_endpoint_xfer_isoc(dep->desc))
607 continue;
608
609 dwc3_gadget_move_request_queued(req);
610 memset(&trb, 0, sizeof(trb));
611 trbs_left--;
612
613 /* Is our TRB pool empty? */
614 if (!trbs_left)
615 last_one = 1;
616 /* Is this the last request? */
617 if (list_empty(&dep->request_list))
618 last_one = 1;
619
620 /*
621 * FIXME we shouldn't need to set LST bit always but we are
622 * facing some weird problem with the Hardware where it doesn't
623 * complete even though it has been previously started.
624 *
625 * While we're debugging the problem, as a workaround to
626 * multiple TRBs handling, use only one TRB at a time.
627 */
628 last_one = 1;
629
630 req->trb = trb_hw;
631 if (!ret)
632 ret = req;
633
634 trb.bplh = req->request.dma;
635
636 if (usb_endpoint_xfer_isoc(dep->desc)) {
637 trb.isp_imi = true;
638 trb.csp = true;
639 } else {
640 trb.lst = last_one;
641 }
642
643 if (usb_endpoint_xfer_bulk(dep->desc) && dep->stream_capable)
644 trb.sid_sofn = req->request.stream_id;
645
646 switch (usb_endpoint_type(dep->desc)) {
647 case USB_ENDPOINT_XFER_CONTROL:
648 trb.trbctl = DWC3_TRBCTL_CONTROL_SETUP;
649 break;
650
651 case USB_ENDPOINT_XFER_ISOC:
652 trb.trbctl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
653
654 /* IOC every DWC3_TRB_NUM / 4 so we can refill */
655 if (!(cur_slot % (DWC3_TRB_NUM / 4)))
656 trb.ioc = last_one;
657 break;
658
659 case USB_ENDPOINT_XFER_BULK:
660 case USB_ENDPOINT_XFER_INT:
661 trb.trbctl = DWC3_TRBCTL_NORMAL;
662 break;
663 default:
664 /*
665 * This is only possible with faulty memory because we
666 * checked it already :)
667 */
668 BUG();
669 }
670
671 trb.length = req->request.length;
672 trb.hwo = true;
673
674 dwc3_trb_to_hw(&trb, trb_hw);
675 req->trb_dma = dwc3_trb_dma_offset(dep, trb_hw);
676
677 if (last_one)
678 break;
679 }
680
681 return ret;
682}
683
684static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param,
685 int start_new)
686{
687 struct dwc3_gadget_ep_cmd_params params;
688 struct dwc3_request *req;
689 struct dwc3 *dwc = dep->dwc;
690 int ret;
691 u32 cmd;
692
693 if (start_new && (dep->flags & DWC3_EP_BUSY)) {
694 dev_vdbg(dwc->dev, "%s: endpoint busy\n", dep->name);
695 return -EBUSY;
696 }
697 dep->flags &= ~DWC3_EP_PENDING_REQUEST;
698
699 /*
700 * If we are getting here after a short-out-packet we don't enqueue any
701 * new requests as we try to set the IOC bit only on the last request.
702 */
703 if (start_new) {
704 if (list_empty(&dep->req_queued))
705 dwc3_prepare_trbs(dep, start_new);
706
707 /* req points to the first request which will be sent */
708 req = next_request(&dep->req_queued);
709 } else {
710 /*
711 * req points to the first request where HWO changed
712 * from 0 to 1
713 */
714 req = dwc3_prepare_trbs(dep, start_new);
715 }
716 if (!req) {
717 dep->flags |= DWC3_EP_PENDING_REQUEST;
718 return 0;
719 }
720
721 memset(&params, 0, sizeof(params));
722 params.param0 = upper_32_bits(req->trb_dma);
723 params.param1 = lower_32_bits(req->trb_dma);
724
725 if (start_new)
726 cmd = DWC3_DEPCMD_STARTTRANSFER;
727 else
728 cmd = DWC3_DEPCMD_UPDATETRANSFER;
729
730 cmd |= DWC3_DEPCMD_PARAM(cmd_param);
731 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
732 if (ret < 0) {
733 dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n");
734
735 /*
736 * FIXME we need to iterate over the list of requests
737 * here and stop, unmap, free and del each of the linked
738 * requests instead of we do now.
739 */
740 dwc3_unmap_buffer_from_dma(req);
741 list_del(&req->list);
742 return ret;
743 }
744
745 dep->flags |= DWC3_EP_BUSY;
746 dep->res_trans_idx = dwc3_gadget_ep_get_transfer_index(dwc,
747 dep->number);
748 if (!dep->res_trans_idx)
749 printk_once(KERN_ERR "%s() res_trans_idx is invalid\n", __func__);
750 return 0;
751}
752
753static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
754{
755 req->request.actual = 0;
756 req->request.status = -EINPROGRESS;
757 req->direction = dep->direction;
758 req->epnum = dep->number;
759
760 /*
761 * We only add to our list of requests now and
762 * start consuming the list once we get XferNotReady
763 * IRQ.
764 *
765 * That way, we avoid doing anything that we don't need
766 * to do now and defer it until the point we receive a
767 * particular token from the Host side.
768 *
769 * This will also avoid Host cancelling URBs due to too
770 * many NACKs.
771 */
772 dwc3_map_buffer_to_dma(req);
773 list_add_tail(&req->list, &dep->request_list);
774
775 /*
776 * There is one special case: XferNotReady with
777 * empty list of requests. We need to kick the
778 * transfer here in that situation, otherwise
779 * we will be NAKing forever.
780 *
781 * If we get XferNotReady before gadget driver
782 * has a chance to queue a request, we will ACK
783 * the IRQ but won't be able to receive the data
784 * until the next request is queued. The following
785 * code is handling exactly that.
786 */
787 if (dep->flags & DWC3_EP_PENDING_REQUEST) {
788 int ret;
789 int start_trans;
790
791 start_trans = 1;
792 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
793 dep->flags & DWC3_EP_BUSY)
794 start_trans = 0;
795
796 ret = __dwc3_gadget_kick_transfer(dep, 0, start_trans);
797 if (ret && ret != -EBUSY) {
798 struct dwc3 *dwc = dep->dwc;
799
800 dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
801 dep->name);
802 }
803 };
804
805 return 0;
806}
807
808static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
809 gfp_t gfp_flags)
810{
811 struct dwc3_request *req = to_dwc3_request(request);
812 struct dwc3_ep *dep = to_dwc3_ep(ep);
813 struct dwc3 *dwc = dep->dwc;
814
815 unsigned long flags;
816
817 int ret;
818
819 if (!dep->desc) {
820 dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n",
821 request, ep->name);
822 return -ESHUTDOWN;
823 }
824
825 dev_vdbg(dwc->dev, "queing request %p to %s length %d\n",
826 request, ep->name, request->length);
827
828 spin_lock_irqsave(&dwc->lock, flags);
829 ret = __dwc3_gadget_ep_queue(dep, req);
830 spin_unlock_irqrestore(&dwc->lock, flags);
831
832 return ret;
833}
834
835static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
836 struct usb_request *request)
837{
838 struct dwc3_request *req = to_dwc3_request(request);
839 struct dwc3_request *r = NULL;
840
841 struct dwc3_ep *dep = to_dwc3_ep(ep);
842 struct dwc3 *dwc = dep->dwc;
843
844 unsigned long flags;
845 int ret = 0;
846
847 spin_lock_irqsave(&dwc->lock, flags);
848
849 list_for_each_entry(r, &dep->request_list, list) {
850 if (r == req)
851 break;
852 }
853
854 if (r != req) {
855 list_for_each_entry(r, &dep->req_queued, list) {
856 if (r == req)
857 break;
858 }
859 if (r == req) {
860 /* wait until it is processed */
861 dwc3_stop_active_transfer(dwc, dep->number);
862 goto out0;
863 }
864 dev_err(dwc->dev, "request %p was not queued to %s\n",
865 request, ep->name);
866 ret = -EINVAL;
867 goto out0;
868 }
869
870 /* giveback the request */
871 dwc3_gadget_giveback(dep, req, -ECONNRESET);
872
873out0:
874 spin_unlock_irqrestore(&dwc->lock, flags);
875
876 return ret;
877}
878
879int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value)
880{
881 struct dwc3_gadget_ep_cmd_params params;
882 struct dwc3 *dwc = dep->dwc;
883 int ret;
884
885 memset(&params, 0x00, sizeof(params));
886
887 if (value) {
888 if (dep->number == 0 || dep->number == 1) {
889 /*
890 * Whenever EP0 is stalled, we will restart
891 * the state machine, thus moving back to
892 * Setup Phase
893 */
894 dwc->ep0state = EP0_SETUP_PHASE;
895 }
896
897 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
898 DWC3_DEPCMD_SETSTALL, &params);
899 if (ret)
900 dev_err(dwc->dev, "failed to %s STALL on %s\n",
901 value ? "set" : "clear",
902 dep->name);
903 else
904 dep->flags |= DWC3_EP_STALL;
905 } else {
906 if (dep->flags & DWC3_EP_WEDGE)
907 return 0;
908
909 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
910 DWC3_DEPCMD_CLEARSTALL, &params);
911 if (ret)
912 dev_err(dwc->dev, "failed to %s STALL on %s\n",
913 value ? "set" : "clear",
914 dep->name);
915 else
916 dep->flags &= ~DWC3_EP_STALL;
917 }
918
919 return ret;
920}
921
922static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
923{
924 struct dwc3_ep *dep = to_dwc3_ep(ep);
925 struct dwc3 *dwc = dep->dwc;
926
927 unsigned long flags;
928
929 int ret;
930
931 spin_lock_irqsave(&dwc->lock, flags);
932
933 if (usb_endpoint_xfer_isoc(dep->desc)) {
934 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
935 ret = -EINVAL;
936 goto out;
937 }
938
939 ret = __dwc3_gadget_ep_set_halt(dep, value);
940out:
941 spin_unlock_irqrestore(&dwc->lock, flags);
942
943 return ret;
944}
945
946static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
947{
948 struct dwc3_ep *dep = to_dwc3_ep(ep);
949
950 dep->flags |= DWC3_EP_WEDGE;
951
952 return dwc3_gadget_ep_set_halt(ep, 1);
953}
954
955/* -------------------------------------------------------------------------- */
956
957static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
958 .bLength = USB_DT_ENDPOINT_SIZE,
959 .bDescriptorType = USB_DT_ENDPOINT,
960 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
961};
962
963static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
964 .enable = dwc3_gadget_ep0_enable,
965 .disable = dwc3_gadget_ep0_disable,
966 .alloc_request = dwc3_gadget_ep_alloc_request,
967 .free_request = dwc3_gadget_ep_free_request,
968 .queue = dwc3_gadget_ep0_queue,
969 .dequeue = dwc3_gadget_ep_dequeue,
970 .set_halt = dwc3_gadget_ep_set_halt,
971 .set_wedge = dwc3_gadget_ep_set_wedge,
972};
973
974static const struct usb_ep_ops dwc3_gadget_ep_ops = {
975 .enable = dwc3_gadget_ep_enable,
976 .disable = dwc3_gadget_ep_disable,
977 .alloc_request = dwc3_gadget_ep_alloc_request,
978 .free_request = dwc3_gadget_ep_free_request,
979 .queue = dwc3_gadget_ep_queue,
980 .dequeue = dwc3_gadget_ep_dequeue,
981 .set_halt = dwc3_gadget_ep_set_halt,
982 .set_wedge = dwc3_gadget_ep_set_wedge,
983};
984
985/* -------------------------------------------------------------------------- */
986
987static int dwc3_gadget_get_frame(struct usb_gadget *g)
988{
989 struct dwc3 *dwc = gadget_to_dwc(g);
990 u32 reg;
991
992 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
993 return DWC3_DSTS_SOFFN(reg);
994}
995
996static int dwc3_gadget_wakeup(struct usb_gadget *g)
997{
998 struct dwc3 *dwc = gadget_to_dwc(g);
999
1000 unsigned long timeout;
1001 unsigned long flags;
1002
1003 u32 reg;
1004
1005 int ret = 0;
1006
1007 u8 link_state;
1008 u8 speed;
1009
1010 spin_lock_irqsave(&dwc->lock, flags);
1011
1012 /*
1013 * According to the Databook Remote wakeup request should
1014 * be issued only when the device is in early suspend state.
1015 *
1016 * We can check that via USB Link State bits in DSTS register.
1017 */
1018 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1019
1020 speed = reg & DWC3_DSTS_CONNECTSPD;
1021 if (speed == DWC3_DSTS_SUPERSPEED) {
1022 dev_dbg(dwc->dev, "no wakeup on SuperSpeed\n");
1023 ret = -EINVAL;
1024 goto out;
1025 }
1026
1027 link_state = DWC3_DSTS_USBLNKST(reg);
1028
1029 switch (link_state) {
1030 case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */
1031 case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */
1032 break;
1033 default:
1034 dev_dbg(dwc->dev, "can't wakeup from link state %d\n",
1035 link_state);
1036 ret = -EINVAL;
1037 goto out;
1038 }
1039
1040 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1041
1042 /*
1043 * Switch link state to Recovery. In HS/FS/LS this means
1044 * RemoteWakeup Request
1045 */
1046 reg |= DWC3_DCTL_ULSTCHNG_RECOVERY;
1047 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1048
1049 /* wait for at least 2000us */
1050 usleep_range(2000, 2500);
1051
1052 /* write zeroes to Link Change Request */
1053 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1054 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1055
1056 /* pool until Link State change to ON */
1057 timeout = jiffies + msecs_to_jiffies(100);
1058
1059 while (!(time_after(jiffies, timeout))) {
1060 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1061
1062 /* in HS, means ON */
1063 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1064 break;
1065 }
1066
1067 if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1068 dev_err(dwc->dev, "failed to send remote wakeup\n");
1069 ret = -EINVAL;
1070 }
1071
1072out:
1073 spin_unlock_irqrestore(&dwc->lock, flags);
1074
1075 return ret;
1076}
1077
1078static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1079 int is_selfpowered)
1080{
1081 struct dwc3 *dwc = gadget_to_dwc(g);
1082
1083 dwc->is_selfpowered = !!is_selfpowered;
1084
1085 return 0;
1086}
1087
1088static void dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on)
1089{
1090 u32 reg;
1091 u32 timeout = 500;
1092
1093 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1094 if (is_on)
1095 reg |= DWC3_DCTL_RUN_STOP;
1096 else
1097 reg &= ~DWC3_DCTL_RUN_STOP;
1098
1099 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1100
1101 do {
1102 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1103 if (is_on) {
1104 if (!(reg & DWC3_DSTS_DEVCTRLHLT))
1105 break;
1106 } else {
1107 if (reg & DWC3_DSTS_DEVCTRLHLT)
1108 break;
1109 }
1110 timeout--;
1111 if (!timeout)
1112 break;
1113 udelay(1);
1114 } while (1);
1115
1116 dev_vdbg(dwc->dev, "gadget %s data soft-%s\n",
1117 dwc->gadget_driver
1118 ? dwc->gadget_driver->function : "no-function",
1119 is_on ? "connect" : "disconnect");
1120}
1121
1122static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
1123{
1124 struct dwc3 *dwc = gadget_to_dwc(g);
1125 unsigned long flags;
1126
1127 is_on = !!is_on;
1128
1129 spin_lock_irqsave(&dwc->lock, flags);
1130 dwc3_gadget_run_stop(dwc, is_on);
1131 spin_unlock_irqrestore(&dwc->lock, flags);
1132
1133 return 0;
1134}
1135
1136static int dwc3_gadget_start(struct usb_gadget *g,
1137 struct usb_gadget_driver *driver)
1138{
1139 struct dwc3 *dwc = gadget_to_dwc(g);
1140 struct dwc3_ep *dep;
1141 unsigned long flags;
1142 int ret = 0;
1143 u32 reg;
1144
1145 spin_lock_irqsave(&dwc->lock, flags);
1146
1147 if (dwc->gadget_driver) {
1148 dev_err(dwc->dev, "%s is already bound to %s\n",
1149 dwc->gadget.name,
1150 dwc->gadget_driver->driver.name);
1151 ret = -EBUSY;
1152 goto err0;
1153 }
1154
1155 dwc->gadget_driver = driver;
1156 dwc->gadget.dev.driver = &driver->driver;
1157
1158 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
1159
1160 reg &= ~DWC3_GCTL_SCALEDOWN(3);
1161 reg &= ~DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG);
1162 reg &= ~DWC3_GCTL_DISSCRAMBLE;
1163 reg |= DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_DEVICE);
1164
1165 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams0)) {
1166 case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
1167 reg &= ~DWC3_GCTL_DSBLCLKGTNG;
1168 break;
1169 default:
1170 dev_dbg(dwc->dev, "No power optimization available\n");
1171 }
1172
1173 /*
1174 * WORKAROUND: DWC3 revisions <1.90a have a bug
1175 * when The device fails to connect at SuperSpeed
1176 * and falls back to high-speed mode which causes
1177 * the device to enter in a Connect/Disconnect loop
1178 */
1179 if (dwc->revision < DWC3_REVISION_190A)
1180 reg |= DWC3_GCTL_U2RSTECN;
1181
1182 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
1183
1184 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1185 reg &= ~(DWC3_DCFG_SPEED_MASK);
1186 reg |= DWC3_DCFG_SUPERSPEED;
1187 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1188
1189 dwc->start_config_issued = false;
1190
1191 /* Start with SuperSpeed Default */
1192 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1193
1194 dep = dwc->eps[0];
1195 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc);
1196 if (ret) {
1197 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1198 goto err0;
1199 }
1200
1201 dep = dwc->eps[1];
1202 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc);
1203 if (ret) {
1204 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1205 goto err1;
1206 }
1207
1208 /* begin to receive SETUP packets */
1209 dwc->ep0state = EP0_SETUP_PHASE;
1210 dwc3_ep0_out_start(dwc);
1211
1212 spin_unlock_irqrestore(&dwc->lock, flags);
1213
1214 return 0;
1215
1216err1:
1217 __dwc3_gadget_ep_disable(dwc->eps[0]);
1218
1219err0:
1220 spin_unlock_irqrestore(&dwc->lock, flags);
1221
1222 return ret;
1223}
1224
1225static int dwc3_gadget_stop(struct usb_gadget *g,
1226 struct usb_gadget_driver *driver)
1227{
1228 struct dwc3 *dwc = gadget_to_dwc(g);
1229 unsigned long flags;
1230
1231 spin_lock_irqsave(&dwc->lock, flags);
1232
1233 __dwc3_gadget_ep_disable(dwc->eps[0]);
1234 __dwc3_gadget_ep_disable(dwc->eps[1]);
1235
1236 dwc->gadget_driver = NULL;
1237 dwc->gadget.dev.driver = NULL;
1238
1239 spin_unlock_irqrestore(&dwc->lock, flags);
1240
1241 return 0;
1242}
1243static const struct usb_gadget_ops dwc3_gadget_ops = {
1244 .get_frame = dwc3_gadget_get_frame,
1245 .wakeup = dwc3_gadget_wakeup,
1246 .set_selfpowered = dwc3_gadget_set_selfpowered,
1247 .pullup = dwc3_gadget_pullup,
1248 .udc_start = dwc3_gadget_start,
1249 .udc_stop = dwc3_gadget_stop,
1250};
1251
1252/* -------------------------------------------------------------------------- */
1253
1254static int __devinit dwc3_gadget_init_endpoints(struct dwc3 *dwc)
1255{
1256 struct dwc3_ep *dep;
1257 u8 epnum;
1258
1259 INIT_LIST_HEAD(&dwc->gadget.ep_list);
1260
1261 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1262 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
1263 if (!dep) {
1264 dev_err(dwc->dev, "can't allocate endpoint %d\n",
1265 epnum);
1266 return -ENOMEM;
1267 }
1268
1269 dep->dwc = dwc;
1270 dep->number = epnum;
1271 dwc->eps[epnum] = dep;
1272
1273 snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1,
1274 (epnum & 1) ? "in" : "out");
1275 dep->endpoint.name = dep->name;
1276 dep->direction = (epnum & 1);
1277
1278 if (epnum == 0 || epnum == 1) {
1279 dep->endpoint.maxpacket = 512;
1280 dep->endpoint.ops = &dwc3_gadget_ep0_ops;
1281 if (!epnum)
1282 dwc->gadget.ep0 = &dep->endpoint;
1283 } else {
1284 int ret;
1285
1286 dep->endpoint.maxpacket = 1024;
1287 dep->endpoint.max_streams = 15;
1288 dep->endpoint.ops = &dwc3_gadget_ep_ops;
1289 list_add_tail(&dep->endpoint.ep_list,
1290 &dwc->gadget.ep_list);
1291
1292 ret = dwc3_alloc_trb_pool(dep);
1293 if (ret) {
1294 dev_err(dwc->dev, "%s: failed to allocate TRB pool\n", dep->name);
1295 return ret;
1296 }
1297 }
1298 INIT_LIST_HEAD(&dep->request_list);
1299 INIT_LIST_HEAD(&dep->req_queued);
1300 }
1301
1302 return 0;
1303}
1304
1305static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
1306{
1307 struct dwc3_ep *dep;
1308 u8 epnum;
1309
1310 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1311 dep = dwc->eps[epnum];
1312 dwc3_free_trb_pool(dep);
1313
1314 if (epnum != 0 && epnum != 1)
1315 list_del(&dep->endpoint.ep_list);
1316
1317 kfree(dep);
1318 }
1319}
1320
1321static void dwc3_gadget_release(struct device *dev)
1322{
1323 dev_dbg(dev, "%s\n", __func__);
1324}
1325
1326/* -------------------------------------------------------------------------- */
1327static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
1328 const struct dwc3_event_depevt *event, int status)
1329{
1330 struct dwc3_request *req;
1331 struct dwc3_trb trb;
1332 unsigned int count;
1333 unsigned int s_pkt = 0;
1334
1335 do {
1336 req = next_request(&dep->req_queued);
1337 if (!req)
1338 break;
1339
1340 dwc3_trb_to_nat(req->trb, &trb);
1341
1342 if (trb.hwo && status != -ESHUTDOWN)
1343 /*
1344 * We continue despite the error. There is not much we
1345 * can do. If we don't clean in up we loop for ever. If
1346 * we skip the TRB than it gets overwritten reused after
1347 * a while since we use them in a ring buffer. a BUG()
1348 * would help. Lets hope that if this occures, someone
1349 * fixes the root cause instead of looking away :)
1350 */
1351 dev_err(dwc->dev, "%s's TRB (%p) still owned by HW\n",
1352 dep->name, req->trb);
1353 count = trb.length;
1354
1355 if (dep->direction) {
1356 if (count) {
1357 dev_err(dwc->dev, "incomplete IN transfer %s\n",
1358 dep->name);
1359 status = -ECONNRESET;
1360 }
1361 } else {
1362 if (count && (event->status & DEPEVT_STATUS_SHORT))
1363 s_pkt = 1;
1364 }
1365
1366 /*
1367 * We assume here we will always receive the entire data block
1368 * which we should receive. Meaning, if we program RX to
1369 * receive 4K but we receive only 2K, we assume that's all we
1370 * should receive and we simply bounce the request back to the
1371 * gadget driver for further processing.
1372 */
1373 req->request.actual += req->request.length - count;
1374 dwc3_gadget_giveback(dep, req, status);
1375 if (s_pkt)
1376 break;
1377 if ((event->status & DEPEVT_STATUS_LST) && trb.lst)
1378 break;
1379 if ((event->status & DEPEVT_STATUS_IOC) && trb.ioc)
1380 break;
1381 } while (1);
1382
1383 if ((event->status & DEPEVT_STATUS_IOC) && trb.ioc)
1384 return 0;
1385 return 1;
1386}
1387
1388static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc,
1389 struct dwc3_ep *dep, const struct dwc3_event_depevt *event,
1390 int start_new)
1391{
1392 unsigned status = 0;
1393 int clean_busy;
1394
1395 if (event->status & DEPEVT_STATUS_BUSERR)
1396 status = -ECONNRESET;
1397
1398 clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status);
1399 if (clean_busy) {
1400 dep->flags &= ~DWC3_EP_BUSY;
1401 dep->res_trans_idx = 0;
1402 }
1403}
1404
1405static void dwc3_gadget_start_isoc(struct dwc3 *dwc,
1406 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
1407{
1408 u32 uf;
1409
1410 if (list_empty(&dep->request_list)) {
1411 dev_vdbg(dwc->dev, "ISOC ep %s run out for requests.\n",
1412 dep->name);
1413 return;
1414 }
1415
1416 if (event->parameters) {
1417 u32 mask;
1418
1419 mask = ~(dep->interval - 1);
1420 uf = event->parameters & mask;
1421 /* 4 micro frames in the future */
1422 uf += dep->interval * 4;
1423 } else {
1424 uf = 0;
1425 }
1426
1427 __dwc3_gadget_kick_transfer(dep, uf, 1);
1428}
1429
1430static void dwc3_process_ep_cmd_complete(struct dwc3_ep *dep,
1431 const struct dwc3_event_depevt *event)
1432{
1433 struct dwc3 *dwc = dep->dwc;
1434 struct dwc3_event_depevt mod_ev = *event;
1435
1436 /*
1437 * We were asked to remove one requests. It is possible that this
1438 * request and a few other were started together and have the same
1439 * transfer index. Since we stopped the complete endpoint we don't
1440 * know how many requests were already completed (and not yet)
1441 * reported and how could be done (later). We purge them all until
1442 * the end of the list.
1443 */
1444 mod_ev.status = DEPEVT_STATUS_LST;
1445 dwc3_cleanup_done_reqs(dwc, dep, &mod_ev, -ESHUTDOWN);
1446 dep->flags &= ~DWC3_EP_BUSY;
1447 /* pending requets are ignored and are queued on XferNotReady */
1448}
1449
1450static void dwc3_ep_cmd_compl(struct dwc3_ep *dep,
1451 const struct dwc3_event_depevt *event)
1452{
1453 u32 param = event->parameters;
1454 u32 cmd_type = (param >> 8) & ((1 << 5) - 1);
1455
1456 switch (cmd_type) {
1457 case DWC3_DEPCMD_ENDTRANSFER:
1458 dwc3_process_ep_cmd_complete(dep, event);
1459 break;
1460 case DWC3_DEPCMD_STARTTRANSFER:
1461 dep->res_trans_idx = param & 0x7f;
1462 break;
1463 default:
1464 printk(KERN_ERR "%s() unknown /unexpected type: %d\n",
1465 __func__, cmd_type);
1466 break;
1467 };
1468}
1469
1470static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
1471 const struct dwc3_event_depevt *event)
1472{
1473 struct dwc3_ep *dep;
1474 u8 epnum = event->endpoint_number;
1475
1476 dep = dwc->eps[epnum];
1477
1478 dev_vdbg(dwc->dev, "%s: %s\n", dep->name,
1479 dwc3_ep_event_string(event->endpoint_event));
1480
1481 if (epnum == 0 || epnum == 1) {
1482 dwc3_ep0_interrupt(dwc, event);
1483 return;
1484 }
1485
1486 switch (event->endpoint_event) {
1487 case DWC3_DEPEVT_XFERCOMPLETE:
1488 if (usb_endpoint_xfer_isoc(dep->desc)) {
1489 dev_dbg(dwc->dev, "%s is an Isochronous endpoint\n",
1490 dep->name);
1491 return;
1492 }
1493
1494 dwc3_endpoint_transfer_complete(dwc, dep, event, 1);
1495 break;
1496 case DWC3_DEPEVT_XFERINPROGRESS:
1497 if (!usb_endpoint_xfer_isoc(dep->desc)) {
1498 dev_dbg(dwc->dev, "%s is not an Isochronous endpoint\n",
1499 dep->name);
1500 return;
1501 }
1502
1503 dwc3_endpoint_transfer_complete(dwc, dep, event, 0);
1504 break;
1505 case DWC3_DEPEVT_XFERNOTREADY:
1506 if (usb_endpoint_xfer_isoc(dep->desc)) {
1507 dwc3_gadget_start_isoc(dwc, dep, event);
1508 } else {
1509 int ret;
1510
1511 dev_vdbg(dwc->dev, "%s: reason %s\n",
1512 dep->name, event->status
1513 ? "Transfer Active"
1514 : "Transfer Not Active");
1515
1516 ret = __dwc3_gadget_kick_transfer(dep, 0, 1);
1517 if (!ret || ret == -EBUSY)
1518 return;
1519
1520 dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1521 dep->name);
1522 }
1523
1524 break;
1525 case DWC3_DEPEVT_STREAMEVT:
1526 if (!usb_endpoint_xfer_bulk(dep->desc)) {
1527 dev_err(dwc->dev, "Stream event for non-Bulk %s\n",
1528 dep->name);
1529 return;
1530 }
1531
1532 switch (event->status) {
1533 case DEPEVT_STREAMEVT_FOUND:
1534 dev_vdbg(dwc->dev, "Stream %d found and started\n",
1535 event->parameters);
1536
1537 break;
1538 case DEPEVT_STREAMEVT_NOTFOUND:
1539 /* FALLTHROUGH */
1540 default:
1541 dev_dbg(dwc->dev, "Couldn't find suitable stream\n");
1542 }
1543 break;
1544 case DWC3_DEPEVT_RXTXFIFOEVT:
1545 dev_dbg(dwc->dev, "%s FIFO Overrun\n", dep->name);
1546 break;
1547 case DWC3_DEPEVT_EPCMDCMPLT:
1548 dwc3_ep_cmd_compl(dep, event);
1549 break;
1550 }
1551}
1552
1553static void dwc3_disconnect_gadget(struct dwc3 *dwc)
1554{
1555 if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
1556 spin_unlock(&dwc->lock);
1557 dwc->gadget_driver->disconnect(&dwc->gadget);
1558 spin_lock(&dwc->lock);
1559 }
1560}
1561
1562static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum)
1563{
1564 struct dwc3_ep *dep;
1565 struct dwc3_gadget_ep_cmd_params params;
1566 u32 cmd;
1567 int ret;
1568
1569 dep = dwc->eps[epnum];
1570
1571 WARN_ON(!dep->res_trans_idx);
1572 if (dep->res_trans_idx) {
1573 cmd = DWC3_DEPCMD_ENDTRANSFER;
1574 cmd |= DWC3_DEPCMD_HIPRI_FORCERM | DWC3_DEPCMD_CMDIOC;
1575 cmd |= DWC3_DEPCMD_PARAM(dep->res_trans_idx);
1576 memset(&params, 0, sizeof(params));
1577 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
1578 WARN_ON_ONCE(ret);
1579 dep->res_trans_idx = 0;
1580 }
1581}
1582
1583static void dwc3_stop_active_transfers(struct dwc3 *dwc)
1584{
1585 u32 epnum;
1586
1587 for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1588 struct dwc3_ep *dep;
1589
1590 dep = dwc->eps[epnum];
1591 if (!(dep->flags & DWC3_EP_ENABLED))
1592 continue;
1593
1594 dwc3_remove_requests(dwc, dep);
1595 }
1596}
1597
1598static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
1599{
1600 u32 epnum;
1601
1602 for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1603 struct dwc3_ep *dep;
1604 struct dwc3_gadget_ep_cmd_params params;
1605 int ret;
1606
1607 dep = dwc->eps[epnum];
1608
1609 if (!(dep->flags & DWC3_EP_STALL))
1610 continue;
1611
1612 dep->flags &= ~DWC3_EP_STALL;
1613
1614 memset(&params, 0, sizeof(params));
1615 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1616 DWC3_DEPCMD_CLEARSTALL, &params);
1617 WARN_ON_ONCE(ret);
1618 }
1619}
1620
1621static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
1622{
1623 dev_vdbg(dwc->dev, "%s\n", __func__);
1624#if 0
1625 XXX
1626 U1/U2 is powersave optimization. Skip it for now. Anyway we need to
1627 enable it before we can disable it.
1628
1629 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1630 reg &= ~DWC3_DCTL_INITU1ENA;
1631 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1632
1633 reg &= ~DWC3_DCTL_INITU2ENA;
1634 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1635#endif
1636
1637 dwc3_stop_active_transfers(dwc);
1638 dwc3_disconnect_gadget(dwc);
1639 dwc->start_config_issued = false;
1640
1641 dwc->gadget.speed = USB_SPEED_UNKNOWN;
1642}
1643
1644static void dwc3_gadget_usb3_phy_power(struct dwc3 *dwc, int on)
1645{
1646 u32 reg;
1647
1648 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
1649
1650 if (on)
1651 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
1652 else
1653 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
1654
1655 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
1656}
1657
1658static void dwc3_gadget_usb2_phy_power(struct dwc3 *dwc, int on)
1659{
1660 u32 reg;
1661
1662 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
1663
1664 if (on)
1665 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
1666 else
1667 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
1668
1669 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
1670}
1671
1672static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
1673{
1674 u32 reg;
1675
1676 dev_vdbg(dwc->dev, "%s\n", __func__);
1677
1678 /* Enable PHYs */
1679 dwc3_gadget_usb2_phy_power(dwc, true);
1680 dwc3_gadget_usb3_phy_power(dwc, true);
1681
1682 if (dwc->gadget.speed != USB_SPEED_UNKNOWN)
1683 dwc3_disconnect_gadget(dwc);
1684
1685 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1686 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
1687 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1688
1689 dwc3_stop_active_transfers(dwc);
1690 dwc3_clear_stall_all_ep(dwc);
1691 dwc->start_config_issued = false;
1692
1693 /* Reset device address to zero */
1694 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1695 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
1696 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1697}
1698
1699static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed)
1700{
1701 u32 reg;
1702 u32 usb30_clock = DWC3_GCTL_CLK_BUS;
1703
1704 /*
1705 * We change the clock only at SS but I dunno why I would want to do
1706 * this. Maybe it becomes part of the power saving plan.
1707 */
1708
1709 if (speed != DWC3_DSTS_SUPERSPEED)
1710 return;
1711
1712 /*
1713 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
1714 * each time on Connect Done.
1715 */
1716 if (!usb30_clock)
1717 return;
1718
1719 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
1720 reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock);
1721 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
1722}
1723
1724static void dwc3_gadget_disable_phy(struct dwc3 *dwc, u8 speed)
1725{
1726 switch (speed) {
1727 case USB_SPEED_SUPER:
1728 dwc3_gadget_usb2_phy_power(dwc, false);
1729 break;
1730 case USB_SPEED_HIGH:
1731 case USB_SPEED_FULL:
1732 case USB_SPEED_LOW:
1733 dwc3_gadget_usb3_phy_power(dwc, false);
1734 break;
1735 }
1736}
1737
1738static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
1739{
1740 struct dwc3_gadget_ep_cmd_params params;
1741 struct dwc3_ep *dep;
1742 int ret;
1743 u32 reg;
1744 u8 speed;
1745
1746 dev_vdbg(dwc->dev, "%s\n", __func__);
1747
1748 memset(&params, 0x00, sizeof(params));
1749
1750 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1751 speed = reg & DWC3_DSTS_CONNECTSPD;
1752 dwc->speed = speed;
1753
1754 dwc3_update_ram_clk_sel(dwc, speed);
1755
1756 switch (speed) {
1757 case DWC3_DCFG_SUPERSPEED:
1758 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1759 dwc->gadget.ep0->maxpacket = 512;
1760 dwc->gadget.speed = USB_SPEED_SUPER;
1761 break;
1762 case DWC3_DCFG_HIGHSPEED:
1763 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
1764 dwc->gadget.ep0->maxpacket = 64;
1765 dwc->gadget.speed = USB_SPEED_HIGH;
1766 break;
1767 case DWC3_DCFG_FULLSPEED2:
1768 case DWC3_DCFG_FULLSPEED1:
1769 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
1770 dwc->gadget.ep0->maxpacket = 64;
1771 dwc->gadget.speed = USB_SPEED_FULL;
1772 break;
1773 case DWC3_DCFG_LOWSPEED:
1774 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
1775 dwc->gadget.ep0->maxpacket = 8;
1776 dwc->gadget.speed = USB_SPEED_LOW;
1777 break;
1778 }
1779
1780 /* Disable unneded PHY */
1781 dwc3_gadget_disable_phy(dwc, dwc->gadget.speed);
1782
1783 dep = dwc->eps[0];
1784 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc);
1785 if (ret) {
1786 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1787 return;
1788 }
1789
1790 dep = dwc->eps[1];
1791 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc);
1792 if (ret) {
1793 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1794 return;
1795 }
1796
1797 /*
1798 * Configure PHY via GUSB3PIPECTLn if required.
1799 *
1800 * Update GTXFIFOSIZn
1801 *
1802 * In both cases reset values should be sufficient.
1803 */
1804}
1805
1806static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
1807{
1808 dev_vdbg(dwc->dev, "%s\n", __func__);
1809
1810 /*
1811 * TODO take core out of low power mode when that's
1812 * implemented.
1813 */
1814
1815 dwc->gadget_driver->resume(&dwc->gadget);
1816}
1817
1818static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
1819 unsigned int evtinfo)
1820{
1821 /* The fith bit says SuperSpeed yes or no. */
1822 dwc->link_state = evtinfo & DWC3_LINK_STATE_MASK;
1823
1824 dev_vdbg(dwc->dev, "%s link %d\n", __func__, dwc->link_state);
1825}
1826
1827static void dwc3_gadget_interrupt(struct dwc3 *dwc,
1828 const struct dwc3_event_devt *event)
1829{
1830 switch (event->type) {
1831 case DWC3_DEVICE_EVENT_DISCONNECT:
1832 dwc3_gadget_disconnect_interrupt(dwc);
1833 break;
1834 case DWC3_DEVICE_EVENT_RESET:
1835 dwc3_gadget_reset_interrupt(dwc);
1836 break;
1837 case DWC3_DEVICE_EVENT_CONNECT_DONE:
1838 dwc3_gadget_conndone_interrupt(dwc);
1839 break;
1840 case DWC3_DEVICE_EVENT_WAKEUP:
1841 dwc3_gadget_wakeup_interrupt(dwc);
1842 break;
1843 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
1844 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
1845 break;
1846 case DWC3_DEVICE_EVENT_EOPF:
1847 dev_vdbg(dwc->dev, "End of Periodic Frame\n");
1848 break;
1849 case DWC3_DEVICE_EVENT_SOF:
1850 dev_vdbg(dwc->dev, "Start of Periodic Frame\n");
1851 break;
1852 case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
1853 dev_vdbg(dwc->dev, "Erratic Error\n");
1854 break;
1855 case DWC3_DEVICE_EVENT_CMD_CMPL:
1856 dev_vdbg(dwc->dev, "Command Complete\n");
1857 break;
1858 case DWC3_DEVICE_EVENT_OVERFLOW:
1859 dev_vdbg(dwc->dev, "Overflow\n");
1860 break;
1861 default:
1862 dev_dbg(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
1863 }
1864}
1865
1866static void dwc3_process_event_entry(struct dwc3 *dwc,
1867 const union dwc3_event *event)
1868{
1869 /* Endpoint IRQ, handle it and return early */
1870 if (event->type.is_devspec == 0) {
1871 /* depevt */
1872 return dwc3_endpoint_interrupt(dwc, &event->depevt);
1873 }
1874
1875 switch (event->type.type) {
1876 case DWC3_EVENT_TYPE_DEV:
1877 dwc3_gadget_interrupt(dwc, &event->devt);
1878 break;
1879 /* REVISIT what to do with Carkit and I2C events ? */
1880 default:
1881 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
1882 }
1883}
1884
1885static irqreturn_t dwc3_process_event_buf(struct dwc3 *dwc, u32 buf)
1886{
1887 struct dwc3_event_buffer *evt;
1888 int left;
1889 u32 count;
1890
1891 count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(buf));
1892 count &= DWC3_GEVNTCOUNT_MASK;
1893 if (!count)
1894 return IRQ_NONE;
1895
1896 evt = dwc->ev_buffs[buf];
1897 left = count;
1898
1899 while (left > 0) {
1900 union dwc3_event event;
1901
1902 memcpy(&event.raw, (evt->buf + evt->lpos), sizeof(event.raw));
1903 dwc3_process_event_entry(dwc, &event);
1904 /*
1905 * XXX we wrap around correctly to the next entry as almost all
1906 * entries are 4 bytes in size. There is one entry which has 12
1907 * bytes which is a regular entry followed by 8 bytes data. ATM
1908 * I don't know how things are organized if were get next to the
1909 * a boundary so I worry about that once we try to handle that.
1910 */
1911 evt->lpos = (evt->lpos + 4) % DWC3_EVENT_BUFFERS_SIZE;
1912 left -= 4;
1913
1914 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(buf), 4);
1915 }
1916
1917 return IRQ_HANDLED;
1918}
1919
1920static irqreturn_t dwc3_interrupt(int irq, void *_dwc)
1921{
1922 struct dwc3 *dwc = _dwc;
1923 int i;
1924 irqreturn_t ret = IRQ_NONE;
1925
1926 spin_lock(&dwc->lock);
1927
1928 for (i = 0; i < DWC3_EVENT_BUFFERS_NUM; i++) {
1929 irqreturn_t status;
1930
1931 status = dwc3_process_event_buf(dwc, i);
1932 if (status == IRQ_HANDLED)
1933 ret = status;
1934 }
1935
1936 spin_unlock(&dwc->lock);
1937
1938 return ret;
1939}
1940
1941/**
1942 * dwc3_gadget_init - Initializes gadget related registers
1943 * @dwc: Pointer to out controller context structure
1944 *
1945 * Returns 0 on success otherwise negative errno.
1946 */
1947int __devinit dwc3_gadget_init(struct dwc3 *dwc)
1948{
1949 u32 reg;
1950 int ret;
1951 int irq;
1952
1953 dwc->ctrl_req = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
1954 &dwc->ctrl_req_addr, GFP_KERNEL);
1955 if (!dwc->ctrl_req) {
1956 dev_err(dwc->dev, "failed to allocate ctrl request\n");
1957 ret = -ENOMEM;
1958 goto err0;
1959 }
1960
1961 dwc->ep0_trb = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
1962 &dwc->ep0_trb_addr, GFP_KERNEL);
1963 if (!dwc->ep0_trb) {
1964 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
1965 ret = -ENOMEM;
1966 goto err1;
1967 }
1968
1969 dwc->setup_buf = dma_alloc_coherent(dwc->dev,
1970 sizeof(*dwc->setup_buf) * 2,
1971 &dwc->setup_buf_addr, GFP_KERNEL);
1972 if (!dwc->setup_buf) {
1973 dev_err(dwc->dev, "failed to allocate setup buffer\n");
1974 ret = -ENOMEM;
1975 goto err2;
1976 }
1977
1978 dwc->ep0_bounce = dma_alloc_coherent(dwc->dev,
1979 512, &dwc->ep0_bounce_addr, GFP_KERNEL);
1980 if (!dwc->ep0_bounce) {
1981 dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n");
1982 ret = -ENOMEM;
1983 goto err3;
1984 }
1985
1986 dev_set_name(&dwc->gadget.dev, "gadget");
1987
1988 dwc->gadget.ops = &dwc3_gadget_ops;
1989 dwc->gadget.is_dualspeed = true;
1990 dwc->gadget.speed = USB_SPEED_UNKNOWN;
1991 dwc->gadget.dev.parent = dwc->dev;
1992
1993 dma_set_coherent_mask(&dwc->gadget.dev, dwc->dev->coherent_dma_mask);
1994
1995 dwc->gadget.dev.dma_parms = dwc->dev->dma_parms;
1996 dwc->gadget.dev.dma_mask = dwc->dev->dma_mask;
1997 dwc->gadget.dev.release = dwc3_gadget_release;
1998 dwc->gadget.name = "dwc3-gadget";
1999
2000 /*
2001 * REVISIT: Here we should clear all pending IRQs to be
2002 * sure we're starting from a well known location.
2003 */
2004
2005 ret = dwc3_gadget_init_endpoints(dwc);
2006 if (ret)
2007 goto err4;
2008
2009 irq = platform_get_irq(to_platform_device(dwc->dev), 0);
2010
2011 ret = request_irq(irq, dwc3_interrupt, IRQF_SHARED,
2012 "dwc3", dwc);
2013 if (ret) {
2014 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
2015 irq, ret);
2016 goto err5;
2017 }
2018
2019 /* Enable all but Start and End of Frame IRQs */
2020 reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
2021 DWC3_DEVTEN_EVNTOVERFLOWEN |
2022 DWC3_DEVTEN_CMDCMPLTEN |
2023 DWC3_DEVTEN_ERRTICERREN |
2024 DWC3_DEVTEN_WKUPEVTEN |
2025 DWC3_DEVTEN_ULSTCNGEN |
2026 DWC3_DEVTEN_CONNECTDONEEN |
2027 DWC3_DEVTEN_USBRSTEN |
2028 DWC3_DEVTEN_DISCONNEVTEN);
2029 dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
2030
2031 ret = device_register(&dwc->gadget.dev);
2032 if (ret) {
2033 dev_err(dwc->dev, "failed to register gadget device\n");
2034 put_device(&dwc->gadget.dev);
2035 goto err6;
2036 }
2037
2038 ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
2039 if (ret) {
2040 dev_err(dwc->dev, "failed to register udc\n");
2041 goto err7;
2042 }
2043
2044 return 0;
2045
2046err7:
2047 device_unregister(&dwc->gadget.dev);
2048
2049err6:
2050 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
2051 free_irq(irq, dwc);
2052
2053err5:
2054 dwc3_gadget_free_endpoints(dwc);
2055
2056err4:
2057 dma_free_coherent(dwc->dev, 512, dwc->ep0_bounce,
2058 dwc->ep0_bounce_addr);
2059
2060err3:
2061 dma_free_coherent(dwc->dev, sizeof(*dwc->setup_buf) * 2,
2062 dwc->setup_buf, dwc->setup_buf_addr);
2063
2064err2:
2065 dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2066 dwc->ep0_trb, dwc->ep0_trb_addr);
2067
2068err1:
2069 dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2070 dwc->ctrl_req, dwc->ctrl_req_addr);
2071
2072err0:
2073 return ret;
2074}
2075
2076void dwc3_gadget_exit(struct dwc3 *dwc)
2077{
2078 int irq;
2079 int i;
2080
2081 usb_del_gadget_udc(&dwc->gadget);
2082 irq = platform_get_irq(to_platform_device(dwc->dev), 0);
2083
2084 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
2085 free_irq(irq, dwc);
2086
2087 for (i = 0; i < ARRAY_SIZE(dwc->eps); i++)
2088 __dwc3_gadget_ep_disable(dwc->eps[i]);
2089
2090 dwc3_gadget_free_endpoints(dwc);
2091
2092 dma_free_coherent(dwc->dev, 512, dwc->ep0_bounce,
2093 dwc->ep0_bounce_addr);
2094
2095 dma_free_coherent(dwc->dev, sizeof(*dwc->setup_buf) * 2,
2096 dwc->setup_buf, dwc->setup_buf_addr);
2097
2098 dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2099 dwc->ep0_trb, dwc->ep0_trb_addr);
2100
2101 dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2102 dwc->ctrl_req, dwc->ctrl_req_addr);
2103
2104 device_unregister(&dwc->gadget.dev);
2105}
diff --git a/drivers/usb/dwc3/gadget.h b/drivers/usb/dwc3/gadget.h
new file mode 100644
index 000000000000..71145a449d99
--- /dev/null
+++ b/drivers/usb/dwc3/gadget.h
@@ -0,0 +1,211 @@
1/**
2 * gadget.h - DesignWare USB3 DRD Gadget Header
3 *
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
5 *
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions, and the following disclaimer,
14 * without modification.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. The names of the above-listed copyright holders may not be used
19 * to endorse or promote products derived from this software without
20 * specific prior written permission.
21 *
22 * ALTERNATIVELY, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2, as published by the Free
24 * Software Foundation.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
27 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
28 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
30 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
31 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
32 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
33 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
34 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
35 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
36 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 */
38
39#ifndef __DRIVERS_USB_DWC3_GADGET_H
40#define __DRIVERS_USB_DWC3_GADGET_H
41
42#include <linux/list.h>
43#include <linux/usb/gadget.h>
44#include "io.h"
45
46struct dwc3;
47#define to_dwc3_ep(ep) (container_of(ep, struct dwc3_ep, endpoint))
48#define gadget_to_dwc(g) (container_of(g, struct dwc3, gadget))
49
50/* DEPCFG parameter 1 */
51#define DWC3_DEPCFG_INT_NUM(n) ((n) << 0)
52#define DWC3_DEPCFG_XFER_COMPLETE_EN (1 << 8)
53#define DWC3_DEPCFG_XFER_IN_PROGRESS_EN (1 << 9)
54#define DWC3_DEPCFG_XFER_NOT_READY_EN (1 << 10)
55#define DWC3_DEPCFG_FIFO_ERROR_EN (1 << 11)
56#define DWC3_DEPCFG_STREAM_EVENT_EN (1 << 13)
57#define DWC3_DEPCFG_BINTERVAL_M1(n) ((n) << 16)
58#define DWC3_DEPCFG_STREAM_CAPABLE (1 << 24)
59#define DWC3_DEPCFG_EP_NUMBER(n) ((n) << 25)
60#define DWC3_DEPCFG_BULK_BASED (1 << 30)
61#define DWC3_DEPCFG_FIFO_BASED (1 << 31)
62
63/* DEPCFG parameter 0 */
64#define DWC3_DEPCFG_EP_TYPE(n) ((n) << 1)
65#define DWC3_DEPCFG_MAX_PACKET_SIZE(n) ((n) << 3)
66#define DWC3_DEPCFG_FIFO_NUMBER(n) ((n) << 17)
67#define DWC3_DEPCFG_BURST_SIZE(n) ((n) << 22)
68#define DWC3_DEPCFG_DATA_SEQ_NUM(n) ((n) << 26)
69#define DWC3_DEPCFG_IGN_SEQ_NUM (1 << 31)
70
71/* DEPXFERCFG parameter 0 */
72#define DWC3_DEPXFERCFG_NUM_XFER_RES(n) ((n) & 0xffff)
73
74struct dwc3_gadget_ep_cmd_params {
75 u32 param2;
76 u32 param1;
77 u32 param0;
78};
79
80/* -------------------------------------------------------------------------- */
81
82struct dwc3_request {
83 struct usb_request request;
84 struct list_head list;
85 struct dwc3_ep *dep;
86
87 u8 epnum;
88 struct dwc3_trb_hw *trb;
89 dma_addr_t trb_dma;
90
91 unsigned direction:1;
92 unsigned mapped:1;
93 unsigned queued:1;
94};
95#define to_dwc3_request(r) (container_of(r, struct dwc3_request, request))
96
97static inline struct dwc3_request *next_request(struct list_head *list)
98{
99 if (list_empty(list))
100 return NULL;
101
102 return list_first_entry(list, struct dwc3_request, list);
103}
104
105static inline void dwc3_gadget_move_request_queued(struct dwc3_request *req)
106{
107 struct dwc3_ep *dep = req->dep;
108
109 req->queued = true;
110 list_move_tail(&req->list, &dep->req_queued);
111}
112
113#if defined(CONFIG_USB_GADGET_DWC3) || defined(CONFIG_USB_GADGET_DWC3_MODULE)
114int dwc3_gadget_init(struct dwc3 *dwc);
115void dwc3_gadget_exit(struct dwc3 *dwc);
116#else
117static inline int dwc3_gadget_init(struct dwc3 *dwc) { return 0; }
118static inline void dwc3_gadget_exit(struct dwc3 *dwc) { }
119static inline int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep,
120 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params)
121{
122 return 0;
123}
124#endif
125
126void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
127 int status);
128
129void dwc3_ep0_interrupt(struct dwc3 *dwc, const struct dwc3_event_depevt *event);
130void dwc3_ep0_out_start(struct dwc3 *dwc);
131int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request,
132 gfp_t gfp_flags);
133int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value);
134int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep,
135 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params);
136void dwc3_map_buffer_to_dma(struct dwc3_request *req);
137void dwc3_unmap_buffer_from_dma(struct dwc3_request *req);
138
139/**
140 * dwc3_gadget_ep_get_transfer_index - Gets transfer index from HW
141 * @dwc: DesignWare USB3 Pointer
142 * @number: DWC endpoint number
143 *
144 * Caller should take care of locking
145 */
146static inline u32 dwc3_gadget_ep_get_transfer_index(struct dwc3 *dwc, u8 number)
147{
148 u32 res_id;
149
150 res_id = dwc3_readl(dwc->regs, DWC3_DEPCMD(number));
151
152 return DWC3_DEPCMD_GET_RSC_IDX(res_id);
153}
154
155/**
156 * dwc3_gadget_event_string - returns event name
157 * @event: the event code
158 */
159static inline const char *dwc3_gadget_event_string(u8 event)
160{
161 switch (event) {
162 case DWC3_DEVICE_EVENT_DISCONNECT:
163 return "Disconnect";
164 case DWC3_DEVICE_EVENT_RESET:
165 return "Reset";
166 case DWC3_DEVICE_EVENT_CONNECT_DONE:
167 return "Connection Done";
168 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
169 return "Link Status Change";
170 case DWC3_DEVICE_EVENT_WAKEUP:
171 return "WakeUp";
172 case DWC3_DEVICE_EVENT_EOPF:
173 return "End-Of-Frame";
174 case DWC3_DEVICE_EVENT_SOF:
175 return "Start-Of-Frame";
176 case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
177 return "Erratic Error";
178 case DWC3_DEVICE_EVENT_CMD_CMPL:
179 return "Command Complete";
180 case DWC3_DEVICE_EVENT_OVERFLOW:
181 return "Overflow";
182 }
183
184 return "UNKNOWN";
185}
186
187/**
188 * dwc3_ep_event_string - returns event name
189 * @event: then event code
190 */
191static inline const char *dwc3_ep_event_string(u8 event)
192{
193 switch (event) {
194 case DWC3_DEPEVT_XFERCOMPLETE:
195 return "Transfer Complete";
196 case DWC3_DEPEVT_XFERINPROGRESS:
197 return "Transfer In-Progress";
198 case DWC3_DEPEVT_XFERNOTREADY:
199 return "Transfer Not Ready";
200 case DWC3_DEPEVT_RXTXFIFOEVT:
201 return "FIFO";
202 case DWC3_DEPEVT_STREAMEVT:
203 return "Stream";
204 case DWC3_DEPEVT_EPCMDCMPLT:
205 return "Endpoint Command Complete";
206 }
207
208 return "UNKNOWN";
209}
210
211#endif /* __DRIVERS_USB_DWC3_GADGET_H */
diff --git a/drivers/usb/dwc3/io.h b/drivers/usb/dwc3/io.h
new file mode 100644
index 000000000000..bc957db1ea4b
--- /dev/null
+++ b/drivers/usb/dwc3/io.h
@@ -0,0 +1,54 @@
1/**
2 * io.h - DesignWare USB3 DRD IO Header
3 *
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
5 *
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions, and the following disclaimer,
14 * without modification.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. The names of the above-listed copyright holders may not be used
19 * to endorse or promote products derived from this software without
20 * specific prior written permission.
21 *
22 * ALTERNATIVELY, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2, as published by the Free
24 * Software Foundation.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
27 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
28 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
30 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
31 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
32 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
33 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
34 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
35 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
36 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 */
38
39#ifndef __DRIVERS_USB_DWC3_IO_H
40#define __DRIVERS_USB_DWC3_IO_H
41
42#include <asm/io.h>
43
44static inline u32 dwc3_readl(void __iomem *base, u32 offset)
45{
46 return readl(base + offset);
47}
48
49static inline void dwc3_writel(void __iomem *base, u32 offset, u32 value)
50{
51 writel(value, base + offset);
52}
53
54#endif /* __DRIVERS_USB_DWC3_IO_H */
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-29 03:03:53 -0500