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authorFelipe Balbi <balbi@ti.com>2011-09-30 03:58:51 -0400
committerGreg Kroah-Hartman <gregkh@suse.de>2011-10-04 13:25:56 -0400
commitdc1c70a774b6fe3744b330d58bb9cf802f7eac89 (patch)
treee12ab3ac678d858968799c0f22d1b89283ce2982 /drivers/usb/dwc3/gadget.h
parentaabb70752361a8b8ca44142a942a5bd133c4d304 (diff)
usb: dwc3: convert structures into bitshifts
our parameter structures need to be written to HW, so instead of assuming little endian, we convert those into bit shifts. Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'drivers/usb/dwc3/gadget.h')
-rw-r--r--drivers/usb/dwc3/gadget.h139
1 files changed, 27 insertions, 112 deletions
diff --git a/drivers/usb/dwc3/gadget.h b/drivers/usb/dwc3/gadget.h
index b025651e0138..71145a449d99 100644
--- a/drivers/usb/dwc3/gadget.h
+++ b/drivers/usb/dwc3/gadget.h
@@ -47,120 +47,35 @@ struct dwc3;
47#define to_dwc3_ep(ep) (container_of(ep, struct dwc3_ep, endpoint)) 47#define to_dwc3_ep(ep) (container_of(ep, struct dwc3_ep, endpoint))
48#define gadget_to_dwc(g) (container_of(g, struct dwc3, gadget)) 48#define gadget_to_dwc(g) (container_of(g, struct dwc3, gadget))
49 49
50/** 50/* DEPCFG parameter 1 */
51 * struct dwc3_gadget_ep_depcfg_param1 - DEPCMDPAR0 for DEPCFG command 51#define DWC3_DEPCFG_INT_NUM(n) ((n) << 0)
52 * @interrupt_number: self-explanatory 52#define DWC3_DEPCFG_XFER_COMPLETE_EN (1 << 8)
53 * @reserved7_5: set to zero 53#define DWC3_DEPCFG_XFER_IN_PROGRESS_EN (1 << 9)
54 * @xfer_complete_enable: event generated when transfer completed 54#define DWC3_DEPCFG_XFER_NOT_READY_EN (1 << 10)
55 * @xfer_in_progress_enable: event generated when transfer in progress 55#define DWC3_DEPCFG_FIFO_ERROR_EN (1 << 11)
56 * @xfer_not_ready_enable: event generated when transfer not read 56#define DWC3_DEPCFG_STREAM_EVENT_EN (1 << 13)
57 * @fifo_error_enable: generates events when FIFO Underrun (IN eps) 57#define DWC3_DEPCFG_BINTERVAL_M1(n) ((n) << 16)
58 * or FIFO Overrun (OUT) eps 58#define DWC3_DEPCFG_STREAM_CAPABLE (1 << 24)
59 * @reserved_12: set to zero 59#define DWC3_DEPCFG_EP_NUMBER(n) ((n) << 25)
60 * @stream_event_enable: event generated on stream 60#define DWC3_DEPCFG_BULK_BASED (1 << 30)
61 * @reserved14_15: set to zero 61#define DWC3_DEPCFG_FIFO_BASED (1 << 31)
62 * @binterval_m1: bInterval minus 1 62
63 * @stream_capable: this EP is capable of handling streams 63/* DEPCFG parameter 0 */
64 * @ep_number: self-explanatory 64#define DWC3_DEPCFG_EP_TYPE(n) ((n) << 1)
65 * @bulk_based: Set to ‘1’ if this isochronous endpoint represents a bulk 65#define DWC3_DEPCFG_MAX_PACKET_SIZE(n) ((n) << 3)
66 * data stream that ignores the relationship of bus time to the 66#define DWC3_DEPCFG_FIFO_NUMBER(n) ((n) << 17)
67 * intervals programmed in TRBs. 67#define DWC3_DEPCFG_BURST_SIZE(n) ((n) << 22)
68 * @fifo_based: Set to ‘1’ if this isochronous endpoint represents a 68#define DWC3_DEPCFG_DATA_SEQ_NUM(n) ((n) << 26)
69 * FIFO-based data stream where TRBs have fixed values and are never 69#define DWC3_DEPCFG_IGN_SEQ_NUM (1 << 31)
70 * written back by the core. 70
71 */ 71/* DEPXFERCFG parameter 0 */
72struct dwc3_gadget_ep_depcfg_param1 { 72#define DWC3_DEPXFERCFG_NUM_XFER_RES(n) ((n) & 0xffff)
73 u32 interrupt_number:5;
74 u32 reserved7_5:3; /* set to zero */
75 u32 xfer_complete_enable:1;
76 u32 xfer_in_progress_enable:1;
77 u32 xfer_not_ready_enable:1;
78 u32 fifo_error_enable:1; /* IN-underrun, OUT-overrun */
79 u32 reserved12:1; /* set to zero */
80 u32 stream_event_enable:1;
81 u32 reserved14_15:2;
82 u32 binterval_m1:8; /* bInterval minus 1 */
83 u32 stream_capable:1;
84 u32 ep_number:5;
85 u32 bulk_based:1;
86 u32 fifo_based:1;
87} __packed;
88
89/**
90 * struct dwc3_gadget_ep_depcfg_param0 - Parameter 0 for DEPCFG
91 * @reserved0: set to zero
92 * @ep_type: Endpoint Type (control, bulk, iso, interrupt)
93 * @max_packet_size: max packet size in bytes
94 * @reserved16_14: set to zero
95 * @fifo_number: self-explanatory
96 * @burst_size: burst size minus 1
97 * @data_sequence_number: Must be 0 when an endpoint is initially configured
98 * May be non-zero when an endpoint is configured after a power transition
99 * that requires a save/restore.
100 * @ignore_sequence_number: Set to ‘1’ to avoid resetting the sequence
101 * number. This setting is used by software to modify the DEPEVTEN
102 * event enable bits without modifying other endpoint settings.
103 */
104struct dwc3_gadget_ep_depcfg_param0 {
105 u32 reserved0:1;
106 u32 ep_type:2;
107 u32 max_packet_size:11;
108 u32 reserved16_14:3;
109 u32 fifo_number:5;
110 u32 burst_size:4;
111 u32 data_sequence_number:5;
112 u32 ignore_sequence_number:1;
113} __packed;
114
115/**
116 * struct dwc3_gadget_ep_depxfercfg_param0 - Parameter 0 of DEPXFERCFG
117 * @number_xfer_resources: Defines the number of Transfer Resources allocated
118 * to this endpoint. This field must be set to 1.
119 * @reserved16_31: set to zero;
120 */
121struct dwc3_gadget_ep_depxfercfg_param0 {
122 u32 number_xfer_resources:16;
123 u32 reserved16_31:16;
124} __packed;
125
126/**
127 * struct dwc3_gadget_ep_depstrtxfer_param1 - Parameter 1 of DEPSTRTXFER
128 * @transfer_desc_addr_low: Indicates the lower 32 bits of the external
129 * memory's start address for the transfer descriptor. Because TRBs
130 * must be aligned to a 16-byte boundary, the lower 4 bits of this
131 * address must be 0.
132 */
133struct dwc3_gadget_ep_depstrtxfer_param1 {
134 u32 transfer_desc_addr_low;
135} __packed;
136
137/**
138 * struct dwc3_gadget_ep_depstrtxfer_param1 - Parameter 1 of DEPSTRTXFER
139 * @transfer_desc_addr_high: Indicates the higher 32 bits of the external
140 * memory’s start address for the transfer descriptor.
141 */
142struct dwc3_gadget_ep_depstrtxfer_param0 {
143 u32 transfer_desc_addr_high;
144} __packed;
145 73
146struct dwc3_gadget_ep_cmd_params { 74struct dwc3_gadget_ep_cmd_params {
147 union { 75 u32 param2;
148 u32 raw; 76 u32 param1;
149 } param2; 77 u32 param0;
150 78};
151 union {
152 u32 raw;
153 struct dwc3_gadget_ep_depcfg_param1 depcfg;
154 struct dwc3_gadget_ep_depstrtxfer_param1 depstrtxfer;
155 } param1;
156
157 union {
158 u32 raw;
159 struct dwc3_gadget_ep_depcfg_param0 depcfg;
160 struct dwc3_gadget_ep_depxfercfg_param0 depxfercfg;
161 struct dwc3_gadget_ep_depstrtxfer_param0 depstrtxfer;
162 } param0;
163} __packed;
164 79
165/* -------------------------------------------------------------------------- */ 80/* -------------------------------------------------------------------------- */
166 81