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authorOlof Johansson <olof@lixom.net>2012-09-23 01:20:37 -0400
committerOlof Johansson <olof@lixom.net>2012-09-23 01:20:37 -0400
commit40169a7c399346281da55ed9905a104d3da47945 (patch)
tree47181afbd7ccf73af8ec0b840d637a794062faa0 /drivers/tty
parent84bae6c379e362aa017efd417199f51d5c2273ac (diff)
parentc164fa62b93782165f12c0e8366f7b46507edb4d (diff)
Merge branch 'for-arm-soc-next' of git://git.linaro.org/people/ljones/linux-3.0-ux500 into next/dt
* 'for-arm-soc-next' of git://git.linaro.org/people/ljones/linux-3.0-ux500: ARM: ux500: Fix SSP register address format ARM: ux500: Apply tc3589x's GPIO/IRQ properties to HREF's DT ARM: ux500: Remove redundant #gpio-cell properties from Snowball DT ARM: ux500: Add all encompassing sound node to the HREF Device Tree ARM: ux500: Add nodes for the MSP into the HREF Device Tree ARM: ux500: Add all known I2C sub-device nodes to the HREF DT ARM: ux500: Stop registering I2C sub-devices for HREF when DT is enabled ARM: ux500: Stop registering Audio devices for HREF when DT is enabled ARM: ux500: Add all encompassing sound node to the Snowball Device Tree ARM: ux500: Add nodes for the MSP into Device Tree ARM: ux500: Rename MSP board file to something more meaningful ARM: ux500: Remove platform registration of MSP devices ARM: ux500: Stop registering the MOP500 Audio driver from platform code ARM: ux500: Pass MSP DMA platform data though AUXDATA ARM: ux500: Fork MSP platform registration for step-by-step DT enablement ARM: ux500: Add AB8500 CODEC node to DB8500 Device Tree ARM: ux500: Clean-up MSP platform code ARM: ux500: Pass SDI DMA information though AUX_DATA to MMCI ARM: ux500: Add UART support to the HREF Device Tree ARM: ux500: Add skeleton Device Tree for the HREF reference board ... + sync to v3.6-rc6
Diffstat (limited to 'drivers/tty')
-rw-r--r--drivers/tty/serial/imx.c30
1 files changed, 15 insertions, 15 deletions
diff --git a/drivers/tty/serial/imx.c b/drivers/tty/serial/imx.c
index 72ec56e6d42f..5952b25c288e 100644
--- a/drivers/tty/serial/imx.c
+++ b/drivers/tty/serial/imx.c
@@ -132,6 +132,7 @@
132#define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */ 132#define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
133#define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */ 133#define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
134#define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */ 134#define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
135#define UFCR_DCEDTE (1<<6) /* DCE/DTE mode select */
135#define UFCR_RFDIV (7<<7) /* Reference freq divider mask */ 136#define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
136#define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7) 137#define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7)
137#define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */ 138#define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
@@ -667,22 +668,11 @@ static void imx_break_ctl(struct uart_port *port, int break_state)
667static int imx_setup_ufcr(struct imx_port *sport, unsigned int mode) 668static int imx_setup_ufcr(struct imx_port *sport, unsigned int mode)
668{ 669{
669 unsigned int val; 670 unsigned int val;
670 unsigned int ufcr_rfdiv;
671
672 /* set receiver / transmitter trigger level.
673 * RFDIV is set such way to satisfy requested uartclk value
674 */
675 val = TXTL << 10 | RXTL;
676 ufcr_rfdiv = (clk_get_rate(sport->clk_per) + sport->port.uartclk / 2)
677 / sport->port.uartclk;
678
679 if(!ufcr_rfdiv)
680 ufcr_rfdiv = 1;
681
682 val |= UFCR_RFDIV_REG(ufcr_rfdiv);
683 671
672 /* set receiver / transmitter trigger level */
673 val = readl(sport->port.membase + UFCR) & (UFCR_RFDIV | UFCR_DCEDTE);
674 val |= TXTL << UFCR_TXTL_SHF | RXTL;
684 writel(val, sport->port.membase + UFCR); 675 writel(val, sport->port.membase + UFCR);
685
686 return 0; 676 return 0;
687} 677}
688 678
@@ -754,6 +744,7 @@ static int imx_startup(struct uart_port *port)
754 } 744 }
755 } 745 }
756 746
747 spin_lock_irqsave(&sport->port.lock, flags);
757 /* 748 /*
758 * Finally, clear and enable interrupts 749 * Finally, clear and enable interrupts
759 */ 750 */
@@ -807,7 +798,6 @@ static int imx_startup(struct uart_port *port)
807 /* 798 /*
808 * Enable modem status interrupts 799 * Enable modem status interrupts
809 */ 800 */
810 spin_lock_irqsave(&sport->port.lock,flags);
811 imx_enable_ms(&sport->port); 801 imx_enable_ms(&sport->port);
812 spin_unlock_irqrestore(&sport->port.lock,flags); 802 spin_unlock_irqrestore(&sport->port.lock,flags);
813 803
@@ -837,10 +827,13 @@ static void imx_shutdown(struct uart_port *port)
837{ 827{
838 struct imx_port *sport = (struct imx_port *)port; 828 struct imx_port *sport = (struct imx_port *)port;
839 unsigned long temp; 829 unsigned long temp;
830 unsigned long flags;
840 831
832 spin_lock_irqsave(&sport->port.lock, flags);
841 temp = readl(sport->port.membase + UCR2); 833 temp = readl(sport->port.membase + UCR2);
842 temp &= ~(UCR2_TXEN); 834 temp &= ~(UCR2_TXEN);
843 writel(temp, sport->port.membase + UCR2); 835 writel(temp, sport->port.membase + UCR2);
836 spin_unlock_irqrestore(&sport->port.lock, flags);
844 837
845 if (USE_IRDA(sport)) { 838 if (USE_IRDA(sport)) {
846 struct imxuart_platform_data *pdata; 839 struct imxuart_platform_data *pdata;
@@ -869,12 +862,14 @@ static void imx_shutdown(struct uart_port *port)
869 * Disable all interrupts, port and break condition. 862 * Disable all interrupts, port and break condition.
870 */ 863 */
871 864
865 spin_lock_irqsave(&sport->port.lock, flags);
872 temp = readl(sport->port.membase + UCR1); 866 temp = readl(sport->port.membase + UCR1);
873 temp &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN); 867 temp &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN);
874 if (USE_IRDA(sport)) 868 if (USE_IRDA(sport))
875 temp &= ~(UCR1_IREN); 869 temp &= ~(UCR1_IREN);
876 870
877 writel(temp, sport->port.membase + UCR1); 871 writel(temp, sport->port.membase + UCR1);
872 spin_unlock_irqrestore(&sport->port.lock, flags);
878} 873}
879 874
880static void 875static void
@@ -1217,6 +1212,9 @@ imx_console_write(struct console *co, const char *s, unsigned int count)
1217 struct imx_port *sport = imx_ports[co->index]; 1212 struct imx_port *sport = imx_ports[co->index];
1218 struct imx_port_ucrs old_ucr; 1213 struct imx_port_ucrs old_ucr;
1219 unsigned int ucr1; 1214 unsigned int ucr1;
1215 unsigned long flags;
1216
1217 spin_lock_irqsave(&sport->port.lock, flags);
1220 1218
1221 /* 1219 /*
1222 * First, save UCR1/2/3 and then disable interrupts 1220 * First, save UCR1/2/3 and then disable interrupts
@@ -1242,6 +1240,8 @@ imx_console_write(struct console *co, const char *s, unsigned int count)
1242 while (!(readl(sport->port.membase + USR2) & USR2_TXDC)); 1240 while (!(readl(sport->port.membase + USR2) & USR2_TXDC));
1243 1241
1244 imx_port_ucrs_restore(&sport->port, &old_ucr); 1242 imx_port_ucrs_restore(&sport->port, &old_ucr);
1243
1244 spin_unlock_irqrestore(&sport->port.lock, flags);
1245} 1245}
1246 1246
1247/* 1247/*