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authorSonic Zhang <sonic.zhang@analog.com>2012-05-16 02:22:23 -0400
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2012-05-17 16:25:55 -0400
commitb06d2f20cdf57841b309d30d895b1fd502655e48 (patch)
treedd86c8d2ef8e1d97403988f9dc2d1d4bbd3e7f50 /drivers/tty
parent55e4b8b416849753bd7eacd1f2ac3947fcf1c78e (diff)
serial: bfin_uart: Adapt bf5xx serial driver to bf60x serial4 controller.
The serial4 controller on bf60x is an enhanced version of serial controller on bf5xx. MMR size is 32 bits other than 16 bits. MMR GCTL, MCR and LCR are combined into one control MMR. MSR and LSR are combined into one status MMR. This patch adapts current bf5xx serial driver to serial4 controller on bf60x. Signed-off-by: Sonic Zhang <sonic.zhang@analog.com> Signed-off-by: Bob Liu <lliubbo@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/tty')
-rw-r--r--drivers/tty/serial/bfin_uart.c32
1 files changed, 13 insertions, 19 deletions
diff --git a/drivers/tty/serial/bfin_uart.c b/drivers/tty/serial/bfin_uart.c
index 5832fdef11e9..9acab114d804 100644
--- a/drivers/tty/serial/bfin_uart.c
+++ b/drivers/tty/serial/bfin_uart.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * Blackfin On-Chip Serial Driver 2 * Blackfin On-Chip Serial Driver
3 * 3 *
4 * Copyright 2006-2010 Analog Devices Inc. 4 * Copyright 2006-2011 Analog Devices Inc.
5 * 5 *
6 * Enter bugs at http://blackfin.uclinux.org/ 6 * Enter bugs at http://blackfin.uclinux.org/
7 * 7 *
@@ -35,10 +35,6 @@
35#include <asm/portmux.h> 35#include <asm/portmux.h>
36#include <asm/cacheflush.h> 36#include <asm/cacheflush.h>
37#include <asm/dma.h> 37#include <asm/dma.h>
38
39#define port_membase(uart) (((struct bfin_serial_port *)(uart))->port.membase)
40#define get_lsr_cache(uart) (((struct bfin_serial_port *)(uart))->lsr)
41#define put_lsr_cache(uart, v) (((struct bfin_serial_port *)(uart))->lsr = (v))
42#include <asm/bfin_serial.h> 38#include <asm/bfin_serial.h>
43 39
44#ifdef CONFIG_SERIAL_BFIN_MODULE 40#ifdef CONFIG_SERIAL_BFIN_MODULE
@@ -166,7 +162,7 @@ static void bfin_serial_stop_tx(struct uart_port *port)
166 uart->tx_count = 0; 162 uart->tx_count = 0;
167 uart->tx_done = 1; 163 uart->tx_done = 1;
168#else 164#else
169#ifdef CONFIG_BF54x 165#if defined(CONFIG_BF54x) || defined(CONFIG_BF60x)
170 /* Clear TFI bit */ 166 /* Clear TFI bit */
171 UART_PUT_LSR(uart, TFI); 167 UART_PUT_LSR(uart, TFI);
172#endif 168#endif
@@ -337,7 +333,7 @@ static void bfin_serial_tx_chars(struct bfin_serial_port *uart)
337 struct circ_buf *xmit = &uart->port.state->xmit; 333 struct circ_buf *xmit = &uart->port.state->xmit;
338 334
339 if (uart_circ_empty(xmit) || uart_tx_stopped(&uart->port)) { 335 if (uart_circ_empty(xmit) || uart_tx_stopped(&uart->port)) {
340#ifdef CONFIG_BF54x 336#if defined(CONFIG_BF54x) || defined(CONFIG_BF60x)
341 /* Clear TFI bit */ 337 /* Clear TFI bit */
342 UART_PUT_LSR(uart, TFI); 338 UART_PUT_LSR(uart, TFI);
343#endif 339#endif
@@ -877,11 +873,10 @@ bfin_serial_set_termios(struct uart_port *port, struct ktermios *termios,
877 ier = UART_GET_IER(uart); 873 ier = UART_GET_IER(uart);
878 UART_DISABLE_INTS(uart); 874 UART_DISABLE_INTS(uart);
879 875
880 /* Set DLAB in LCR to Access DLL and DLH */ 876 /* Set DLAB in LCR to Access CLK */
881 UART_SET_DLAB(uart); 877 UART_SET_DLAB(uart);
882 878
883 UART_PUT_DLL(uart, quot & 0xFF); 879 UART_PUT_CLK(uart, quot);
884 UART_PUT_DLH(uart, (quot >> 8) & 0xFF);
885 SSYNC(); 880 SSYNC();
886 881
887 /* Clear DLAB in LCR to Access THR RBR IER */ 882 /* Clear DLAB in LCR to Access THR RBR IER */
@@ -959,12 +954,12 @@ static void bfin_serial_set_ldisc(struct uart_port *port, int ld)
959 switch (ld) { 954 switch (ld) {
960 case N_IRDA: 955 case N_IRDA:
961 val = UART_GET_GCTL(uart); 956 val = UART_GET_GCTL(uart);
962 val |= (IREN | RPOLC); 957 val |= (UMOD_IRDA | RPOLC);
963 UART_PUT_GCTL(uart, val); 958 UART_PUT_GCTL(uart, val);
964 break; 959 break;
965 default: 960 default:
966 val = UART_GET_GCTL(uart); 961 val = UART_GET_GCTL(uart);
967 val &= ~(IREN | RPOLC); 962 val &= ~(UMOD_MASK | RPOLC);
968 UART_PUT_GCTL(uart, val); 963 UART_PUT_GCTL(uart, val);
969 } 964 }
970} 965}
@@ -975,10 +970,10 @@ static void bfin_serial_reset_irda(struct uart_port *port)
975 unsigned short val; 970 unsigned short val;
976 971
977 val = UART_GET_GCTL(uart); 972 val = UART_GET_GCTL(uart);
978 val &= ~(IREN | RPOLC); 973 val &= ~(UMOD_MASK | RPOLC);
979 UART_PUT_GCTL(uart, val); 974 UART_PUT_GCTL(uart, val);
980 SSYNC(); 975 SSYNC();
981 val |= (IREN | RPOLC); 976 val |= (UMOD_IRDA | RPOLC);
982 UART_PUT_GCTL(uart, val); 977 UART_PUT_GCTL(uart, val);
983 SSYNC(); 978 SSYNC();
984} 979}
@@ -1075,7 +1070,7 @@ bfin_serial_console_get_options(struct bfin_serial_port *uart, int *baud,
1075 status = UART_GET_IER(uart) & (ERBFI | ETBEI); 1070 status = UART_GET_IER(uart) & (ERBFI | ETBEI);
1076 if (status == (ERBFI | ETBEI)) { 1071 if (status == (ERBFI | ETBEI)) {
1077 /* ok, the port was enabled */ 1072 /* ok, the port was enabled */
1078 u16 lcr, dlh, dll; 1073 u16 lcr, clk;
1079 1074
1080 lcr = UART_GET_LCR(uart); 1075 lcr = UART_GET_LCR(uart);
1081 1076
@@ -1100,16 +1095,15 @@ bfin_serial_console_get_options(struct bfin_serial_port *uart, int *baud,
1100 *bits = 8; 1095 *bits = 8;
1101 break; 1096 break;
1102 } 1097 }
1103 /* Set DLAB in LCR to Access DLL and DLH */ 1098 /* Set DLAB in LCR to Access CLK */
1104 UART_SET_DLAB(uart); 1099 UART_SET_DLAB(uart);
1105 1100
1106 dll = UART_GET_DLL(uart); 1101 clk = UART_GET_CLK(uart);
1107 dlh = UART_GET_DLH(uart);
1108 1102
1109 /* Clear DLAB in LCR to Access THR RBR IER */ 1103 /* Clear DLAB in LCR to Access THR RBR IER */
1110 UART_CLEAR_DLAB(uart); 1104 UART_CLEAR_DLAB(uart);
1111 1105
1112 *baud = get_sclk() / (16*(dll | dlh << 8)); 1106 *baud = get_sclk() / (16*clk);
1113 } 1107 }
1114 pr_debug("%s:baud = %d, parity = %c, bits= %d\n", __func__, *baud, *parity, *bits); 1108 pr_debug("%s:baud = %d, parity = %c, bits= %d\n", __func__, *baud, *parity, *bits);
1115} 1109}