tty/serial: Add explicit PORT_TEGRA type

Tegra's UART is currently auto-detected as PORT_XSCALE due to register
bit UART_IER.UUE being writable. However, the Tegra documentation states
that this register bit is reserved. Hence, we should not program it.

Instead, the documentation specifies that the UART is 16550 compatible.
However, Tegra does need register bit UART_IER.RTOIE set, which is not
enabled by any 16550 port type. This was not noticed before, since
PORT_XSCALE enables CAP_UUE, which conflates both UUE and RTOIE bit
programming.

This change defines PORT_TEGRA that doesn't set UART_CAP_UUE, but does
set UART_CAP_RTOIE, which is a new capability indicating that the RTOIE
bit needs to be enabled.

Based-on-code-by: Laxman Dewangan <ldewangan@nvidia.com>
Cc: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Alan Cox <alan@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>

2 files changed, 13 insertions, 2 deletions

diff --git a/drivers/tty/serial/8250.c b/drivers/tty/serial/8250.c
index 54482d724fee..a5e290de8c93 100644
--- a/drivers/tty/serial/8250.c
+++ b/drivers/tty/serial/8250.c
@@ -271,7 +271,7 @@ static const struct serial8250_config uart_config[] = {
                 .fifo_size      = 32,
                 .tx_loadsz      = 32,
                 .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
-                .flags          = UART_CAP_FIFO | UART_CAP_UUE,
+                .flags          = UART_CAP_FIFO | UART_CAP_UUE | UART_CAP_RTOIE,
         },
         [PORT_RM9000] = {
                 .name           = "RM9000",
@@ -301,6 +301,14 @@ static const struct serial8250_config uart_config[] = {
                 .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
                 .flags          = UART_CAP_FIFO | UART_CAP_AFE,
         },
+        [PORT_TEGRA] = {
+                .name           = "Tegra",
+                .fifo_size      = 32,
+                .tx_loadsz      = 8,
+                .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
+                                  UART_FCR_T_TRIG_01,
+                .flags          = UART_CAP_FIFO | UART_CAP_RTOIE,
+        },
 };
 
 #if defined(CONFIG_MIPS_ALCHEMY)
@@ -2403,7 +2411,9 @@ serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
                         UART_ENABLE_MS(&up->port, termios->c_cflag))
                 up->ier |= UART_IER_MSI;
         if (up->capabilities & UART_CAP_UUE)
-                up->ier |= UART_IER_UUE | UART_IER_RTOIE;
+                up->ier |= UART_IER_UUE;
+        if (up->capabilities & UART_CAP_RTOIE)
+                up->ier |= UART_IER_RTOIE;
 
         serial_out(up, UART_IER, up->ier);
 
diff --git a/drivers/tty/serial/8250.h b/drivers/tty/serial/8250.h
index d13b586c0f72..6edf4a6a22d4 100644
--- a/drivers/tty/serial/8250.h
+++ b/drivers/tty/serial/8250.h
@@ -42,6 +42,7 @@ struct serial8250_config {
 #define UART_CAP_SLEEP  (1 << 10)       /* UART has IER sleep */
 #define UART_CAP_AFE    (1 << 11)       /* MCR-based hw flow control */
 #define UART_CAP_UUE    (1 << 12)       /* UART needs IER bit 6 set (Xscale) */
+#define UART_CAP_RTOIE  (1 << 13)       /* UART needs IER bit 4 set (Xscale, Tegra) */
 
 #define UART_BUG_QUOT   (1 << 0)        /* UART has buggy quot LSB */
 #define UART_BUG_TXEN   (1 << 1)        /* UART has buggy TX IIR status */