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authorGreg Kroah-Hartman <gregkh@suse.de>2011-01-13 15:10:18 -0500
committerGreg Kroah-Hartman <gregkh@suse.de>2011-01-13 15:10:18 -0500
commitab4382d27412e7e3e7c936e8d50d8888dfac3df8 (patch)
tree51d96dea2431140358784b6b426715f37f74fd53 /drivers/tty/serial/jsm
parent728674a7e466628df2aeec6d11a2ae1ef968fb67 (diff)
tty: move drivers/serial/ to drivers/tty/serial/
The serial drivers are really just tty drivers, so move them to drivers/tty/ to make things a bit neater overall. This is part of the tty/serial driver movement proceedure as proposed by Arnd Bergmann and approved by everyone involved a number of months ago. Cc: Arnd Bergmann <arnd@arndb.de> Cc: Alan Cox <alan@lxorguk.ukuu.org.uk> Cc: Geert Uytterhoeven <geert@linux-m68k.org> Cc: Rogier Wolff <R.E.Wolff@bitwizard.nl> Cc: Michael H. Warfield <mhw@wittsend.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'drivers/tty/serial/jsm')
-rw-r--r--drivers/tty/serial/jsm/Makefile8
-rw-r--r--drivers/tty/serial/jsm/jsm.h388
-rw-r--r--drivers/tty/serial/jsm/jsm_driver.c297
-rw-r--r--drivers/tty/serial/jsm/jsm_neo.c1412
-rw-r--r--drivers/tty/serial/jsm/jsm_tty.c910
5 files changed, 3015 insertions, 0 deletions
diff --git a/drivers/tty/serial/jsm/Makefile b/drivers/tty/serial/jsm/Makefile
new file mode 100644
index 000000000000..e46b6e0f8b18
--- /dev/null
+++ b/drivers/tty/serial/jsm/Makefile
@@ -0,0 +1,8 @@
1#
2# Makefile for Jasmine adapter
3#
4
5obj-$(CONFIG_SERIAL_JSM) += jsm.o
6
7jsm-objs := jsm_driver.o jsm_neo.o jsm_tty.o
8
diff --git a/drivers/tty/serial/jsm/jsm.h b/drivers/tty/serial/jsm/jsm.h
new file mode 100644
index 000000000000..38a509c684cd
--- /dev/null
+++ b/drivers/tty/serial/jsm/jsm.h
@@ -0,0 +1,388 @@
1/************************************************************************
2 * Copyright 2003 Digi International (www.digi.com)
3 *
4 * Copyright (C) 2004 IBM Corporation. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2, or (at your option)
9 * any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY, EXPRESS OR IMPLIED; without even the
13 * implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
14 * PURPOSE. See the GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 * Temple Place - Suite 330, Boston,
19 * MA 02111-1307, USA.
20 *
21 * Contact Information:
22 * Scott H Kilau <Scott_Kilau@digi.com>
23 * Wendy Xiong <wendyx@us.ibm.com>
24 *
25 ***********************************************************************/
26
27#ifndef __JSM_DRIVER_H
28#define __JSM_DRIVER_H
29
30#include <linux/kernel.h>
31#include <linux/types.h> /* To pick up the varions Linux types */
32#include <linux/tty.h>
33#include <linux/serial_core.h>
34#include <linux/device.h>
35
36/*
37 * Debugging levels can be set using debug insmod variable
38 * They can also be compiled out completely.
39 */
40enum {
41 DBG_INIT = 0x01,
42 DBG_BASIC = 0x02,
43 DBG_CORE = 0x04,
44 DBG_OPEN = 0x08,
45 DBG_CLOSE = 0x10,
46 DBG_READ = 0x20,
47 DBG_WRITE = 0x40,
48 DBG_IOCTL = 0x80,
49 DBG_PROC = 0x100,
50 DBG_PARAM = 0x200,
51 DBG_PSCAN = 0x400,
52 DBG_EVENT = 0x800,
53 DBG_DRAIN = 0x1000,
54 DBG_MSIGS = 0x2000,
55 DBG_MGMT = 0x4000,
56 DBG_INTR = 0x8000,
57 DBG_CARR = 0x10000,
58};
59
60#define jsm_printk(nlevel, klevel, pdev, fmt, args...) \
61 if ((DBG_##nlevel & jsm_debug)) \
62 dev_printk(KERN_##klevel, pdev->dev, fmt, ## args)
63
64#define MAXLINES 256
65#define MAXPORTS 8
66#define MAX_STOPS_SENT 5
67
68/* Board type definitions */
69
70#define T_NEO 0000
71#define T_CLASSIC 0001
72#define T_PCIBUS 0400
73
74/* Board State Definitions */
75
76#define BD_RUNNING 0x0
77#define BD_REASON 0x7f
78#define BD_NOTFOUND 0x1
79#define BD_NOIOPORT 0x2
80#define BD_NOMEM 0x3
81#define BD_NOBIOS 0x4
82#define BD_NOFEP 0x5
83#define BD_FAILED 0x6
84#define BD_ALLOCATED 0x7
85#define BD_TRIBOOT 0x8
86#define BD_BADKME 0x80
87
88
89/* 4 extra for alignment play space */
90#define WRITEBUFLEN ((4096) + 4)
91#define MYFLIPLEN N_TTY_BUF_SIZE
92
93#define JSM_VERSION "jsm: 1.2-1-INKERNEL"
94#define JSM_PARTNUM "40002438_A-INKERNEL"
95
96struct jsm_board;
97struct jsm_channel;
98
99/************************************************************************
100 * Per board operations structure *
101 ************************************************************************/
102struct board_ops {
103 irq_handler_t intr;
104 void (*uart_init) (struct jsm_channel *ch);
105 void (*uart_off) (struct jsm_channel *ch);
106 void (*param) (struct jsm_channel *ch);
107 void (*assert_modem_signals) (struct jsm_channel *ch);
108 void (*flush_uart_write) (struct jsm_channel *ch);
109 void (*flush_uart_read) (struct jsm_channel *ch);
110 void (*disable_receiver) (struct jsm_channel *ch);
111 void (*enable_receiver) (struct jsm_channel *ch);
112 void (*send_break) (struct jsm_channel *ch);
113 void (*clear_break) (struct jsm_channel *ch, int);
114 void (*send_start_character) (struct jsm_channel *ch);
115 void (*send_stop_character) (struct jsm_channel *ch);
116 void (*copy_data_from_queue_to_uart) (struct jsm_channel *ch);
117 u32 (*get_uart_bytes_left) (struct jsm_channel *ch);
118 void (*send_immediate_char) (struct jsm_channel *ch, unsigned char);
119};
120
121
122/*
123 * Per-board information
124 */
125struct jsm_board
126{
127 int boardnum; /* Board number: 0-32 */
128
129 int type; /* Type of board */
130 u8 rev; /* PCI revision ID */
131 struct pci_dev *pci_dev;
132 u32 maxports; /* MAX ports this board can handle */
133
134 spinlock_t bd_intr_lock; /* Used to protect the poller tasklet and
135 * the interrupt routine from each other.
136 */
137
138 u32 nasync; /* Number of ports on card */
139
140 u32 irq; /* Interrupt request number */
141
142 u64 membase; /* Start of base memory of the card */
143 u64 membase_end; /* End of base memory of the card */
144
145 u8 __iomem *re_map_membase;/* Remapped memory of the card */
146
147 u64 iobase; /* Start of io base of the card */
148 u64 iobase_end; /* End of io base of the card */
149
150 u32 bd_uart_offset; /* Space between each UART */
151
152 struct jsm_channel *channels[MAXPORTS]; /* array of pointers to our channels. */
153 char *flipbuf; /* Our flip buffer, alloced if board is found */
154
155 u32 bd_dividend; /* Board/UARTs specific dividend */
156
157 struct board_ops *bd_ops;
158
159 struct list_head jsm_board_entry;
160};
161
162/************************************************************************
163 * Device flag definitions for ch_flags.
164 ************************************************************************/
165#define CH_PRON 0x0001 /* Printer on string */
166#define CH_STOP 0x0002 /* Output is stopped */
167#define CH_STOPI 0x0004 /* Input is stopped */
168#define CH_CD 0x0008 /* Carrier is present */
169#define CH_FCAR 0x0010 /* Carrier forced on */
170#define CH_HANGUP 0x0020 /* Hangup received */
171
172#define CH_RECEIVER_OFF 0x0040 /* Receiver is off */
173#define CH_OPENING 0x0080 /* Port in fragile open state */
174#define CH_CLOSING 0x0100 /* Port in fragile close state */
175#define CH_FIFO_ENABLED 0x0200 /* Port has FIFOs enabled */
176#define CH_TX_FIFO_EMPTY 0x0400 /* TX Fifo is completely empty */
177#define CH_TX_FIFO_LWM 0x0800 /* TX Fifo is below Low Water */
178#define CH_BREAK_SENDING 0x1000 /* Break is being sent */
179#define CH_LOOPBACK 0x2000 /* Channel is in lookback mode */
180#define CH_FLIPBUF_IN_USE 0x4000 /* Channel's flipbuf is in use */
181#define CH_BAUD0 0x08000 /* Used for checking B0 transitions */
182
183/* Our Read/Error/Write queue sizes */
184#define RQUEUEMASK 0x1FFF /* 8 K - 1 */
185#define EQUEUEMASK 0x1FFF /* 8 K - 1 */
186#define WQUEUEMASK 0x0FFF /* 4 K - 1 */
187#define RQUEUESIZE (RQUEUEMASK + 1)
188#define EQUEUESIZE RQUEUESIZE
189#define WQUEUESIZE (WQUEUEMASK + 1)
190
191
192/************************************************************************
193 * Channel information structure.
194 ************************************************************************/
195struct jsm_channel {
196 struct uart_port uart_port;
197 struct jsm_board *ch_bd; /* Board structure pointer */
198
199 spinlock_t ch_lock; /* provide for serialization */
200 wait_queue_head_t ch_flags_wait;
201
202 u32 ch_portnum; /* Port number, 0 offset. */
203 u32 ch_open_count; /* open count */
204 u32 ch_flags; /* Channel flags */
205
206 u64 ch_close_delay; /* How long we should drop RTS/DTR for */
207
208 tcflag_t ch_c_iflag; /* channel iflags */
209 tcflag_t ch_c_cflag; /* channel cflags */
210 tcflag_t ch_c_oflag; /* channel oflags */
211 tcflag_t ch_c_lflag; /* channel lflags */
212 u8 ch_stopc; /* Stop character */
213 u8 ch_startc; /* Start character */
214
215 u8 ch_mostat; /* FEP output modem status */
216 u8 ch_mistat; /* FEP input modem status */
217
218 struct neo_uart_struct __iomem *ch_neo_uart; /* Pointer to the "mapped" UART struct */
219 u8 ch_cached_lsr; /* Cached value of the LSR register */
220
221 u8 *ch_rqueue; /* Our read queue buffer - malloc'ed */
222 u16 ch_r_head; /* Head location of the read queue */
223 u16 ch_r_tail; /* Tail location of the read queue */
224
225 u8 *ch_equeue; /* Our error queue buffer - malloc'ed */
226 u16 ch_e_head; /* Head location of the error queue */
227 u16 ch_e_tail; /* Tail location of the error queue */
228
229 u8 *ch_wqueue; /* Our write queue buffer - malloc'ed */
230 u16 ch_w_head; /* Head location of the write queue */
231 u16 ch_w_tail; /* Tail location of the write queue */
232
233 u64 ch_rxcount; /* total of data received so far */
234 u64 ch_txcount; /* total of data transmitted so far */
235
236 u8 ch_r_tlevel; /* Receive Trigger level */
237 u8 ch_t_tlevel; /* Transmit Trigger level */
238
239 u8 ch_r_watermark; /* Receive Watermark */
240
241
242 u32 ch_stops_sent; /* How many times I have sent a stop character
243 * to try to stop the other guy sending.
244 */
245 u64 ch_err_parity; /* Count of parity errors on channel */
246 u64 ch_err_frame; /* Count of framing errors on channel */
247 u64 ch_err_break; /* Count of breaks on channel */
248 u64 ch_err_overrun; /* Count of overruns on channel */
249
250 u64 ch_xon_sends; /* Count of xons transmitted */
251 u64 ch_xoff_sends; /* Count of xoffs transmitted */
252};
253
254
255/************************************************************************
256 * Per channel/port NEO UART structure *
257 ************************************************************************
258 * Base Structure Entries Usage Meanings to Host *
259 * *
260 * W = read write R = read only *
261 * U = Unused. *
262 ************************************************************************/
263
264struct neo_uart_struct {
265 u8 txrx; /* WR RHR/THR - Holding Reg */
266 u8 ier; /* WR IER - Interrupt Enable Reg */
267 u8 isr_fcr; /* WR ISR/FCR - Interrupt Status Reg/Fifo Control Reg */
268 u8 lcr; /* WR LCR - Line Control Reg */
269 u8 mcr; /* WR MCR - Modem Control Reg */
270 u8 lsr; /* WR LSR - Line Status Reg */
271 u8 msr; /* WR MSR - Modem Status Reg */
272 u8 spr; /* WR SPR - Scratch Pad Reg */
273 u8 fctr; /* WR FCTR - Feature Control Reg */
274 u8 efr; /* WR EFR - Enhanced Function Reg */
275 u8 tfifo; /* WR TXCNT/TXTRG - Transmit FIFO Reg */
276 u8 rfifo; /* WR RXCNT/RXTRG - Recieve FIFO Reg */
277 u8 xoffchar1; /* WR XOFF 1 - XOff Character 1 Reg */
278 u8 xoffchar2; /* WR XOFF 2 - XOff Character 2 Reg */
279 u8 xonchar1; /* WR XON 1 - Xon Character 1 Reg */
280 u8 xonchar2; /* WR XON 2 - XOn Character 2 Reg */
281
282 u8 reserved1[0x2ff - 0x200]; /* U Reserved by Exar */
283 u8 txrxburst[64]; /* RW 64 bytes of RX/TX FIFO Data */
284 u8 reserved2[0x37f - 0x340]; /* U Reserved by Exar */
285 u8 rxburst_with_errors[64]; /* R 64 bytes of RX FIFO Data + LSR */
286};
287
288/* Where to read the extended interrupt register (32bits instead of 8bits) */
289#define UART_17158_POLL_ADDR_OFFSET 0x80
290
291/*
292 * These are the redefinitions for the FCTR on the XR17C158, since
293 * Exar made them different than their earlier design. (XR16C854)
294 */
295
296/* These are only applicable when table D is selected */
297#define UART_17158_FCTR_RTS_NODELAY 0x00
298#define UART_17158_FCTR_RTS_4DELAY 0x01
299#define UART_17158_FCTR_RTS_6DELAY 0x02
300#define UART_17158_FCTR_RTS_8DELAY 0x03
301#define UART_17158_FCTR_RTS_12DELAY 0x12
302#define UART_17158_FCTR_RTS_16DELAY 0x05
303#define UART_17158_FCTR_RTS_20DELAY 0x13
304#define UART_17158_FCTR_RTS_24DELAY 0x06
305#define UART_17158_FCTR_RTS_28DELAY 0x14
306#define UART_17158_FCTR_RTS_32DELAY 0x07
307#define UART_17158_FCTR_RTS_36DELAY 0x16
308#define UART_17158_FCTR_RTS_40DELAY 0x08
309#define UART_17158_FCTR_RTS_44DELAY 0x09
310#define UART_17158_FCTR_RTS_48DELAY 0x10
311#define UART_17158_FCTR_RTS_52DELAY 0x11
312
313#define UART_17158_FCTR_RTS_IRDA 0x10
314#define UART_17158_FCTR_RS485 0x20
315#define UART_17158_FCTR_TRGA 0x00
316#define UART_17158_FCTR_TRGB 0x40
317#define UART_17158_FCTR_TRGC 0x80
318#define UART_17158_FCTR_TRGD 0xC0
319
320/* 17158 trigger table selects.. */
321#define UART_17158_FCTR_BIT6 0x40
322#define UART_17158_FCTR_BIT7 0x80
323
324/* 17158 TX/RX memmapped buffer offsets */
325#define UART_17158_RX_FIFOSIZE 64
326#define UART_17158_TX_FIFOSIZE 64
327
328/* 17158 Extended IIR's */
329#define UART_17158_IIR_RDI_TIMEOUT 0x0C /* Receiver data TIMEOUT */
330#define UART_17158_IIR_XONXOFF 0x10 /* Received an XON/XOFF char */
331#define UART_17158_IIR_HWFLOW_STATE_CHANGE 0x20 /* CTS/DSR or RTS/DTR state change */
332#define UART_17158_IIR_FIFO_ENABLED 0xC0 /* 16550 FIFOs are Enabled */
333
334/*
335 * These are the extended interrupts that get sent
336 * back to us from the UART's 32bit interrupt register
337 */
338#define UART_17158_RX_LINE_STATUS 0x1 /* RX Ready */
339#define UART_17158_RXRDY_TIMEOUT 0x2 /* RX Ready Timeout */
340#define UART_17158_TXRDY 0x3 /* TX Ready */
341#define UART_17158_MSR 0x4 /* Modem State Change */
342#define UART_17158_TX_AND_FIFO_CLR 0x40 /* Transmitter Holding Reg Empty */
343#define UART_17158_RX_FIFO_DATA_ERROR 0x80 /* UART detected an RX FIFO Data error */
344
345/*
346 * These are the EXTENDED definitions for the 17C158's Interrupt
347 * Enable Register.
348 */
349#define UART_17158_EFR_ECB 0x10 /* Enhanced control bit */
350#define UART_17158_EFR_IXON 0x2 /* Receiver compares Xon1/Xoff1 */
351#define UART_17158_EFR_IXOFF 0x8 /* Transmit Xon1/Xoff1 */
352#define UART_17158_EFR_RTSDTR 0x40 /* Auto RTS/DTR Flow Control Enable */
353#define UART_17158_EFR_CTSDSR 0x80 /* Auto CTS/DSR Flow COntrol Enable */
354
355#define UART_17158_XOFF_DETECT 0x1 /* Indicates whether chip saw an incoming XOFF char */
356#define UART_17158_XON_DETECT 0x2 /* Indicates whether chip saw an incoming XON char */
357
358#define UART_17158_IER_RSVD1 0x10 /* Reserved by Exar */
359#define UART_17158_IER_XOFF 0x20 /* Xoff Interrupt Enable */
360#define UART_17158_IER_RTSDTR 0x40 /* Output Interrupt Enable */
361#define UART_17158_IER_CTSDSR 0x80 /* Input Interrupt Enable */
362
363#define PCI_DEVICE_NEO_2DB9_PCI_NAME "Neo 2 - DB9 Universal PCI"
364#define PCI_DEVICE_NEO_2DB9PRI_PCI_NAME "Neo 2 - DB9 Universal PCI - Powered Ring Indicator"
365#define PCI_DEVICE_NEO_2RJ45_PCI_NAME "Neo 2 - RJ45 Universal PCI"
366#define PCI_DEVICE_NEO_2RJ45PRI_PCI_NAME "Neo 2 - RJ45 Universal PCI - Powered Ring Indicator"
367#define PCIE_DEVICE_NEO_IBM_PCI_NAME "Neo 4 - PCI Express - IBM"
368
369/*
370 * Our Global Variables.
371 */
372extern struct uart_driver jsm_uart_driver;
373extern struct board_ops jsm_neo_ops;
374extern int jsm_debug;
375
376/*************************************************************************
377 *
378 * Prototypes for non-static functions used in more than one module
379 *
380 *************************************************************************/
381int jsm_tty_write(struct uart_port *port);
382int jsm_tty_init(struct jsm_board *);
383int jsm_uart_port_init(struct jsm_board *);
384int jsm_remove_uart_port(struct jsm_board *);
385void jsm_input(struct jsm_channel *ch);
386void jsm_check_queue_flow_control(struct jsm_channel *ch);
387
388#endif
diff --git a/drivers/tty/serial/jsm/jsm_driver.c b/drivers/tty/serial/jsm/jsm_driver.c
new file mode 100644
index 000000000000..18f548449c63
--- /dev/null
+++ b/drivers/tty/serial/jsm/jsm_driver.c
@@ -0,0 +1,297 @@
1/************************************************************************
2 * Copyright 2003 Digi International (www.digi.com)
3 *
4 * Copyright (C) 2004 IBM Corporation. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2, or (at your option)
9 * any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY, EXPRESS OR IMPLIED; without even the
13 * implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
14 * PURPOSE. See the GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 * Temple Place - Suite 330, Boston,
19 * MA 02111-1307, USA.
20 *
21 * Contact Information:
22 * Scott H Kilau <Scott_Kilau@digi.com>
23 * Wendy Xiong <wendyx@us.ibm.com>
24 *
25 *
26 ***********************************************************************/
27#include <linux/moduleparam.h>
28#include <linux/pci.h>
29#include <linux/slab.h>
30
31#include "jsm.h"
32
33MODULE_AUTHOR("Digi International, http://www.digi.com");
34MODULE_DESCRIPTION("Driver for the Digi International "
35 "Neo PCI based product line");
36MODULE_LICENSE("GPL");
37MODULE_SUPPORTED_DEVICE("jsm");
38
39#define JSM_DRIVER_NAME "jsm"
40#define NR_PORTS 32
41#define JSM_MINOR_START 0
42
43struct uart_driver jsm_uart_driver = {
44 .owner = THIS_MODULE,
45 .driver_name = JSM_DRIVER_NAME,
46 .dev_name = "ttyn",
47 .major = 0,
48 .minor = JSM_MINOR_START,
49 .nr = NR_PORTS,
50};
51
52static pci_ers_result_t jsm_io_error_detected(struct pci_dev *pdev,
53 pci_channel_state_t state);
54static pci_ers_result_t jsm_io_slot_reset(struct pci_dev *pdev);
55static void jsm_io_resume(struct pci_dev *pdev);
56
57static struct pci_error_handlers jsm_err_handler = {
58 .error_detected = jsm_io_error_detected,
59 .slot_reset = jsm_io_slot_reset,
60 .resume = jsm_io_resume,
61};
62
63int jsm_debug;
64module_param(jsm_debug, int, 0);
65MODULE_PARM_DESC(jsm_debug, "Driver debugging level");
66
67static int __devinit jsm_probe_one(struct pci_dev *pdev, const struct pci_device_id *ent)
68{
69 int rc = 0;
70 struct jsm_board *brd;
71 static int adapter_count = 0;
72
73 rc = pci_enable_device(pdev);
74 if (rc) {
75 dev_err(&pdev->dev, "Device enable FAILED\n");
76 goto out;
77 }
78
79 rc = pci_request_regions(pdev, "jsm");
80 if (rc) {
81 dev_err(&pdev->dev, "pci_request_region FAILED\n");
82 goto out_disable_device;
83 }
84
85 brd = kzalloc(sizeof(struct jsm_board), GFP_KERNEL);
86 if (!brd) {
87 dev_err(&pdev->dev,
88 "memory allocation for board structure failed\n");
89 rc = -ENOMEM;
90 goto out_release_regions;
91 }
92
93 /* store the info for the board we've found */
94 brd->boardnum = adapter_count++;
95 brd->pci_dev = pdev;
96 if (pdev->device == PCIE_DEVICE_ID_NEO_4_IBM)
97 brd->maxports = 4;
98 else if (pdev->device == PCI_DEVICE_ID_DIGI_NEO_8)
99 brd->maxports = 8;
100 else
101 brd->maxports = 2;
102
103 spin_lock_init(&brd->bd_intr_lock);
104
105 /* store which revision we have */
106 brd->rev = pdev->revision;
107
108 brd->irq = pdev->irq;
109
110 jsm_printk(INIT, INFO, &brd->pci_dev,
111 "jsm_found_board - NEO adapter\n");
112
113 /* get the PCI Base Address Registers */
114 brd->membase = pci_resource_start(pdev, 0);
115 brd->membase_end = pci_resource_end(pdev, 0);
116
117 if (brd->membase & 1)
118 brd->membase &= ~3;
119 else
120 brd->membase &= ~15;
121
122 /* Assign the board_ops struct */
123 brd->bd_ops = &jsm_neo_ops;
124
125 brd->bd_uart_offset = 0x200;
126 brd->bd_dividend = 921600;
127
128 brd->re_map_membase = ioremap(brd->membase, 0x1000);
129 if (!brd->re_map_membase) {
130 dev_err(&pdev->dev,
131 "card has no PCI Memory resources, "
132 "failing board.\n");
133 rc = -ENOMEM;
134 goto out_kfree_brd;
135 }
136
137 rc = request_irq(brd->irq, brd->bd_ops->intr,
138 IRQF_SHARED, "JSM", brd);
139 if (rc) {
140 printk(KERN_WARNING "Failed to hook IRQ %d\n",brd->irq);
141 goto out_iounmap;
142 }
143
144 rc = jsm_tty_init(brd);
145 if (rc < 0) {
146 dev_err(&pdev->dev, "Can't init tty devices (%d)\n", rc);
147 rc = -ENXIO;
148 goto out_free_irq;
149 }
150
151 rc = jsm_uart_port_init(brd);
152 if (rc < 0) {
153 /* XXX: leaking all resources from jsm_tty_init here! */
154 dev_err(&pdev->dev, "Can't init uart port (%d)\n", rc);
155 rc = -ENXIO;
156 goto out_free_irq;
157 }
158
159 /* Log the information about the board */
160 dev_info(&pdev->dev, "board %d: Digi Neo (rev %d), irq %d\n",
161 adapter_count, brd->rev, brd->irq);
162
163 /*
164 * allocate flip buffer for board.
165 *
166 * Okay to malloc with GFP_KERNEL, we are not at interrupt
167 * context, and there are no locks held.
168 */
169 brd->flipbuf = kzalloc(MYFLIPLEN, GFP_KERNEL);
170 if (!brd->flipbuf) {
171 /* XXX: leaking all resources from jsm_tty_init and
172 jsm_uart_port_init here! */
173 dev_err(&pdev->dev, "memory allocation for flipbuf failed\n");
174 rc = -ENOMEM;
175 goto out_free_uart;
176 }
177
178 pci_set_drvdata(pdev, brd);
179 pci_save_state(pdev);
180
181 return 0;
182 out_free_uart:
183 jsm_remove_uart_port(brd);
184 out_free_irq:
185 jsm_remove_uart_port(brd);
186 free_irq(brd->irq, brd);
187 out_iounmap:
188 iounmap(brd->re_map_membase);
189 out_kfree_brd:
190 kfree(brd);
191 out_release_regions:
192 pci_release_regions(pdev);
193 out_disable_device:
194 pci_disable_device(pdev);
195 out:
196 return rc;
197}
198
199static void __devexit jsm_remove_one(struct pci_dev *pdev)
200{
201 struct jsm_board *brd = pci_get_drvdata(pdev);
202 int i = 0;
203
204 jsm_remove_uart_port(brd);
205
206 free_irq(brd->irq, brd);
207 iounmap(brd->re_map_membase);
208
209 /* Free all allocated channels structs */
210 for (i = 0; i < brd->maxports; i++) {
211 if (brd->channels[i]) {
212 kfree(brd->channels[i]->ch_rqueue);
213 kfree(brd->channels[i]->ch_equeue);
214 kfree(brd->channels[i]->ch_wqueue);
215 kfree(brd->channels[i]);
216 }
217 }
218
219 pci_release_regions(pdev);
220 pci_disable_device(pdev);
221 kfree(brd->flipbuf);
222 kfree(brd);
223}
224
225static struct pci_device_id jsm_pci_tbl[] = {
226 { PCI_DEVICE(PCI_VENDOR_ID_DIGI, PCI_DEVICE_ID_NEO_2DB9), 0, 0, 0 },
227 { PCI_DEVICE(PCI_VENDOR_ID_DIGI, PCI_DEVICE_ID_NEO_2DB9PRI), 0, 0, 1 },
228 { PCI_DEVICE(PCI_VENDOR_ID_DIGI, PCI_DEVICE_ID_NEO_2RJ45), 0, 0, 2 },
229 { PCI_DEVICE(PCI_VENDOR_ID_DIGI, PCI_DEVICE_ID_NEO_2RJ45PRI), 0, 0, 3 },
230 { PCI_DEVICE(PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_4_IBM), 0, 0, 4 },
231 { PCI_DEVICE(PCI_VENDOR_ID_DIGI, PCI_DEVICE_ID_DIGI_NEO_8), 0, 0, 5 },
232 { 0, }
233};
234MODULE_DEVICE_TABLE(pci, jsm_pci_tbl);
235
236static struct pci_driver jsm_driver = {
237 .name = "jsm",
238 .id_table = jsm_pci_tbl,
239 .probe = jsm_probe_one,
240 .remove = __devexit_p(jsm_remove_one),
241 .err_handler = &jsm_err_handler,
242};
243
244static pci_ers_result_t jsm_io_error_detected(struct pci_dev *pdev,
245 pci_channel_state_t state)
246{
247 struct jsm_board *brd = pci_get_drvdata(pdev);
248
249 jsm_remove_uart_port(brd);
250
251 return PCI_ERS_RESULT_NEED_RESET;
252}
253
254static pci_ers_result_t jsm_io_slot_reset(struct pci_dev *pdev)
255{
256 int rc;
257
258 rc = pci_enable_device(pdev);
259
260 if (rc)
261 return PCI_ERS_RESULT_DISCONNECT;
262
263 pci_set_master(pdev);
264
265 return PCI_ERS_RESULT_RECOVERED;
266}
267
268static void jsm_io_resume(struct pci_dev *pdev)
269{
270 struct jsm_board *brd = pci_get_drvdata(pdev);
271
272 pci_restore_state(pdev);
273
274 jsm_uart_port_init(brd);
275}
276
277static int __init jsm_init_module(void)
278{
279 int rc;
280
281 rc = uart_register_driver(&jsm_uart_driver);
282 if (!rc) {
283 rc = pci_register_driver(&jsm_driver);
284 if (rc)
285 uart_unregister_driver(&jsm_uart_driver);
286 }
287 return rc;
288}
289
290static void __exit jsm_exit_module(void)
291{
292 pci_unregister_driver(&jsm_driver);
293 uart_unregister_driver(&jsm_uart_driver);
294}
295
296module_init(jsm_init_module);
297module_exit(jsm_exit_module);
diff --git a/drivers/tty/serial/jsm/jsm_neo.c b/drivers/tty/serial/jsm/jsm_neo.c
new file mode 100644
index 000000000000..7960d9633c15
--- /dev/null
+++ b/drivers/tty/serial/jsm/jsm_neo.c
@@ -0,0 +1,1412 @@
1/************************************************************************
2 * Copyright 2003 Digi International (www.digi.com)
3 *
4 * Copyright (C) 2004 IBM Corporation. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2, or (at your option)
9 * any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY, EXPRESS OR IMPLIED; without even the
13 * implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
14 * PURPOSE. See the GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 * Temple Place - Suite 330, Boston,
19 * MA 02111-1307, USA.
20 *
21 * Contact Information:
22 * Scott H Kilau <Scott_Kilau@digi.com>
23 * Wendy Xiong <wendyx@us.ibm.com>
24 *
25 ***********************************************************************/
26#include <linux/delay.h> /* For udelay */
27#include <linux/serial_reg.h> /* For the various UART offsets */
28#include <linux/tty.h>
29#include <linux/pci.h>
30#include <asm/io.h>
31
32#include "jsm.h" /* Driver main header file */
33
34static u32 jsm_offset_table[8] = { 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 };
35
36/*
37 * This function allows calls to ensure that all outstanding
38 * PCI writes have been completed, by doing a PCI read against
39 * a non-destructive, read-only location on the Neo card.
40 *
41 * In this case, we are reading the DVID (Read-only Device Identification)
42 * value of the Neo card.
43 */
44static inline void neo_pci_posting_flush(struct jsm_board *bd)
45{
46 readb(bd->re_map_membase + 0x8D);
47}
48
49static void neo_set_cts_flow_control(struct jsm_channel *ch)
50{
51 u8 ier, efr;
52 ier = readb(&ch->ch_neo_uart->ier);
53 efr = readb(&ch->ch_neo_uart->efr);
54
55 jsm_printk(PARAM, INFO, &ch->ch_bd->pci_dev, "Setting CTSFLOW\n");
56
57 /* Turn on auto CTS flow control */
58 ier |= (UART_17158_IER_CTSDSR);
59 efr |= (UART_17158_EFR_ECB | UART_17158_EFR_CTSDSR);
60
61 /* Turn off auto Xon flow control */
62 efr &= ~(UART_17158_EFR_IXON);
63
64 /* Why? Becuz Exar's spec says we have to zero it out before setting it */
65 writeb(0, &ch->ch_neo_uart->efr);
66
67 /* Turn on UART enhanced bits */
68 writeb(efr, &ch->ch_neo_uart->efr);
69
70 /* Turn on table D, with 8 char hi/low watermarks */
71 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_4DELAY), &ch->ch_neo_uart->fctr);
72
73 /* Feed the UART our trigger levels */
74 writeb(8, &ch->ch_neo_uart->tfifo);
75 ch->ch_t_tlevel = 8;
76
77 writeb(ier, &ch->ch_neo_uart->ier);
78}
79
80static void neo_set_rts_flow_control(struct jsm_channel *ch)
81{
82 u8 ier, efr;
83 ier = readb(&ch->ch_neo_uart->ier);
84 efr = readb(&ch->ch_neo_uart->efr);
85
86 jsm_printk(PARAM, INFO, &ch->ch_bd->pci_dev, "Setting RTSFLOW\n");
87
88 /* Turn on auto RTS flow control */
89 ier |= (UART_17158_IER_RTSDTR);
90 efr |= (UART_17158_EFR_ECB | UART_17158_EFR_RTSDTR);
91
92 /* Turn off auto Xoff flow control */
93 ier &= ~(UART_17158_IER_XOFF);
94 efr &= ~(UART_17158_EFR_IXOFF);
95
96 /* Why? Becuz Exar's spec says we have to zero it out before setting it */
97 writeb(0, &ch->ch_neo_uart->efr);
98
99 /* Turn on UART enhanced bits */
100 writeb(efr, &ch->ch_neo_uart->efr);
101
102 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_4DELAY), &ch->ch_neo_uart->fctr);
103 ch->ch_r_watermark = 4;
104
105 writeb(56, &ch->ch_neo_uart->rfifo);
106 ch->ch_r_tlevel = 56;
107
108 writeb(ier, &ch->ch_neo_uart->ier);
109
110 /*
111 * From the Neo UART spec sheet:
112 * The auto RTS/DTR function must be started by asserting
113 * RTS/DTR# output pin (MCR bit-0 or 1 to logic 1 after
114 * it is enabled.
115 */
116 ch->ch_mostat |= (UART_MCR_RTS);
117}
118
119
120static void neo_set_ixon_flow_control(struct jsm_channel *ch)
121{
122 u8 ier, efr;
123 ier = readb(&ch->ch_neo_uart->ier);
124 efr = readb(&ch->ch_neo_uart->efr);
125
126 jsm_printk(PARAM, INFO, &ch->ch_bd->pci_dev, "Setting IXON FLOW\n");
127
128 /* Turn off auto CTS flow control */
129 ier &= ~(UART_17158_IER_CTSDSR);
130 efr &= ~(UART_17158_EFR_CTSDSR);
131
132 /* Turn on auto Xon flow control */
133 efr |= (UART_17158_EFR_ECB | UART_17158_EFR_IXON);
134
135 /* Why? Becuz Exar's spec says we have to zero it out before setting it */
136 writeb(0, &ch->ch_neo_uart->efr);
137
138 /* Turn on UART enhanced bits */
139 writeb(efr, &ch->ch_neo_uart->efr);
140
141 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr);
142 ch->ch_r_watermark = 4;
143
144 writeb(32, &ch->ch_neo_uart->rfifo);
145 ch->ch_r_tlevel = 32;
146
147 /* Tell UART what start/stop chars it should be looking for */
148 writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1);
149 writeb(0, &ch->ch_neo_uart->xonchar2);
150
151 writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1);
152 writeb(0, &ch->ch_neo_uart->xoffchar2);
153
154 writeb(ier, &ch->ch_neo_uart->ier);
155}
156
157static void neo_set_ixoff_flow_control(struct jsm_channel *ch)
158{
159 u8 ier, efr;
160 ier = readb(&ch->ch_neo_uart->ier);
161 efr = readb(&ch->ch_neo_uart->efr);
162
163 jsm_printk(PARAM, INFO, &ch->ch_bd->pci_dev, "Setting IXOFF FLOW\n");
164
165 /* Turn off auto RTS flow control */
166 ier &= ~(UART_17158_IER_RTSDTR);
167 efr &= ~(UART_17158_EFR_RTSDTR);
168
169 /* Turn on auto Xoff flow control */
170 ier |= (UART_17158_IER_XOFF);
171 efr |= (UART_17158_EFR_ECB | UART_17158_EFR_IXOFF);
172
173 /* Why? Becuz Exar's spec says we have to zero it out before setting it */
174 writeb(0, &ch->ch_neo_uart->efr);
175
176 /* Turn on UART enhanced bits */
177 writeb(efr, &ch->ch_neo_uart->efr);
178
179 /* Turn on table D, with 8 char hi/low watermarks */
180 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr);
181
182 writeb(8, &ch->ch_neo_uart->tfifo);
183 ch->ch_t_tlevel = 8;
184
185 /* Tell UART what start/stop chars it should be looking for */
186 writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1);
187 writeb(0, &ch->ch_neo_uart->xonchar2);
188
189 writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1);
190 writeb(0, &ch->ch_neo_uart->xoffchar2);
191
192 writeb(ier, &ch->ch_neo_uart->ier);
193}
194
195static void neo_set_no_input_flow_control(struct jsm_channel *ch)
196{
197 u8 ier, efr;
198 ier = readb(&ch->ch_neo_uart->ier);
199 efr = readb(&ch->ch_neo_uart->efr);
200
201 jsm_printk(PARAM, INFO, &ch->ch_bd->pci_dev, "Unsetting Input FLOW\n");
202
203 /* Turn off auto RTS flow control */
204 ier &= ~(UART_17158_IER_RTSDTR);
205 efr &= ~(UART_17158_EFR_RTSDTR);
206
207 /* Turn off auto Xoff flow control */
208 ier &= ~(UART_17158_IER_XOFF);
209 if (ch->ch_c_iflag & IXON)
210 efr &= ~(UART_17158_EFR_IXOFF);
211 else
212 efr &= ~(UART_17158_EFR_ECB | UART_17158_EFR_IXOFF);
213
214 /* Why? Becuz Exar's spec says we have to zero it out before setting it */
215 writeb(0, &ch->ch_neo_uart->efr);
216
217 /* Turn on UART enhanced bits */
218 writeb(efr, &ch->ch_neo_uart->efr);
219
220 /* Turn on table D, with 8 char hi/low watermarks */
221 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr);
222
223 ch->ch_r_watermark = 0;
224
225 writeb(16, &ch->ch_neo_uart->tfifo);
226 ch->ch_t_tlevel = 16;
227
228 writeb(16, &ch->ch_neo_uart->rfifo);
229 ch->ch_r_tlevel = 16;
230
231 writeb(ier, &ch->ch_neo_uart->ier);
232}
233
234static void neo_set_no_output_flow_control(struct jsm_channel *ch)
235{
236 u8 ier, efr;
237 ier = readb(&ch->ch_neo_uart->ier);
238 efr = readb(&ch->ch_neo_uart->efr);
239
240 jsm_printk(PARAM, INFO, &ch->ch_bd->pci_dev, "Unsetting Output FLOW\n");
241
242 /* Turn off auto CTS flow control */
243 ier &= ~(UART_17158_IER_CTSDSR);
244 efr &= ~(UART_17158_EFR_CTSDSR);
245
246 /* Turn off auto Xon flow control */
247 if (ch->ch_c_iflag & IXOFF)
248 efr &= ~(UART_17158_EFR_IXON);
249 else
250 efr &= ~(UART_17158_EFR_ECB | UART_17158_EFR_IXON);
251
252 /* Why? Becuz Exar's spec says we have to zero it out before setting it */
253 writeb(0, &ch->ch_neo_uart->efr);
254
255 /* Turn on UART enhanced bits */
256 writeb(efr, &ch->ch_neo_uart->efr);
257
258 /* Turn on table D, with 8 char hi/low watermarks */
259 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr);
260
261 ch->ch_r_watermark = 0;
262
263 writeb(16, &ch->ch_neo_uart->tfifo);
264 ch->ch_t_tlevel = 16;
265
266 writeb(16, &ch->ch_neo_uart->rfifo);
267 ch->ch_r_tlevel = 16;
268
269 writeb(ier, &ch->ch_neo_uart->ier);
270}
271
272static inline void neo_set_new_start_stop_chars(struct jsm_channel *ch)
273{
274
275 /* if hardware flow control is set, then skip this whole thing */
276 if (ch->ch_c_cflag & CRTSCTS)
277 return;
278
279 jsm_printk(PARAM, INFO, &ch->ch_bd->pci_dev, "start\n");
280
281 /* Tell UART what start/stop chars it should be looking for */
282 writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1);
283 writeb(0, &ch->ch_neo_uart->xonchar2);
284
285 writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1);
286 writeb(0, &ch->ch_neo_uart->xoffchar2);
287}
288
289static void neo_copy_data_from_uart_to_queue(struct jsm_channel *ch)
290{
291 int qleft = 0;
292 u8 linestatus = 0;
293 u8 error_mask = 0;
294 int n = 0;
295 int total = 0;
296 u16 head;
297 u16 tail;
298
299 if (!ch)
300 return;
301
302 /* cache head and tail of queue */
303 head = ch->ch_r_head & RQUEUEMASK;
304 tail = ch->ch_r_tail & RQUEUEMASK;
305
306 /* Get our cached LSR */
307 linestatus = ch->ch_cached_lsr;
308 ch->ch_cached_lsr = 0;
309
310 /* Store how much space we have left in the queue */
311 if ((qleft = tail - head - 1) < 0)
312 qleft += RQUEUEMASK + 1;
313
314 /*
315 * If the UART is not in FIFO mode, force the FIFO copy to
316 * NOT be run, by setting total to 0.
317 *
318 * On the other hand, if the UART IS in FIFO mode, then ask
319 * the UART to give us an approximation of data it has RX'ed.
320 */
321 if (!(ch->ch_flags & CH_FIFO_ENABLED))
322 total = 0;
323 else {
324 total = readb(&ch->ch_neo_uart->rfifo);
325
326 /*
327 * EXAR chip bug - RX FIFO COUNT - Fudge factor.
328 *
329 * This resolves a problem/bug with the Exar chip that sometimes
330 * returns a bogus value in the rfifo register.
331 * The count can be any where from 0-3 bytes "off".
332 * Bizarre, but true.
333 */
334 total -= 3;
335 }
336
337 /*
338 * Finally, bound the copy to make sure we don't overflow
339 * our own queue...
340 * The byte by byte copy loop below this loop this will
341 * deal with the queue overflow possibility.
342 */
343 total = min(total, qleft);
344
345 while (total > 0) {
346 /*
347 * Grab the linestatus register, we need to check
348 * to see if there are any errors in the FIFO.
349 */
350 linestatus = readb(&ch->ch_neo_uart->lsr);
351
352 /*
353 * Break out if there is a FIFO error somewhere.
354 * This will allow us to go byte by byte down below,
355 * finding the exact location of the error.
356 */
357 if (linestatus & UART_17158_RX_FIFO_DATA_ERROR)
358 break;
359
360 /* Make sure we don't go over the end of our queue */
361 n = min(((u32) total), (RQUEUESIZE - (u32) head));
362
363 /*
364 * Cut down n even further if needed, this is to fix
365 * a problem with memcpy_fromio() with the Neo on the
366 * IBM pSeries platform.
367 * 15 bytes max appears to be the magic number.
368 */
369 n = min((u32) n, (u32) 12);
370
371 /*
372 * Since we are grabbing the linestatus register, which
373 * will reset some bits after our read, we need to ensure
374 * we don't miss our TX FIFO emptys.
375 */
376 if (linestatus & (UART_LSR_THRE | UART_17158_TX_AND_FIFO_CLR))
377 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
378
379 linestatus = 0;
380
381 /* Copy data from uart to the queue */
382 memcpy_fromio(ch->ch_rqueue + head, &ch->ch_neo_uart->txrxburst, n);
383 /*
384 * Since RX_FIFO_DATA_ERROR was 0, we are guarenteed
385 * that all the data currently in the FIFO is free of
386 * breaks and parity/frame/orun errors.
387 */
388 memset(ch->ch_equeue + head, 0, n);
389
390 /* Add to and flip head if needed */
391 head = (head + n) & RQUEUEMASK;
392 total -= n;
393 qleft -= n;
394 ch->ch_rxcount += n;
395 }
396
397 /*
398 * Create a mask to determine whether we should
399 * insert the character (if any) into our queue.
400 */
401 if (ch->ch_c_iflag & IGNBRK)
402 error_mask |= UART_LSR_BI;
403
404 /*
405 * Now cleanup any leftover bytes still in the UART.
406 * Also deal with any possible queue overflow here as well.
407 */
408 while (1) {
409
410 /*
411 * Its possible we have a linestatus from the loop above
412 * this, so we "OR" on any extra bits.
413 */
414 linestatus |= readb(&ch->ch_neo_uart->lsr);
415
416 /*
417 * If the chip tells us there is no more data pending to
418 * be read, we can then leave.
419 * But before we do, cache the linestatus, just in case.
420 */
421 if (!(linestatus & UART_LSR_DR)) {
422 ch->ch_cached_lsr = linestatus;
423 break;
424 }
425
426 /* No need to store this bit */
427 linestatus &= ~UART_LSR_DR;
428
429 /*
430 * Since we are grabbing the linestatus register, which
431 * will reset some bits after our read, we need to ensure
432 * we don't miss our TX FIFO emptys.
433 */
434 if (linestatus & (UART_LSR_THRE | UART_17158_TX_AND_FIFO_CLR)) {
435 linestatus &= ~(UART_LSR_THRE | UART_17158_TX_AND_FIFO_CLR);
436 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
437 }
438
439 /*
440 * Discard character if we are ignoring the error mask.
441 */
442 if (linestatus & error_mask) {
443 u8 discard;
444 linestatus = 0;
445 memcpy_fromio(&discard, &ch->ch_neo_uart->txrxburst, 1);
446 continue;
447 }
448
449 /*
450 * If our queue is full, we have no choice but to drop some data.
451 * The assumption is that HWFLOW or SWFLOW should have stopped
452 * things way way before we got to this point.
453 *
454 * I decided that I wanted to ditch the oldest data first,
455 * I hope thats okay with everyone? Yes? Good.
456 */
457 while (qleft < 1) {
458 jsm_printk(READ, INFO, &ch->ch_bd->pci_dev,
459 "Queue full, dropping DATA:%x LSR:%x\n",
460 ch->ch_rqueue[tail], ch->ch_equeue[tail]);
461
462 ch->ch_r_tail = tail = (tail + 1) & RQUEUEMASK;
463 ch->ch_err_overrun++;
464 qleft++;
465 }
466
467 memcpy_fromio(ch->ch_rqueue + head, &ch->ch_neo_uart->txrxburst, 1);
468 ch->ch_equeue[head] = (u8) linestatus;
469
470 jsm_printk(READ, INFO, &ch->ch_bd->pci_dev,
471 "DATA/LSR pair: %x %x\n", ch->ch_rqueue[head], ch->ch_equeue[head]);
472
473 /* Ditch any remaining linestatus value. */
474 linestatus = 0;
475
476 /* Add to and flip head if needed */
477 head = (head + 1) & RQUEUEMASK;
478
479 qleft--;
480 ch->ch_rxcount++;
481 }
482
483 /*
484 * Write new final heads to channel structure.
485 */
486 ch->ch_r_head = head & RQUEUEMASK;
487 ch->ch_e_head = head & EQUEUEMASK;
488 jsm_input(ch);
489}
490
491static void neo_copy_data_from_queue_to_uart(struct jsm_channel *ch)
492{
493 u16 head;
494 u16 tail;
495 int n;
496 int s;
497 int qlen;
498 u32 len_written = 0;
499
500 if (!ch)
501 return;
502
503 /* No data to write to the UART */
504 if (ch->ch_w_tail == ch->ch_w_head)
505 return;
506
507 /* If port is "stopped", don't send any data to the UART */
508 if ((ch->ch_flags & CH_STOP) || (ch->ch_flags & CH_BREAK_SENDING))
509 return;
510 /*
511 * If FIFOs are disabled. Send data directly to txrx register
512 */
513 if (!(ch->ch_flags & CH_FIFO_ENABLED)) {
514 u8 lsrbits = readb(&ch->ch_neo_uart->lsr);
515
516 ch->ch_cached_lsr |= lsrbits;
517 if (ch->ch_cached_lsr & UART_LSR_THRE) {
518 ch->ch_cached_lsr &= ~(UART_LSR_THRE);
519
520 writeb(ch->ch_wqueue[ch->ch_w_tail], &ch->ch_neo_uart->txrx);
521 jsm_printk(WRITE, INFO, &ch->ch_bd->pci_dev,
522 "Tx data: %x\n", ch->ch_wqueue[ch->ch_w_head]);
523 ch->ch_w_tail++;
524 ch->ch_w_tail &= WQUEUEMASK;
525 ch->ch_txcount++;
526 }
527 return;
528 }
529
530 /*
531 * We have to do it this way, because of the EXAR TXFIFO count bug.
532 */
533 if (!(ch->ch_flags & (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM)))
534 return;
535
536 n = UART_17158_TX_FIFOSIZE - ch->ch_t_tlevel;
537
538 /* cache head and tail of queue */
539 head = ch->ch_w_head & WQUEUEMASK;
540 tail = ch->ch_w_tail & WQUEUEMASK;
541 qlen = (head - tail) & WQUEUEMASK;
542
543 /* Find minimum of the FIFO space, versus queue length */
544 n = min(n, qlen);
545
546 while (n > 0) {
547
548 s = ((head >= tail) ? head : WQUEUESIZE) - tail;
549 s = min(s, n);
550
551 if (s <= 0)
552 break;
553
554 memcpy_toio(&ch->ch_neo_uart->txrxburst, ch->ch_wqueue + tail, s);
555 /* Add and flip queue if needed */
556 tail = (tail + s) & WQUEUEMASK;
557 n -= s;
558 ch->ch_txcount += s;
559 len_written += s;
560 }
561
562 /* Update the final tail */
563 ch->ch_w_tail = tail & WQUEUEMASK;
564
565 if (len_written >= ch->ch_t_tlevel)
566 ch->ch_flags &= ~(CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
567
568 if (!jsm_tty_write(&ch->uart_port))
569 uart_write_wakeup(&ch->uart_port);
570}
571
572static void neo_parse_modem(struct jsm_channel *ch, u8 signals)
573{
574 u8 msignals = signals;
575
576 jsm_printk(MSIGS, INFO, &ch->ch_bd->pci_dev,
577 "neo_parse_modem: port: %d msignals: %x\n", ch->ch_portnum, msignals);
578
579 /* Scrub off lower bits. They signify delta's, which I don't care about */
580 /* Keep DDCD and DDSR though */
581 msignals &= 0xf8;
582
583 if (msignals & UART_MSR_DDCD)
584 uart_handle_dcd_change(&ch->uart_port, msignals & UART_MSR_DCD);
585 if (msignals & UART_MSR_DDSR)
586 uart_handle_cts_change(&ch->uart_port, msignals & UART_MSR_CTS);
587 if (msignals & UART_MSR_DCD)
588 ch->ch_mistat |= UART_MSR_DCD;
589 else
590 ch->ch_mistat &= ~UART_MSR_DCD;
591
592 if (msignals & UART_MSR_DSR)
593 ch->ch_mistat |= UART_MSR_DSR;
594 else
595 ch->ch_mistat &= ~UART_MSR_DSR;
596
597 if (msignals & UART_MSR_RI)
598 ch->ch_mistat |= UART_MSR_RI;
599 else
600 ch->ch_mistat &= ~UART_MSR_RI;
601
602 if (msignals & UART_MSR_CTS)
603 ch->ch_mistat |= UART_MSR_CTS;
604 else
605 ch->ch_mistat &= ~UART_MSR_CTS;
606
607 jsm_printk(MSIGS, INFO, &ch->ch_bd->pci_dev,
608 "Port: %d DTR: %d RTS: %d CTS: %d DSR: %d " "RI: %d CD: %d\n",
609 ch->ch_portnum,
610 !!((ch->ch_mistat | ch->ch_mostat) & UART_MCR_DTR),
611 !!((ch->ch_mistat | ch->ch_mostat) & UART_MCR_RTS),
612 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_CTS),
613 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_DSR),
614 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_RI),
615 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_DCD));
616}
617
618/* Make the UART raise any of the output signals we want up */
619static void neo_assert_modem_signals(struct jsm_channel *ch)
620{
621 if (!ch)
622 return;
623
624 writeb(ch->ch_mostat, &ch->ch_neo_uart->mcr);
625
626 /* flush write operation */
627 neo_pci_posting_flush(ch->ch_bd);
628}
629
630/*
631 * Flush the WRITE FIFO on the Neo.
632 *
633 * NOTE: Channel lock MUST be held before calling this function!
634 */
635static void neo_flush_uart_write(struct jsm_channel *ch)
636{
637 u8 tmp = 0;
638 int i = 0;
639
640 if (!ch)
641 return;
642
643 writeb((UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_XMIT), &ch->ch_neo_uart->isr_fcr);
644
645 for (i = 0; i < 10; i++) {
646
647 /* Check to see if the UART feels it completely flushed the FIFO. */
648 tmp = readb(&ch->ch_neo_uart->isr_fcr);
649 if (tmp & 4) {
650 jsm_printk(IOCTL, INFO, &ch->ch_bd->pci_dev,
651 "Still flushing TX UART... i: %d\n", i);
652 udelay(10);
653 }
654 else
655 break;
656 }
657
658 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
659}
660
661
662/*
663 * Flush the READ FIFO on the Neo.
664 *
665 * NOTE: Channel lock MUST be held before calling this function!
666 */
667static void neo_flush_uart_read(struct jsm_channel *ch)
668{
669 u8 tmp = 0;
670 int i = 0;
671
672 if (!ch)
673 return;
674
675 writeb((UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR), &ch->ch_neo_uart->isr_fcr);
676
677 for (i = 0; i < 10; i++) {
678
679 /* Check to see if the UART feels it completely flushed the FIFO. */
680 tmp = readb(&ch->ch_neo_uart->isr_fcr);
681 if (tmp & 2) {
682 jsm_printk(IOCTL, INFO, &ch->ch_bd->pci_dev,
683 "Still flushing RX UART... i: %d\n", i);
684 udelay(10);
685 }
686 else
687 break;
688 }
689}
690
691/*
692 * No locks are assumed to be held when calling this function.
693 */
694static void neo_clear_break(struct jsm_channel *ch, int force)
695{
696 unsigned long lock_flags;
697
698 spin_lock_irqsave(&ch->ch_lock, lock_flags);
699
700 /* Turn break off, and unset some variables */
701 if (ch->ch_flags & CH_BREAK_SENDING) {
702 u8 temp = readb(&ch->ch_neo_uart->lcr);
703 writeb((temp & ~UART_LCR_SBC), &ch->ch_neo_uart->lcr);
704
705 ch->ch_flags &= ~(CH_BREAK_SENDING);
706 jsm_printk(IOCTL, INFO, &ch->ch_bd->pci_dev,
707 "clear break Finishing UART_LCR_SBC! finished: %lx\n", jiffies);
708
709 /* flush write operation */
710 neo_pci_posting_flush(ch->ch_bd);
711 }
712 spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
713}
714
715/*
716 * Parse the ISR register.
717 */
718static inline void neo_parse_isr(struct jsm_board *brd, u32 port)
719{
720 struct jsm_channel *ch;
721 u8 isr;
722 u8 cause;
723 unsigned long lock_flags;
724
725 if (!brd)
726 return;
727
728 if (port > brd->maxports)
729 return;
730
731 ch = brd->channels[port];
732 if (!ch)
733 return;
734
735 /* Here we try to figure out what caused the interrupt to happen */
736 while (1) {
737
738 isr = readb(&ch->ch_neo_uart->isr_fcr);
739
740 /* Bail if no pending interrupt */
741 if (isr & UART_IIR_NO_INT)
742 break;
743
744 /*
745 * Yank off the upper 2 bits, which just show that the FIFO's are enabled.
746 */
747 isr &= ~(UART_17158_IIR_FIFO_ENABLED);
748
749 jsm_printk(INTR, INFO, &ch->ch_bd->pci_dev,
750 "%s:%d isr: %x\n", __FILE__, __LINE__, isr);
751
752 if (isr & (UART_17158_IIR_RDI_TIMEOUT | UART_IIR_RDI)) {
753 /* Read data from uart -> queue */
754 neo_copy_data_from_uart_to_queue(ch);
755
756 /* Call our tty layer to enforce queue flow control if needed. */
757 spin_lock_irqsave(&ch->ch_lock, lock_flags);
758 jsm_check_queue_flow_control(ch);
759 spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
760 }
761
762 if (isr & UART_IIR_THRI) {
763 /* Transfer data (if any) from Write Queue -> UART. */
764 spin_lock_irqsave(&ch->ch_lock, lock_flags);
765 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
766 spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
767 neo_copy_data_from_queue_to_uart(ch);
768 }
769
770 if (isr & UART_17158_IIR_XONXOFF) {
771 cause = readb(&ch->ch_neo_uart->xoffchar1);
772
773 jsm_printk(INTR, INFO, &ch->ch_bd->pci_dev,
774 "Port %d. Got ISR_XONXOFF: cause:%x\n", port, cause);
775
776 /*
777 * Since the UART detected either an XON or
778 * XOFF match, we need to figure out which
779 * one it was, so we can suspend or resume data flow.
780 */
781 spin_lock_irqsave(&ch->ch_lock, lock_flags);
782 if (cause == UART_17158_XON_DETECT) {
783 /* Is output stopped right now, if so, resume it */
784 if (brd->channels[port]->ch_flags & CH_STOP) {
785 ch->ch_flags &= ~(CH_STOP);
786 }
787 jsm_printk(INTR, INFO, &ch->ch_bd->pci_dev,
788 "Port %d. XON detected in incoming data\n", port);
789 }
790 else if (cause == UART_17158_XOFF_DETECT) {
791 if (!(brd->channels[port]->ch_flags & CH_STOP)) {
792 ch->ch_flags |= CH_STOP;
793 jsm_printk(INTR, INFO, &ch->ch_bd->pci_dev,
794 "Setting CH_STOP\n");
795 }
796 jsm_printk(INTR, INFO, &ch->ch_bd->pci_dev,
797 "Port: %d. XOFF detected in incoming data\n", port);
798 }
799 spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
800 }
801
802 if (isr & UART_17158_IIR_HWFLOW_STATE_CHANGE) {
803 /*
804 * If we get here, this means the hardware is doing auto flow control.
805 * Check to see whether RTS/DTR or CTS/DSR caused this interrupt.
806 */
807 cause = readb(&ch->ch_neo_uart->mcr);
808
809 /* Which pin is doing auto flow? RTS or DTR? */
810 spin_lock_irqsave(&ch->ch_lock, lock_flags);
811 if ((cause & 0x4) == 0) {
812 if (cause & UART_MCR_RTS)
813 ch->ch_mostat |= UART_MCR_RTS;
814 else
815 ch->ch_mostat &= ~(UART_MCR_RTS);
816 } else {
817 if (cause & UART_MCR_DTR)
818 ch->ch_mostat |= UART_MCR_DTR;
819 else
820 ch->ch_mostat &= ~(UART_MCR_DTR);
821 }
822 spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
823 }
824
825 /* Parse any modem signal changes */
826 jsm_printk(INTR, INFO, &ch->ch_bd->pci_dev,
827 "MOD_STAT: sending to parse_modem_sigs\n");
828 neo_parse_modem(ch, readb(&ch->ch_neo_uart->msr));
829 }
830}
831
832static inline void neo_parse_lsr(struct jsm_board *brd, u32 port)
833{
834 struct jsm_channel *ch;
835 int linestatus;
836 unsigned long lock_flags;
837
838 if (!brd)
839 return;
840
841 if (port > brd->maxports)
842 return;
843
844 ch = brd->channels[port];
845 if (!ch)
846 return;
847
848 linestatus = readb(&ch->ch_neo_uart->lsr);
849
850 jsm_printk(INTR, INFO, &ch->ch_bd->pci_dev,
851 "%s:%d port: %d linestatus: %x\n", __FILE__, __LINE__, port, linestatus);
852
853 ch->ch_cached_lsr |= linestatus;
854
855 if (ch->ch_cached_lsr & UART_LSR_DR) {
856 /* Read data from uart -> queue */
857 neo_copy_data_from_uart_to_queue(ch);
858 spin_lock_irqsave(&ch->ch_lock, lock_flags);
859 jsm_check_queue_flow_control(ch);
860 spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
861 }
862
863 /*
864 * This is a special flag. It indicates that at least 1
865 * RX error (parity, framing, or break) has happened.
866 * Mark this in our struct, which will tell me that I have
867 *to do the special RX+LSR read for this FIFO load.
868 */
869 if (linestatus & UART_17158_RX_FIFO_DATA_ERROR)
870 jsm_printk(INTR, DEBUG, &ch->ch_bd->pci_dev,
871 "%s:%d Port: %d Got an RX error, need to parse LSR\n",
872 __FILE__, __LINE__, port);
873
874 /*
875 * The next 3 tests should *NOT* happen, as the above test
876 * should encapsulate all 3... At least, thats what Exar says.
877 */
878
879 if (linestatus & UART_LSR_PE) {
880 ch->ch_err_parity++;
881 jsm_printk(INTR, DEBUG, &ch->ch_bd->pci_dev,
882 "%s:%d Port: %d. PAR ERR!\n", __FILE__, __LINE__, port);
883 }
884
885 if (linestatus & UART_LSR_FE) {
886 ch->ch_err_frame++;
887 jsm_printk(INTR, DEBUG, &ch->ch_bd->pci_dev,
888 "%s:%d Port: %d. FRM ERR!\n", __FILE__, __LINE__, port);
889 }
890
891 if (linestatus & UART_LSR_BI) {
892 ch->ch_err_break++;
893 jsm_printk(INTR, DEBUG, &ch->ch_bd->pci_dev,
894 "%s:%d Port: %d. BRK INTR!\n", __FILE__, __LINE__, port);
895 }
896
897 if (linestatus & UART_LSR_OE) {
898 /*
899 * Rx Oruns. Exar says that an orun will NOT corrupt
900 * the FIFO. It will just replace the holding register
901 * with this new data byte. So basically just ignore this.
902 * Probably we should eventually have an orun stat in our driver...
903 */
904 ch->ch_err_overrun++;
905 jsm_printk(INTR, DEBUG, &ch->ch_bd->pci_dev,
906 "%s:%d Port: %d. Rx Overrun!\n", __FILE__, __LINE__, port);
907 }
908
909 if (linestatus & UART_LSR_THRE) {
910 spin_lock_irqsave(&ch->ch_lock, lock_flags);
911 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
912 spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
913
914 /* Transfer data (if any) from Write Queue -> UART. */
915 neo_copy_data_from_queue_to_uart(ch);
916 }
917 else if (linestatus & UART_17158_TX_AND_FIFO_CLR) {
918 spin_lock_irqsave(&ch->ch_lock, lock_flags);
919 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
920 spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
921
922 /* Transfer data (if any) from Write Queue -> UART. */
923 neo_copy_data_from_queue_to_uart(ch);
924 }
925}
926
927/*
928 * neo_param()
929 * Send any/all changes to the line to the UART.
930 */
931static void neo_param(struct jsm_channel *ch)
932{
933 u8 lcr = 0;
934 u8 uart_lcr, ier;
935 u32 baud;
936 int quot;
937 struct jsm_board *bd;
938
939 bd = ch->ch_bd;
940 if (!bd)
941 return;
942
943 /*
944 * If baud rate is zero, flush queues, and set mval to drop DTR.
945 */
946 if ((ch->ch_c_cflag & (CBAUD)) == 0) {
947 ch->ch_r_head = ch->ch_r_tail = 0;
948 ch->ch_e_head = ch->ch_e_tail = 0;
949 ch->ch_w_head = ch->ch_w_tail = 0;
950
951 neo_flush_uart_write(ch);
952 neo_flush_uart_read(ch);
953
954 ch->ch_flags |= (CH_BAUD0);
955 ch->ch_mostat &= ~(UART_MCR_RTS | UART_MCR_DTR);
956 neo_assert_modem_signals(ch);
957 return;
958
959 } else {
960 int i;
961 unsigned int cflag;
962 static struct {
963 unsigned int rate;
964 unsigned int cflag;
965 } baud_rates[] = {
966 { 921600, B921600 },
967 { 460800, B460800 },
968 { 230400, B230400 },
969 { 115200, B115200 },
970 { 57600, B57600 },
971 { 38400, B38400 },
972 { 19200, B19200 },
973 { 9600, B9600 },
974 { 4800, B4800 },
975 { 2400, B2400 },
976 { 1200, B1200 },
977 { 600, B600 },
978 { 300, B300 },
979 { 200, B200 },
980 { 150, B150 },
981 { 134, B134 },
982 { 110, B110 },
983 { 75, B75 },
984 { 50, B50 },
985 };
986
987 cflag = C_BAUD(ch->uart_port.state->port.tty);
988 baud = 9600;
989 for (i = 0; i < ARRAY_SIZE(baud_rates); i++) {
990 if (baud_rates[i].cflag == cflag) {
991 baud = baud_rates[i].rate;
992 break;
993 }
994 }
995
996 if (ch->ch_flags & CH_BAUD0)
997 ch->ch_flags &= ~(CH_BAUD0);
998 }
999
1000 if (ch->ch_c_cflag & PARENB)
1001 lcr |= UART_LCR_PARITY;
1002
1003 if (!(ch->ch_c_cflag & PARODD))
1004 lcr |= UART_LCR_EPAR;
1005
1006 /*
1007 * Not all platforms support mark/space parity,
1008 * so this will hide behind an ifdef.
1009 */
1010#ifdef CMSPAR
1011 if (ch->ch_c_cflag & CMSPAR)
1012 lcr |= UART_LCR_SPAR;
1013#endif
1014
1015 if (ch->ch_c_cflag & CSTOPB)
1016 lcr |= UART_LCR_STOP;
1017
1018 switch (ch->ch_c_cflag & CSIZE) {
1019 case CS5:
1020 lcr |= UART_LCR_WLEN5;
1021 break;
1022 case CS6:
1023 lcr |= UART_LCR_WLEN6;
1024 break;
1025 case CS7:
1026 lcr |= UART_LCR_WLEN7;
1027 break;
1028 case CS8:
1029 default:
1030 lcr |= UART_LCR_WLEN8;
1031 break;
1032 }
1033
1034 ier = readb(&ch->ch_neo_uart->ier);
1035 uart_lcr = readb(&ch->ch_neo_uart->lcr);
1036
1037 if (baud == 0)
1038 baud = 9600;
1039
1040 quot = ch->ch_bd->bd_dividend / baud;
1041
1042 if (quot != 0) {
1043 writeb(UART_LCR_DLAB, &ch->ch_neo_uart->lcr);
1044 writeb((quot & 0xff), &ch->ch_neo_uart->txrx);
1045 writeb((quot >> 8), &ch->ch_neo_uart->ier);
1046 writeb(lcr, &ch->ch_neo_uart->lcr);
1047 }
1048
1049 if (uart_lcr != lcr)
1050 writeb(lcr, &ch->ch_neo_uart->lcr);
1051
1052 if (ch->ch_c_cflag & CREAD)
1053 ier |= (UART_IER_RDI | UART_IER_RLSI);
1054
1055 ier |= (UART_IER_THRI | UART_IER_MSI);
1056
1057 writeb(ier, &ch->ch_neo_uart->ier);
1058
1059 /* Set new start/stop chars */
1060 neo_set_new_start_stop_chars(ch);
1061
1062 if (ch->ch_c_cflag & CRTSCTS)
1063 neo_set_cts_flow_control(ch);
1064 else if (ch->ch_c_iflag & IXON) {
1065 /* If start/stop is set to disable, then we should disable flow control */
1066 if ((ch->ch_startc == __DISABLED_CHAR) || (ch->ch_stopc == __DISABLED_CHAR))
1067 neo_set_no_output_flow_control(ch);
1068 else
1069 neo_set_ixon_flow_control(ch);
1070 }
1071 else
1072 neo_set_no_output_flow_control(ch);
1073
1074 if (ch->ch_c_cflag & CRTSCTS)
1075 neo_set_rts_flow_control(ch);
1076 else if (ch->ch_c_iflag & IXOFF) {
1077 /* If start/stop is set to disable, then we should disable flow control */
1078 if ((ch->ch_startc == __DISABLED_CHAR) || (ch->ch_stopc == __DISABLED_CHAR))
1079 neo_set_no_input_flow_control(ch);
1080 else
1081 neo_set_ixoff_flow_control(ch);
1082 }
1083 else
1084 neo_set_no_input_flow_control(ch);
1085 /*
1086 * Adjust the RX FIFO Trigger level if baud is less than 9600.
1087 * Not exactly elegant, but this is needed because of the Exar chip's
1088 * delay on firing off the RX FIFO interrupt on slower baud rates.
1089 */
1090 if (baud < 9600) {
1091 writeb(1, &ch->ch_neo_uart->rfifo);
1092 ch->ch_r_tlevel = 1;
1093 }
1094
1095 neo_assert_modem_signals(ch);
1096
1097 /* Get current status of the modem signals now */
1098 neo_parse_modem(ch, readb(&ch->ch_neo_uart->msr));
1099 return;
1100}
1101
1102/*
1103 * jsm_neo_intr()
1104 *
1105 * Neo specific interrupt handler.
1106 */
1107static irqreturn_t neo_intr(int irq, void *voidbrd)
1108{
1109 struct jsm_board *brd = voidbrd;
1110 struct jsm_channel *ch;
1111 int port = 0;
1112 int type = 0;
1113 int current_port;
1114 u32 tmp;
1115 u32 uart_poll;
1116 unsigned long lock_flags;
1117 unsigned long lock_flags2;
1118 int outofloop_count = 0;
1119
1120 /* Lock out the slow poller from running on this board. */
1121 spin_lock_irqsave(&brd->bd_intr_lock, lock_flags);
1122
1123 /*
1124 * Read in "extended" IRQ information from the 32bit Neo register.
1125 * Bits 0-7: What port triggered the interrupt.
1126 * Bits 8-31: Each 3bits indicate what type of interrupt occurred.
1127 */
1128 uart_poll = readl(brd->re_map_membase + UART_17158_POLL_ADDR_OFFSET);
1129
1130 jsm_printk(INTR, INFO, &brd->pci_dev,
1131 "%s:%d uart_poll: %x\n", __FILE__, __LINE__, uart_poll);
1132
1133 if (!uart_poll) {
1134 jsm_printk(INTR, INFO, &brd->pci_dev,
1135 "Kernel interrupted to me, but no pending interrupts...\n");
1136 spin_unlock_irqrestore(&brd->bd_intr_lock, lock_flags);
1137 return IRQ_NONE;
1138 }
1139
1140 /* At this point, we have at least SOMETHING to service, dig further... */
1141
1142 current_port = 0;
1143
1144 /* Loop on each port */
1145 while (((uart_poll & 0xff) != 0) && (outofloop_count < 0xff)){
1146
1147 tmp = uart_poll;
1148 outofloop_count++;
1149
1150 /* Check current port to see if it has interrupt pending */
1151 if ((tmp & jsm_offset_table[current_port]) != 0) {
1152 port = current_port;
1153 type = tmp >> (8 + (port * 3));
1154 type &= 0x7;
1155 } else {
1156 current_port++;
1157 continue;
1158 }
1159
1160 jsm_printk(INTR, INFO, &brd->pci_dev,
1161 "%s:%d port: %x type: %x\n", __FILE__, __LINE__, port, type);
1162
1163 /* Remove this port + type from uart_poll */
1164 uart_poll &= ~(jsm_offset_table[port]);
1165
1166 if (!type) {
1167 /* If no type, just ignore it, and move onto next port */
1168 jsm_printk(INTR, ERR, &brd->pci_dev,
1169 "Interrupt with no type! port: %d\n", port);
1170 continue;
1171 }
1172
1173 /* Switch on type of interrupt we have */
1174 switch (type) {
1175
1176 case UART_17158_RXRDY_TIMEOUT:
1177 /*
1178 * RXRDY Time-out is cleared by reading data in the
1179 * RX FIFO until it falls below the trigger level.
1180 */
1181
1182 /* Verify the port is in range. */
1183 if (port > brd->nasync)
1184 continue;
1185
1186 ch = brd->channels[port];
1187 neo_copy_data_from_uart_to_queue(ch);
1188
1189 /* Call our tty layer to enforce queue flow control if needed. */
1190 spin_lock_irqsave(&ch->ch_lock, lock_flags2);
1191 jsm_check_queue_flow_control(ch);
1192 spin_unlock_irqrestore(&ch->ch_lock, lock_flags2);
1193
1194 continue;
1195
1196 case UART_17158_RX_LINE_STATUS:
1197 /*
1198 * RXRDY and RX LINE Status (logic OR of LSR[4:1])
1199 */
1200 neo_parse_lsr(brd, port);
1201 continue;
1202
1203 case UART_17158_TXRDY:
1204 /*
1205 * TXRDY interrupt clears after reading ISR register for the UART channel.
1206 */
1207
1208 /*
1209 * Yes, this is odd...
1210 * Why would I check EVERY possibility of type of
1211 * interrupt, when we know its TXRDY???
1212 * Becuz for some reason, even tho we got triggered for TXRDY,
1213 * it seems to be occassionally wrong. Instead of TX, which
1214 * it should be, I was getting things like RXDY too. Weird.
1215 */
1216 neo_parse_isr(brd, port);
1217 continue;
1218
1219 case UART_17158_MSR:
1220 /*
1221 * MSR or flow control was seen.
1222 */
1223 neo_parse_isr(brd, port);
1224 continue;
1225
1226 default:
1227 /*
1228 * The UART triggered us with a bogus interrupt type.
1229 * It appears the Exar chip, when REALLY bogged down, will throw
1230 * these once and awhile.
1231 * Its harmless, just ignore it and move on.
1232 */
1233 jsm_printk(INTR, ERR, &brd->pci_dev,
1234 "%s:%d Unknown Interrupt type: %x\n", __FILE__, __LINE__, type);
1235 continue;
1236 }
1237 }
1238
1239 spin_unlock_irqrestore(&brd->bd_intr_lock, lock_flags);
1240
1241 jsm_printk(INTR, INFO, &brd->pci_dev, "finish.\n");
1242 return IRQ_HANDLED;
1243}
1244
1245/*
1246 * Neo specific way of turning off the receiver.
1247 * Used as a way to enforce queue flow control when in
1248 * hardware flow control mode.
1249 */
1250static void neo_disable_receiver(struct jsm_channel *ch)
1251{
1252 u8 tmp = readb(&ch->ch_neo_uart->ier);
1253 tmp &= ~(UART_IER_RDI);
1254 writeb(tmp, &ch->ch_neo_uart->ier);
1255
1256 /* flush write operation */
1257 neo_pci_posting_flush(ch->ch_bd);
1258}
1259
1260
1261/*
1262 * Neo specific way of turning on the receiver.
1263 * Used as a way to un-enforce queue flow control when in
1264 * hardware flow control mode.
1265 */
1266static void neo_enable_receiver(struct jsm_channel *ch)
1267{
1268 u8 tmp = readb(&ch->ch_neo_uart->ier);
1269 tmp |= (UART_IER_RDI);
1270 writeb(tmp, &ch->ch_neo_uart->ier);
1271
1272 /* flush write operation */
1273 neo_pci_posting_flush(ch->ch_bd);
1274}
1275
1276static void neo_send_start_character(struct jsm_channel *ch)
1277{
1278 if (!ch)
1279 return;
1280
1281 if (ch->ch_startc != __DISABLED_CHAR) {
1282 ch->ch_xon_sends++;
1283 writeb(ch->ch_startc, &ch->ch_neo_uart->txrx);
1284
1285 /* flush write operation */
1286 neo_pci_posting_flush(ch->ch_bd);
1287 }
1288}
1289
1290static void neo_send_stop_character(struct jsm_channel *ch)
1291{
1292 if (!ch)
1293 return;
1294
1295 if (ch->ch_stopc != __DISABLED_CHAR) {
1296 ch->ch_xoff_sends++;
1297 writeb(ch->ch_stopc, &ch->ch_neo_uart->txrx);
1298
1299 /* flush write operation */
1300 neo_pci_posting_flush(ch->ch_bd);
1301 }
1302}
1303
1304/*
1305 * neo_uart_init
1306 */
1307static void neo_uart_init(struct jsm_channel *ch)
1308{
1309 writeb(0, &ch->ch_neo_uart->ier);
1310 writeb(0, &ch->ch_neo_uart->efr);
1311 writeb(UART_EFR_ECB, &ch->ch_neo_uart->efr);
1312
1313 /* Clear out UART and FIFO */
1314 readb(&ch->ch_neo_uart->txrx);
1315 writeb((UART_FCR_ENABLE_FIFO|UART_FCR_CLEAR_RCVR|UART_FCR_CLEAR_XMIT), &ch->ch_neo_uart->isr_fcr);
1316 readb(&ch->ch_neo_uart->lsr);
1317 readb(&ch->ch_neo_uart->msr);
1318
1319 ch->ch_flags |= CH_FIFO_ENABLED;
1320
1321 /* Assert any signals we want up */
1322 writeb(ch->ch_mostat, &ch->ch_neo_uart->mcr);
1323}
1324
1325/*
1326 * Make the UART completely turn off.
1327 */
1328static void neo_uart_off(struct jsm_channel *ch)
1329{
1330 /* Turn off UART enhanced bits */
1331 writeb(0, &ch->ch_neo_uart->efr);
1332
1333 /* Stop all interrupts from occurring. */
1334 writeb(0, &ch->ch_neo_uart->ier);
1335}
1336
1337static u32 neo_get_uart_bytes_left(struct jsm_channel *ch)
1338{
1339 u8 left = 0;
1340 u8 lsr = readb(&ch->ch_neo_uart->lsr);
1341
1342 /* We must cache the LSR as some of the bits get reset once read... */
1343 ch->ch_cached_lsr |= lsr;
1344
1345 /* Determine whether the Transmitter is empty or not */
1346 if (!(lsr & UART_LSR_TEMT))
1347 left = 1;
1348 else {
1349 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
1350 left = 0;
1351 }
1352
1353 return left;
1354}
1355
1356/* Channel lock MUST be held by the calling function! */
1357static void neo_send_break(struct jsm_channel *ch)
1358{
1359 /*
1360 * Set the time we should stop sending the break.
1361 * If we are already sending a break, toss away the existing
1362 * time to stop, and use this new value instead.
1363 */
1364
1365 /* Tell the UART to start sending the break */
1366 if (!(ch->ch_flags & CH_BREAK_SENDING)) {
1367 u8 temp = readb(&ch->ch_neo_uart->lcr);
1368 writeb((temp | UART_LCR_SBC), &ch->ch_neo_uart->lcr);
1369 ch->ch_flags |= (CH_BREAK_SENDING);
1370
1371 /* flush write operation */
1372 neo_pci_posting_flush(ch->ch_bd);
1373 }
1374}
1375
1376/*
1377 * neo_send_immediate_char.
1378 *
1379 * Sends a specific character as soon as possible to the UART,
1380 * jumping over any bytes that might be in the write queue.
1381 *
1382 * The channel lock MUST be held by the calling function.
1383 */
1384static void neo_send_immediate_char(struct jsm_channel *ch, unsigned char c)
1385{
1386 if (!ch)
1387 return;
1388
1389 writeb(c, &ch->ch_neo_uart->txrx);
1390
1391 /* flush write operation */
1392 neo_pci_posting_flush(ch->ch_bd);
1393}
1394
1395struct board_ops jsm_neo_ops = {
1396 .intr = neo_intr,
1397 .uart_init = neo_uart_init,
1398 .uart_off = neo_uart_off,
1399 .param = neo_param,
1400 .assert_modem_signals = neo_assert_modem_signals,
1401 .flush_uart_write = neo_flush_uart_write,
1402 .flush_uart_read = neo_flush_uart_read,
1403 .disable_receiver = neo_disable_receiver,
1404 .enable_receiver = neo_enable_receiver,
1405 .send_break = neo_send_break,
1406 .clear_break = neo_clear_break,
1407 .send_start_character = neo_send_start_character,
1408 .send_stop_character = neo_send_stop_character,
1409 .copy_data_from_queue_to_uart = neo_copy_data_from_queue_to_uart,
1410 .get_uart_bytes_left = neo_get_uart_bytes_left,
1411 .send_immediate_char = neo_send_immediate_char
1412};
diff --git a/drivers/tty/serial/jsm/jsm_tty.c b/drivers/tty/serial/jsm/jsm_tty.c
new file mode 100644
index 000000000000..7a4a914ecff0
--- /dev/null
+++ b/drivers/tty/serial/jsm/jsm_tty.c
@@ -0,0 +1,910 @@
1/************************************************************************
2 * Copyright 2003 Digi International (www.digi.com)
3 *
4 * Copyright (C) 2004 IBM Corporation. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2, or (at your option)
9 * any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY, EXPRESS OR IMPLIED; without even the
13 * implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
14 * PURPOSE. See the GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 * Temple Place - Suite 330, Boston,
19 * MA 02111-1307, USA.
20 *
21 * Contact Information:
22 * Scott H Kilau <Scott_Kilau@digi.com>
23 * Ananda Venkatarman <mansarov@us.ibm.com>
24 * Modifications:
25 * 01/19/06: changed jsm_input routine to use the dynamically allocated
26 * tty_buffer changes. Contributors: Scott Kilau and Ananda V.
27 ***********************************************************************/
28#include <linux/tty.h>
29#include <linux/tty_flip.h>
30#include <linux/serial_reg.h>
31#include <linux/delay.h> /* For udelay */
32#include <linux/pci.h>
33#include <linux/slab.h>
34
35#include "jsm.h"
36
37static DECLARE_BITMAP(linemap, MAXLINES);
38
39static void jsm_carrier(struct jsm_channel *ch);
40
41static inline int jsm_get_mstat(struct jsm_channel *ch)
42{
43 unsigned char mstat;
44 unsigned result;
45
46 jsm_printk(IOCTL, INFO, &ch->ch_bd->pci_dev, "start\n");
47
48 mstat = (ch->ch_mostat | ch->ch_mistat);
49
50 result = 0;
51
52 if (mstat & UART_MCR_DTR)
53 result |= TIOCM_DTR;
54 if (mstat & UART_MCR_RTS)
55 result |= TIOCM_RTS;
56 if (mstat & UART_MSR_CTS)
57 result |= TIOCM_CTS;
58 if (mstat & UART_MSR_DSR)
59 result |= TIOCM_DSR;
60 if (mstat & UART_MSR_RI)
61 result |= TIOCM_RI;
62 if (mstat & UART_MSR_DCD)
63 result |= TIOCM_CD;
64
65 jsm_printk(IOCTL, INFO, &ch->ch_bd->pci_dev, "finish\n");
66 return result;
67}
68
69static unsigned int jsm_tty_tx_empty(struct uart_port *port)
70{
71 return TIOCSER_TEMT;
72}
73
74/*
75 * Return modem signals to ld.
76 */
77static unsigned int jsm_tty_get_mctrl(struct uart_port *port)
78{
79 int result;
80 struct jsm_channel *channel = (struct jsm_channel *)port;
81
82 jsm_printk(IOCTL, INFO, &channel->ch_bd->pci_dev, "start\n");
83
84 result = jsm_get_mstat(channel);
85
86 if (result < 0)
87 return -ENXIO;
88
89 jsm_printk(IOCTL, INFO, &channel->ch_bd->pci_dev, "finish\n");
90
91 return result;
92}
93
94/*
95 * jsm_set_modem_info()
96 *
97 * Set modem signals, called by ld.
98 */
99static void jsm_tty_set_mctrl(struct uart_port *port, unsigned int mctrl)
100{
101 struct jsm_channel *channel = (struct jsm_channel *)port;
102
103 jsm_printk(IOCTL, INFO, &channel->ch_bd->pci_dev, "start\n");
104
105 if (mctrl & TIOCM_RTS)
106 channel->ch_mostat |= UART_MCR_RTS;
107 else
108 channel->ch_mostat &= ~UART_MCR_RTS;
109
110 if (mctrl & TIOCM_DTR)
111 channel->ch_mostat |= UART_MCR_DTR;
112 else
113 channel->ch_mostat &= ~UART_MCR_DTR;
114
115 channel->ch_bd->bd_ops->assert_modem_signals(channel);
116
117 jsm_printk(IOCTL, INFO, &channel->ch_bd->pci_dev, "finish\n");
118 udelay(10);
119}
120
121static void jsm_tty_start_tx(struct uart_port *port)
122{
123 struct jsm_channel *channel = (struct jsm_channel *)port;
124
125 jsm_printk(IOCTL, INFO, &channel->ch_bd->pci_dev, "start\n");
126
127 channel->ch_flags &= ~(CH_STOP);
128 jsm_tty_write(port);
129
130 jsm_printk(IOCTL, INFO, &channel->ch_bd->pci_dev, "finish\n");
131}
132
133static void jsm_tty_stop_tx(struct uart_port *port)
134{
135 struct jsm_channel *channel = (struct jsm_channel *)port;
136
137 jsm_printk(IOCTL, INFO, &channel->ch_bd->pci_dev, "start\n");
138
139 channel->ch_flags |= (CH_STOP);
140
141 jsm_printk(IOCTL, INFO, &channel->ch_bd->pci_dev, "finish\n");
142}
143
144static void jsm_tty_send_xchar(struct uart_port *port, char ch)
145{
146 unsigned long lock_flags;
147 struct jsm_channel *channel = (struct jsm_channel *)port;
148 struct ktermios *termios;
149
150 spin_lock_irqsave(&port->lock, lock_flags);
151 termios = port->state->port.tty->termios;
152 if (ch == termios->c_cc[VSTART])
153 channel->ch_bd->bd_ops->send_start_character(channel);
154
155 if (ch == termios->c_cc[VSTOP])
156 channel->ch_bd->bd_ops->send_stop_character(channel);
157 spin_unlock_irqrestore(&port->lock, lock_flags);
158}
159
160static void jsm_tty_stop_rx(struct uart_port *port)
161{
162 struct jsm_channel *channel = (struct jsm_channel *)port;
163
164 channel->ch_bd->bd_ops->disable_receiver(channel);
165}
166
167static void jsm_tty_enable_ms(struct uart_port *port)
168{
169 /* Nothing needed */
170}
171
172static void jsm_tty_break(struct uart_port *port, int break_state)
173{
174 unsigned long lock_flags;
175 struct jsm_channel *channel = (struct jsm_channel *)port;
176
177 spin_lock_irqsave(&port->lock, lock_flags);
178 if (break_state == -1)
179 channel->ch_bd->bd_ops->send_break(channel);
180 else
181 channel->ch_bd->bd_ops->clear_break(channel, 0);
182
183 spin_unlock_irqrestore(&port->lock, lock_flags);
184}
185
186static int jsm_tty_open(struct uart_port *port)
187{
188 struct jsm_board *brd;
189 struct jsm_channel *channel = (struct jsm_channel *)port;
190 struct ktermios *termios;
191
192 /* Get board pointer from our array of majors we have allocated */
193 brd = channel->ch_bd;
194
195 /*
196 * Allocate channel buffers for read/write/error.
197 * Set flag, so we don't get trounced on.
198 */
199 channel->ch_flags |= (CH_OPENING);
200
201 /* Drop locks, as malloc with GFP_KERNEL can sleep */
202
203 if (!channel->ch_rqueue) {
204 channel->ch_rqueue = kzalloc(RQUEUESIZE, GFP_KERNEL);
205 if (!channel->ch_rqueue) {
206 jsm_printk(INIT, ERR, &channel->ch_bd->pci_dev,
207 "unable to allocate read queue buf");
208 return -ENOMEM;
209 }
210 }
211 if (!channel->ch_equeue) {
212 channel->ch_equeue = kzalloc(EQUEUESIZE, GFP_KERNEL);
213 if (!channel->ch_equeue) {
214 jsm_printk(INIT, ERR, &channel->ch_bd->pci_dev,
215 "unable to allocate error queue buf");
216 return -ENOMEM;
217 }
218 }
219 if (!channel->ch_wqueue) {
220 channel->ch_wqueue = kzalloc(WQUEUESIZE, GFP_KERNEL);
221 if (!channel->ch_wqueue) {
222 jsm_printk(INIT, ERR, &channel->ch_bd->pci_dev,
223 "unable to allocate write queue buf");
224 return -ENOMEM;
225 }
226 }
227
228 channel->ch_flags &= ~(CH_OPENING);
229 /*
230 * Initialize if neither terminal is open.
231 */
232 jsm_printk(OPEN, INFO, &channel->ch_bd->pci_dev,
233 "jsm_open: initializing channel in open...\n");
234
235 /*
236 * Flush input queues.
237 */
238 channel->ch_r_head = channel->ch_r_tail = 0;
239 channel->ch_e_head = channel->ch_e_tail = 0;
240 channel->ch_w_head = channel->ch_w_tail = 0;
241
242 brd->bd_ops->flush_uart_write(channel);
243 brd->bd_ops->flush_uart_read(channel);
244
245 channel->ch_flags = 0;
246 channel->ch_cached_lsr = 0;
247 channel->ch_stops_sent = 0;
248
249 termios = port->state->port.tty->termios;
250 channel->ch_c_cflag = termios->c_cflag;
251 channel->ch_c_iflag = termios->c_iflag;
252 channel->ch_c_oflag = termios->c_oflag;
253 channel->ch_c_lflag = termios->c_lflag;
254 channel->ch_startc = termios->c_cc[VSTART];
255 channel->ch_stopc = termios->c_cc[VSTOP];
256
257 /* Tell UART to init itself */
258 brd->bd_ops->uart_init(channel);
259
260 /*
261 * Run param in case we changed anything
262 */
263 brd->bd_ops->param(channel);
264
265 jsm_carrier(channel);
266
267 channel->ch_open_count++;
268
269 jsm_printk(OPEN, INFO, &channel->ch_bd->pci_dev, "finish\n");
270 return 0;
271}
272
273static void jsm_tty_close(struct uart_port *port)
274{
275 struct jsm_board *bd;
276 struct ktermios *ts;
277 struct jsm_channel *channel = (struct jsm_channel *)port;
278
279 jsm_printk(CLOSE, INFO, &channel->ch_bd->pci_dev, "start\n");
280
281 bd = channel->ch_bd;
282 ts = port->state->port.tty->termios;
283
284 channel->ch_flags &= ~(CH_STOPI);
285
286 channel->ch_open_count--;
287
288 /*
289 * If we have HUPCL set, lower DTR and RTS
290 */
291 if (channel->ch_c_cflag & HUPCL) {
292 jsm_printk(CLOSE, INFO, &channel->ch_bd->pci_dev,
293 "Close. HUPCL set, dropping DTR/RTS\n");
294
295 /* Drop RTS/DTR */
296 channel->ch_mostat &= ~(UART_MCR_DTR | UART_MCR_RTS);
297 bd->bd_ops->assert_modem_signals(channel);
298 }
299
300 /* Turn off UART interrupts for this port */
301 channel->ch_bd->bd_ops->uart_off(channel);
302
303 jsm_printk(CLOSE, INFO, &channel->ch_bd->pci_dev, "finish\n");
304}
305
306static void jsm_tty_set_termios(struct uart_port *port,
307 struct ktermios *termios,
308 struct ktermios *old_termios)
309{
310 unsigned long lock_flags;
311 struct jsm_channel *channel = (struct jsm_channel *)port;
312
313 spin_lock_irqsave(&port->lock, lock_flags);
314 channel->ch_c_cflag = termios->c_cflag;
315 channel->ch_c_iflag = termios->c_iflag;
316 channel->ch_c_oflag = termios->c_oflag;
317 channel->ch_c_lflag = termios->c_lflag;
318 channel->ch_startc = termios->c_cc[VSTART];
319 channel->ch_stopc = termios->c_cc[VSTOP];
320
321 channel->ch_bd->bd_ops->param(channel);
322 jsm_carrier(channel);
323 spin_unlock_irqrestore(&port->lock, lock_flags);
324}
325
326static const char *jsm_tty_type(struct uart_port *port)
327{
328 return "jsm";
329}
330
331static void jsm_tty_release_port(struct uart_port *port)
332{
333}
334
335static int jsm_tty_request_port(struct uart_port *port)
336{
337 return 0;
338}
339
340static void jsm_config_port(struct uart_port *port, int flags)
341{
342 port->type = PORT_JSM;
343}
344
345static struct uart_ops jsm_ops = {
346 .tx_empty = jsm_tty_tx_empty,
347 .set_mctrl = jsm_tty_set_mctrl,
348 .get_mctrl = jsm_tty_get_mctrl,
349 .stop_tx = jsm_tty_stop_tx,
350 .start_tx = jsm_tty_start_tx,
351 .send_xchar = jsm_tty_send_xchar,
352 .stop_rx = jsm_tty_stop_rx,
353 .enable_ms = jsm_tty_enable_ms,
354 .break_ctl = jsm_tty_break,
355 .startup = jsm_tty_open,
356 .shutdown = jsm_tty_close,
357 .set_termios = jsm_tty_set_termios,
358 .type = jsm_tty_type,
359 .release_port = jsm_tty_release_port,
360 .request_port = jsm_tty_request_port,
361 .config_port = jsm_config_port,
362};
363
364/*
365 * jsm_tty_init()
366 *
367 * Init the tty subsystem. Called once per board after board has been
368 * downloaded and init'ed.
369 */
370int __devinit jsm_tty_init(struct jsm_board *brd)
371{
372 int i;
373 void __iomem *vaddr;
374 struct jsm_channel *ch;
375
376 if (!brd)
377 return -ENXIO;
378
379 jsm_printk(INIT, INFO, &brd->pci_dev, "start\n");
380
381 /*
382 * Initialize board structure elements.
383 */
384
385 brd->nasync = brd->maxports;
386
387 /*
388 * Allocate channel memory that might not have been allocated
389 * when the driver was first loaded.
390 */
391 for (i = 0; i < brd->nasync; i++) {
392 if (!brd->channels[i]) {
393
394 /*
395 * Okay to malloc with GFP_KERNEL, we are not at
396 * interrupt context, and there are no locks held.
397 */
398 brd->channels[i] = kzalloc(sizeof(struct jsm_channel), GFP_KERNEL);
399 if (!brd->channels[i]) {
400 jsm_printk(CORE, ERR, &brd->pci_dev,
401 "%s:%d Unable to allocate memory for channel struct\n",
402 __FILE__, __LINE__);
403 }
404 }
405 }
406
407 ch = brd->channels[0];
408 vaddr = brd->re_map_membase;
409
410 /* Set up channel variables */
411 for (i = 0; i < brd->nasync; i++, ch = brd->channels[i]) {
412
413 if (!brd->channels[i])
414 continue;
415
416 spin_lock_init(&ch->ch_lock);
417
418 if (brd->bd_uart_offset == 0x200)
419 ch->ch_neo_uart = vaddr + (brd->bd_uart_offset * i);
420
421 ch->ch_bd = brd;
422 ch->ch_portnum = i;
423
424 /* .25 second delay */
425 ch->ch_close_delay = 250;
426
427 init_waitqueue_head(&ch->ch_flags_wait);
428 }
429
430 jsm_printk(INIT, INFO, &brd->pci_dev, "finish\n");
431 return 0;
432}
433
434int jsm_uart_port_init(struct jsm_board *brd)
435{
436 int i, rc;
437 unsigned int line;
438 struct jsm_channel *ch;
439
440 if (!brd)
441 return -ENXIO;
442
443 jsm_printk(INIT, INFO, &brd->pci_dev, "start\n");
444
445 /*
446 * Initialize board structure elements.
447 */
448
449 brd->nasync = brd->maxports;
450
451 /* Set up channel variables */
452 for (i = 0; i < brd->nasync; i++, ch = brd->channels[i]) {
453
454 if (!brd->channels[i])
455 continue;
456
457 brd->channels[i]->uart_port.irq = brd->irq;
458 brd->channels[i]->uart_port.uartclk = 14745600;
459 brd->channels[i]->uart_port.type = PORT_JSM;
460 brd->channels[i]->uart_port.iotype = UPIO_MEM;
461 brd->channels[i]->uart_port.membase = brd->re_map_membase;
462 brd->channels[i]->uart_port.fifosize = 16;
463 brd->channels[i]->uart_port.ops = &jsm_ops;
464 line = find_first_zero_bit(linemap, MAXLINES);
465 if (line >= MAXLINES) {
466 printk(KERN_INFO "jsm: linemap is full, added device failed\n");
467 continue;
468 } else
469 set_bit(line, linemap);
470 brd->channels[i]->uart_port.line = line;
471 rc = uart_add_one_port (&jsm_uart_driver, &brd->channels[i]->uart_port);
472 if (rc){
473 printk(KERN_INFO "jsm: Port %d failed. Aborting...\n", i);
474 return rc;
475 }
476 else
477 printk(KERN_INFO "jsm: Port %d added\n", i);
478 }
479
480 jsm_printk(INIT, INFO, &brd->pci_dev, "finish\n");
481 return 0;
482}
483
484int jsm_remove_uart_port(struct jsm_board *brd)
485{
486 int i;
487 struct jsm_channel *ch;
488
489 if (!brd)
490 return -ENXIO;
491
492 jsm_printk(INIT, INFO, &brd->pci_dev, "start\n");
493
494 /*
495 * Initialize board structure elements.
496 */
497
498 brd->nasync = brd->maxports;
499
500 /* Set up channel variables */
501 for (i = 0; i < brd->nasync; i++) {
502
503 if (!brd->channels[i])
504 continue;
505
506 ch = brd->channels[i];
507
508 clear_bit(ch->uart_port.line, linemap);
509 uart_remove_one_port(&jsm_uart_driver, &brd->channels[i]->uart_port);
510 }
511
512 jsm_printk(INIT, INFO, &brd->pci_dev, "finish\n");
513 return 0;
514}
515
516void jsm_input(struct jsm_channel *ch)
517{
518 struct jsm_board *bd;
519 struct tty_struct *tp;
520 u32 rmask;
521 u16 head;
522 u16 tail;
523 int data_len;
524 unsigned long lock_flags;
525 int len = 0;
526 int n = 0;
527 int s = 0;
528 int i = 0;
529
530 jsm_printk(READ, INFO, &ch->ch_bd->pci_dev, "start\n");
531
532 if (!ch)
533 return;
534
535 tp = ch->uart_port.state->port.tty;
536
537 bd = ch->ch_bd;
538 if(!bd)
539 return;
540
541 spin_lock_irqsave(&ch->ch_lock, lock_flags);
542
543 /*
544 *Figure the number of characters in the buffer.
545 *Exit immediately if none.
546 */
547
548 rmask = RQUEUEMASK;
549
550 head = ch->ch_r_head & rmask;
551 tail = ch->ch_r_tail & rmask;
552
553 data_len = (head - tail) & rmask;
554 if (data_len == 0) {
555 spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
556 return;
557 }
558
559 jsm_printk(READ, INFO, &ch->ch_bd->pci_dev, "start\n");
560
561 /*
562 *If the device is not open, or CREAD is off, flush
563 *input data and return immediately.
564 */
565 if (!tp ||
566 !(tp->termios->c_cflag & CREAD) ) {
567
568 jsm_printk(READ, INFO, &ch->ch_bd->pci_dev,
569 "input. dropping %d bytes on port %d...\n", data_len, ch->ch_portnum);
570 ch->ch_r_head = tail;
571
572 /* Force queue flow control to be released, if needed */
573 jsm_check_queue_flow_control(ch);
574
575 spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
576 return;
577 }
578
579 /*
580 * If we are throttled, simply don't read any data.
581 */
582 if (ch->ch_flags & CH_STOPI) {
583 spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
584 jsm_printk(READ, INFO, &ch->ch_bd->pci_dev,
585 "Port %d throttled, not reading any data. head: %x tail: %x\n",
586 ch->ch_portnum, head, tail);
587 return;
588 }
589
590 jsm_printk(READ, INFO, &ch->ch_bd->pci_dev, "start 2\n");
591
592 if (data_len <= 0) {
593 spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
594 jsm_printk(READ, INFO, &ch->ch_bd->pci_dev, "jsm_input 1\n");
595 return;
596 }
597
598 len = tty_buffer_request_room(tp, data_len);
599 n = len;
600
601 /*
602 * n now contains the most amount of data we can copy,
603 * bounded either by the flip buffer size or the amount
604 * of data the card actually has pending...
605 */
606 while (n) {
607 s = ((head >= tail) ? head : RQUEUESIZE) - tail;
608 s = min(s, n);
609
610 if (s <= 0)
611 break;
612
613 /*
614 * If conditions are such that ld needs to see all
615 * UART errors, we will have to walk each character
616 * and error byte and send them to the buffer one at
617 * a time.
618 */
619
620 if (I_PARMRK(tp) || I_BRKINT(tp) || I_INPCK(tp)) {
621 for (i = 0; i < s; i++) {
622 /*
623 * Give the Linux ld the flags in the
624 * format it likes.
625 */
626 if (*(ch->ch_equeue +tail +i) & UART_LSR_BI)
627 tty_insert_flip_char(tp, *(ch->ch_rqueue +tail +i), TTY_BREAK);
628 else if (*(ch->ch_equeue +tail +i) & UART_LSR_PE)
629 tty_insert_flip_char(tp, *(ch->ch_rqueue +tail +i), TTY_PARITY);
630 else if (*(ch->ch_equeue +tail +i) & UART_LSR_FE)
631 tty_insert_flip_char(tp, *(ch->ch_rqueue +tail +i), TTY_FRAME);
632 else
633 tty_insert_flip_char(tp, *(ch->ch_rqueue +tail +i), TTY_NORMAL);
634 }
635 } else {
636 tty_insert_flip_string(tp, ch->ch_rqueue + tail, s) ;
637 }
638 tail += s;
639 n -= s;
640 /* Flip queue if needed */
641 tail &= rmask;
642 }
643
644 ch->ch_r_tail = tail & rmask;
645 ch->ch_e_tail = tail & rmask;
646 jsm_check_queue_flow_control(ch);
647 spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
648
649 /* Tell the tty layer its okay to "eat" the data now */
650 tty_flip_buffer_push(tp);
651
652 jsm_printk(IOCTL, INFO, &ch->ch_bd->pci_dev, "finish\n");
653}
654
655static void jsm_carrier(struct jsm_channel *ch)
656{
657 struct jsm_board *bd;
658
659 int virt_carrier = 0;
660 int phys_carrier = 0;
661
662 jsm_printk(CARR, INFO, &ch->ch_bd->pci_dev, "start\n");
663 if (!ch)
664 return;
665
666 bd = ch->ch_bd;
667
668 if (!bd)
669 return;
670
671 if (ch->ch_mistat & UART_MSR_DCD) {
672 jsm_printk(CARR, INFO, &ch->ch_bd->pci_dev,
673 "mistat: %x D_CD: %x\n", ch->ch_mistat, ch->ch_mistat & UART_MSR_DCD);
674 phys_carrier = 1;
675 }
676
677 if (ch->ch_c_cflag & CLOCAL)
678 virt_carrier = 1;
679
680 jsm_printk(CARR, INFO, &ch->ch_bd->pci_dev,
681 "DCD: physical: %d virt: %d\n", phys_carrier, virt_carrier);
682
683 /*
684 * Test for a VIRTUAL carrier transition to HIGH.
685 */
686 if (((ch->ch_flags & CH_FCAR) == 0) && (virt_carrier == 1)) {
687
688 /*
689 * When carrier rises, wake any threads waiting
690 * for carrier in the open routine.
691 */
692
693 jsm_printk(CARR, INFO, &ch->ch_bd->pci_dev,
694 "carrier: virt DCD rose\n");
695
696 if (waitqueue_active(&(ch->ch_flags_wait)))
697 wake_up_interruptible(&ch->ch_flags_wait);
698 }
699
700 /*
701 * Test for a PHYSICAL carrier transition to HIGH.
702 */
703 if (((ch->ch_flags & CH_CD) == 0) && (phys_carrier == 1)) {
704
705 /*
706 * When carrier rises, wake any threads waiting
707 * for carrier in the open routine.
708 */
709
710 jsm_printk(CARR, INFO, &ch->ch_bd->pci_dev,
711 "carrier: physical DCD rose\n");
712
713 if (waitqueue_active(&(ch->ch_flags_wait)))
714 wake_up_interruptible(&ch->ch_flags_wait);
715 }
716
717 /*
718 * Test for a PHYSICAL transition to low, so long as we aren't
719 * currently ignoring physical transitions (which is what "virtual
720 * carrier" indicates).
721 *
722 * The transition of the virtual carrier to low really doesn't
723 * matter... it really only means "ignore carrier state", not
724 * "make pretend that carrier is there".
725 */
726 if ((virt_carrier == 0) && ((ch->ch_flags & CH_CD) != 0)
727 && (phys_carrier == 0)) {
728 /*
729 * When carrier drops:
730 *
731 * Drop carrier on all open units.
732 *
733 * Flush queues, waking up any task waiting in the
734 * line discipline.
735 *
736 * Send a hangup to the control terminal.
737 *
738 * Enable all select calls.
739 */
740 if (waitqueue_active(&(ch->ch_flags_wait)))
741 wake_up_interruptible(&ch->ch_flags_wait);
742 }
743
744 /*
745 * Make sure that our cached values reflect the current reality.
746 */
747 if (virt_carrier == 1)
748 ch->ch_flags |= CH_FCAR;
749 else
750 ch->ch_flags &= ~CH_FCAR;
751
752 if (phys_carrier == 1)
753 ch->ch_flags |= CH_CD;
754 else
755 ch->ch_flags &= ~CH_CD;
756}
757
758
759void jsm_check_queue_flow_control(struct jsm_channel *ch)
760{
761 struct board_ops *bd_ops = ch->ch_bd->bd_ops;
762 int qleft;
763
764 /* Store how much space we have left in the queue */
765 if ((qleft = ch->ch_r_tail - ch->ch_r_head - 1) < 0)
766 qleft += RQUEUEMASK + 1;
767
768 /*
769 * Check to see if we should enforce flow control on our queue because
770 * the ld (or user) isn't reading data out of our queue fast enuf.
771 *
772 * NOTE: This is done based on what the current flow control of the
773 * port is set for.
774 *
775 * 1) HWFLOW (RTS) - Turn off the UART's Receive interrupt.
776 * This will cause the UART's FIFO to back up, and force
777 * the RTS signal to be dropped.
778 * 2) SWFLOW (IXOFF) - Keep trying to send a stop character to
779 * the other side, in hopes it will stop sending data to us.
780 * 3) NONE - Nothing we can do. We will simply drop any extra data
781 * that gets sent into us when the queue fills up.
782 */
783 if (qleft < 256) {
784 /* HWFLOW */
785 if (ch->ch_c_cflag & CRTSCTS) {
786 if(!(ch->ch_flags & CH_RECEIVER_OFF)) {
787 bd_ops->disable_receiver(ch);
788 ch->ch_flags |= (CH_RECEIVER_OFF);
789 jsm_printk(READ, INFO, &ch->ch_bd->pci_dev,
790 "Internal queue hit hilevel mark (%d)! Turning off interrupts.\n",
791 qleft);
792 }
793 }
794 /* SWFLOW */
795 else if (ch->ch_c_iflag & IXOFF) {
796 if (ch->ch_stops_sent <= MAX_STOPS_SENT) {
797 bd_ops->send_stop_character(ch);
798 ch->ch_stops_sent++;
799 jsm_printk(READ, INFO, &ch->ch_bd->pci_dev,
800 "Sending stop char! Times sent: %x\n", ch->ch_stops_sent);
801 }
802 }
803 }
804
805 /*
806 * Check to see if we should unenforce flow control because
807 * ld (or user) finally read enuf data out of our queue.
808 *
809 * NOTE: This is done based on what the current flow control of the
810 * port is set for.
811 *
812 * 1) HWFLOW (RTS) - Turn back on the UART's Receive interrupt.
813 * This will cause the UART's FIFO to raise RTS back up,
814 * which will allow the other side to start sending data again.
815 * 2) SWFLOW (IXOFF) - Send a start character to
816 * the other side, so it will start sending data to us again.
817 * 3) NONE - Do nothing. Since we didn't do anything to turn off the
818 * other side, we don't need to do anything now.
819 */
820 if (qleft > (RQUEUESIZE / 2)) {
821 /* HWFLOW */
822 if (ch->ch_c_cflag & CRTSCTS) {
823 if (ch->ch_flags & CH_RECEIVER_OFF) {
824 bd_ops->enable_receiver(ch);
825 ch->ch_flags &= ~(CH_RECEIVER_OFF);
826 jsm_printk(READ, INFO, &ch->ch_bd->pci_dev,
827 "Internal queue hit lowlevel mark (%d)! Turning on interrupts.\n",
828 qleft);
829 }
830 }
831 /* SWFLOW */
832 else if (ch->ch_c_iflag & IXOFF && ch->ch_stops_sent) {
833 ch->ch_stops_sent = 0;
834 bd_ops->send_start_character(ch);
835 jsm_printk(READ, INFO, &ch->ch_bd->pci_dev, "Sending start char!\n");
836 }
837 }
838}
839
840/*
841 * jsm_tty_write()
842 *
843 * Take data from the user or kernel and send it out to the FEP.
844 * In here exists all the Transparent Print magic as well.
845 */
846int jsm_tty_write(struct uart_port *port)
847{
848 int bufcount;
849 int data_count = 0,data_count1 =0;
850 u16 head;
851 u16 tail;
852 u16 tmask;
853 u32 remain;
854 int temp_tail = port->state->xmit.tail;
855 struct jsm_channel *channel = (struct jsm_channel *)port;
856
857 tmask = WQUEUEMASK;
858 head = (channel->ch_w_head) & tmask;
859 tail = (channel->ch_w_tail) & tmask;
860
861 if ((bufcount = tail - head - 1) < 0)
862 bufcount += WQUEUESIZE;
863
864 bufcount = min(bufcount, 56);
865 remain = WQUEUESIZE - head;
866
867 data_count = 0;
868 if (bufcount >= remain) {
869 bufcount -= remain;
870 while ((port->state->xmit.head != temp_tail) &&
871 (data_count < remain)) {
872 channel->ch_wqueue[head++] =
873 port->state->xmit.buf[temp_tail];
874
875 temp_tail++;
876 temp_tail &= (UART_XMIT_SIZE - 1);
877 data_count++;
878 }
879 if (data_count == remain) head = 0;
880 }
881
882 data_count1 = 0;
883 if (bufcount > 0) {
884 remain = bufcount;
885 while ((port->state->xmit.head != temp_tail) &&
886 (data_count1 < remain)) {
887 channel->ch_wqueue[head++] =
888 port->state->xmit.buf[temp_tail];
889
890 temp_tail++;
891 temp_tail &= (UART_XMIT_SIZE - 1);
892 data_count1++;
893
894 }
895 }
896
897 port->state->xmit.tail = temp_tail;
898
899 data_count += data_count1;
900 if (data_count) {
901 head &= tmask;
902 channel->ch_w_head = head;
903 }
904
905 if (data_count) {
906 channel->ch_bd->bd_ops->copy_data_from_queue_to_uart(channel);
907 }
908
909 return data_count;
910}
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-22 15:47:22 -0500