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authorOlof Johansson <olof@lixom.net>2012-02-07 18:04:15 -0500
committerOlof Johansson <olof@lixom.net>2012-02-07 18:05:20 -0500
commita5f17d1f4c2831b9b9bf8b1a537cdbac995d6e13 (patch)
treecce7eab28de00a88d75b8eda704f5838e10947b1 /drivers/tty/serial/8250
parentdcf81c1af839b77b44404453ecae6e5ac5a75f05 (diff)
parent62aa2b537c6f5957afd98e29f96897419ed5ebab (diff)
Merge tag 'v3.3-rc2' into depends/rmk/for-armsoc
There were conflicts between fixes going in after 3.3-rc1 and Russell's stable arm-soc base branch. Resolving it in the dependency branch so that each topic branch shares the same resolution. Conflicts: arch/arm/mach-at91/at91cap9.c arch/arm/mach-at91/at91sam9g45.c
Diffstat (limited to 'drivers/tty/serial/8250')
-rw-r--r--drivers/tty/serial/8250/8250.c3357
-rw-r--r--drivers/tty/serial/8250/8250.h105
-rw-r--r--drivers/tty/serial/8250/8250_accent.c45
-rw-r--r--drivers/tty/serial/8250/8250_acorn.c141
-rw-r--r--drivers/tty/serial/8250/8250_boca.c59
-rw-r--r--drivers/tty/serial/8250/8250_dw.c184
-rw-r--r--drivers/tty/serial/8250/8250_early.c287
-rw-r--r--drivers/tty/serial/8250/8250_exar_st16c554.c50
-rw-r--r--drivers/tty/serial/8250/8250_fourport.c51
-rw-r--r--drivers/tty/serial/8250/8250_fsl.c63
-rw-r--r--drivers/tty/serial/8250/8250_gsc.c122
-rw-r--r--drivers/tty/serial/8250/8250_hp300.c327
-rw-r--r--drivers/tty/serial/8250/8250_hub6.c56
-rw-r--r--drivers/tty/serial/8250/8250_mca.c61
-rw-r--r--drivers/tty/serial/8250/8250_pci.c4223
-rw-r--r--drivers/tty/serial/8250/8250_pnp.c524
-rw-r--r--drivers/tty/serial/8250/Kconfig280
-rw-r--r--drivers/tty/serial/8250/Makefile20
-rw-r--r--drivers/tty/serial/8250/m32r_sio.c1191
-rw-r--r--drivers/tty/serial/8250/m32r_sio.h48
-rw-r--r--drivers/tty/serial/8250/m32r_sio_reg.h152
-rw-r--r--drivers/tty/serial/8250/serial_cs.c870
22 files changed, 12216 insertions, 0 deletions
diff --git a/drivers/tty/serial/8250/8250.c b/drivers/tty/serial/8250/8250.c
new file mode 100644
index 000000000000..9f50c4e3c2be
--- /dev/null
+++ b/drivers/tty/serial/8250/8250.c
@@ -0,0 +1,3357 @@
1/*
2 * Driver for 8250/16550-type serial ports
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Copyright (C) 2001 Russell King.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * A note about mapbase / membase
14 *
15 * mapbase is the physical address of the IO port.
16 * membase is an 'ioremapped' cookie.
17 */
18
19#if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
20#define SUPPORT_SYSRQ
21#endif
22
23#include <linux/module.h>
24#include <linux/moduleparam.h>
25#include <linux/ioport.h>
26#include <linux/init.h>
27#include <linux/console.h>
28#include <linux/sysrq.h>
29#include <linux/delay.h>
30#include <linux/platform_device.h>
31#include <linux/tty.h>
32#include <linux/ratelimit.h>
33#include <linux/tty_flip.h>
34#include <linux/serial_reg.h>
35#include <linux/serial_core.h>
36#include <linux/serial.h>
37#include <linux/serial_8250.h>
38#include <linux/nmi.h>
39#include <linux/mutex.h>
40#include <linux/slab.h>
41
42#include <asm/io.h>
43#include <asm/irq.h>
44
45#include "8250.h"
46
47#ifdef CONFIG_SPARC
48#include "suncore.h"
49#endif
50
51/*
52 * Configuration:
53 * share_irqs - whether we pass IRQF_SHARED to request_irq(). This option
54 * is unsafe when used on edge-triggered interrupts.
55 */
56static unsigned int share_irqs = SERIAL8250_SHARE_IRQS;
57
58static unsigned int nr_uarts = CONFIG_SERIAL_8250_RUNTIME_UARTS;
59
60static struct uart_driver serial8250_reg;
61
62static int serial_index(struct uart_port *port)
63{
64 return (serial8250_reg.minor - 64) + port->line;
65}
66
67static unsigned int skip_txen_test; /* force skip of txen test at init time */
68
69/*
70 * Debugging.
71 */
72#if 0
73#define DEBUG_AUTOCONF(fmt...) printk(fmt)
74#else
75#define DEBUG_AUTOCONF(fmt...) do { } while (0)
76#endif
77
78#if 0
79#define DEBUG_INTR(fmt...) printk(fmt)
80#else
81#define DEBUG_INTR(fmt...) do { } while (0)
82#endif
83
84#define PASS_LIMIT 512
85
86#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
87
88
89/*
90 * We default to IRQ0 for the "no irq" hack. Some
91 * machine types want others as well - they're free
92 * to redefine this in their header file.
93 */
94#define is_real_interrupt(irq) ((irq) != 0)
95
96#ifdef CONFIG_SERIAL_8250_DETECT_IRQ
97#define CONFIG_SERIAL_DETECT_IRQ 1
98#endif
99#ifdef CONFIG_SERIAL_8250_MANY_PORTS
100#define CONFIG_SERIAL_MANY_PORTS 1
101#endif
102
103/*
104 * HUB6 is always on. This will be removed once the header
105 * files have been cleaned.
106 */
107#define CONFIG_HUB6 1
108
109#include <asm/serial.h>
110/*
111 * SERIAL_PORT_DFNS tells us about built-in ports that have no
112 * standard enumeration mechanism. Platforms that can find all
113 * serial ports via mechanisms like ACPI or PCI need not supply it.
114 */
115#ifndef SERIAL_PORT_DFNS
116#define SERIAL_PORT_DFNS
117#endif
118
119static const struct old_serial_port old_serial_port[] = {
120 SERIAL_PORT_DFNS /* defined in asm/serial.h */
121};
122
123#define UART_NR CONFIG_SERIAL_8250_NR_UARTS
124
125#ifdef CONFIG_SERIAL_8250_RSA
126
127#define PORT_RSA_MAX 4
128static unsigned long probe_rsa[PORT_RSA_MAX];
129static unsigned int probe_rsa_count;
130#endif /* CONFIG_SERIAL_8250_RSA */
131
132struct irq_info {
133 struct hlist_node node;
134 int irq;
135 spinlock_t lock; /* Protects list not the hash */
136 struct list_head *head;
137};
138
139#define NR_IRQ_HASH 32 /* Can be adjusted later */
140static struct hlist_head irq_lists[NR_IRQ_HASH];
141static DEFINE_MUTEX(hash_mutex); /* Used to walk the hash */
142
143/*
144 * Here we define the default xmit fifo size used for each type of UART.
145 */
146static const struct serial8250_config uart_config[] = {
147 [PORT_UNKNOWN] = {
148 .name = "unknown",
149 .fifo_size = 1,
150 .tx_loadsz = 1,
151 },
152 [PORT_8250] = {
153 .name = "8250",
154 .fifo_size = 1,
155 .tx_loadsz = 1,
156 },
157 [PORT_16450] = {
158 .name = "16450",
159 .fifo_size = 1,
160 .tx_loadsz = 1,
161 },
162 [PORT_16550] = {
163 .name = "16550",
164 .fifo_size = 1,
165 .tx_loadsz = 1,
166 },
167 [PORT_16550A] = {
168 .name = "16550A",
169 .fifo_size = 16,
170 .tx_loadsz = 16,
171 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
172 .flags = UART_CAP_FIFO,
173 },
174 [PORT_CIRRUS] = {
175 .name = "Cirrus",
176 .fifo_size = 1,
177 .tx_loadsz = 1,
178 },
179 [PORT_16650] = {
180 .name = "ST16650",
181 .fifo_size = 1,
182 .tx_loadsz = 1,
183 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
184 },
185 [PORT_16650V2] = {
186 .name = "ST16650V2",
187 .fifo_size = 32,
188 .tx_loadsz = 16,
189 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
190 UART_FCR_T_TRIG_00,
191 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
192 },
193 [PORT_16750] = {
194 .name = "TI16750",
195 .fifo_size = 64,
196 .tx_loadsz = 64,
197 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
198 UART_FCR7_64BYTE,
199 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
200 },
201 [PORT_STARTECH] = {
202 .name = "Startech",
203 .fifo_size = 1,
204 .tx_loadsz = 1,
205 },
206 [PORT_16C950] = {
207 .name = "16C950/954",
208 .fifo_size = 128,
209 .tx_loadsz = 128,
210 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
211 /* UART_CAP_EFR breaks billionon CF bluetooth card. */
212 .flags = UART_CAP_FIFO | UART_CAP_SLEEP,
213 },
214 [PORT_16654] = {
215 .name = "ST16654",
216 .fifo_size = 64,
217 .tx_loadsz = 32,
218 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
219 UART_FCR_T_TRIG_10,
220 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
221 },
222 [PORT_16850] = {
223 .name = "XR16850",
224 .fifo_size = 128,
225 .tx_loadsz = 128,
226 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
227 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
228 },
229 [PORT_RSA] = {
230 .name = "RSA",
231 .fifo_size = 2048,
232 .tx_loadsz = 2048,
233 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
234 .flags = UART_CAP_FIFO,
235 },
236 [PORT_NS16550A] = {
237 .name = "NS16550A",
238 .fifo_size = 16,
239 .tx_loadsz = 16,
240 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
241 .flags = UART_CAP_FIFO | UART_NATSEMI,
242 },
243 [PORT_XSCALE] = {
244 .name = "XScale",
245 .fifo_size = 32,
246 .tx_loadsz = 32,
247 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
248 .flags = UART_CAP_FIFO | UART_CAP_UUE | UART_CAP_RTOIE,
249 },
250 [PORT_RM9000] = {
251 .name = "RM9000",
252 .fifo_size = 16,
253 .tx_loadsz = 16,
254 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
255 .flags = UART_CAP_FIFO,
256 },
257 [PORT_OCTEON] = {
258 .name = "OCTEON",
259 .fifo_size = 64,
260 .tx_loadsz = 64,
261 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
262 .flags = UART_CAP_FIFO,
263 },
264 [PORT_AR7] = {
265 .name = "AR7",
266 .fifo_size = 16,
267 .tx_loadsz = 16,
268 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
269 .flags = UART_CAP_FIFO | UART_CAP_AFE,
270 },
271 [PORT_U6_16550A] = {
272 .name = "U6_16550A",
273 .fifo_size = 64,
274 .tx_loadsz = 64,
275 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
276 .flags = UART_CAP_FIFO | UART_CAP_AFE,
277 },
278 [PORT_TEGRA] = {
279 .name = "Tegra",
280 .fifo_size = 32,
281 .tx_loadsz = 8,
282 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
283 UART_FCR_T_TRIG_01,
284 .flags = UART_CAP_FIFO | UART_CAP_RTOIE,
285 },
286 [PORT_XR17D15X] = {
287 .name = "XR17D15X",
288 .fifo_size = 64,
289 .tx_loadsz = 64,
290 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
291 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR,
292 },
293};
294
295#if defined(CONFIG_MIPS_ALCHEMY)
296
297/* Au1x00 UART hardware has a weird register layout */
298static const u8 au_io_in_map[] = {
299 [UART_RX] = 0,
300 [UART_IER] = 2,
301 [UART_IIR] = 3,
302 [UART_LCR] = 5,
303 [UART_MCR] = 6,
304 [UART_LSR] = 7,
305 [UART_MSR] = 8,
306};
307
308static const u8 au_io_out_map[] = {
309 [UART_TX] = 1,
310 [UART_IER] = 2,
311 [UART_FCR] = 4,
312 [UART_LCR] = 5,
313 [UART_MCR] = 6,
314};
315
316/* sane hardware needs no mapping */
317static inline int map_8250_in_reg(struct uart_port *p, int offset)
318{
319 if (p->iotype != UPIO_AU)
320 return offset;
321 return au_io_in_map[offset];
322}
323
324static inline int map_8250_out_reg(struct uart_port *p, int offset)
325{
326 if (p->iotype != UPIO_AU)
327 return offset;
328 return au_io_out_map[offset];
329}
330
331#elif defined(CONFIG_SERIAL_8250_RM9K)
332
333static const u8
334 regmap_in[8] = {
335 [UART_RX] = 0x00,
336 [UART_IER] = 0x0c,
337 [UART_IIR] = 0x14,
338 [UART_LCR] = 0x1c,
339 [UART_MCR] = 0x20,
340 [UART_LSR] = 0x24,
341 [UART_MSR] = 0x28,
342 [UART_SCR] = 0x2c
343 },
344 regmap_out[8] = {
345 [UART_TX] = 0x04,
346 [UART_IER] = 0x0c,
347 [UART_FCR] = 0x18,
348 [UART_LCR] = 0x1c,
349 [UART_MCR] = 0x20,
350 [UART_LSR] = 0x24,
351 [UART_MSR] = 0x28,
352 [UART_SCR] = 0x2c
353 };
354
355static inline int map_8250_in_reg(struct uart_port *p, int offset)
356{
357 if (p->iotype != UPIO_RM9000)
358 return offset;
359 return regmap_in[offset];
360}
361
362static inline int map_8250_out_reg(struct uart_port *p, int offset)
363{
364 if (p->iotype != UPIO_RM9000)
365 return offset;
366 return regmap_out[offset];
367}
368
369#else
370
371/* sane hardware needs no mapping */
372#define map_8250_in_reg(up, offset) (offset)
373#define map_8250_out_reg(up, offset) (offset)
374
375#endif
376
377static unsigned int hub6_serial_in(struct uart_port *p, int offset)
378{
379 offset = map_8250_in_reg(p, offset) << p->regshift;
380 outb(p->hub6 - 1 + offset, p->iobase);
381 return inb(p->iobase + 1);
382}
383
384static void hub6_serial_out(struct uart_port *p, int offset, int value)
385{
386 offset = map_8250_out_reg(p, offset) << p->regshift;
387 outb(p->hub6 - 1 + offset, p->iobase);
388 outb(value, p->iobase + 1);
389}
390
391static unsigned int mem_serial_in(struct uart_port *p, int offset)
392{
393 offset = map_8250_in_reg(p, offset) << p->regshift;
394 return readb(p->membase + offset);
395}
396
397static void mem_serial_out(struct uart_port *p, int offset, int value)
398{
399 offset = map_8250_out_reg(p, offset) << p->regshift;
400 writeb(value, p->membase + offset);
401}
402
403static void mem32_serial_out(struct uart_port *p, int offset, int value)
404{
405 offset = map_8250_out_reg(p, offset) << p->regshift;
406 writel(value, p->membase + offset);
407}
408
409static unsigned int mem32_serial_in(struct uart_port *p, int offset)
410{
411 offset = map_8250_in_reg(p, offset) << p->regshift;
412 return readl(p->membase + offset);
413}
414
415static unsigned int au_serial_in(struct uart_port *p, int offset)
416{
417 offset = map_8250_in_reg(p, offset) << p->regshift;
418 return __raw_readl(p->membase + offset);
419}
420
421static void au_serial_out(struct uart_port *p, int offset, int value)
422{
423 offset = map_8250_out_reg(p, offset) << p->regshift;
424 __raw_writel(value, p->membase + offset);
425}
426
427static unsigned int io_serial_in(struct uart_port *p, int offset)
428{
429 offset = map_8250_in_reg(p, offset) << p->regshift;
430 return inb(p->iobase + offset);
431}
432
433static void io_serial_out(struct uart_port *p, int offset, int value)
434{
435 offset = map_8250_out_reg(p, offset) << p->regshift;
436 outb(value, p->iobase + offset);
437}
438
439static int serial8250_default_handle_irq(struct uart_port *port);
440
441static void set_io_from_upio(struct uart_port *p)
442{
443 struct uart_8250_port *up =
444 container_of(p, struct uart_8250_port, port);
445 switch (p->iotype) {
446 case UPIO_HUB6:
447 p->serial_in = hub6_serial_in;
448 p->serial_out = hub6_serial_out;
449 break;
450
451 case UPIO_MEM:
452 p->serial_in = mem_serial_in;
453 p->serial_out = mem_serial_out;
454 break;
455
456 case UPIO_RM9000:
457 case UPIO_MEM32:
458 p->serial_in = mem32_serial_in;
459 p->serial_out = mem32_serial_out;
460 break;
461
462 case UPIO_AU:
463 p->serial_in = au_serial_in;
464 p->serial_out = au_serial_out;
465 break;
466
467 default:
468 p->serial_in = io_serial_in;
469 p->serial_out = io_serial_out;
470 break;
471 }
472 /* Remember loaded iotype */
473 up->cur_iotype = p->iotype;
474 p->handle_irq = serial8250_default_handle_irq;
475}
476
477static void
478serial_out_sync(struct uart_8250_port *up, int offset, int value)
479{
480 struct uart_port *p = &up->port;
481 switch (p->iotype) {
482 case UPIO_MEM:
483 case UPIO_MEM32:
484 case UPIO_AU:
485 p->serial_out(p, offset, value);
486 p->serial_in(p, UART_LCR); /* safe, no side-effects */
487 break;
488 default:
489 p->serial_out(p, offset, value);
490 }
491}
492
493#define serial_in(up, offset) \
494 (up->port.serial_in(&(up)->port, (offset)))
495#define serial_out(up, offset, value) \
496 (up->port.serial_out(&(up)->port, (offset), (value)))
497/*
498 * We used to support using pause I/O for certain machines. We
499 * haven't supported this for a while, but just in case it's badly
500 * needed for certain old 386 machines, I've left these #define's
501 * in....
502 */
503#define serial_inp(up, offset) serial_in(up, offset)
504#define serial_outp(up, offset, value) serial_out(up, offset, value)
505
506/* Uart divisor latch read */
507static inline int _serial_dl_read(struct uart_8250_port *up)
508{
509 return serial_inp(up, UART_DLL) | serial_inp(up, UART_DLM) << 8;
510}
511
512/* Uart divisor latch write */
513static inline void _serial_dl_write(struct uart_8250_port *up, int value)
514{
515 serial_outp(up, UART_DLL, value & 0xff);
516 serial_outp(up, UART_DLM, value >> 8 & 0xff);
517}
518
519#if defined(CONFIG_MIPS_ALCHEMY)
520/* Au1x00 haven't got a standard divisor latch */
521static int serial_dl_read(struct uart_8250_port *up)
522{
523 if (up->port.iotype == UPIO_AU)
524 return __raw_readl(up->port.membase + 0x28);
525 else
526 return _serial_dl_read(up);
527}
528
529static void serial_dl_write(struct uart_8250_port *up, int value)
530{
531 if (up->port.iotype == UPIO_AU)
532 __raw_writel(value, up->port.membase + 0x28);
533 else
534 _serial_dl_write(up, value);
535}
536#elif defined(CONFIG_SERIAL_8250_RM9K)
537static int serial_dl_read(struct uart_8250_port *up)
538{
539 return (up->port.iotype == UPIO_RM9000) ?
540 (((__raw_readl(up->port.membase + 0x10) << 8) |
541 (__raw_readl(up->port.membase + 0x08) & 0xff)) & 0xffff) :
542 _serial_dl_read(up);
543}
544
545static void serial_dl_write(struct uart_8250_port *up, int value)
546{
547 if (up->port.iotype == UPIO_RM9000) {
548 __raw_writel(value, up->port.membase + 0x08);
549 __raw_writel(value >> 8, up->port.membase + 0x10);
550 } else {
551 _serial_dl_write(up, value);
552 }
553}
554#else
555#define serial_dl_read(up) _serial_dl_read(up)
556#define serial_dl_write(up, value) _serial_dl_write(up, value)
557#endif
558
559/*
560 * For the 16C950
561 */
562static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
563{
564 serial_out(up, UART_SCR, offset);
565 serial_out(up, UART_ICR, value);
566}
567
568static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
569{
570 unsigned int value;
571
572 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
573 serial_out(up, UART_SCR, offset);
574 value = serial_in(up, UART_ICR);
575 serial_icr_write(up, UART_ACR, up->acr);
576
577 return value;
578}
579
580/*
581 * FIFO support.
582 */
583static void serial8250_clear_fifos(struct uart_8250_port *p)
584{
585 if (p->capabilities & UART_CAP_FIFO) {
586 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO);
587 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO |
588 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
589 serial_outp(p, UART_FCR, 0);
590 }
591}
592
593/*
594 * IER sleep support. UARTs which have EFRs need the "extended
595 * capability" bit enabled. Note that on XR16C850s, we need to
596 * reset LCR to write to IER.
597 */
598static void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
599{
600 if (p->capabilities & UART_CAP_SLEEP) {
601 if (p->capabilities & UART_CAP_EFR) {
602 serial_outp(p, UART_LCR, UART_LCR_CONF_MODE_B);
603 serial_outp(p, UART_EFR, UART_EFR_ECB);
604 serial_outp(p, UART_LCR, 0);
605 }
606 serial_outp(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
607 if (p->capabilities & UART_CAP_EFR) {
608 serial_outp(p, UART_LCR, UART_LCR_CONF_MODE_B);
609 serial_outp(p, UART_EFR, 0);
610 serial_outp(p, UART_LCR, 0);
611 }
612 }
613}
614
615#ifdef CONFIG_SERIAL_8250_RSA
616/*
617 * Attempts to turn on the RSA FIFO. Returns zero on failure.
618 * We set the port uart clock rate if we succeed.
619 */
620static int __enable_rsa(struct uart_8250_port *up)
621{
622 unsigned char mode;
623 int result;
624
625 mode = serial_inp(up, UART_RSA_MSR);
626 result = mode & UART_RSA_MSR_FIFO;
627
628 if (!result) {
629 serial_outp(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
630 mode = serial_inp(up, UART_RSA_MSR);
631 result = mode & UART_RSA_MSR_FIFO;
632 }
633
634 if (result)
635 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
636
637 return result;
638}
639
640static void enable_rsa(struct uart_8250_port *up)
641{
642 if (up->port.type == PORT_RSA) {
643 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
644 spin_lock_irq(&up->port.lock);
645 __enable_rsa(up);
646 spin_unlock_irq(&up->port.lock);
647 }
648 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
649 serial_outp(up, UART_RSA_FRR, 0);
650 }
651}
652
653/*
654 * Attempts to turn off the RSA FIFO. Returns zero on failure.
655 * It is unknown why interrupts were disabled in here. However,
656 * the caller is expected to preserve this behaviour by grabbing
657 * the spinlock before calling this function.
658 */
659static void disable_rsa(struct uart_8250_port *up)
660{
661 unsigned char mode;
662 int result;
663
664 if (up->port.type == PORT_RSA &&
665 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
666 spin_lock_irq(&up->port.lock);
667
668 mode = serial_inp(up, UART_RSA_MSR);
669 result = !(mode & UART_RSA_MSR_FIFO);
670
671 if (!result) {
672 serial_outp(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
673 mode = serial_inp(up, UART_RSA_MSR);
674 result = !(mode & UART_RSA_MSR_FIFO);
675 }
676
677 if (result)
678 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
679 spin_unlock_irq(&up->port.lock);
680 }
681}
682#endif /* CONFIG_SERIAL_8250_RSA */
683
684/*
685 * This is a quickie test to see how big the FIFO is.
686 * It doesn't work at all the time, more's the pity.
687 */
688static int size_fifo(struct uart_8250_port *up)
689{
690 unsigned char old_fcr, old_mcr, old_lcr;
691 unsigned short old_dl;
692 int count;
693
694 old_lcr = serial_inp(up, UART_LCR);
695 serial_outp(up, UART_LCR, 0);
696 old_fcr = serial_inp(up, UART_FCR);
697 old_mcr = serial_inp(up, UART_MCR);
698 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO |
699 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
700 serial_outp(up, UART_MCR, UART_MCR_LOOP);
701 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_A);
702 old_dl = serial_dl_read(up);
703 serial_dl_write(up, 0x0001);
704 serial_outp(up, UART_LCR, 0x03);
705 for (count = 0; count < 256; count++)
706 serial_outp(up, UART_TX, count);
707 mdelay(20);/* FIXME - schedule_timeout */
708 for (count = 0; (serial_inp(up, UART_LSR) & UART_LSR_DR) &&
709 (count < 256); count++)
710 serial_inp(up, UART_RX);
711 serial_outp(up, UART_FCR, old_fcr);
712 serial_outp(up, UART_MCR, old_mcr);
713 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_A);
714 serial_dl_write(up, old_dl);
715 serial_outp(up, UART_LCR, old_lcr);
716
717 return count;
718}
719
720/*
721 * Read UART ID using the divisor method - set DLL and DLM to zero
722 * and the revision will be in DLL and device type in DLM. We
723 * preserve the device state across this.
724 */
725static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
726{
727 unsigned char old_dll, old_dlm, old_lcr;
728 unsigned int id;
729
730 old_lcr = serial_inp(p, UART_LCR);
731 serial_outp(p, UART_LCR, UART_LCR_CONF_MODE_A);
732
733 old_dll = serial_inp(p, UART_DLL);
734 old_dlm = serial_inp(p, UART_DLM);
735
736 serial_outp(p, UART_DLL, 0);
737 serial_outp(p, UART_DLM, 0);
738
739 id = serial_inp(p, UART_DLL) | serial_inp(p, UART_DLM) << 8;
740
741 serial_outp(p, UART_DLL, old_dll);
742 serial_outp(p, UART_DLM, old_dlm);
743 serial_outp(p, UART_LCR, old_lcr);
744
745 return id;
746}
747
748/*
749 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
750 * When this function is called we know it is at least a StarTech
751 * 16650 V2, but it might be one of several StarTech UARTs, or one of
752 * its clones. (We treat the broken original StarTech 16650 V1 as a
753 * 16550, and why not? Startech doesn't seem to even acknowledge its
754 * existence.)
755 *
756 * What evil have men's minds wrought...
757 */
758static void autoconfig_has_efr(struct uart_8250_port *up)
759{
760 unsigned int id1, id2, id3, rev;
761
762 /*
763 * Everything with an EFR has SLEEP
764 */
765 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
766
767 /*
768 * First we check to see if it's an Oxford Semiconductor UART.
769 *
770 * If we have to do this here because some non-National
771 * Semiconductor clone chips lock up if you try writing to the
772 * LSR register (which serial_icr_read does)
773 */
774
775 /*
776 * Check for Oxford Semiconductor 16C950.
777 *
778 * EFR [4] must be set else this test fails.
779 *
780 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
781 * claims that it's needed for 952 dual UART's (which are not
782 * recommended for new designs).
783 */
784 up->acr = 0;
785 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
786 serial_out(up, UART_EFR, UART_EFR_ECB);
787 serial_out(up, UART_LCR, 0x00);
788 id1 = serial_icr_read(up, UART_ID1);
789 id2 = serial_icr_read(up, UART_ID2);
790 id3 = serial_icr_read(up, UART_ID3);
791 rev = serial_icr_read(up, UART_REV);
792
793 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
794
795 if (id1 == 0x16 && id2 == 0xC9 &&
796 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
797 up->port.type = PORT_16C950;
798
799 /*
800 * Enable work around for the Oxford Semiconductor 952 rev B
801 * chip which causes it to seriously miscalculate baud rates
802 * when DLL is 0.
803 */
804 if (id3 == 0x52 && rev == 0x01)
805 up->bugs |= UART_BUG_QUOT;
806 return;
807 }
808
809 /*
810 * We check for a XR16C850 by setting DLL and DLM to 0, and then
811 * reading back DLL and DLM. The chip type depends on the DLM
812 * value read back:
813 * 0x10 - XR16C850 and the DLL contains the chip revision.
814 * 0x12 - XR16C2850.
815 * 0x14 - XR16C854.
816 */
817 id1 = autoconfig_read_divisor_id(up);
818 DEBUG_AUTOCONF("850id=%04x ", id1);
819
820 id2 = id1 >> 8;
821 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
822 up->port.type = PORT_16850;
823 return;
824 }
825
826 /*
827 * It wasn't an XR16C850.
828 *
829 * We distinguish between the '654 and the '650 by counting
830 * how many bytes are in the FIFO. I'm using this for now,
831 * since that's the technique that was sent to me in the
832 * serial driver update, but I'm not convinced this works.
833 * I've had problems doing this in the past. -TYT
834 */
835 if (size_fifo(up) == 64)
836 up->port.type = PORT_16654;
837 else
838 up->port.type = PORT_16650V2;
839}
840
841/*
842 * We detected a chip without a FIFO. Only two fall into
843 * this category - the original 8250 and the 16450. The
844 * 16450 has a scratch register (accessible with LCR=0)
845 */
846static void autoconfig_8250(struct uart_8250_port *up)
847{
848 unsigned char scratch, status1, status2;
849
850 up->port.type = PORT_8250;
851
852 scratch = serial_in(up, UART_SCR);
853 serial_outp(up, UART_SCR, 0xa5);
854 status1 = serial_in(up, UART_SCR);
855 serial_outp(up, UART_SCR, 0x5a);
856 status2 = serial_in(up, UART_SCR);
857 serial_outp(up, UART_SCR, scratch);
858
859 if (status1 == 0xa5 && status2 == 0x5a)
860 up->port.type = PORT_16450;
861}
862
863static int broken_efr(struct uart_8250_port *up)
864{
865 /*
866 * Exar ST16C2550 "A2" devices incorrectly detect as
867 * having an EFR, and report an ID of 0x0201. See
868 * http://linux.derkeiler.com/Mailing-Lists/Kernel/2004-11/4812.html
869 */
870 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
871 return 1;
872
873 return 0;
874}
875
876static inline int ns16550a_goto_highspeed(struct uart_8250_port *up)
877{
878 unsigned char status;
879
880 status = serial_in(up, 0x04); /* EXCR2 */
881#define PRESL(x) ((x) & 0x30)
882 if (PRESL(status) == 0x10) {
883 /* already in high speed mode */
884 return 0;
885 } else {
886 status &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
887 status |= 0x10; /* 1.625 divisor for baud_base --> 921600 */
888 serial_outp(up, 0x04, status);
889 }
890 return 1;
891}
892
893/*
894 * We know that the chip has FIFOs. Does it have an EFR? The
895 * EFR is located in the same register position as the IIR and
896 * we know the top two bits of the IIR are currently set. The
897 * EFR should contain zero. Try to read the EFR.
898 */
899static void autoconfig_16550a(struct uart_8250_port *up)
900{
901 unsigned char status1, status2;
902 unsigned int iersave;
903
904 up->port.type = PORT_16550A;
905 up->capabilities |= UART_CAP_FIFO;
906
907 /*
908 * Check for presence of the EFR when DLAB is set.
909 * Only ST16C650V1 UARTs pass this test.
910 */
911 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_A);
912 if (serial_in(up, UART_EFR) == 0) {
913 serial_outp(up, UART_EFR, 0xA8);
914 if (serial_in(up, UART_EFR) != 0) {
915 DEBUG_AUTOCONF("EFRv1 ");
916 up->port.type = PORT_16650;
917 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
918 } else {
919 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
920 }
921 serial_outp(up, UART_EFR, 0);
922 return;
923 }
924
925 /*
926 * Maybe it requires 0xbf to be written to the LCR.
927 * (other ST16C650V2 UARTs, TI16C752A, etc)
928 */
929 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
930 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
931 DEBUG_AUTOCONF("EFRv2 ");
932 autoconfig_has_efr(up);
933 return;
934 }
935
936 /*
937 * Check for a National Semiconductor SuperIO chip.
938 * Attempt to switch to bank 2, read the value of the LOOP bit
939 * from EXCR1. Switch back to bank 0, change it in MCR. Then
940 * switch back to bank 2, read it from EXCR1 again and check
941 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
942 */
943 serial_outp(up, UART_LCR, 0);
944 status1 = serial_in(up, UART_MCR);
945 serial_outp(up, UART_LCR, 0xE0);
946 status2 = serial_in(up, 0x02); /* EXCR1 */
947
948 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
949 serial_outp(up, UART_LCR, 0);
950 serial_outp(up, UART_MCR, status1 ^ UART_MCR_LOOP);
951 serial_outp(up, UART_LCR, 0xE0);
952 status2 = serial_in(up, 0x02); /* EXCR1 */
953 serial_outp(up, UART_LCR, 0);
954 serial_outp(up, UART_MCR, status1);
955
956 if ((status2 ^ status1) & UART_MCR_LOOP) {
957 unsigned short quot;
958
959 serial_outp(up, UART_LCR, 0xE0);
960
961 quot = serial_dl_read(up);
962 quot <<= 3;
963
964 if (ns16550a_goto_highspeed(up))
965 serial_dl_write(up, quot);
966
967 serial_outp(up, UART_LCR, 0);
968
969 up->port.uartclk = 921600*16;
970 up->port.type = PORT_NS16550A;
971 up->capabilities |= UART_NATSEMI;
972 return;
973 }
974 }
975
976 /*
977 * No EFR. Try to detect a TI16750, which only sets bit 5 of
978 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
979 * Try setting it with and without DLAB set. Cheap clones
980 * set bit 5 without DLAB set.
981 */
982 serial_outp(up, UART_LCR, 0);
983 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
984 status1 = serial_in(up, UART_IIR) >> 5;
985 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
986 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_A);
987 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
988 status2 = serial_in(up, UART_IIR) >> 5;
989 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
990 serial_outp(up, UART_LCR, 0);
991
992 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
993
994 if (status1 == 6 && status2 == 7) {
995 up->port.type = PORT_16750;
996 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
997 return;
998 }
999
1000 /*
1001 * Try writing and reading the UART_IER_UUE bit (b6).
1002 * If it works, this is probably one of the Xscale platform's
1003 * internal UARTs.
1004 * We're going to explicitly set the UUE bit to 0 before
1005 * trying to write and read a 1 just to make sure it's not
1006 * already a 1 and maybe locked there before we even start start.
1007 */
1008 iersave = serial_in(up, UART_IER);
1009 serial_outp(up, UART_IER, iersave & ~UART_IER_UUE);
1010 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
1011 /*
1012 * OK it's in a known zero state, try writing and reading
1013 * without disturbing the current state of the other bits.
1014 */
1015 serial_outp(up, UART_IER, iersave | UART_IER_UUE);
1016 if (serial_in(up, UART_IER) & UART_IER_UUE) {
1017 /*
1018 * It's an Xscale.
1019 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
1020 */
1021 DEBUG_AUTOCONF("Xscale ");
1022 up->port.type = PORT_XSCALE;
1023 up->capabilities |= UART_CAP_UUE | UART_CAP_RTOIE;
1024 return;
1025 }
1026 } else {
1027 /*
1028 * If we got here we couldn't force the IER_UUE bit to 0.
1029 * Log it and continue.
1030 */
1031 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
1032 }
1033 serial_outp(up, UART_IER, iersave);
1034
1035 /*
1036 * Exar uarts have EFR in a weird location
1037 */
1038 if (up->port.flags & UPF_EXAR_EFR) {
1039 up->port.type = PORT_XR17D15X;
1040 up->capabilities |= UART_CAP_AFE | UART_CAP_EFR;
1041 }
1042
1043 /*
1044 * We distinguish between 16550A and U6 16550A by counting
1045 * how many bytes are in the FIFO.
1046 */
1047 if (up->port.type == PORT_16550A && size_fifo(up) == 64) {
1048 up->port.type = PORT_U6_16550A;
1049 up->capabilities |= UART_CAP_AFE;
1050 }
1051}
1052
1053/*
1054 * This routine is called by rs_init() to initialize a specific serial
1055 * port. It determines what type of UART chip this serial port is
1056 * using: 8250, 16450, 16550, 16550A. The important question is
1057 * whether or not this UART is a 16550A or not, since this will
1058 * determine whether or not we can use its FIFO features or not.
1059 */
1060static void autoconfig(struct uart_8250_port *up, unsigned int probeflags)
1061{
1062 unsigned char status1, scratch, scratch2, scratch3;
1063 unsigned char save_lcr, save_mcr;
1064 unsigned long flags;
1065
1066 if (!up->port.iobase && !up->port.mapbase && !up->port.membase)
1067 return;
1068
1069 DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04lx, 0x%p): ",
1070 serial_index(&up->port), up->port.iobase, up->port.membase);
1071
1072 /*
1073 * We really do need global IRQs disabled here - we're going to
1074 * be frobbing the chips IRQ enable register to see if it exists.
1075 */
1076 spin_lock_irqsave(&up->port.lock, flags);
1077
1078 up->capabilities = 0;
1079 up->bugs = 0;
1080
1081 if (!(up->port.flags & UPF_BUGGY_UART)) {
1082 /*
1083 * Do a simple existence test first; if we fail this,
1084 * there's no point trying anything else.
1085 *
1086 * 0x80 is used as a nonsense port to prevent against
1087 * false positives due to ISA bus float. The
1088 * assumption is that 0x80 is a non-existent port;
1089 * which should be safe since include/asm/io.h also
1090 * makes this assumption.
1091 *
1092 * Note: this is safe as long as MCR bit 4 is clear
1093 * and the device is in "PC" mode.
1094 */
1095 scratch = serial_inp(up, UART_IER);
1096 serial_outp(up, UART_IER, 0);
1097#ifdef __i386__
1098 outb(0xff, 0x080);
1099#endif
1100 /*
1101 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1102 * 16C754B) allow only to modify them if an EFR bit is set.
1103 */
1104 scratch2 = serial_inp(up, UART_IER) & 0x0f;
1105 serial_outp(up, UART_IER, 0x0F);
1106#ifdef __i386__
1107 outb(0, 0x080);
1108#endif
1109 scratch3 = serial_inp(up, UART_IER) & 0x0f;
1110 serial_outp(up, UART_IER, scratch);
1111 if (scratch2 != 0 || scratch3 != 0x0F) {
1112 /*
1113 * We failed; there's nothing here
1114 */
1115 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1116 scratch2, scratch3);
1117 goto out;
1118 }
1119 }
1120
1121 save_mcr = serial_in(up, UART_MCR);
1122 save_lcr = serial_in(up, UART_LCR);
1123
1124 /*
1125 * Check to see if a UART is really there. Certain broken
1126 * internal modems based on the Rockwell chipset fail this
1127 * test, because they apparently don't implement the loopback
1128 * test mode. So this test is skipped on the COM 1 through
1129 * COM 4 ports. This *should* be safe, since no board
1130 * manufacturer would be stupid enough to design a board
1131 * that conflicts with COM 1-4 --- we hope!
1132 */
1133 if (!(up->port.flags & UPF_SKIP_TEST)) {
1134 serial_outp(up, UART_MCR, UART_MCR_LOOP | 0x0A);
1135 status1 = serial_inp(up, UART_MSR) & 0xF0;
1136 serial_outp(up, UART_MCR, save_mcr);
1137 if (status1 != 0x90) {
1138 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1139 status1);
1140 goto out;
1141 }
1142 }
1143
1144 /*
1145 * We're pretty sure there's a port here. Lets find out what
1146 * type of port it is. The IIR top two bits allows us to find
1147 * out if it's 8250 or 16450, 16550, 16550A or later. This
1148 * determines what we test for next.
1149 *
1150 * We also initialise the EFR (if any) to zero for later. The
1151 * EFR occupies the same register location as the FCR and IIR.
1152 */
1153 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
1154 serial_outp(up, UART_EFR, 0);
1155 serial_outp(up, UART_LCR, 0);
1156
1157 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1158 scratch = serial_in(up, UART_IIR) >> 6;
1159
1160 DEBUG_AUTOCONF("iir=%d ", scratch);
1161
1162 switch (scratch) {
1163 case 0:
1164 autoconfig_8250(up);
1165 break;
1166 case 1:
1167 up->port.type = PORT_UNKNOWN;
1168 break;
1169 case 2:
1170 up->port.type = PORT_16550;
1171 break;
1172 case 3:
1173 autoconfig_16550a(up);
1174 break;
1175 }
1176
1177#ifdef CONFIG_SERIAL_8250_RSA
1178 /*
1179 * Only probe for RSA ports if we got the region.
1180 */
1181 if (up->port.type == PORT_16550A && probeflags & PROBE_RSA) {
1182 int i;
1183
1184 for (i = 0 ; i < probe_rsa_count; ++i) {
1185 if (probe_rsa[i] == up->port.iobase &&
1186 __enable_rsa(up)) {
1187 up->port.type = PORT_RSA;
1188 break;
1189 }
1190 }
1191 }
1192#endif
1193
1194 serial_outp(up, UART_LCR, save_lcr);
1195
1196 if (up->capabilities != uart_config[up->port.type].flags) {
1197 printk(KERN_WARNING
1198 "ttyS%d: detected caps %08x should be %08x\n",
1199 serial_index(&up->port), up->capabilities,
1200 uart_config[up->port.type].flags);
1201 }
1202
1203 up->port.fifosize = uart_config[up->port.type].fifo_size;
1204 up->capabilities = uart_config[up->port.type].flags;
1205 up->tx_loadsz = uart_config[up->port.type].tx_loadsz;
1206
1207 if (up->port.type == PORT_UNKNOWN)
1208 goto out;
1209
1210 /*
1211 * Reset the UART.
1212 */
1213#ifdef CONFIG_SERIAL_8250_RSA
1214 if (up->port.type == PORT_RSA)
1215 serial_outp(up, UART_RSA_FRR, 0);
1216#endif
1217 serial_outp(up, UART_MCR, save_mcr);
1218 serial8250_clear_fifos(up);
1219 serial_in(up, UART_RX);
1220 if (up->capabilities & UART_CAP_UUE)
1221 serial_outp(up, UART_IER, UART_IER_UUE);
1222 else
1223 serial_outp(up, UART_IER, 0);
1224
1225 out:
1226 spin_unlock_irqrestore(&up->port.lock, flags);
1227 DEBUG_AUTOCONF("type=%s\n", uart_config[up->port.type].name);
1228}
1229
1230static void autoconfig_irq(struct uart_8250_port *up)
1231{
1232 unsigned char save_mcr, save_ier;
1233 unsigned char save_ICP = 0;
1234 unsigned int ICP = 0;
1235 unsigned long irqs;
1236 int irq;
1237
1238 if (up->port.flags & UPF_FOURPORT) {
1239 ICP = (up->port.iobase & 0xfe0) | 0x1f;
1240 save_ICP = inb_p(ICP);
1241 outb_p(0x80, ICP);
1242 (void) inb_p(ICP);
1243 }
1244
1245 /* forget possible initially masked and pending IRQ */
1246 probe_irq_off(probe_irq_on());
1247 save_mcr = serial_inp(up, UART_MCR);
1248 save_ier = serial_inp(up, UART_IER);
1249 serial_outp(up, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2);
1250
1251 irqs = probe_irq_on();
1252 serial_outp(up, UART_MCR, 0);
1253 udelay(10);
1254 if (up->port.flags & UPF_FOURPORT) {
1255 serial_outp(up, UART_MCR,
1256 UART_MCR_DTR | UART_MCR_RTS);
1257 } else {
1258 serial_outp(up, UART_MCR,
1259 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1260 }
1261 serial_outp(up, UART_IER, 0x0f); /* enable all intrs */
1262 (void)serial_inp(up, UART_LSR);
1263 (void)serial_inp(up, UART_RX);
1264 (void)serial_inp(up, UART_IIR);
1265 (void)serial_inp(up, UART_MSR);
1266 serial_outp(up, UART_TX, 0xFF);
1267 udelay(20);
1268 irq = probe_irq_off(irqs);
1269
1270 serial_outp(up, UART_MCR, save_mcr);
1271 serial_outp(up, UART_IER, save_ier);
1272
1273 if (up->port.flags & UPF_FOURPORT)
1274 outb_p(save_ICP, ICP);
1275
1276 up->port.irq = (irq > 0) ? irq : 0;
1277}
1278
1279static inline void __stop_tx(struct uart_8250_port *p)
1280{
1281 if (p->ier & UART_IER_THRI) {
1282 p->ier &= ~UART_IER_THRI;
1283 serial_out(p, UART_IER, p->ier);
1284 }
1285}
1286
1287static void serial8250_stop_tx(struct uart_port *port)
1288{
1289 struct uart_8250_port *up =
1290 container_of(port, struct uart_8250_port, port);
1291
1292 __stop_tx(up);
1293
1294 /*
1295 * We really want to stop the transmitter from sending.
1296 */
1297 if (up->port.type == PORT_16C950) {
1298 up->acr |= UART_ACR_TXDIS;
1299 serial_icr_write(up, UART_ACR, up->acr);
1300 }
1301}
1302
1303static void serial8250_start_tx(struct uart_port *port)
1304{
1305 struct uart_8250_port *up =
1306 container_of(port, struct uart_8250_port, port);
1307
1308 if (!(up->ier & UART_IER_THRI)) {
1309 up->ier |= UART_IER_THRI;
1310 serial_out(up, UART_IER, up->ier);
1311
1312 if (up->bugs & UART_BUG_TXEN) {
1313 unsigned char lsr;
1314 lsr = serial_in(up, UART_LSR);
1315 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1316 if ((up->port.type == PORT_RM9000) ?
1317 (lsr & UART_LSR_THRE) :
1318 (lsr & UART_LSR_TEMT))
1319 serial8250_tx_chars(up);
1320 }
1321 }
1322
1323 /*
1324 * Re-enable the transmitter if we disabled it.
1325 */
1326 if (up->port.type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1327 up->acr &= ~UART_ACR_TXDIS;
1328 serial_icr_write(up, UART_ACR, up->acr);
1329 }
1330}
1331
1332static void serial8250_stop_rx(struct uart_port *port)
1333{
1334 struct uart_8250_port *up =
1335 container_of(port, struct uart_8250_port, port);
1336
1337 up->ier &= ~UART_IER_RLSI;
1338 up->port.read_status_mask &= ~UART_LSR_DR;
1339 serial_out(up, UART_IER, up->ier);
1340}
1341
1342static void serial8250_enable_ms(struct uart_port *port)
1343{
1344 struct uart_8250_port *up =
1345 container_of(port, struct uart_8250_port, port);
1346
1347 /* no MSR capabilities */
1348 if (up->bugs & UART_BUG_NOMSR)
1349 return;
1350
1351 up->ier |= UART_IER_MSI;
1352 serial_out(up, UART_IER, up->ier);
1353}
1354
1355/*
1356 * Clear the Tegra rx fifo after a break
1357 *
1358 * FIXME: This needs to become a port specific callback once we have a
1359 * framework for this
1360 */
1361static void clear_rx_fifo(struct uart_8250_port *up)
1362{
1363 unsigned int status, tmout = 10000;
1364 do {
1365 status = serial_in(up, UART_LSR);
1366 if (status & (UART_LSR_FIFOE | UART_LSR_BRK_ERROR_BITS))
1367 status = serial_in(up, UART_RX);
1368 else
1369 break;
1370 if (--tmout == 0)
1371 break;
1372 udelay(1);
1373 } while (1);
1374}
1375
1376/*
1377 * serial8250_rx_chars: processes according to the passed in LSR
1378 * value, and returns the remaining LSR bits not handled
1379 * by this Rx routine.
1380 */
1381unsigned char
1382serial8250_rx_chars(struct uart_8250_port *up, unsigned char lsr)
1383{
1384 struct tty_struct *tty = up->port.state->port.tty;
1385 unsigned char ch;
1386 int max_count = 256;
1387 char flag;
1388
1389 do {
1390 if (likely(lsr & UART_LSR_DR))
1391 ch = serial_inp(up, UART_RX);
1392 else
1393 /*
1394 * Intel 82571 has a Serial Over Lan device that will
1395 * set UART_LSR_BI without setting UART_LSR_DR when
1396 * it receives a break. To avoid reading from the
1397 * receive buffer without UART_LSR_DR bit set, we
1398 * just force the read character to be 0
1399 */
1400 ch = 0;
1401
1402 flag = TTY_NORMAL;
1403 up->port.icount.rx++;
1404
1405 lsr |= up->lsr_saved_flags;
1406 up->lsr_saved_flags = 0;
1407
1408 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
1409 /*
1410 * For statistics only
1411 */
1412 if (lsr & UART_LSR_BI) {
1413 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1414 up->port.icount.brk++;
1415 /*
1416 * If tegra port then clear the rx fifo to
1417 * accept another break/character.
1418 */
1419 if (up->port.type == PORT_TEGRA)
1420 clear_rx_fifo(up);
1421
1422 /*
1423 * We do the SysRQ and SAK checking
1424 * here because otherwise the break
1425 * may get masked by ignore_status_mask
1426 * or read_status_mask.
1427 */
1428 if (uart_handle_break(&up->port))
1429 goto ignore_char;
1430 } else if (lsr & UART_LSR_PE)
1431 up->port.icount.parity++;
1432 else if (lsr & UART_LSR_FE)
1433 up->port.icount.frame++;
1434 if (lsr & UART_LSR_OE)
1435 up->port.icount.overrun++;
1436
1437 /*
1438 * Mask off conditions which should be ignored.
1439 */
1440 lsr &= up->port.read_status_mask;
1441
1442 if (lsr & UART_LSR_BI) {
1443 DEBUG_INTR("handling break....");
1444 flag = TTY_BREAK;
1445 } else if (lsr & UART_LSR_PE)
1446 flag = TTY_PARITY;
1447 else if (lsr & UART_LSR_FE)
1448 flag = TTY_FRAME;
1449 }
1450 if (uart_handle_sysrq_char(&up->port, ch))
1451 goto ignore_char;
1452
1453 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
1454
1455ignore_char:
1456 lsr = serial_inp(up, UART_LSR);
1457 } while ((lsr & (UART_LSR_DR | UART_LSR_BI)) && (max_count-- > 0));
1458 spin_unlock(&up->port.lock);
1459 tty_flip_buffer_push(tty);
1460 spin_lock(&up->port.lock);
1461 return lsr;
1462}
1463EXPORT_SYMBOL_GPL(serial8250_rx_chars);
1464
1465void serial8250_tx_chars(struct uart_8250_port *up)
1466{
1467 struct circ_buf *xmit = &up->port.state->xmit;
1468 int count;
1469
1470 if (up->port.x_char) {
1471 serial_outp(up, UART_TX, up->port.x_char);
1472 up->port.icount.tx++;
1473 up->port.x_char = 0;
1474 return;
1475 }
1476 if (uart_tx_stopped(&up->port)) {
1477 serial8250_stop_tx(&up->port);
1478 return;
1479 }
1480 if (uart_circ_empty(xmit)) {
1481 __stop_tx(up);
1482 return;
1483 }
1484
1485 count = up->tx_loadsz;
1486 do {
1487 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1488 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1489 up->port.icount.tx++;
1490 if (uart_circ_empty(xmit))
1491 break;
1492 } while (--count > 0);
1493
1494 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1495 uart_write_wakeup(&up->port);
1496
1497 DEBUG_INTR("THRE...");
1498
1499 if (uart_circ_empty(xmit))
1500 __stop_tx(up);
1501}
1502EXPORT_SYMBOL_GPL(serial8250_tx_chars);
1503
1504unsigned int serial8250_modem_status(struct uart_8250_port *up)
1505{
1506 unsigned int status = serial_in(up, UART_MSR);
1507
1508 status |= up->msr_saved_flags;
1509 up->msr_saved_flags = 0;
1510 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
1511 up->port.state != NULL) {
1512 if (status & UART_MSR_TERI)
1513 up->port.icount.rng++;
1514 if (status & UART_MSR_DDSR)
1515 up->port.icount.dsr++;
1516 if (status & UART_MSR_DDCD)
1517 uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
1518 if (status & UART_MSR_DCTS)
1519 uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
1520
1521 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
1522 }
1523
1524 return status;
1525}
1526EXPORT_SYMBOL_GPL(serial8250_modem_status);
1527
1528/*
1529 * This handles the interrupt from one port.
1530 */
1531int serial8250_handle_irq(struct uart_port *port, unsigned int iir)
1532{
1533 unsigned char status;
1534 unsigned long flags;
1535 struct uart_8250_port *up =
1536 container_of(port, struct uart_8250_port, port);
1537
1538 if (iir & UART_IIR_NO_INT)
1539 return 0;
1540
1541 spin_lock_irqsave(&up->port.lock, flags);
1542
1543 status = serial_inp(up, UART_LSR);
1544
1545 DEBUG_INTR("status = %x...", status);
1546
1547 if (status & (UART_LSR_DR | UART_LSR_BI))
1548 status = serial8250_rx_chars(up, status);
1549 serial8250_modem_status(up);
1550 if (status & UART_LSR_THRE)
1551 serial8250_tx_chars(up);
1552
1553 spin_unlock_irqrestore(&up->port.lock, flags);
1554 return 1;
1555}
1556EXPORT_SYMBOL_GPL(serial8250_handle_irq);
1557
1558static int serial8250_default_handle_irq(struct uart_port *port)
1559{
1560 struct uart_8250_port *up =
1561 container_of(port, struct uart_8250_port, port);
1562 unsigned int iir = serial_in(up, UART_IIR);
1563
1564 return serial8250_handle_irq(port, iir);
1565}
1566
1567/*
1568 * This is the serial driver's interrupt routine.
1569 *
1570 * Arjan thinks the old way was overly complex, so it got simplified.
1571 * Alan disagrees, saying that need the complexity to handle the weird
1572 * nature of ISA shared interrupts. (This is a special exception.)
1573 *
1574 * In order to handle ISA shared interrupts properly, we need to check
1575 * that all ports have been serviced, and therefore the ISA interrupt
1576 * line has been de-asserted.
1577 *
1578 * This means we need to loop through all ports. checking that they
1579 * don't have an interrupt pending.
1580 */
1581static irqreturn_t serial8250_interrupt(int irq, void *dev_id)
1582{
1583 struct irq_info *i = dev_id;
1584 struct list_head *l, *end = NULL;
1585 int pass_counter = 0, handled = 0;
1586
1587 DEBUG_INTR("serial8250_interrupt(%d)...", irq);
1588
1589 spin_lock(&i->lock);
1590
1591 l = i->head;
1592 do {
1593 struct uart_8250_port *up;
1594 struct uart_port *port;
1595 bool skip;
1596
1597 up = list_entry(l, struct uart_8250_port, list);
1598 port = &up->port;
1599 skip = pass_counter && up->port.flags & UPF_IIR_ONCE;
1600
1601 if (!skip && port->handle_irq(port)) {
1602 handled = 1;
1603 end = NULL;
1604 } else if (end == NULL)
1605 end = l;
1606
1607 l = l->next;
1608
1609 if (l == i->head && pass_counter++ > PASS_LIMIT) {
1610 /* If we hit this, we're dead. */
1611 printk_ratelimited(KERN_ERR
1612 "serial8250: too much work for irq%d\n", irq);
1613 break;
1614 }
1615 } while (l != end);
1616
1617 spin_unlock(&i->lock);
1618
1619 DEBUG_INTR("end.\n");
1620
1621 return IRQ_RETVAL(handled);
1622}
1623
1624/*
1625 * To support ISA shared interrupts, we need to have one interrupt
1626 * handler that ensures that the IRQ line has been deasserted
1627 * before returning. Failing to do this will result in the IRQ
1628 * line being stuck active, and, since ISA irqs are edge triggered,
1629 * no more IRQs will be seen.
1630 */
1631static void serial_do_unlink(struct irq_info *i, struct uart_8250_port *up)
1632{
1633 spin_lock_irq(&i->lock);
1634
1635 if (!list_empty(i->head)) {
1636 if (i->head == &up->list)
1637 i->head = i->head->next;
1638 list_del(&up->list);
1639 } else {
1640 BUG_ON(i->head != &up->list);
1641 i->head = NULL;
1642 }
1643 spin_unlock_irq(&i->lock);
1644 /* List empty so throw away the hash node */
1645 if (i->head == NULL) {
1646 hlist_del(&i->node);
1647 kfree(i);
1648 }
1649}
1650
1651static int serial_link_irq_chain(struct uart_8250_port *up)
1652{
1653 struct hlist_head *h;
1654 struct hlist_node *n;
1655 struct irq_info *i;
1656 int ret, irq_flags = up->port.flags & UPF_SHARE_IRQ ? IRQF_SHARED : 0;
1657
1658 mutex_lock(&hash_mutex);
1659
1660 h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1661
1662 hlist_for_each(n, h) {
1663 i = hlist_entry(n, struct irq_info, node);
1664 if (i->irq == up->port.irq)
1665 break;
1666 }
1667
1668 if (n == NULL) {
1669 i = kzalloc(sizeof(struct irq_info), GFP_KERNEL);
1670 if (i == NULL) {
1671 mutex_unlock(&hash_mutex);
1672 return -ENOMEM;
1673 }
1674 spin_lock_init(&i->lock);
1675 i->irq = up->port.irq;
1676 hlist_add_head(&i->node, h);
1677 }
1678 mutex_unlock(&hash_mutex);
1679
1680 spin_lock_irq(&i->lock);
1681
1682 if (i->head) {
1683 list_add(&up->list, i->head);
1684 spin_unlock_irq(&i->lock);
1685
1686 ret = 0;
1687 } else {
1688 INIT_LIST_HEAD(&up->list);
1689 i->head = &up->list;
1690 spin_unlock_irq(&i->lock);
1691 irq_flags |= up->port.irqflags;
1692 ret = request_irq(up->port.irq, serial8250_interrupt,
1693 irq_flags, "serial", i);
1694 if (ret < 0)
1695 serial_do_unlink(i, up);
1696 }
1697
1698 return ret;
1699}
1700
1701static void serial_unlink_irq_chain(struct uart_8250_port *up)
1702{
1703 struct irq_info *i;
1704 struct hlist_node *n;
1705 struct hlist_head *h;
1706
1707 mutex_lock(&hash_mutex);
1708
1709 h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1710
1711 hlist_for_each(n, h) {
1712 i = hlist_entry(n, struct irq_info, node);
1713 if (i->irq == up->port.irq)
1714 break;
1715 }
1716
1717 BUG_ON(n == NULL);
1718 BUG_ON(i->head == NULL);
1719
1720 if (list_empty(i->head))
1721 free_irq(up->port.irq, i);
1722
1723 serial_do_unlink(i, up);
1724 mutex_unlock(&hash_mutex);
1725}
1726
1727/*
1728 * This function is used to handle ports that do not have an
1729 * interrupt. This doesn't work very well for 16450's, but gives
1730 * barely passable results for a 16550A. (Although at the expense
1731 * of much CPU overhead).
1732 */
1733static void serial8250_timeout(unsigned long data)
1734{
1735 struct uart_8250_port *up = (struct uart_8250_port *)data;
1736
1737 up->port.handle_irq(&up->port);
1738 mod_timer(&up->timer, jiffies + uart_poll_timeout(&up->port));
1739}
1740
1741static void serial8250_backup_timeout(unsigned long data)
1742{
1743 struct uart_8250_port *up = (struct uart_8250_port *)data;
1744 unsigned int iir, ier = 0, lsr;
1745 unsigned long flags;
1746
1747 spin_lock_irqsave(&up->port.lock, flags);
1748
1749 /*
1750 * Must disable interrupts or else we risk racing with the interrupt
1751 * based handler.
1752 */
1753 if (is_real_interrupt(up->port.irq)) {
1754 ier = serial_in(up, UART_IER);
1755 serial_out(up, UART_IER, 0);
1756 }
1757
1758 iir = serial_in(up, UART_IIR);
1759
1760 /*
1761 * This should be a safe test for anyone who doesn't trust the
1762 * IIR bits on their UART, but it's specifically designed for
1763 * the "Diva" UART used on the management processor on many HP
1764 * ia64 and parisc boxes.
1765 */
1766 lsr = serial_in(up, UART_LSR);
1767 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1768 if ((iir & UART_IIR_NO_INT) && (up->ier & UART_IER_THRI) &&
1769 (!uart_circ_empty(&up->port.state->xmit) || up->port.x_char) &&
1770 (lsr & UART_LSR_THRE)) {
1771 iir &= ~(UART_IIR_ID | UART_IIR_NO_INT);
1772 iir |= UART_IIR_THRI;
1773 }
1774
1775 if (!(iir & UART_IIR_NO_INT))
1776 serial8250_tx_chars(up);
1777
1778 if (is_real_interrupt(up->port.irq))
1779 serial_out(up, UART_IER, ier);
1780
1781 spin_unlock_irqrestore(&up->port.lock, flags);
1782
1783 /* Standard timer interval plus 0.2s to keep the port running */
1784 mod_timer(&up->timer,
1785 jiffies + uart_poll_timeout(&up->port) + HZ / 5);
1786}
1787
1788static unsigned int serial8250_tx_empty(struct uart_port *port)
1789{
1790 struct uart_8250_port *up =
1791 container_of(port, struct uart_8250_port, port);
1792 unsigned long flags;
1793 unsigned int lsr;
1794
1795 spin_lock_irqsave(&up->port.lock, flags);
1796 lsr = serial_in(up, UART_LSR);
1797 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1798 spin_unlock_irqrestore(&up->port.lock, flags);
1799
1800 return (lsr & BOTH_EMPTY) == BOTH_EMPTY ? TIOCSER_TEMT : 0;
1801}
1802
1803static unsigned int serial8250_get_mctrl(struct uart_port *port)
1804{
1805 struct uart_8250_port *up =
1806 container_of(port, struct uart_8250_port, port);
1807 unsigned int status;
1808 unsigned int ret;
1809
1810 status = serial8250_modem_status(up);
1811
1812 ret = 0;
1813 if (status & UART_MSR_DCD)
1814 ret |= TIOCM_CAR;
1815 if (status & UART_MSR_RI)
1816 ret |= TIOCM_RNG;
1817 if (status & UART_MSR_DSR)
1818 ret |= TIOCM_DSR;
1819 if (status & UART_MSR_CTS)
1820 ret |= TIOCM_CTS;
1821 return ret;
1822}
1823
1824static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1825{
1826 struct uart_8250_port *up =
1827 container_of(port, struct uart_8250_port, port);
1828 unsigned char mcr = 0;
1829
1830 if (mctrl & TIOCM_RTS)
1831 mcr |= UART_MCR_RTS;
1832 if (mctrl & TIOCM_DTR)
1833 mcr |= UART_MCR_DTR;
1834 if (mctrl & TIOCM_OUT1)
1835 mcr |= UART_MCR_OUT1;
1836 if (mctrl & TIOCM_OUT2)
1837 mcr |= UART_MCR_OUT2;
1838 if (mctrl & TIOCM_LOOP)
1839 mcr |= UART_MCR_LOOP;
1840
1841 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
1842
1843 serial_out(up, UART_MCR, mcr);
1844}
1845
1846static void serial8250_break_ctl(struct uart_port *port, int break_state)
1847{
1848 struct uart_8250_port *up =
1849 container_of(port, struct uart_8250_port, port);
1850 unsigned long flags;
1851
1852 spin_lock_irqsave(&up->port.lock, flags);
1853 if (break_state == -1)
1854 up->lcr |= UART_LCR_SBC;
1855 else
1856 up->lcr &= ~UART_LCR_SBC;
1857 serial_out(up, UART_LCR, up->lcr);
1858 spin_unlock_irqrestore(&up->port.lock, flags);
1859}
1860
1861/*
1862 * Wait for transmitter & holding register to empty
1863 */
1864static void wait_for_xmitr(struct uart_8250_port *up, int bits)
1865{
1866 unsigned int status, tmout = 10000;
1867
1868 /* Wait up to 10ms for the character(s) to be sent. */
1869 for (;;) {
1870 status = serial_in(up, UART_LSR);
1871
1872 up->lsr_saved_flags |= status & LSR_SAVE_FLAGS;
1873
1874 if ((status & bits) == bits)
1875 break;
1876 if (--tmout == 0)
1877 break;
1878 udelay(1);
1879 }
1880
1881 /* Wait up to 1s for flow control if necessary */
1882 if (up->port.flags & UPF_CONS_FLOW) {
1883 unsigned int tmout;
1884 for (tmout = 1000000; tmout; tmout--) {
1885 unsigned int msr = serial_in(up, UART_MSR);
1886 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1887 if (msr & UART_MSR_CTS)
1888 break;
1889 udelay(1);
1890 touch_nmi_watchdog();
1891 }
1892 }
1893}
1894
1895#ifdef CONFIG_CONSOLE_POLL
1896/*
1897 * Console polling routines for writing and reading from the uart while
1898 * in an interrupt or debug context.
1899 */
1900
1901static int serial8250_get_poll_char(struct uart_port *port)
1902{
1903 struct uart_8250_port *up =
1904 container_of(port, struct uart_8250_port, port);
1905 unsigned char lsr = serial_inp(up, UART_LSR);
1906
1907 if (!(lsr & UART_LSR_DR))
1908 return NO_POLL_CHAR;
1909
1910 return serial_inp(up, UART_RX);
1911}
1912
1913
1914static void serial8250_put_poll_char(struct uart_port *port,
1915 unsigned char c)
1916{
1917 unsigned int ier;
1918 struct uart_8250_port *up =
1919 container_of(port, struct uart_8250_port, port);
1920
1921 /*
1922 * First save the IER then disable the interrupts
1923 */
1924 ier = serial_in(up, UART_IER);
1925 if (up->capabilities & UART_CAP_UUE)
1926 serial_out(up, UART_IER, UART_IER_UUE);
1927 else
1928 serial_out(up, UART_IER, 0);
1929
1930 wait_for_xmitr(up, BOTH_EMPTY);
1931 /*
1932 * Send the character out.
1933 * If a LF, also do CR...
1934 */
1935 serial_out(up, UART_TX, c);
1936 if (c == 10) {
1937 wait_for_xmitr(up, BOTH_EMPTY);
1938 serial_out(up, UART_TX, 13);
1939 }
1940
1941 /*
1942 * Finally, wait for transmitter to become empty
1943 * and restore the IER
1944 */
1945 wait_for_xmitr(up, BOTH_EMPTY);
1946 serial_out(up, UART_IER, ier);
1947}
1948
1949#endif /* CONFIG_CONSOLE_POLL */
1950
1951static int serial8250_startup(struct uart_port *port)
1952{
1953 struct uart_8250_port *up =
1954 container_of(port, struct uart_8250_port, port);
1955 unsigned long flags;
1956 unsigned char lsr, iir;
1957 int retval;
1958
1959 up->port.fifosize = uart_config[up->port.type].fifo_size;
1960 up->tx_loadsz = uart_config[up->port.type].tx_loadsz;
1961 up->capabilities = uart_config[up->port.type].flags;
1962 up->mcr = 0;
1963
1964 if (up->port.iotype != up->cur_iotype)
1965 set_io_from_upio(port);
1966
1967 if (up->port.type == PORT_16C950) {
1968 /* Wake up and initialize UART */
1969 up->acr = 0;
1970 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
1971 serial_outp(up, UART_EFR, UART_EFR_ECB);
1972 serial_outp(up, UART_IER, 0);
1973 serial_outp(up, UART_LCR, 0);
1974 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
1975 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
1976 serial_outp(up, UART_EFR, UART_EFR_ECB);
1977 serial_outp(up, UART_LCR, 0);
1978 }
1979
1980#ifdef CONFIG_SERIAL_8250_RSA
1981 /*
1982 * If this is an RSA port, see if we can kick it up to the
1983 * higher speed clock.
1984 */
1985 enable_rsa(up);
1986#endif
1987
1988 /*
1989 * Clear the FIFO buffers and disable them.
1990 * (they will be reenabled in set_termios())
1991 */
1992 serial8250_clear_fifos(up);
1993
1994 /*
1995 * Clear the interrupt registers.
1996 */
1997 (void) serial_inp(up, UART_LSR);
1998 (void) serial_inp(up, UART_RX);
1999 (void) serial_inp(up, UART_IIR);
2000 (void) serial_inp(up, UART_MSR);
2001
2002 /*
2003 * At this point, there's no way the LSR could still be 0xff;
2004 * if it is, then bail out, because there's likely no UART
2005 * here.
2006 */
2007 if (!(up->port.flags & UPF_BUGGY_UART) &&
2008 (serial_inp(up, UART_LSR) == 0xff)) {
2009 printk_ratelimited(KERN_INFO "ttyS%d: LSR safety check engaged!\n",
2010 serial_index(&up->port));
2011 return -ENODEV;
2012 }
2013
2014 /*
2015 * For a XR16C850, we need to set the trigger levels
2016 */
2017 if (up->port.type == PORT_16850) {
2018 unsigned char fctr;
2019
2020 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
2021
2022 fctr = serial_inp(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
2023 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_RX);
2024 serial_outp(up, UART_TRG, UART_TRG_96);
2025 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_TX);
2026 serial_outp(up, UART_TRG, UART_TRG_96);
2027
2028 serial_outp(up, UART_LCR, 0);
2029 }
2030
2031 if (is_real_interrupt(up->port.irq)) {
2032 unsigned char iir1;
2033 /*
2034 * Test for UARTs that do not reassert THRE when the
2035 * transmitter is idle and the interrupt has already
2036 * been cleared. Real 16550s should always reassert
2037 * this interrupt whenever the transmitter is idle and
2038 * the interrupt is enabled. Delays are necessary to
2039 * allow register changes to become visible.
2040 */
2041 spin_lock_irqsave(&up->port.lock, flags);
2042 if (up->port.irqflags & IRQF_SHARED)
2043 disable_irq_nosync(up->port.irq);
2044
2045 wait_for_xmitr(up, UART_LSR_THRE);
2046 serial_out_sync(up, UART_IER, UART_IER_THRI);
2047 udelay(1); /* allow THRE to set */
2048 iir1 = serial_in(up, UART_IIR);
2049 serial_out(up, UART_IER, 0);
2050 serial_out_sync(up, UART_IER, UART_IER_THRI);
2051 udelay(1); /* allow a working UART time to re-assert THRE */
2052 iir = serial_in(up, UART_IIR);
2053 serial_out(up, UART_IER, 0);
2054
2055 if (up->port.irqflags & IRQF_SHARED)
2056 enable_irq(up->port.irq);
2057 spin_unlock_irqrestore(&up->port.lock, flags);
2058
2059 /*
2060 * If the interrupt is not reasserted, setup a timer to
2061 * kick the UART on a regular basis.
2062 */
2063 if (!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) {
2064 up->bugs |= UART_BUG_THRE;
2065 pr_debug("ttyS%d - using backup timer\n",
2066 serial_index(port));
2067 }
2068 }
2069
2070 /*
2071 * The above check will only give an accurate result the first time
2072 * the port is opened so this value needs to be preserved.
2073 */
2074 if (up->bugs & UART_BUG_THRE) {
2075 up->timer.function = serial8250_backup_timeout;
2076 up->timer.data = (unsigned long)up;
2077 mod_timer(&up->timer, jiffies +
2078 uart_poll_timeout(port) + HZ / 5);
2079 }
2080
2081 /*
2082 * If the "interrupt" for this port doesn't correspond with any
2083 * hardware interrupt, we use a timer-based system. The original
2084 * driver used to do this with IRQ0.
2085 */
2086 if (!is_real_interrupt(up->port.irq)) {
2087 up->timer.data = (unsigned long)up;
2088 mod_timer(&up->timer, jiffies + uart_poll_timeout(port));
2089 } else {
2090 retval = serial_link_irq_chain(up);
2091 if (retval)
2092 return retval;
2093 }
2094
2095 /*
2096 * Now, initialize the UART
2097 */
2098 serial_outp(up, UART_LCR, UART_LCR_WLEN8);
2099
2100 spin_lock_irqsave(&up->port.lock, flags);
2101 if (up->port.flags & UPF_FOURPORT) {
2102 if (!is_real_interrupt(up->port.irq))
2103 up->port.mctrl |= TIOCM_OUT1;
2104 } else
2105 /*
2106 * Most PC uarts need OUT2 raised to enable interrupts.
2107 */
2108 if (is_real_interrupt(up->port.irq))
2109 up->port.mctrl |= TIOCM_OUT2;
2110
2111 serial8250_set_mctrl(&up->port, up->port.mctrl);
2112
2113 /* Serial over Lan (SoL) hack:
2114 Intel 8257x Gigabit ethernet chips have a
2115 16550 emulation, to be used for Serial Over Lan.
2116 Those chips take a longer time than a normal
2117 serial device to signalize that a transmission
2118 data was queued. Due to that, the above test generally
2119 fails. One solution would be to delay the reading of
2120 iir. However, this is not reliable, since the timeout
2121 is variable. So, let's just don't test if we receive
2122 TX irq. This way, we'll never enable UART_BUG_TXEN.
2123 */
2124 if (skip_txen_test || up->port.flags & UPF_NO_TXEN_TEST)
2125 goto dont_test_tx_en;
2126
2127 /*
2128 * Do a quick test to see if we receive an
2129 * interrupt when we enable the TX irq.
2130 */
2131 serial_outp(up, UART_IER, UART_IER_THRI);
2132 lsr = serial_in(up, UART_LSR);
2133 iir = serial_in(up, UART_IIR);
2134 serial_outp(up, UART_IER, 0);
2135
2136 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
2137 if (!(up->bugs & UART_BUG_TXEN)) {
2138 up->bugs |= UART_BUG_TXEN;
2139 pr_debug("ttyS%d - enabling bad tx status workarounds\n",
2140 serial_index(port));
2141 }
2142 } else {
2143 up->bugs &= ~UART_BUG_TXEN;
2144 }
2145
2146dont_test_tx_en:
2147 spin_unlock_irqrestore(&up->port.lock, flags);
2148
2149 /*
2150 * Clear the interrupt registers again for luck, and clear the
2151 * saved flags to avoid getting false values from polling
2152 * routines or the previous session.
2153 */
2154 serial_inp(up, UART_LSR);
2155 serial_inp(up, UART_RX);
2156 serial_inp(up, UART_IIR);
2157 serial_inp(up, UART_MSR);
2158 up->lsr_saved_flags = 0;
2159 up->msr_saved_flags = 0;
2160
2161 /*
2162 * Finally, enable interrupts. Note: Modem status interrupts
2163 * are set via set_termios(), which will be occurring imminently
2164 * anyway, so we don't enable them here.
2165 */
2166 up->ier = UART_IER_RLSI | UART_IER_RDI;
2167 serial_outp(up, UART_IER, up->ier);
2168
2169 if (up->port.flags & UPF_FOURPORT) {
2170 unsigned int icp;
2171 /*
2172 * Enable interrupts on the AST Fourport board
2173 */
2174 icp = (up->port.iobase & 0xfe0) | 0x01f;
2175 outb_p(0x80, icp);
2176 (void) inb_p(icp);
2177 }
2178
2179 return 0;
2180}
2181
2182static void serial8250_shutdown(struct uart_port *port)
2183{
2184 struct uart_8250_port *up =
2185 container_of(port, struct uart_8250_port, port);
2186 unsigned long flags;
2187
2188 /*
2189 * Disable interrupts from this port
2190 */
2191 up->ier = 0;
2192 serial_outp(up, UART_IER, 0);
2193
2194 spin_lock_irqsave(&up->port.lock, flags);
2195 if (up->port.flags & UPF_FOURPORT) {
2196 /* reset interrupts on the AST Fourport board */
2197 inb((up->port.iobase & 0xfe0) | 0x1f);
2198 up->port.mctrl |= TIOCM_OUT1;
2199 } else
2200 up->port.mctrl &= ~TIOCM_OUT2;
2201
2202 serial8250_set_mctrl(&up->port, up->port.mctrl);
2203 spin_unlock_irqrestore(&up->port.lock, flags);
2204
2205 /*
2206 * Disable break condition and FIFOs
2207 */
2208 serial_out(up, UART_LCR, serial_inp(up, UART_LCR) & ~UART_LCR_SBC);
2209 serial8250_clear_fifos(up);
2210
2211#ifdef CONFIG_SERIAL_8250_RSA
2212 /*
2213 * Reset the RSA board back to 115kbps compat mode.
2214 */
2215 disable_rsa(up);
2216#endif
2217
2218 /*
2219 * Read data port to reset things, and then unlink from
2220 * the IRQ chain.
2221 */
2222 (void) serial_in(up, UART_RX);
2223
2224 del_timer_sync(&up->timer);
2225 up->timer.function = serial8250_timeout;
2226 if (is_real_interrupt(up->port.irq))
2227 serial_unlink_irq_chain(up);
2228}
2229
2230static unsigned int serial8250_get_divisor(struct uart_port *port, unsigned int baud)
2231{
2232 unsigned int quot;
2233
2234 /*
2235 * Handle magic divisors for baud rates above baud_base on
2236 * SMSC SuperIO chips.
2237 */
2238 if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2239 baud == (port->uartclk/4))
2240 quot = 0x8001;
2241 else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2242 baud == (port->uartclk/8))
2243 quot = 0x8002;
2244 else
2245 quot = uart_get_divisor(port, baud);
2246
2247 return quot;
2248}
2249
2250void
2251serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
2252 struct ktermios *old)
2253{
2254 struct uart_8250_port *up =
2255 container_of(port, struct uart_8250_port, port);
2256 unsigned char cval, fcr = 0;
2257 unsigned long flags;
2258 unsigned int baud, quot;
2259
2260 switch (termios->c_cflag & CSIZE) {
2261 case CS5:
2262 cval = UART_LCR_WLEN5;
2263 break;
2264 case CS6:
2265 cval = UART_LCR_WLEN6;
2266 break;
2267 case CS7:
2268 cval = UART_LCR_WLEN7;
2269 break;
2270 default:
2271 case CS8:
2272 cval = UART_LCR_WLEN8;
2273 break;
2274 }
2275
2276 if (termios->c_cflag & CSTOPB)
2277 cval |= UART_LCR_STOP;
2278 if (termios->c_cflag & PARENB)
2279 cval |= UART_LCR_PARITY;
2280 if (!(termios->c_cflag & PARODD))
2281 cval |= UART_LCR_EPAR;
2282#ifdef CMSPAR
2283 if (termios->c_cflag & CMSPAR)
2284 cval |= UART_LCR_SPAR;
2285#endif
2286
2287 /*
2288 * Ask the core to calculate the divisor for us.
2289 */
2290 baud = uart_get_baud_rate(port, termios, old,
2291 port->uartclk / 16 / 0xffff,
2292 port->uartclk / 16);
2293 quot = serial8250_get_divisor(port, baud);
2294
2295 /*
2296 * Oxford Semi 952 rev B workaround
2297 */
2298 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
2299 quot++;
2300
2301 if (up->capabilities & UART_CAP_FIFO && up->port.fifosize > 1) {
2302 if (baud < 2400)
2303 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_1;
2304 else
2305 fcr = uart_config[up->port.type].fcr;
2306 }
2307
2308 /*
2309 * MCR-based auto flow control. When AFE is enabled, RTS will be
2310 * deasserted when the receive FIFO contains more characters than
2311 * the trigger, or the MCR RTS bit is cleared. In the case where
2312 * the remote UART is not using CTS auto flow control, we must
2313 * have sufficient FIFO entries for the latency of the remote
2314 * UART to respond. IOW, at least 32 bytes of FIFO.
2315 */
2316 if (up->capabilities & UART_CAP_AFE && up->port.fifosize >= 32) {
2317 up->mcr &= ~UART_MCR_AFE;
2318 if (termios->c_cflag & CRTSCTS)
2319 up->mcr |= UART_MCR_AFE;
2320 }
2321
2322 /*
2323 * Ok, we're now changing the port state. Do it with
2324 * interrupts disabled.
2325 */
2326 spin_lock_irqsave(&up->port.lock, flags);
2327
2328 /*
2329 * Update the per-port timeout.
2330 */
2331 uart_update_timeout(port, termios->c_cflag, baud);
2332
2333 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
2334 if (termios->c_iflag & INPCK)
2335 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
2336 if (termios->c_iflag & (BRKINT | PARMRK))
2337 up->port.read_status_mask |= UART_LSR_BI;
2338
2339 /*
2340 * Characteres to ignore
2341 */
2342 up->port.ignore_status_mask = 0;
2343 if (termios->c_iflag & IGNPAR)
2344 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
2345 if (termios->c_iflag & IGNBRK) {
2346 up->port.ignore_status_mask |= UART_LSR_BI;
2347 /*
2348 * If we're ignoring parity and break indicators,
2349 * ignore overruns too (for real raw support).
2350 */
2351 if (termios->c_iflag & IGNPAR)
2352 up->port.ignore_status_mask |= UART_LSR_OE;
2353 }
2354
2355 /*
2356 * ignore all characters if CREAD is not set
2357 */
2358 if ((termios->c_cflag & CREAD) == 0)
2359 up->port.ignore_status_mask |= UART_LSR_DR;
2360
2361 /*
2362 * CTS flow control flag and modem status interrupts
2363 */
2364 up->ier &= ~UART_IER_MSI;
2365 if (!(up->bugs & UART_BUG_NOMSR) &&
2366 UART_ENABLE_MS(&up->port, termios->c_cflag))
2367 up->ier |= UART_IER_MSI;
2368 if (up->capabilities & UART_CAP_UUE)
2369 up->ier |= UART_IER_UUE;
2370 if (up->capabilities & UART_CAP_RTOIE)
2371 up->ier |= UART_IER_RTOIE;
2372
2373 serial_out(up, UART_IER, up->ier);
2374
2375 if (up->capabilities & UART_CAP_EFR) {
2376 unsigned char efr = 0;
2377 /*
2378 * TI16C752/Startech hardware flow control. FIXME:
2379 * - TI16C752 requires control thresholds to be set.
2380 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2381 */
2382 if (termios->c_cflag & CRTSCTS)
2383 efr |= UART_EFR_CTS;
2384
2385 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
2386 if (up->port.flags & UPF_EXAR_EFR)
2387 serial_outp(up, UART_XR_EFR, efr);
2388 else
2389 serial_outp(up, UART_EFR, efr);
2390 }
2391
2392#ifdef CONFIG_ARCH_OMAP
2393 /* Workaround to enable 115200 baud on OMAP1510 internal ports */
2394 if (cpu_is_omap1510() && is_omap_port(up)) {
2395 if (baud == 115200) {
2396 quot = 1;
2397 serial_out(up, UART_OMAP_OSC_12M_SEL, 1);
2398 } else
2399 serial_out(up, UART_OMAP_OSC_12M_SEL, 0);
2400 }
2401#endif
2402
2403 if (up->capabilities & UART_NATSEMI) {
2404 /* Switch to bank 2 not bank 1, to avoid resetting EXCR2 */
2405 serial_outp(up, UART_LCR, 0xe0);
2406 } else {
2407 serial_outp(up, UART_LCR, cval | UART_LCR_DLAB);/* set DLAB */
2408 }
2409
2410 serial_dl_write(up, quot);
2411
2412 /*
2413 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2414 * is written without DLAB set, this mode will be disabled.
2415 */
2416 if (up->port.type == PORT_16750)
2417 serial_outp(up, UART_FCR, fcr);
2418
2419 serial_outp(up, UART_LCR, cval); /* reset DLAB */
2420 up->lcr = cval; /* Save LCR */
2421 if (up->port.type != PORT_16750) {
2422 if (fcr & UART_FCR_ENABLE_FIFO) {
2423 /* emulated UARTs (Lucent Venus 167x) need two steps */
2424 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
2425 }
2426 serial_outp(up, UART_FCR, fcr); /* set fcr */
2427 }
2428 serial8250_set_mctrl(&up->port, up->port.mctrl);
2429 spin_unlock_irqrestore(&up->port.lock, flags);
2430 /* Don't rewrite B0 */
2431 if (tty_termios_baud_rate(termios))
2432 tty_termios_encode_baud_rate(termios, baud, baud);
2433}
2434EXPORT_SYMBOL(serial8250_do_set_termios);
2435
2436static void
2437serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
2438 struct ktermios *old)
2439{
2440 if (port->set_termios)
2441 port->set_termios(port, termios, old);
2442 else
2443 serial8250_do_set_termios(port, termios, old);
2444}
2445
2446static void
2447serial8250_set_ldisc(struct uart_port *port, int new)
2448{
2449 if (new == N_PPS) {
2450 port->flags |= UPF_HARDPPS_CD;
2451 serial8250_enable_ms(port);
2452 } else
2453 port->flags &= ~UPF_HARDPPS_CD;
2454}
2455
2456
2457void serial8250_do_pm(struct uart_port *port, unsigned int state,
2458 unsigned int oldstate)
2459{
2460 struct uart_8250_port *p =
2461 container_of(port, struct uart_8250_port, port);
2462
2463 serial8250_set_sleep(p, state != 0);
2464}
2465EXPORT_SYMBOL(serial8250_do_pm);
2466
2467static void
2468serial8250_pm(struct uart_port *port, unsigned int state,
2469 unsigned int oldstate)
2470{
2471 if (port->pm)
2472 port->pm(port, state, oldstate);
2473 else
2474 serial8250_do_pm(port, state, oldstate);
2475}
2476
2477static unsigned int serial8250_port_size(struct uart_8250_port *pt)
2478{
2479 if (pt->port.iotype == UPIO_AU)
2480 return 0x1000;
2481#ifdef CONFIG_ARCH_OMAP
2482 if (is_omap_port(pt))
2483 return 0x16 << pt->port.regshift;
2484#endif
2485 return 8 << pt->port.regshift;
2486}
2487
2488/*
2489 * Resource handling.
2490 */
2491static int serial8250_request_std_resource(struct uart_8250_port *up)
2492{
2493 unsigned int size = serial8250_port_size(up);
2494 int ret = 0;
2495
2496 switch (up->port.iotype) {
2497 case UPIO_AU:
2498 case UPIO_TSI:
2499 case UPIO_MEM32:
2500 case UPIO_MEM:
2501 if (!up->port.mapbase)
2502 break;
2503
2504 if (!request_mem_region(up->port.mapbase, size, "serial")) {
2505 ret = -EBUSY;
2506 break;
2507 }
2508
2509 if (up->port.flags & UPF_IOREMAP) {
2510 up->port.membase = ioremap_nocache(up->port.mapbase,
2511 size);
2512 if (!up->port.membase) {
2513 release_mem_region(up->port.mapbase, size);
2514 ret = -ENOMEM;
2515 }
2516 }
2517 break;
2518
2519 case UPIO_HUB6:
2520 case UPIO_PORT:
2521 if (!request_region(up->port.iobase, size, "serial"))
2522 ret = -EBUSY;
2523 break;
2524 }
2525 return ret;
2526}
2527
2528static void serial8250_release_std_resource(struct uart_8250_port *up)
2529{
2530 unsigned int size = serial8250_port_size(up);
2531
2532 switch (up->port.iotype) {
2533 case UPIO_AU:
2534 case UPIO_TSI:
2535 case UPIO_MEM32:
2536 case UPIO_MEM:
2537 if (!up->port.mapbase)
2538 break;
2539
2540 if (up->port.flags & UPF_IOREMAP) {
2541 iounmap(up->port.membase);
2542 up->port.membase = NULL;
2543 }
2544
2545 release_mem_region(up->port.mapbase, size);
2546 break;
2547
2548 case UPIO_HUB6:
2549 case UPIO_PORT:
2550 release_region(up->port.iobase, size);
2551 break;
2552 }
2553}
2554
2555static int serial8250_request_rsa_resource(struct uart_8250_port *up)
2556{
2557 unsigned long start = UART_RSA_BASE << up->port.regshift;
2558 unsigned int size = 8 << up->port.regshift;
2559 int ret = -EINVAL;
2560
2561 switch (up->port.iotype) {
2562 case UPIO_HUB6:
2563 case UPIO_PORT:
2564 start += up->port.iobase;
2565 if (request_region(start, size, "serial-rsa"))
2566 ret = 0;
2567 else
2568 ret = -EBUSY;
2569 break;
2570 }
2571
2572 return ret;
2573}
2574
2575static void serial8250_release_rsa_resource(struct uart_8250_port *up)
2576{
2577 unsigned long offset = UART_RSA_BASE << up->port.regshift;
2578 unsigned int size = 8 << up->port.regshift;
2579
2580 switch (up->port.iotype) {
2581 case UPIO_HUB6:
2582 case UPIO_PORT:
2583 release_region(up->port.iobase + offset, size);
2584 break;
2585 }
2586}
2587
2588static void serial8250_release_port(struct uart_port *port)
2589{
2590 struct uart_8250_port *up =
2591 container_of(port, struct uart_8250_port, port);
2592
2593 serial8250_release_std_resource(up);
2594 if (up->port.type == PORT_RSA)
2595 serial8250_release_rsa_resource(up);
2596}
2597
2598static int serial8250_request_port(struct uart_port *port)
2599{
2600 struct uart_8250_port *up =
2601 container_of(port, struct uart_8250_port, port);
2602 int ret = 0;
2603
2604 ret = serial8250_request_std_resource(up);
2605 if (ret == 0 && up->port.type == PORT_RSA) {
2606 ret = serial8250_request_rsa_resource(up);
2607 if (ret < 0)
2608 serial8250_release_std_resource(up);
2609 }
2610
2611 return ret;
2612}
2613
2614static void serial8250_config_port(struct uart_port *port, int flags)
2615{
2616 struct uart_8250_port *up =
2617 container_of(port, struct uart_8250_port, port);
2618 int probeflags = PROBE_ANY;
2619 int ret;
2620
2621 /*
2622 * Find the region that we can probe for. This in turn
2623 * tells us whether we can probe for the type of port.
2624 */
2625 ret = serial8250_request_std_resource(up);
2626 if (ret < 0)
2627 return;
2628
2629 ret = serial8250_request_rsa_resource(up);
2630 if (ret < 0)
2631 probeflags &= ~PROBE_RSA;
2632
2633 if (up->port.iotype != up->cur_iotype)
2634 set_io_from_upio(port);
2635
2636 if (flags & UART_CONFIG_TYPE)
2637 autoconfig(up, probeflags);
2638
2639 /* if access method is AU, it is a 16550 with a quirk */
2640 if (up->port.type == PORT_16550A && up->port.iotype == UPIO_AU)
2641 up->bugs |= UART_BUG_NOMSR;
2642
2643 if (up->port.type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
2644 autoconfig_irq(up);
2645
2646 if (up->port.type != PORT_RSA && probeflags & PROBE_RSA)
2647 serial8250_release_rsa_resource(up);
2648 if (up->port.type == PORT_UNKNOWN)
2649 serial8250_release_std_resource(up);
2650}
2651
2652static int
2653serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
2654{
2655 if (ser->irq >= nr_irqs || ser->irq < 0 ||
2656 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
2657 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
2658 ser->type == PORT_STARTECH)
2659 return -EINVAL;
2660 return 0;
2661}
2662
2663static const char *
2664serial8250_type(struct uart_port *port)
2665{
2666 int type = port->type;
2667
2668 if (type >= ARRAY_SIZE(uart_config))
2669 type = 0;
2670 return uart_config[type].name;
2671}
2672
2673static struct uart_ops serial8250_pops = {
2674 .tx_empty = serial8250_tx_empty,
2675 .set_mctrl = serial8250_set_mctrl,
2676 .get_mctrl = serial8250_get_mctrl,
2677 .stop_tx = serial8250_stop_tx,
2678 .start_tx = serial8250_start_tx,
2679 .stop_rx = serial8250_stop_rx,
2680 .enable_ms = serial8250_enable_ms,
2681 .break_ctl = serial8250_break_ctl,
2682 .startup = serial8250_startup,
2683 .shutdown = serial8250_shutdown,
2684 .set_termios = serial8250_set_termios,
2685 .set_ldisc = serial8250_set_ldisc,
2686 .pm = serial8250_pm,
2687 .type = serial8250_type,
2688 .release_port = serial8250_release_port,
2689 .request_port = serial8250_request_port,
2690 .config_port = serial8250_config_port,
2691 .verify_port = serial8250_verify_port,
2692#ifdef CONFIG_CONSOLE_POLL
2693 .poll_get_char = serial8250_get_poll_char,
2694 .poll_put_char = serial8250_put_poll_char,
2695#endif
2696};
2697
2698static struct uart_8250_port serial8250_ports[UART_NR];
2699
2700static void (*serial8250_isa_config)(int port, struct uart_port *up,
2701 unsigned short *capabilities);
2702
2703void serial8250_set_isa_configurator(
2704 void (*v)(int port, struct uart_port *up, unsigned short *capabilities))
2705{
2706 serial8250_isa_config = v;
2707}
2708EXPORT_SYMBOL(serial8250_set_isa_configurator);
2709
2710static void __init serial8250_isa_init_ports(void)
2711{
2712 struct uart_8250_port *up;
2713 static int first = 1;
2714 int i, irqflag = 0;
2715
2716 if (!first)
2717 return;
2718 first = 0;
2719
2720 for (i = 0; i < nr_uarts; i++) {
2721 struct uart_8250_port *up = &serial8250_ports[i];
2722
2723 up->port.line = i;
2724 spin_lock_init(&up->port.lock);
2725
2726 init_timer(&up->timer);
2727 up->timer.function = serial8250_timeout;
2728
2729 /*
2730 * ALPHA_KLUDGE_MCR needs to be killed.
2731 */
2732 up->mcr_mask = ~ALPHA_KLUDGE_MCR;
2733 up->mcr_force = ALPHA_KLUDGE_MCR;
2734
2735 up->port.ops = &serial8250_pops;
2736 }
2737
2738 if (share_irqs)
2739 irqflag = IRQF_SHARED;
2740
2741 for (i = 0, up = serial8250_ports;
2742 i < ARRAY_SIZE(old_serial_port) && i < nr_uarts;
2743 i++, up++) {
2744 up->port.iobase = old_serial_port[i].port;
2745 up->port.irq = irq_canonicalize(old_serial_port[i].irq);
2746 up->port.irqflags = old_serial_port[i].irqflags;
2747 up->port.uartclk = old_serial_port[i].baud_base * 16;
2748 up->port.flags = old_serial_port[i].flags;
2749 up->port.hub6 = old_serial_port[i].hub6;
2750 up->port.membase = old_serial_port[i].iomem_base;
2751 up->port.iotype = old_serial_port[i].io_type;
2752 up->port.regshift = old_serial_port[i].iomem_reg_shift;
2753 set_io_from_upio(&up->port);
2754 up->port.irqflags |= irqflag;
2755 if (serial8250_isa_config != NULL)
2756 serial8250_isa_config(i, &up->port, &up->capabilities);
2757
2758 }
2759}
2760
2761static void
2762serial8250_init_fixed_type_port(struct uart_8250_port *up, unsigned int type)
2763{
2764 up->port.type = type;
2765 up->port.fifosize = uart_config[type].fifo_size;
2766 up->capabilities = uart_config[type].flags;
2767 up->tx_loadsz = uart_config[type].tx_loadsz;
2768}
2769
2770static void __init
2771serial8250_register_ports(struct uart_driver *drv, struct device *dev)
2772{
2773 int i;
2774
2775 for (i = 0; i < nr_uarts; i++) {
2776 struct uart_8250_port *up = &serial8250_ports[i];
2777 up->cur_iotype = 0xFF;
2778 }
2779
2780 serial8250_isa_init_ports();
2781
2782 for (i = 0; i < nr_uarts; i++) {
2783 struct uart_8250_port *up = &serial8250_ports[i];
2784
2785 up->port.dev = dev;
2786
2787 if (up->port.flags & UPF_FIXED_TYPE)
2788 serial8250_init_fixed_type_port(up, up->port.type);
2789
2790 uart_add_one_port(drv, &up->port);
2791 }
2792}
2793
2794#ifdef CONFIG_SERIAL_8250_CONSOLE
2795
2796static void serial8250_console_putchar(struct uart_port *port, int ch)
2797{
2798 struct uart_8250_port *up =
2799 container_of(port, struct uart_8250_port, port);
2800
2801 wait_for_xmitr(up, UART_LSR_THRE);
2802 serial_out(up, UART_TX, ch);
2803}
2804
2805/*
2806 * Print a string to the serial port trying not to disturb
2807 * any possible real use of the port...
2808 *
2809 * The console_lock must be held when we get here.
2810 */
2811static void
2812serial8250_console_write(struct console *co, const char *s, unsigned int count)
2813{
2814 struct uart_8250_port *up = &serial8250_ports[co->index];
2815 unsigned long flags;
2816 unsigned int ier;
2817 int locked = 1;
2818
2819 touch_nmi_watchdog();
2820
2821 local_irq_save(flags);
2822 if (up->port.sysrq) {
2823 /* serial8250_handle_irq() already took the lock */
2824 locked = 0;
2825 } else if (oops_in_progress) {
2826 locked = spin_trylock(&up->port.lock);
2827 } else
2828 spin_lock(&up->port.lock);
2829
2830 /*
2831 * First save the IER then disable the interrupts
2832 */
2833 ier = serial_in(up, UART_IER);
2834
2835 if (up->capabilities & UART_CAP_UUE)
2836 serial_out(up, UART_IER, UART_IER_UUE);
2837 else
2838 serial_out(up, UART_IER, 0);
2839
2840 uart_console_write(&up->port, s, count, serial8250_console_putchar);
2841
2842 /*
2843 * Finally, wait for transmitter to become empty
2844 * and restore the IER
2845 */
2846 wait_for_xmitr(up, BOTH_EMPTY);
2847 serial_out(up, UART_IER, ier);
2848
2849 /*
2850 * The receive handling will happen properly because the
2851 * receive ready bit will still be set; it is not cleared
2852 * on read. However, modem control will not, we must
2853 * call it if we have saved something in the saved flags
2854 * while processing with interrupts off.
2855 */
2856 if (up->msr_saved_flags)
2857 serial8250_modem_status(up);
2858
2859 if (locked)
2860 spin_unlock(&up->port.lock);
2861 local_irq_restore(flags);
2862}
2863
2864static int __init serial8250_console_setup(struct console *co, char *options)
2865{
2866 struct uart_port *port;
2867 int baud = 9600;
2868 int bits = 8;
2869 int parity = 'n';
2870 int flow = 'n';
2871
2872 /*
2873 * Check whether an invalid uart number has been specified, and
2874 * if so, search for the first available port that does have
2875 * console support.
2876 */
2877 if (co->index >= nr_uarts)
2878 co->index = 0;
2879 port = &serial8250_ports[co->index].port;
2880 if (!port->iobase && !port->membase)
2881 return -ENODEV;
2882
2883 if (options)
2884 uart_parse_options(options, &baud, &parity, &bits, &flow);
2885
2886 return uart_set_options(port, co, baud, parity, bits, flow);
2887}
2888
2889static int serial8250_console_early_setup(void)
2890{
2891 return serial8250_find_port_for_earlycon();
2892}
2893
2894static struct console serial8250_console = {
2895 .name = "ttyS",
2896 .write = serial8250_console_write,
2897 .device = uart_console_device,
2898 .setup = serial8250_console_setup,
2899 .early_setup = serial8250_console_early_setup,
2900 .flags = CON_PRINTBUFFER | CON_ANYTIME,
2901 .index = -1,
2902 .data = &serial8250_reg,
2903};
2904
2905static int __init serial8250_console_init(void)
2906{
2907 if (nr_uarts > UART_NR)
2908 nr_uarts = UART_NR;
2909
2910 serial8250_isa_init_ports();
2911 register_console(&serial8250_console);
2912 return 0;
2913}
2914console_initcall(serial8250_console_init);
2915
2916int serial8250_find_port(struct uart_port *p)
2917{
2918 int line;
2919 struct uart_port *port;
2920
2921 for (line = 0; line < nr_uarts; line++) {
2922 port = &serial8250_ports[line].port;
2923 if (uart_match_port(p, port))
2924 return line;
2925 }
2926 return -ENODEV;
2927}
2928
2929#define SERIAL8250_CONSOLE &serial8250_console
2930#else
2931#define SERIAL8250_CONSOLE NULL
2932#endif
2933
2934static struct uart_driver serial8250_reg = {
2935 .owner = THIS_MODULE,
2936 .driver_name = "serial",
2937 .dev_name = "ttyS",
2938 .major = TTY_MAJOR,
2939 .minor = 64,
2940 .cons = SERIAL8250_CONSOLE,
2941};
2942
2943/*
2944 * early_serial_setup - early registration for 8250 ports
2945 *
2946 * Setup an 8250 port structure prior to console initialisation. Use
2947 * after console initialisation will cause undefined behaviour.
2948 */
2949int __init early_serial_setup(struct uart_port *port)
2950{
2951 struct uart_port *p;
2952
2953 if (port->line >= ARRAY_SIZE(serial8250_ports))
2954 return -ENODEV;
2955
2956 serial8250_isa_init_ports();
2957 p = &serial8250_ports[port->line].port;
2958 p->iobase = port->iobase;
2959 p->membase = port->membase;
2960 p->irq = port->irq;
2961 p->irqflags = port->irqflags;
2962 p->uartclk = port->uartclk;
2963 p->fifosize = port->fifosize;
2964 p->regshift = port->regshift;
2965 p->iotype = port->iotype;
2966 p->flags = port->flags;
2967 p->mapbase = port->mapbase;
2968 p->private_data = port->private_data;
2969 p->type = port->type;
2970 p->line = port->line;
2971
2972 set_io_from_upio(p);
2973 if (port->serial_in)
2974 p->serial_in = port->serial_in;
2975 if (port->serial_out)
2976 p->serial_out = port->serial_out;
2977 if (port->handle_irq)
2978 p->handle_irq = port->handle_irq;
2979 else
2980 p->handle_irq = serial8250_default_handle_irq;
2981
2982 return 0;
2983}
2984
2985/**
2986 * serial8250_suspend_port - suspend one serial port
2987 * @line: serial line number
2988 *
2989 * Suspend one serial port.
2990 */
2991void serial8250_suspend_port(int line)
2992{
2993 uart_suspend_port(&serial8250_reg, &serial8250_ports[line].port);
2994}
2995
2996/**
2997 * serial8250_resume_port - resume one serial port
2998 * @line: serial line number
2999 *
3000 * Resume one serial port.
3001 */
3002void serial8250_resume_port(int line)
3003{
3004 struct uart_8250_port *up = &serial8250_ports[line];
3005
3006 if (up->capabilities & UART_NATSEMI) {
3007 /* Ensure it's still in high speed mode */
3008 serial_outp(up, UART_LCR, 0xE0);
3009
3010 ns16550a_goto_highspeed(up);
3011
3012 serial_outp(up, UART_LCR, 0);
3013 up->port.uartclk = 921600*16;
3014 }
3015 uart_resume_port(&serial8250_reg, &up->port);
3016}
3017
3018/*
3019 * Register a set of serial devices attached to a platform device. The
3020 * list is terminated with a zero flags entry, which means we expect
3021 * all entries to have at least UPF_BOOT_AUTOCONF set.
3022 */
3023static int __devinit serial8250_probe(struct platform_device *dev)
3024{
3025 struct plat_serial8250_port *p = dev->dev.platform_data;
3026 struct uart_port port;
3027 int ret, i, irqflag = 0;
3028
3029 memset(&port, 0, sizeof(struct uart_port));
3030
3031 if (share_irqs)
3032 irqflag = IRQF_SHARED;
3033
3034 for (i = 0; p && p->flags != 0; p++, i++) {
3035 port.iobase = p->iobase;
3036 port.membase = p->membase;
3037 port.irq = p->irq;
3038 port.irqflags = p->irqflags;
3039 port.uartclk = p->uartclk;
3040 port.regshift = p->regshift;
3041 port.iotype = p->iotype;
3042 port.flags = p->flags;
3043 port.mapbase = p->mapbase;
3044 port.hub6 = p->hub6;
3045 port.private_data = p->private_data;
3046 port.type = p->type;
3047 port.serial_in = p->serial_in;
3048 port.serial_out = p->serial_out;
3049 port.handle_irq = p->handle_irq;
3050 port.set_termios = p->set_termios;
3051 port.pm = p->pm;
3052 port.dev = &dev->dev;
3053 port.irqflags |= irqflag;
3054 ret = serial8250_register_port(&port);
3055 if (ret < 0) {
3056 dev_err(&dev->dev, "unable to register port at index %d "
3057 "(IO%lx MEM%llx IRQ%d): %d\n", i,
3058 p->iobase, (unsigned long long)p->mapbase,
3059 p->irq, ret);
3060 }
3061 }
3062 return 0;
3063}
3064
3065/*
3066 * Remove serial ports registered against a platform device.
3067 */
3068static int __devexit serial8250_remove(struct platform_device *dev)
3069{
3070 int i;
3071
3072 for (i = 0; i < nr_uarts; i++) {
3073 struct uart_8250_port *up = &serial8250_ports[i];
3074
3075 if (up->port.dev == &dev->dev)
3076 serial8250_unregister_port(i);
3077 }
3078 return 0;
3079}
3080
3081static int serial8250_suspend(struct platform_device *dev, pm_message_t state)
3082{
3083 int i;
3084
3085 for (i = 0; i < UART_NR; i++) {
3086 struct uart_8250_port *up = &serial8250_ports[i];
3087
3088 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
3089 uart_suspend_port(&serial8250_reg, &up->port);
3090 }
3091
3092 return 0;
3093}
3094
3095static int serial8250_resume(struct platform_device *dev)
3096{
3097 int i;
3098
3099 for (i = 0; i < UART_NR; i++) {
3100 struct uart_8250_port *up = &serial8250_ports[i];
3101
3102 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
3103 serial8250_resume_port(i);
3104 }
3105
3106 return 0;
3107}
3108
3109static struct platform_driver serial8250_isa_driver = {
3110 .probe = serial8250_probe,
3111 .remove = __devexit_p(serial8250_remove),
3112 .suspend = serial8250_suspend,
3113 .resume = serial8250_resume,
3114 .driver = {
3115 .name = "serial8250",
3116 .owner = THIS_MODULE,
3117 },
3118};
3119
3120/*
3121 * This "device" covers _all_ ISA 8250-compatible serial devices listed
3122 * in the table in include/asm/serial.h
3123 */
3124static struct platform_device *serial8250_isa_devs;
3125
3126/*
3127 * serial8250_register_port and serial8250_unregister_port allows for
3128 * 16x50 serial ports to be configured at run-time, to support PCMCIA
3129 * modems and PCI multiport cards.
3130 */
3131static DEFINE_MUTEX(serial_mutex);
3132
3133static struct uart_8250_port *serial8250_find_match_or_unused(struct uart_port *port)
3134{
3135 int i;
3136
3137 /*
3138 * First, find a port entry which matches.
3139 */
3140 for (i = 0; i < nr_uarts; i++)
3141 if (uart_match_port(&serial8250_ports[i].port, port))
3142 return &serial8250_ports[i];
3143
3144 /*
3145 * We didn't find a matching entry, so look for the first
3146 * free entry. We look for one which hasn't been previously
3147 * used (indicated by zero iobase).
3148 */
3149 for (i = 0; i < nr_uarts; i++)
3150 if (serial8250_ports[i].port.type == PORT_UNKNOWN &&
3151 serial8250_ports[i].port.iobase == 0)
3152 return &serial8250_ports[i];
3153
3154 /*
3155 * That also failed. Last resort is to find any entry which
3156 * doesn't have a real port associated with it.
3157 */
3158 for (i = 0; i < nr_uarts; i++)
3159 if (serial8250_ports[i].port.type == PORT_UNKNOWN)
3160 return &serial8250_ports[i];
3161
3162 return NULL;
3163}
3164
3165/**
3166 * serial8250_register_port - register a serial port
3167 * @port: serial port template
3168 *
3169 * Configure the serial port specified by the request. If the
3170 * port exists and is in use, it is hung up and unregistered
3171 * first.
3172 *
3173 * The port is then probed and if necessary the IRQ is autodetected
3174 * If this fails an error is returned.
3175 *
3176 * On success the port is ready to use and the line number is returned.
3177 */
3178int serial8250_register_port(struct uart_port *port)
3179{
3180 struct uart_8250_port *uart;
3181 int ret = -ENOSPC;
3182
3183 if (port->uartclk == 0)
3184 return -EINVAL;
3185
3186 mutex_lock(&serial_mutex);
3187
3188 uart = serial8250_find_match_or_unused(port);
3189 if (uart) {
3190 uart_remove_one_port(&serial8250_reg, &uart->port);
3191
3192 uart->port.iobase = port->iobase;
3193 uart->port.membase = port->membase;
3194 uart->port.irq = port->irq;
3195 uart->port.irqflags = port->irqflags;
3196 uart->port.uartclk = port->uartclk;
3197 uart->port.fifosize = port->fifosize;
3198 uart->port.regshift = port->regshift;
3199 uart->port.iotype = port->iotype;
3200 uart->port.flags = port->flags | UPF_BOOT_AUTOCONF;
3201 uart->port.mapbase = port->mapbase;
3202 uart->port.private_data = port->private_data;
3203 if (port->dev)
3204 uart->port.dev = port->dev;
3205
3206 if (port->flags & UPF_FIXED_TYPE)
3207 serial8250_init_fixed_type_port(uart, port->type);
3208
3209 set_io_from_upio(&uart->port);
3210 /* Possibly override default I/O functions. */
3211 if (port->serial_in)
3212 uart->port.serial_in = port->serial_in;
3213 if (port->serial_out)
3214 uart->port.serial_out = port->serial_out;
3215 if (port->handle_irq)
3216 uart->port.handle_irq = port->handle_irq;
3217 /* Possibly override set_termios call */
3218 if (port->set_termios)
3219 uart->port.set_termios = port->set_termios;
3220 if (port->pm)
3221 uart->port.pm = port->pm;
3222
3223 if (serial8250_isa_config != NULL)
3224 serial8250_isa_config(0, &uart->port,
3225 &uart->capabilities);
3226
3227 ret = uart_add_one_port(&serial8250_reg, &uart->port);
3228 if (ret == 0)
3229 ret = uart->port.line;
3230 }
3231 mutex_unlock(&serial_mutex);
3232
3233 return ret;
3234}
3235EXPORT_SYMBOL(serial8250_register_port);
3236
3237/**
3238 * serial8250_unregister_port - remove a 16x50 serial port at runtime
3239 * @line: serial line number
3240 *
3241 * Remove one serial port. This may not be called from interrupt
3242 * context. We hand the port back to the our control.
3243 */
3244void serial8250_unregister_port(int line)
3245{
3246 struct uart_8250_port *uart = &serial8250_ports[line];
3247
3248 mutex_lock(&serial_mutex);
3249 uart_remove_one_port(&serial8250_reg, &uart->port);
3250 if (serial8250_isa_devs) {
3251 uart->port.flags &= ~UPF_BOOT_AUTOCONF;
3252 uart->port.type = PORT_UNKNOWN;
3253 uart->port.dev = &serial8250_isa_devs->dev;
3254 uart->capabilities = uart_config[uart->port.type].flags;
3255 uart_add_one_port(&serial8250_reg, &uart->port);
3256 } else {
3257 uart->port.dev = NULL;
3258 }
3259 mutex_unlock(&serial_mutex);
3260}
3261EXPORT_SYMBOL(serial8250_unregister_port);
3262
3263static int __init serial8250_init(void)
3264{
3265 int ret;
3266
3267 if (nr_uarts > UART_NR)
3268 nr_uarts = UART_NR;
3269
3270 printk(KERN_INFO "Serial: 8250/16550 driver, "
3271 "%d ports, IRQ sharing %sabled\n", nr_uarts,
3272 share_irqs ? "en" : "dis");
3273
3274#ifdef CONFIG_SPARC
3275 ret = sunserial_register_minors(&serial8250_reg, UART_NR);
3276#else
3277 serial8250_reg.nr = UART_NR;
3278 ret = uart_register_driver(&serial8250_reg);
3279#endif
3280 if (ret)
3281 goto out;
3282
3283 serial8250_isa_devs = platform_device_alloc("serial8250",
3284 PLAT8250_DEV_LEGACY);
3285 if (!serial8250_isa_devs) {
3286 ret = -ENOMEM;
3287 goto unreg_uart_drv;
3288 }
3289
3290 ret = platform_device_add(serial8250_isa_devs);
3291 if (ret)
3292 goto put_dev;
3293
3294 serial8250_register_ports(&serial8250_reg, &serial8250_isa_devs->dev);
3295
3296 ret = platform_driver_register(&serial8250_isa_driver);
3297 if (ret == 0)
3298 goto out;
3299
3300 platform_device_del(serial8250_isa_devs);
3301put_dev:
3302 platform_device_put(serial8250_isa_devs);
3303unreg_uart_drv:
3304#ifdef CONFIG_SPARC
3305 sunserial_unregister_minors(&serial8250_reg, UART_NR);
3306#else
3307 uart_unregister_driver(&serial8250_reg);
3308#endif
3309out:
3310 return ret;
3311}
3312
3313static void __exit serial8250_exit(void)
3314{
3315 struct platform_device *isa_dev = serial8250_isa_devs;
3316
3317 /*
3318 * This tells serial8250_unregister_port() not to re-register
3319 * the ports (thereby making serial8250_isa_driver permanently
3320 * in use.)
3321 */
3322 serial8250_isa_devs = NULL;
3323
3324 platform_driver_unregister(&serial8250_isa_driver);
3325 platform_device_unregister(isa_dev);
3326
3327#ifdef CONFIG_SPARC
3328 sunserial_unregister_minors(&serial8250_reg, UART_NR);
3329#else
3330 uart_unregister_driver(&serial8250_reg);
3331#endif
3332}
3333
3334module_init(serial8250_init);
3335module_exit(serial8250_exit);
3336
3337EXPORT_SYMBOL(serial8250_suspend_port);
3338EXPORT_SYMBOL(serial8250_resume_port);
3339
3340MODULE_LICENSE("GPL");
3341MODULE_DESCRIPTION("Generic 8250/16x50 serial driver");
3342
3343module_param(share_irqs, uint, 0644);
3344MODULE_PARM_DESC(share_irqs, "Share IRQs with other non-8250/16x50 devices"
3345 " (unsafe)");
3346
3347module_param(nr_uarts, uint, 0644);
3348MODULE_PARM_DESC(nr_uarts, "Maximum number of UARTs supported. (1-" __MODULE_STRING(CONFIG_SERIAL_8250_NR_UARTS) ")");
3349
3350module_param(skip_txen_test, uint, 0644);
3351MODULE_PARM_DESC(skip_txen_test, "Skip checking for the TXEN bug at init time");
3352
3353#ifdef CONFIG_SERIAL_8250_RSA
3354module_param_array(probe_rsa, ulong, &probe_rsa_count, 0444);
3355MODULE_PARM_DESC(probe_rsa, "Probe I/O ports for RSA");
3356#endif
3357MODULE_ALIAS_CHARDEV_MAJOR(TTY_MAJOR);
diff --git a/drivers/tty/serial/8250/8250.h b/drivers/tty/serial/8250/8250.h
new file mode 100644
index 000000000000..ae027be57e25
--- /dev/null
+++ b/drivers/tty/serial/8250/8250.h
@@ -0,0 +1,105 @@
1/*
2 * Driver for 8250/16550-type serial ports
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Copyright (C) 2001 Russell King.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
14#include <linux/serial_8250.h>
15
16struct uart_8250_port {
17 struct uart_port port;
18 struct timer_list timer; /* "no irq" timer */
19 struct list_head list; /* ports on this IRQ */
20 unsigned short capabilities; /* port capabilities */
21 unsigned short bugs; /* port bugs */
22 unsigned int tx_loadsz; /* transmit fifo load size */
23 unsigned char acr;
24 unsigned char ier;
25 unsigned char lcr;
26 unsigned char mcr;
27 unsigned char mcr_mask; /* mask of user bits */
28 unsigned char mcr_force; /* mask of forced bits */
29 unsigned char cur_iotype; /* Running I/O type */
30
31 /*
32 * Some bits in registers are cleared on a read, so they must
33 * be saved whenever the register is read but the bits will not
34 * be immediately processed.
35 */
36#define LSR_SAVE_FLAGS UART_LSR_BRK_ERROR_BITS
37 unsigned char lsr_saved_flags;
38#define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA
39 unsigned char msr_saved_flags;
40};
41
42struct old_serial_port {
43 unsigned int uart;
44 unsigned int baud_base;
45 unsigned int port;
46 unsigned int irq;
47 unsigned int flags;
48 unsigned char hub6;
49 unsigned char io_type;
50 unsigned char *iomem_base;
51 unsigned short iomem_reg_shift;
52 unsigned long irqflags;
53};
54
55/*
56 * This replaces serial_uart_config in include/linux/serial.h
57 */
58struct serial8250_config {
59 const char *name;
60 unsigned short fifo_size;
61 unsigned short tx_loadsz;
62 unsigned char fcr;
63 unsigned int flags;
64};
65
66#define UART_CAP_FIFO (1 << 8) /* UART has FIFO */
67#define UART_CAP_EFR (1 << 9) /* UART has EFR */
68#define UART_CAP_SLEEP (1 << 10) /* UART has IER sleep */
69#define UART_CAP_AFE (1 << 11) /* MCR-based hw flow control */
70#define UART_CAP_UUE (1 << 12) /* UART needs IER bit 6 set (Xscale) */
71#define UART_CAP_RTOIE (1 << 13) /* UART needs IER bit 4 set (Xscale, Tegra) */
72
73#define UART_BUG_QUOT (1 << 0) /* UART has buggy quot LSB */
74#define UART_BUG_TXEN (1 << 1) /* UART has buggy TX IIR status */
75#define UART_BUG_NOMSR (1 << 2) /* UART has buggy MSR status bits (Au1x00) */
76#define UART_BUG_THRE (1 << 3) /* UART has buggy THRE reassertion */
77
78#define PROBE_RSA (1 << 0)
79#define PROBE_ANY (~0)
80
81#define HIGH_BITS_OFFSET ((sizeof(long)-sizeof(int))*8)
82
83#ifdef CONFIG_SERIAL_8250_SHARE_IRQ
84#define SERIAL8250_SHARE_IRQS 1
85#else
86#define SERIAL8250_SHARE_IRQS 0
87#endif
88
89#if defined(__alpha__) && !defined(CONFIG_PCI)
90/*
91 * Digital did something really horribly wrong with the OUT1 and OUT2
92 * lines on at least some ALPHA's. The failure mode is that if either
93 * is cleared, the machine locks up with endless interrupts.
94 */
95#define ALPHA_KLUDGE_MCR (UART_MCR_OUT2 | UART_MCR_OUT1)
96#elif defined(CONFIG_SBC8560)
97/*
98 * WindRiver did something similarly broken on their SBC8560 board. The
99 * UART tristates its IRQ output while OUT2 is clear, but they pulled
100 * the interrupt line _up_ instead of down, so if we register the IRQ
101 * while the UART is in that state, we die in an IRQ storm. */
102#define ALPHA_KLUDGE_MCR (UART_MCR_OUT2)
103#else
104#define ALPHA_KLUDGE_MCR 0
105#endif
diff --git a/drivers/tty/serial/8250/8250_accent.c b/drivers/tty/serial/8250/8250_accent.c
new file mode 100644
index 000000000000..34b51c651192
--- /dev/null
+++ b/drivers/tty/serial/8250/8250_accent.c
@@ -0,0 +1,45 @@
1/*
2 * Copyright (C) 2005 Russell King.
3 * Data taken from include/asm-i386/serial.h
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9#include <linux/module.h>
10#include <linux/init.h>
11#include <linux/serial_8250.h>
12
13#define PORT(_base,_irq) \
14 { \
15 .iobase = _base, \
16 .irq = _irq, \
17 .uartclk = 1843200, \
18 .iotype = UPIO_PORT, \
19 .flags = UPF_BOOT_AUTOCONF, \
20 }
21
22static struct plat_serial8250_port accent_data[] = {
23 PORT(0x330, 4),
24 PORT(0x338, 4),
25 { },
26};
27
28static struct platform_device accent_device = {
29 .name = "serial8250",
30 .id = PLAT8250_DEV_ACCENT,
31 .dev = {
32 .platform_data = accent_data,
33 },
34};
35
36static int __init accent_init(void)
37{
38 return platform_device_register(&accent_device);
39}
40
41module_init(accent_init);
42
43MODULE_AUTHOR("Russell King");
44MODULE_DESCRIPTION("8250 serial probe module for Accent Async cards");
45MODULE_LICENSE("GPL");
diff --git a/drivers/tty/serial/8250/8250_acorn.c b/drivers/tty/serial/8250/8250_acorn.c
new file mode 100644
index 000000000000..b0ce8c56f1a4
--- /dev/null
+++ b/drivers/tty/serial/8250/8250_acorn.c
@@ -0,0 +1,141 @@
1/*
2 * linux/drivers/serial/acorn.c
3 *
4 * Copyright (C) 1996-2003 Russell King.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#include <linux/module.h>
11#include <linux/types.h>
12#include <linux/tty.h>
13#include <linux/serial_core.h>
14#include <linux/errno.h>
15#include <linux/ioport.h>
16#include <linux/slab.h>
17#include <linux/device.h>
18#include <linux/init.h>
19
20#include <asm/io.h>
21#include <asm/ecard.h>
22#include <asm/string.h>
23
24#include "8250.h"
25
26#define MAX_PORTS 3
27
28struct serial_card_type {
29 unsigned int num_ports;
30 unsigned int uartclk;
31 unsigned int type;
32 unsigned int offset[MAX_PORTS];
33};
34
35struct serial_card_info {
36 unsigned int num_ports;
37 int ports[MAX_PORTS];
38 void __iomem *vaddr;
39};
40
41static int __devinit
42serial_card_probe(struct expansion_card *ec, const struct ecard_id *id)
43{
44 struct serial_card_info *info;
45 struct serial_card_type *type = id->data;
46 struct uart_port port;
47 unsigned long bus_addr;
48 unsigned int i;
49
50 info = kzalloc(sizeof(struct serial_card_info), GFP_KERNEL);
51 if (!info)
52 return -ENOMEM;
53
54 info->num_ports = type->num_ports;
55
56 bus_addr = ecard_resource_start(ec, type->type);
57 info->vaddr = ecardm_iomap(ec, type->type, 0, 0);
58 if (!info->vaddr) {
59 kfree(info);
60 return -ENOMEM;
61 }
62
63 ecard_set_drvdata(ec, info);
64
65 memset(&port, 0, sizeof(struct uart_port));
66 port.irq = ec->irq;
67 port.flags = UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
68 port.uartclk = type->uartclk;
69 port.iotype = UPIO_MEM;
70 port.regshift = 2;
71 port.dev = &ec->dev;
72
73 for (i = 0; i < info->num_ports; i ++) {
74 port.membase = info->vaddr + type->offset[i];
75 port.mapbase = bus_addr + type->offset[i];
76
77 info->ports[i] = serial8250_register_port(&port);
78 }
79
80 return 0;
81}
82
83static void __devexit serial_card_remove(struct expansion_card *ec)
84{
85 struct serial_card_info *info = ecard_get_drvdata(ec);
86 int i;
87
88 ecard_set_drvdata(ec, NULL);
89
90 for (i = 0; i < info->num_ports; i++)
91 if (info->ports[i] > 0)
92 serial8250_unregister_port(info->ports[i]);
93
94 kfree(info);
95}
96
97static struct serial_card_type atomwide_type = {
98 .num_ports = 3,
99 .uartclk = 7372800,
100 .type = ECARD_RES_IOCSLOW,
101 .offset = { 0x2800, 0x2400, 0x2000 },
102};
103
104static struct serial_card_type serport_type = {
105 .num_ports = 2,
106 .uartclk = 3686400,
107 .type = ECARD_RES_IOCSLOW,
108 .offset = { 0x2000, 0x2020 },
109};
110
111static const struct ecard_id serial_cids[] = {
112 { MANU_ATOMWIDE, PROD_ATOMWIDE_3PSERIAL, &atomwide_type },
113 { MANU_SERPORT, PROD_SERPORT_DSPORT, &serport_type },
114 { 0xffff, 0xffff }
115};
116
117static struct ecard_driver serial_card_driver = {
118 .probe = serial_card_probe,
119 .remove = __devexit_p(serial_card_remove),
120 .id_table = serial_cids,
121 .drv = {
122 .name = "8250_acorn",
123 },
124};
125
126static int __init serial_card_init(void)
127{
128 return ecard_register_driver(&serial_card_driver);
129}
130
131static void __exit serial_card_exit(void)
132{
133 ecard_remove_driver(&serial_card_driver);
134}
135
136MODULE_AUTHOR("Russell King");
137MODULE_DESCRIPTION("Acorn 8250-compatible serial port expansion card driver");
138MODULE_LICENSE("GPL");
139
140module_init(serial_card_init);
141module_exit(serial_card_exit);
diff --git a/drivers/tty/serial/8250/8250_boca.c b/drivers/tty/serial/8250/8250_boca.c
new file mode 100644
index 000000000000..d125dc107985
--- /dev/null
+++ b/drivers/tty/serial/8250/8250_boca.c
@@ -0,0 +1,59 @@
1/*
2 * Copyright (C) 2005 Russell King.
3 * Data taken from include/asm-i386/serial.h
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9#include <linux/module.h>
10#include <linux/init.h>
11#include <linux/serial_8250.h>
12
13#define PORT(_base,_irq) \
14 { \
15 .iobase = _base, \
16 .irq = _irq, \
17 .uartclk = 1843200, \
18 .iotype = UPIO_PORT, \
19 .flags = UPF_BOOT_AUTOCONF, \
20 }
21
22static struct plat_serial8250_port boca_data[] = {
23 PORT(0x100, 12),
24 PORT(0x108, 12),
25 PORT(0x110, 12),
26 PORT(0x118, 12),
27 PORT(0x120, 12),
28 PORT(0x128, 12),
29 PORT(0x130, 12),
30 PORT(0x138, 12),
31 PORT(0x140, 12),
32 PORT(0x148, 12),
33 PORT(0x150, 12),
34 PORT(0x158, 12),
35 PORT(0x160, 12),
36 PORT(0x168, 12),
37 PORT(0x170, 12),
38 PORT(0x178, 12),
39 { },
40};
41
42static struct platform_device boca_device = {
43 .name = "serial8250",
44 .id = PLAT8250_DEV_BOCA,
45 .dev = {
46 .platform_data = boca_data,
47 },
48};
49
50static int __init boca_init(void)
51{
52 return platform_device_register(&boca_device);
53}
54
55module_init(boca_init);
56
57MODULE_AUTHOR("Russell King");
58MODULE_DESCRIPTION("8250 serial probe module for Boca cards");
59MODULE_LICENSE("GPL");
diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/8250_dw.c
new file mode 100644
index 000000000000..f574eef3075f
--- /dev/null
+++ b/drivers/tty/serial/8250/8250_dw.c
@@ -0,0 +1,184 @@
1/*
2 * Synopsys DesignWare 8250 driver.
3 *
4 * Copyright 2011 Picochip, Jamie Iles.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * The Synopsys DesignWare 8250 has an extra feature whereby it detects if the
12 * LCR is written whilst busy. If it is, then a busy detect interrupt is
13 * raised, the LCR needs to be rewritten and the uart status register read.
14 */
15#include <linux/device.h>
16#include <linux/init.h>
17#include <linux/io.h>
18#include <linux/module.h>
19#include <linux/serial_8250.h>
20#include <linux/serial_core.h>
21#include <linux/serial_reg.h>
22#include <linux/of.h>
23#include <linux/of_irq.h>
24#include <linux/of_platform.h>
25#include <linux/platform_device.h>
26#include <linux/slab.h>
27
28struct dw8250_data {
29 int last_lcr;
30 int line;
31};
32
33static void dw8250_serial_out(struct uart_port *p, int offset, int value)
34{
35 struct dw8250_data *d = p->private_data;
36
37 if (offset == UART_LCR)
38 d->last_lcr = value;
39
40 offset <<= p->regshift;
41 writeb(value, p->membase + offset);
42}
43
44static unsigned int dw8250_serial_in(struct uart_port *p, int offset)
45{
46 offset <<= p->regshift;
47
48 return readb(p->membase + offset);
49}
50
51static void dw8250_serial_out32(struct uart_port *p, int offset, int value)
52{
53 struct dw8250_data *d = p->private_data;
54
55 if (offset == UART_LCR)
56 d->last_lcr = value;
57
58 offset <<= p->regshift;
59 writel(value, p->membase + offset);
60}
61
62static unsigned int dw8250_serial_in32(struct uart_port *p, int offset)
63{
64 offset <<= p->regshift;
65
66 return readl(p->membase + offset);
67}
68
69/* Offset for the DesignWare's UART Status Register. */
70#define UART_USR 0x1f
71
72static int dw8250_handle_irq(struct uart_port *p)
73{
74 struct dw8250_data *d = p->private_data;
75 unsigned int iir = p->serial_in(p, UART_IIR);
76
77 if (serial8250_handle_irq(p, iir)) {
78 return 1;
79 } else if ((iir & UART_IIR_BUSY) == UART_IIR_BUSY) {
80 /* Clear the USR and write the LCR again. */
81 (void)p->serial_in(p, UART_USR);
82 p->serial_out(p, d->last_lcr, UART_LCR);
83
84 return 1;
85 }
86
87 return 0;
88}
89
90static int __devinit dw8250_probe(struct platform_device *pdev)
91{
92 struct uart_port port = {};
93 struct resource *regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
94 struct resource *irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
95 struct device_node *np = pdev->dev.of_node;
96 u32 val;
97 struct dw8250_data *data;
98
99 if (!regs || !irq) {
100 dev_err(&pdev->dev, "no registers/irq defined\n");
101 return -EINVAL;
102 }
103
104 data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
105 if (!data)
106 return -ENOMEM;
107 port.private_data = data;
108
109 spin_lock_init(&port.lock);
110 port.mapbase = regs->start;
111 port.irq = irq->start;
112 port.handle_irq = dw8250_handle_irq;
113 port.type = PORT_8250;
114 port.flags = UPF_SHARE_IRQ | UPF_BOOT_AUTOCONF | UPF_IOREMAP |
115 UPF_FIXED_PORT | UPF_FIXED_TYPE;
116 port.dev = &pdev->dev;
117
118 port.iotype = UPIO_MEM;
119 port.serial_in = dw8250_serial_in;
120 port.serial_out = dw8250_serial_out;
121 if (!of_property_read_u32(np, "reg-io-width", &val)) {
122 switch (val) {
123 case 1:
124 break;
125 case 4:
126 port.iotype = UPIO_MEM32;
127 port.serial_in = dw8250_serial_in32;
128 port.serial_out = dw8250_serial_out32;
129 break;
130 default:
131 dev_err(&pdev->dev, "unsupported reg-io-width (%u)\n",
132 val);
133 return -EINVAL;
134 }
135 }
136
137 if (!of_property_read_u32(np, "reg-shift", &val))
138 port.regshift = val;
139
140 if (of_property_read_u32(np, "clock-frequency", &val)) {
141 dev_err(&pdev->dev, "no clock-frequency property set\n");
142 return -EINVAL;
143 }
144 port.uartclk = val;
145
146 data->line = serial8250_register_port(&port);
147 if (data->line < 0)
148 return data->line;
149
150 platform_set_drvdata(pdev, data);
151
152 return 0;
153}
154
155static int __devexit dw8250_remove(struct platform_device *pdev)
156{
157 struct dw8250_data *data = platform_get_drvdata(pdev);
158
159 serial8250_unregister_port(data->line);
160
161 return 0;
162}
163
164static const struct of_device_id dw8250_match[] = {
165 { .compatible = "snps,dw-apb-uart" },
166 { /* Sentinel */ }
167};
168MODULE_DEVICE_TABLE(of, dw8250_match);
169
170static struct platform_driver dw8250_platform_driver = {
171 .driver = {
172 .name = "dw-apb-uart",
173 .owner = THIS_MODULE,
174 .of_match_table = dw8250_match,
175 },
176 .probe = dw8250_probe,
177 .remove = __devexit_p(dw8250_remove),
178};
179
180module_platform_driver(dw8250_platform_driver);
181
182MODULE_AUTHOR("Jamie Iles");
183MODULE_LICENSE("GPL");
184MODULE_DESCRIPTION("Synopsys DesignWare 8250 serial port driver");
diff --git a/drivers/tty/serial/8250/8250_early.c b/drivers/tty/serial/8250/8250_early.c
new file mode 100644
index 000000000000..eaafb98debed
--- /dev/null
+++ b/drivers/tty/serial/8250/8250_early.c
@@ -0,0 +1,287 @@
1/*
2 * Early serial console for 8250/16550 devices
3 *
4 * (c) Copyright 2004 Hewlett-Packard Development Company, L.P.
5 * Bjorn Helgaas <bjorn.helgaas@hp.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * Based on the 8250.c serial driver, Copyright (C) 2001 Russell King,
12 * and on early_printk.c by Andi Kleen.
13 *
14 * This is for use before the serial driver has initialized, in
15 * particular, before the UARTs have been discovered and named.
16 * Instead of specifying the console device as, e.g., "ttyS0",
17 * we locate the device directly by its MMIO or I/O port address.
18 *
19 * The user can specify the device directly, e.g.,
20 * earlycon=uart8250,io,0x3f8,9600n8
21 * earlycon=uart8250,mmio,0xff5e0000,115200n8
22 * earlycon=uart8250,mmio32,0xff5e0000,115200n8
23 * or
24 * console=uart8250,io,0x3f8,9600n8
25 * console=uart8250,mmio,0xff5e0000,115200n8
26 * console=uart8250,mmio32,0xff5e0000,115200n8
27 */
28
29#include <linux/tty.h>
30#include <linux/init.h>
31#include <linux/console.h>
32#include <linux/serial_core.h>
33#include <linux/serial_reg.h>
34#include <linux/serial.h>
35#include <linux/serial_8250.h>
36#include <asm/io.h>
37#include <asm/serial.h>
38#ifdef CONFIG_FIX_EARLYCON_MEM
39#include <asm/pgtable.h>
40#include <asm/fixmap.h>
41#endif
42
43struct early_serial8250_device {
44 struct uart_port port;
45 char options[16]; /* e.g., 115200n8 */
46 unsigned int baud;
47};
48
49static struct early_serial8250_device early_device;
50
51static unsigned int __init serial_in(struct uart_port *port, int offset)
52{
53 switch (port->iotype) {
54 case UPIO_MEM:
55 return readb(port->membase + offset);
56 case UPIO_MEM32:
57 return readl(port->membase + (offset << 2));
58 case UPIO_PORT:
59 return inb(port->iobase + offset);
60 default:
61 return 0;
62 }
63}
64
65static void __init serial_out(struct uart_port *port, int offset, int value)
66{
67 switch (port->iotype) {
68 case UPIO_MEM:
69 writeb(value, port->membase + offset);
70 break;
71 case UPIO_MEM32:
72 writel(value, port->membase + (offset << 2));
73 break;
74 case UPIO_PORT:
75 outb(value, port->iobase + offset);
76 break;
77 }
78}
79
80#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
81
82static void __init wait_for_xmitr(struct uart_port *port)
83{
84 unsigned int status;
85
86 for (;;) {
87 status = serial_in(port, UART_LSR);
88 if ((status & BOTH_EMPTY) == BOTH_EMPTY)
89 return;
90 cpu_relax();
91 }
92}
93
94static void __init serial_putc(struct uart_port *port, int c)
95{
96 wait_for_xmitr(port);
97 serial_out(port, UART_TX, c);
98}
99
100static void __init early_serial8250_write(struct console *console,
101 const char *s, unsigned int count)
102{
103 struct uart_port *port = &early_device.port;
104 unsigned int ier;
105
106 /* Save the IER and disable interrupts */
107 ier = serial_in(port, UART_IER);
108 serial_out(port, UART_IER, 0);
109
110 uart_console_write(port, s, count, serial_putc);
111
112 /* Wait for transmitter to become empty and restore the IER */
113 wait_for_xmitr(port);
114 serial_out(port, UART_IER, ier);
115}
116
117static unsigned int __init probe_baud(struct uart_port *port)
118{
119 unsigned char lcr, dll, dlm;
120 unsigned int quot;
121
122 lcr = serial_in(port, UART_LCR);
123 serial_out(port, UART_LCR, lcr | UART_LCR_DLAB);
124 dll = serial_in(port, UART_DLL);
125 dlm = serial_in(port, UART_DLM);
126 serial_out(port, UART_LCR, lcr);
127
128 quot = (dlm << 8) | dll;
129 return (port->uartclk / 16) / quot;
130}
131
132static void __init init_port(struct early_serial8250_device *device)
133{
134 struct uart_port *port = &device->port;
135 unsigned int divisor;
136 unsigned char c;
137
138 serial_out(port, UART_LCR, 0x3); /* 8n1 */
139 serial_out(port, UART_IER, 0); /* no interrupt */
140 serial_out(port, UART_FCR, 0); /* no fifo */
141 serial_out(port, UART_MCR, 0x3); /* DTR + RTS */
142
143 divisor = port->uartclk / (16 * device->baud);
144 c = serial_in(port, UART_LCR);
145 serial_out(port, UART_LCR, c | UART_LCR_DLAB);
146 serial_out(port, UART_DLL, divisor & 0xff);
147 serial_out(port, UART_DLM, (divisor >> 8) & 0xff);
148 serial_out(port, UART_LCR, c & ~UART_LCR_DLAB);
149}
150
151static int __init parse_options(struct early_serial8250_device *device,
152 char *options)
153{
154 struct uart_port *port = &device->port;
155 int mmio, mmio32, length;
156
157 if (!options)
158 return -ENODEV;
159
160 port->uartclk = BASE_BAUD * 16;
161
162 mmio = !strncmp(options, "mmio,", 5);
163 mmio32 = !strncmp(options, "mmio32,", 7);
164 if (mmio || mmio32) {
165 port->iotype = (mmio ? UPIO_MEM : UPIO_MEM32);
166 port->mapbase = simple_strtoul(options + (mmio ? 5 : 7),
167 &options, 0);
168 if (mmio32)
169 port->regshift = 2;
170#ifdef CONFIG_FIX_EARLYCON_MEM
171 set_fixmap_nocache(FIX_EARLYCON_MEM_BASE,
172 port->mapbase & PAGE_MASK);
173 port->membase =
174 (void __iomem *)__fix_to_virt(FIX_EARLYCON_MEM_BASE);
175 port->membase += port->mapbase & ~PAGE_MASK;
176#else
177 port->membase = ioremap_nocache(port->mapbase, 64);
178 if (!port->membase) {
179 printk(KERN_ERR "%s: Couldn't ioremap 0x%llx\n",
180 __func__,
181 (unsigned long long) port->mapbase);
182 return -ENOMEM;
183 }
184#endif
185 } else if (!strncmp(options, "io,", 3)) {
186 port->iotype = UPIO_PORT;
187 port->iobase = simple_strtoul(options + 3, &options, 0);
188 mmio = 0;
189 } else
190 return -EINVAL;
191
192 options = strchr(options, ',');
193 if (options) {
194 options++;
195 device->baud = simple_strtoul(options, NULL, 0);
196 length = min(strcspn(options, " "), sizeof(device->options));
197 strncpy(device->options, options, length);
198 } else {
199 device->baud = probe_baud(port);
200 snprintf(device->options, sizeof(device->options), "%u",
201 device->baud);
202 }
203
204 if (mmio || mmio32)
205 printk(KERN_INFO
206 "Early serial console at MMIO%s 0x%llx (options '%s')\n",
207 mmio32 ? "32" : "",
208 (unsigned long long)port->mapbase,
209 device->options);
210 else
211 printk(KERN_INFO
212 "Early serial console at I/O port 0x%lx (options '%s')\n",
213 port->iobase,
214 device->options);
215
216 return 0;
217}
218
219static struct console early_serial8250_console __initdata = {
220 .name = "uart",
221 .write = early_serial8250_write,
222 .flags = CON_PRINTBUFFER | CON_BOOT,
223 .index = -1,
224};
225
226static int __init early_serial8250_setup(char *options)
227{
228 struct early_serial8250_device *device = &early_device;
229 int err;
230
231 if (device->port.membase || device->port.iobase)
232 return 0;
233
234 err = parse_options(device, options);
235 if (err < 0)
236 return err;
237
238 init_port(device);
239 return 0;
240}
241
242int __init setup_early_serial8250_console(char *cmdline)
243{
244 char *options;
245 int err;
246
247 options = strstr(cmdline, "uart8250,");
248 if (!options) {
249 options = strstr(cmdline, "uart,");
250 if (!options)
251 return 0;
252 }
253
254 options = strchr(cmdline, ',') + 1;
255 err = early_serial8250_setup(options);
256 if (err < 0)
257 return err;
258
259 register_console(&early_serial8250_console);
260
261 return 0;
262}
263
264int serial8250_find_port_for_earlycon(void)
265{
266 struct early_serial8250_device *device = &early_device;
267 struct uart_port *port = &device->port;
268 int line;
269 int ret;
270
271 if (!device->port.membase && !device->port.iobase)
272 return -ENODEV;
273
274 line = serial8250_find_port(port);
275 if (line < 0)
276 return -ENODEV;
277
278 ret = update_console_cmdline("uart", 8250,
279 "ttyS", line, device->options);
280 if (ret < 0)
281 ret = update_console_cmdline("uart", 0,
282 "ttyS", line, device->options);
283
284 return ret;
285}
286
287early_param("earlycon", setup_early_serial8250_console);
diff --git a/drivers/tty/serial/8250/8250_exar_st16c554.c b/drivers/tty/serial/8250/8250_exar_st16c554.c
new file mode 100644
index 000000000000..bf53aabf9b5e
--- /dev/null
+++ b/drivers/tty/serial/8250/8250_exar_st16c554.c
@@ -0,0 +1,50 @@
1/*
2 * Written by Paul B Schroeder < pschroeder "at" uplogix "dot" com >
3 * Based on 8250_boca.
4 *
5 * Copyright (C) 2005 Russell King.
6 * Data taken from include/asm-i386/serial.h
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12#include <linux/module.h>
13#include <linux/init.h>
14#include <linux/serial_8250.h>
15
16#define PORT(_base,_irq) \
17 { \
18 .iobase = _base, \
19 .irq = _irq, \
20 .uartclk = 1843200, \
21 .iotype = UPIO_PORT, \
22 .flags = UPF_BOOT_AUTOCONF, \
23 }
24
25static struct plat_serial8250_port exar_data[] = {
26 PORT(0x100, 5),
27 PORT(0x108, 5),
28 PORT(0x110, 5),
29 PORT(0x118, 5),
30 { },
31};
32
33static struct platform_device exar_device = {
34 .name = "serial8250",
35 .id = PLAT8250_DEV_EXAR_ST16C554,
36 .dev = {
37 .platform_data = exar_data,
38 },
39};
40
41static int __init exar_init(void)
42{
43 return platform_device_register(&exar_device);
44}
45
46module_init(exar_init);
47
48MODULE_AUTHOR("Paul B Schroeder");
49MODULE_DESCRIPTION("8250 serial probe module for Exar cards");
50MODULE_LICENSE("GPL");
diff --git a/drivers/tty/serial/8250/8250_fourport.c b/drivers/tty/serial/8250/8250_fourport.c
new file mode 100644
index 000000000000..be1582609626
--- /dev/null
+++ b/drivers/tty/serial/8250/8250_fourport.c
@@ -0,0 +1,51 @@
1/*
2 * Copyright (C) 2005 Russell King.
3 * Data taken from include/asm-i386/serial.h
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9#include <linux/module.h>
10#include <linux/init.h>
11#include <linux/serial_8250.h>
12
13#define PORT(_base,_irq) \
14 { \
15 .iobase = _base, \
16 .irq = _irq, \
17 .uartclk = 1843200, \
18 .iotype = UPIO_PORT, \
19 .flags = UPF_BOOT_AUTOCONF | UPF_FOURPORT, \
20 }
21
22static struct plat_serial8250_port fourport_data[] = {
23 PORT(0x1a0, 9),
24 PORT(0x1a8, 9),
25 PORT(0x1b0, 9),
26 PORT(0x1b8, 9),
27 PORT(0x2a0, 5),
28 PORT(0x2a8, 5),
29 PORT(0x2b0, 5),
30 PORT(0x2b8, 5),
31 { },
32};
33
34static struct platform_device fourport_device = {
35 .name = "serial8250",
36 .id = PLAT8250_DEV_FOURPORT,
37 .dev = {
38 .platform_data = fourport_data,
39 },
40};
41
42static int __init fourport_init(void)
43{
44 return platform_device_register(&fourport_device);
45}
46
47module_init(fourport_init);
48
49MODULE_AUTHOR("Russell King");
50MODULE_DESCRIPTION("8250 serial probe module for AST Fourport cards");
51MODULE_LICENSE("GPL");
diff --git a/drivers/tty/serial/8250/8250_fsl.c b/drivers/tty/serial/8250/8250_fsl.c
new file mode 100644
index 000000000000..f4d3c47b88e8
--- /dev/null
+++ b/drivers/tty/serial/8250/8250_fsl.c
@@ -0,0 +1,63 @@
1#include <linux/serial_reg.h>
2#include <linux/serial_8250.h>
3
4#include "8250.h"
5
6/*
7 * Freescale 16550 UART "driver", Copyright (C) 2011 Paul Gortmaker.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * This isn't a full driver; it just provides an alternate IRQ
14 * handler to deal with an errata. Everything else is just
15 * using the bog standard 8250 support.
16 *
17 * We follow code flow of serial8250_default_handle_irq() but add
18 * a check for a break and insert a dummy read on the Rx for the
19 * immediately following IRQ event.
20 *
21 * We re-use the already existing "bug handling" lsr_saved_flags
22 * field to carry the "what we just did" information from the one
23 * IRQ event to the next one.
24 */
25
26int fsl8250_handle_irq(struct uart_port *port)
27{
28 unsigned char lsr, orig_lsr;
29 unsigned long flags;
30 unsigned int iir;
31 struct uart_8250_port *up =
32 container_of(port, struct uart_8250_port, port);
33
34 spin_lock_irqsave(&up->port.lock, flags);
35
36 iir = port->serial_in(port, UART_IIR);
37 if (iir & UART_IIR_NO_INT) {
38 spin_unlock_irqrestore(&up->port.lock, flags);
39 return 0;
40 }
41
42 /* This is the WAR; if last event was BRK, then read and return */
43 if (unlikely(up->lsr_saved_flags & UART_LSR_BI)) {
44 up->lsr_saved_flags &= ~UART_LSR_BI;
45 port->serial_in(port, UART_RX);
46 spin_unlock_irqrestore(&up->port.lock, flags);
47 return 1;
48 }
49
50 lsr = orig_lsr = up->port.serial_in(&up->port, UART_LSR);
51
52 if (lsr & (UART_LSR_DR | UART_LSR_BI))
53 lsr = serial8250_rx_chars(up, lsr);
54
55 serial8250_modem_status(up);
56
57 if (lsr & UART_LSR_THRE)
58 serial8250_tx_chars(up);
59
60 up->lsr_saved_flags = orig_lsr;
61 spin_unlock_irqrestore(&up->port.lock, flags);
62 return 1;
63}
diff --git a/drivers/tty/serial/8250/8250_gsc.c b/drivers/tty/serial/8250/8250_gsc.c
new file mode 100644
index 000000000000..d8c0ffbfa6e3
--- /dev/null
+++ b/drivers/tty/serial/8250/8250_gsc.c
@@ -0,0 +1,122 @@
1/*
2 * Serial Device Initialisation for Lasi/Asp/Wax/Dino
3 *
4 * (c) Copyright Matthew Wilcox <willy@debian.org> 2001-2002
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11
12#include <linux/errno.h>
13#include <linux/init.h>
14#include <linux/interrupt.h>
15#include <linux/ioport.h>
16#include <linux/module.h>
17#include <linux/serial_core.h>
18#include <linux/signal.h>
19#include <linux/types.h>
20
21#include <asm/hardware.h>
22#include <asm/parisc-device.h>
23#include <asm/io.h>
24
25#include "8250.h"
26
27static int __init serial_init_chip(struct parisc_device *dev)
28{
29 struct uart_port port;
30 unsigned long address;
31 int err;
32
33 if (!dev->irq) {
34 /* We find some unattached serial ports by walking native
35 * busses. These should be silently ignored. Otherwise,
36 * what we have here is a missing parent device, so tell
37 * the user what they're missing.
38 */
39 if (parisc_parent(dev)->id.hw_type != HPHW_IOA)
40 printk(KERN_INFO
41 "Serial: device 0x%llx not configured.\n"
42 "Enable support for Wax, Lasi, Asp or Dino.\n",
43 (unsigned long long)dev->hpa.start);
44 return -ENODEV;
45 }
46
47 address = dev->hpa.start;
48 if (dev->id.sversion != 0x8d)
49 address += 0x800;
50
51 memset(&port, 0, sizeof(port));
52 port.iotype = UPIO_MEM;
53 /* 7.272727MHz on Lasi. Assumed the same for Dino, Wax and Timi. */
54 port.uartclk = 7272727;
55 port.mapbase = address;
56 port.membase = ioremap_nocache(address, 16);
57 port.irq = dev->irq;
58 port.flags = UPF_BOOT_AUTOCONF;
59 port.dev = &dev->dev;
60
61 err = serial8250_register_port(&port);
62 if (err < 0) {
63 printk(KERN_WARNING
64 "serial8250_register_port returned error %d\n", err);
65 iounmap(port.membase);
66 return err;
67 }
68
69 return 0;
70}
71
72static struct parisc_device_id serial_tbl[] = {
73 { HPHW_FIO, HVERSION_REV_ANY_ID, HVERSION_ANY_ID, 0x00075 },
74 { HPHW_FIO, HVERSION_REV_ANY_ID, HVERSION_ANY_ID, 0x0008c },
75 { HPHW_FIO, HVERSION_REV_ANY_ID, HVERSION_ANY_ID, 0x0008d },
76 { 0 }
77};
78
79/* Hack. Some machines have SERIAL_0 attached to Lasi and SERIAL_1
80 * attached to Dino. Unfortunately, Dino appears before Lasi in the device
81 * tree. To ensure that ttyS0 == SERIAL_0, we register two drivers; one
82 * which only knows about Lasi and then a second which will find all the
83 * other serial ports. HPUX ignores this problem.
84 */
85static struct parisc_device_id lasi_tbl[] = {
86 { HPHW_FIO, HVERSION_REV_ANY_ID, 0x03B, 0x0008C }, /* C1xx/C1xxL */
87 { HPHW_FIO, HVERSION_REV_ANY_ID, 0x03C, 0x0008C }, /* B132L */
88 { HPHW_FIO, HVERSION_REV_ANY_ID, 0x03D, 0x0008C }, /* B160L */
89 { HPHW_FIO, HVERSION_REV_ANY_ID, 0x03E, 0x0008C }, /* B132L+ */
90 { HPHW_FIO, HVERSION_REV_ANY_ID, 0x03F, 0x0008C }, /* B180L+ */
91 { HPHW_FIO, HVERSION_REV_ANY_ID, 0x046, 0x0008C }, /* Rocky2 120 */
92 { HPHW_FIO, HVERSION_REV_ANY_ID, 0x047, 0x0008C }, /* Rocky2 150 */
93 { HPHW_FIO, HVERSION_REV_ANY_ID, 0x04E, 0x0008C }, /* Kiji L2 132 */
94 { HPHW_FIO, HVERSION_REV_ANY_ID, 0x056, 0x0008C }, /* Raven+ */
95 { 0 }
96};
97
98
99MODULE_DEVICE_TABLE(parisc, serial_tbl);
100
101static struct parisc_driver lasi_driver = {
102 .name = "serial_1",
103 .id_table = lasi_tbl,
104 .probe = serial_init_chip,
105};
106
107static struct parisc_driver serial_driver = {
108 .name = "serial",
109 .id_table = serial_tbl,
110 .probe = serial_init_chip,
111};
112
113static int __init probe_serial_gsc(void)
114{
115 register_parisc_driver(&lasi_driver);
116 register_parisc_driver(&serial_driver);
117 return 0;
118}
119
120module_init(probe_serial_gsc);
121
122MODULE_LICENSE("GPL");
diff --git a/drivers/tty/serial/8250/8250_hp300.c b/drivers/tty/serial/8250/8250_hp300.c
new file mode 100644
index 000000000000..c13438c93012
--- /dev/null
+++ b/drivers/tty/serial/8250/8250_hp300.c
@@ -0,0 +1,327 @@
1/*
2 * Driver for the 98626/98644/internal serial interface on hp300/hp400
3 * (based on the National Semiconductor INS8250/NS16550AF/WD16C552 UARTs)
4 *
5 * Ported from 2.2 and modified to use the normal 8250 driver
6 * by Kars de Jong <jongk@linux-m68k.org>, May 2004.
7 */
8#include <linux/module.h>
9#include <linux/init.h>
10#include <linux/string.h>
11#include <linux/kernel.h>
12#include <linux/serial.h>
13#include <linux/serial_core.h>
14#include <linux/serial_8250.h>
15#include <linux/delay.h>
16#include <linux/dio.h>
17#include <linux/console.h>
18#include <linux/slab.h>
19#include <asm/io.h>
20
21#include "8250.h"
22
23#if !defined(CONFIG_HPDCA) && !defined(CONFIG_HPAPCI)
24#warning CONFIG_8250 defined but neither CONFIG_HPDCA nor CONFIG_HPAPCI defined, are you sure?
25#endif
26
27#ifdef CONFIG_HPAPCI
28struct hp300_port
29{
30 struct hp300_port *next; /* next port */
31 int line; /* line (tty) number */
32};
33
34static struct hp300_port *hp300_ports;
35#endif
36
37#ifdef CONFIG_HPDCA
38
39static int __devinit hpdca_init_one(struct dio_dev *d,
40 const struct dio_device_id *ent);
41static void __devexit hpdca_remove_one(struct dio_dev *d);
42
43static struct dio_device_id hpdca_dio_tbl[] = {
44 { DIO_ID_DCA0 },
45 { DIO_ID_DCA0REM },
46 { DIO_ID_DCA1 },
47 { DIO_ID_DCA1REM },
48 { 0 }
49};
50
51static struct dio_driver hpdca_driver = {
52 .name = "hpdca",
53 .id_table = hpdca_dio_tbl,
54 .probe = hpdca_init_one,
55 .remove = __devexit_p(hpdca_remove_one),
56};
57
58#endif
59
60static unsigned int num_ports;
61
62extern int hp300_uart_scode;
63
64/* Offset to UART registers from base of DCA */
65#define UART_OFFSET 17
66
67#define DCA_ID 0x01 /* ID (read), reset (write) */
68#define DCA_IC 0x03 /* Interrupt control */
69
70/* Interrupt control */
71#define DCA_IC_IE 0x80 /* Master interrupt enable */
72
73#define HPDCA_BAUD_BASE 153600
74
75/* Base address of the Frodo part */
76#define FRODO_BASE (0x41c000)
77
78/*
79 * Where we find the 8250-like APCI ports, and how far apart they are.
80 */
81#define FRODO_APCIBASE 0x0
82#define FRODO_APCISPACE 0x20
83#define FRODO_APCI_OFFSET(x) (FRODO_APCIBASE + ((x) * FRODO_APCISPACE))
84
85#define HPAPCI_BAUD_BASE 500400
86
87#ifdef CONFIG_SERIAL_8250_CONSOLE
88/*
89 * Parse the bootinfo to find descriptions for headless console and
90 * debug serial ports and register them with the 8250 driver.
91 * This function should be called before serial_console_init() is called
92 * to make sure the serial console will be available for use. IA-64 kernel
93 * calls this function from setup_arch() after the EFI and ACPI tables have
94 * been parsed.
95 */
96int __init hp300_setup_serial_console(void)
97{
98 int scode;
99 struct uart_port port;
100
101 memset(&port, 0, sizeof(port));
102
103 if (hp300_uart_scode < 0 || hp300_uart_scode > DIO_SCMAX)
104 return 0;
105
106 if (DIO_SCINHOLE(hp300_uart_scode))
107 return 0;
108
109 scode = hp300_uart_scode;
110
111 /* Memory mapped I/O */
112 port.iotype = UPIO_MEM;
113 port.flags = UPF_SKIP_TEST | UPF_SHARE_IRQ | UPF_BOOT_AUTOCONF;
114 port.type = PORT_UNKNOWN;
115
116 /* Check for APCI console */
117 if (scode == 256) {
118#ifdef CONFIG_HPAPCI
119 printk(KERN_INFO "Serial console is HP APCI 1\n");
120
121 port.uartclk = HPAPCI_BAUD_BASE * 16;
122 port.mapbase = (FRODO_BASE + FRODO_APCI_OFFSET(1));
123 port.membase = (char *)(port.mapbase + DIO_VIRADDRBASE);
124 port.regshift = 2;
125 add_preferred_console("ttyS", port.line, "9600n8");
126#else
127 printk(KERN_WARNING "Serial console is APCI but support is disabled (CONFIG_HPAPCI)!\n");
128 return 0;
129#endif
130 } else {
131#ifdef CONFIG_HPDCA
132 unsigned long pa = dio_scodetophysaddr(scode);
133 if (!pa)
134 return 0;
135
136 printk(KERN_INFO "Serial console is HP DCA at select code %d\n", scode);
137
138 port.uartclk = HPDCA_BAUD_BASE * 16;
139 port.mapbase = (pa + UART_OFFSET);
140 port.membase = (char *)(port.mapbase + DIO_VIRADDRBASE);
141 port.regshift = 1;
142 port.irq = DIO_IPL(pa + DIO_VIRADDRBASE);
143
144 /* Enable board-interrupts */
145 out_8(pa + DIO_VIRADDRBASE + DCA_IC, DCA_IC_IE);
146
147 if (DIO_ID(pa + DIO_VIRADDRBASE) & 0x80)
148 add_preferred_console("ttyS", port.line, "9600n8");
149#else
150 printk(KERN_WARNING "Serial console is DCA but support is disabled (CONFIG_HPDCA)!\n");
151 return 0;
152#endif
153 }
154
155 if (early_serial_setup(&port) < 0)
156 printk(KERN_WARNING "hp300_setup_serial_console(): early_serial_setup() failed.\n");
157 return 0;
158}
159#endif /* CONFIG_SERIAL_8250_CONSOLE */
160
161#ifdef CONFIG_HPDCA
162static int __devinit hpdca_init_one(struct dio_dev *d,
163 const struct dio_device_id *ent)
164{
165 struct uart_port port;
166 int line;
167
168#ifdef CONFIG_SERIAL_8250_CONSOLE
169 if (hp300_uart_scode == d->scode) {
170 /* Already got it. */
171 return 0;
172 }
173#endif
174 memset(&port, 0, sizeof(struct uart_port));
175
176 /* Memory mapped I/O */
177 port.iotype = UPIO_MEM;
178 port.flags = UPF_SKIP_TEST | UPF_SHARE_IRQ | UPF_BOOT_AUTOCONF;
179 port.irq = d->ipl;
180 port.uartclk = HPDCA_BAUD_BASE * 16;
181 port.mapbase = (d->resource.start + UART_OFFSET);
182 port.membase = (char *)(port.mapbase + DIO_VIRADDRBASE);
183 port.regshift = 1;
184 port.dev = &d->dev;
185 line = serial8250_register_port(&port);
186
187 if (line < 0) {
188 printk(KERN_NOTICE "8250_hp300: register_serial() DCA scode %d"
189 " irq %d failed\n", d->scode, port.irq);
190 return -ENOMEM;
191 }
192
193 /* Enable board-interrupts */
194 out_8(d->resource.start + DIO_VIRADDRBASE + DCA_IC, DCA_IC_IE);
195 dio_set_drvdata(d, (void *)line);
196
197 /* Reset the DCA */
198 out_8(d->resource.start + DIO_VIRADDRBASE + DCA_ID, 0xff);
199 udelay(100);
200
201 num_ports++;
202
203 return 0;
204}
205#endif
206
207static int __init hp300_8250_init(void)
208{
209 static int called;
210#ifdef CONFIG_HPAPCI
211 int line;
212 unsigned long base;
213 struct uart_port uport;
214 struct hp300_port *port;
215 int i;
216#endif
217 if (called)
218 return -ENODEV;
219 called = 1;
220
221 if (!MACH_IS_HP300)
222 return -ENODEV;
223
224#ifdef CONFIG_HPDCA
225 dio_register_driver(&hpdca_driver);
226#endif
227#ifdef CONFIG_HPAPCI
228 if (hp300_model < HP_400) {
229 if (!num_ports)
230 return -ENODEV;
231 return 0;
232 }
233 /* These models have the Frodo chip.
234 * Port 0 is reserved for the Apollo Domain keyboard.
235 * Port 1 is either the console or the DCA.
236 */
237 for (i = 1; i < 4; i++) {
238 /* Port 1 is the console on a 425e, on other machines it's
239 * mapped to DCA.
240 */
241#ifdef CONFIG_SERIAL_8250_CONSOLE
242 if (i == 1)
243 continue;
244#endif
245
246 /* Create new serial device */
247 port = kmalloc(sizeof(struct hp300_port), GFP_KERNEL);
248 if (!port)
249 return -ENOMEM;
250
251 memset(&uport, 0, sizeof(struct uart_port));
252
253 base = (FRODO_BASE + FRODO_APCI_OFFSET(i));
254
255 /* Memory mapped I/O */
256 uport.iotype = UPIO_MEM;
257 uport.flags = UPF_SKIP_TEST | UPF_SHARE_IRQ \
258 | UPF_BOOT_AUTOCONF;
259 /* XXX - no interrupt support yet */
260 uport.irq = 0;
261 uport.uartclk = HPAPCI_BAUD_BASE * 16;
262 uport.mapbase = base;
263 uport.membase = (char *)(base + DIO_VIRADDRBASE);
264 uport.regshift = 2;
265
266 line = serial8250_register_port(&uport);
267
268 if (line < 0) {
269 printk(KERN_NOTICE "8250_hp300: register_serial() APCI"
270 " %d irq %d failed\n", i, uport.irq);
271 kfree(port);
272 continue;
273 }
274
275 port->line = line;
276 port->next = hp300_ports;
277 hp300_ports = port;
278
279 num_ports++;
280 }
281#endif
282
283 /* Any boards found? */
284 if (!num_ports)
285 return -ENODEV;
286
287 return 0;
288}
289
290#ifdef CONFIG_HPDCA
291static void __devexit hpdca_remove_one(struct dio_dev *d)
292{
293 int line;
294
295 line = (int) dio_get_drvdata(d);
296 if (d->resource.start) {
297 /* Disable board-interrupts */
298 out_8(d->resource.start + DIO_VIRADDRBASE + DCA_IC, 0);
299 }
300 serial8250_unregister_port(line);
301}
302#endif
303
304static void __exit hp300_8250_exit(void)
305{
306#ifdef CONFIG_HPAPCI
307 struct hp300_port *port, *to_free;
308
309 for (port = hp300_ports; port; ) {
310 serial8250_unregister_port(port->line);
311 to_free = port;
312 port = port->next;
313 kfree(to_free);
314 }
315
316 hp300_ports = NULL;
317#endif
318#ifdef CONFIG_HPDCA
319 dio_unregister_driver(&hpdca_driver);
320#endif
321}
322
323module_init(hp300_8250_init);
324module_exit(hp300_8250_exit);
325MODULE_DESCRIPTION("HP DCA/APCI serial driver");
326MODULE_AUTHOR("Kars de Jong <jongk@linux-m68k.org>");
327MODULE_LICENSE("GPL");
diff --git a/drivers/tty/serial/8250/8250_hub6.c b/drivers/tty/serial/8250/8250_hub6.c
new file mode 100644
index 000000000000..a5c778e83de0
--- /dev/null
+++ b/drivers/tty/serial/8250/8250_hub6.c
@@ -0,0 +1,56 @@
1/*
2 * Copyright (C) 2005 Russell King.
3 * Data taken from include/asm-i386/serial.h
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9#include <linux/module.h>
10#include <linux/init.h>
11#include <linux/serial_8250.h>
12
13#define HUB6(card,port) \
14 { \
15 .iobase = 0x302, \
16 .irq = 3, \
17 .uartclk = 1843200, \
18 .iotype = UPIO_HUB6, \
19 .flags = UPF_BOOT_AUTOCONF, \
20 .hub6 = (card) << 6 | (port) << 3 | 1, \
21 }
22
23static struct plat_serial8250_port hub6_data[] = {
24 HUB6(0, 0),
25 HUB6(0, 1),
26 HUB6(0, 2),
27 HUB6(0, 3),
28 HUB6(0, 4),
29 HUB6(0, 5),
30 HUB6(1, 0),
31 HUB6(1, 1),
32 HUB6(1, 2),
33 HUB6(1, 3),
34 HUB6(1, 4),
35 HUB6(1, 5),
36 { },
37};
38
39static struct platform_device hub6_device = {
40 .name = "serial8250",
41 .id = PLAT8250_DEV_HUB6,
42 .dev = {
43 .platform_data = hub6_data,
44 },
45};
46
47static int __init hub6_init(void)
48{
49 return platform_device_register(&hub6_device);
50}
51
52module_init(hub6_init);
53
54MODULE_AUTHOR("Russell King");
55MODULE_DESCRIPTION("8250 serial probe module for Hub6 cards");
56MODULE_LICENSE("GPL");
diff --git a/drivers/tty/serial/8250/8250_mca.c b/drivers/tty/serial/8250/8250_mca.c
new file mode 100644
index 000000000000..d20abf04541e
--- /dev/null
+++ b/drivers/tty/serial/8250/8250_mca.c
@@ -0,0 +1,61 @@
1/*
2 * Copyright (C) 2005 Russell King.
3 * Data taken from include/asm-i386/serial.h
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9#include <linux/module.h>
10#include <linux/init.h>
11#include <linux/mca.h>
12#include <linux/serial_8250.h>
13
14/*
15 * FIXME: Should we be doing AUTO_IRQ here?
16 */
17#ifdef CONFIG_SERIAL_8250_DETECT_IRQ
18#define MCA_FLAGS UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_AUTO_IRQ
19#else
20#define MCA_FLAGS UPF_BOOT_AUTOCONF | UPF_SKIP_TEST
21#endif
22
23#define PORT(_base,_irq) \
24 { \
25 .iobase = _base, \
26 .irq = _irq, \
27 .uartclk = 1843200, \
28 .iotype = UPIO_PORT, \
29 .flags = MCA_FLAGS, \
30 }
31
32static struct plat_serial8250_port mca_data[] = {
33 PORT(0x3220, 3),
34 PORT(0x3228, 3),
35 PORT(0x4220, 3),
36 PORT(0x4228, 3),
37 PORT(0x5220, 3),
38 PORT(0x5228, 3),
39 { },
40};
41
42static struct platform_device mca_device = {
43 .name = "serial8250",
44 .id = PLAT8250_DEV_MCA,
45 .dev = {
46 .platform_data = mca_data,
47 },
48};
49
50static int __init mca_init(void)
51{
52 if (!MCA_bus)
53 return -ENODEV;
54 return platform_device_register(&mca_device);
55}
56
57module_init(mca_init);
58
59MODULE_AUTHOR("Russell King");
60MODULE_DESCRIPTION("8250 serial probe module for MCA ports");
61MODULE_LICENSE("GPL");
diff --git a/drivers/tty/serial/8250/8250_pci.c b/drivers/tty/serial/8250/8250_pci.c
new file mode 100644
index 000000000000..da2b0b0a183f
--- /dev/null
+++ b/drivers/tty/serial/8250/8250_pci.c
@@ -0,0 +1,4223 @@
1/*
2 * Probe module for 8250/16550-type PCI serial ports.
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Copyright (C) 2001 Russell King, All Rights Reserved.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License.
11 */
12#include <linux/module.h>
13#include <linux/init.h>
14#include <linux/pci.h>
15#include <linux/string.h>
16#include <linux/kernel.h>
17#include <linux/slab.h>
18#include <linux/delay.h>
19#include <linux/tty.h>
20#include <linux/serial_core.h>
21#include <linux/8250_pci.h>
22#include <linux/bitops.h>
23
24#include <asm/byteorder.h>
25#include <asm/io.h>
26
27#include "8250.h"
28
29#undef SERIAL_DEBUG_PCI
30
31/*
32 * init function returns:
33 * > 0 - number of ports
34 * = 0 - use board->num_ports
35 * < 0 - error
36 */
37struct pci_serial_quirk {
38 u32 vendor;
39 u32 device;
40 u32 subvendor;
41 u32 subdevice;
42 int (*probe)(struct pci_dev *dev);
43 int (*init)(struct pci_dev *dev);
44 int (*setup)(struct serial_private *,
45 const struct pciserial_board *,
46 struct uart_port *, int);
47 void (*exit)(struct pci_dev *dev);
48};
49
50#define PCI_NUM_BAR_RESOURCES 6
51
52struct serial_private {
53 struct pci_dev *dev;
54 unsigned int nr;
55 void __iomem *remapped_bar[PCI_NUM_BAR_RESOURCES];
56 struct pci_serial_quirk *quirk;
57 int line[0];
58};
59
60static int pci_default_setup(struct serial_private*,
61 const struct pciserial_board*, struct uart_port*, int);
62
63static void moan_device(const char *str, struct pci_dev *dev)
64{
65 printk(KERN_WARNING
66 "%s: %s\n"
67 "Please send the output of lspci -vv, this\n"
68 "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
69 "manufacturer and name of serial board or\n"
70 "modem board to rmk+serial@arm.linux.org.uk.\n",
71 pci_name(dev), str, dev->vendor, dev->device,
72 dev->subsystem_vendor, dev->subsystem_device);
73}
74
75static int
76setup_port(struct serial_private *priv, struct uart_port *port,
77 int bar, int offset, int regshift)
78{
79 struct pci_dev *dev = priv->dev;
80 unsigned long base, len;
81
82 if (bar >= PCI_NUM_BAR_RESOURCES)
83 return -EINVAL;
84
85 base = pci_resource_start(dev, bar);
86
87 if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
88 len = pci_resource_len(dev, bar);
89
90 if (!priv->remapped_bar[bar])
91 priv->remapped_bar[bar] = ioremap_nocache(base, len);
92 if (!priv->remapped_bar[bar])
93 return -ENOMEM;
94
95 port->iotype = UPIO_MEM;
96 port->iobase = 0;
97 port->mapbase = base + offset;
98 port->membase = priv->remapped_bar[bar] + offset;
99 port->regshift = regshift;
100 } else {
101 port->iotype = UPIO_PORT;
102 port->iobase = base + offset;
103 port->mapbase = 0;
104 port->membase = NULL;
105 port->regshift = 0;
106 }
107 return 0;
108}
109
110/*
111 * ADDI-DATA GmbH communication cards <info@addi-data.com>
112 */
113static int addidata_apci7800_setup(struct serial_private *priv,
114 const struct pciserial_board *board,
115 struct uart_port *port, int idx)
116{
117 unsigned int bar = 0, offset = board->first_offset;
118 bar = FL_GET_BASE(board->flags);
119
120 if (idx < 2) {
121 offset += idx * board->uart_offset;
122 } else if ((idx >= 2) && (idx < 4)) {
123 bar += 1;
124 offset += ((idx - 2) * board->uart_offset);
125 } else if ((idx >= 4) && (idx < 6)) {
126 bar += 2;
127 offset += ((idx - 4) * board->uart_offset);
128 } else if (idx >= 6) {
129 bar += 3;
130 offset += ((idx - 6) * board->uart_offset);
131 }
132
133 return setup_port(priv, port, bar, offset, board->reg_shift);
134}
135
136/*
137 * AFAVLAB uses a different mixture of BARs and offsets
138 * Not that ugly ;) -- HW
139 */
140static int
141afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
142 struct uart_port *port, int idx)
143{
144 unsigned int bar, offset = board->first_offset;
145
146 bar = FL_GET_BASE(board->flags);
147 if (idx < 4)
148 bar += idx;
149 else {
150 bar = 4;
151 offset += (idx - 4) * board->uart_offset;
152 }
153
154 return setup_port(priv, port, bar, offset, board->reg_shift);
155}
156
157/*
158 * HP's Remote Management Console. The Diva chip came in several
159 * different versions. N-class, L2000 and A500 have two Diva chips, each
160 * with 3 UARTs (the third UART on the second chip is unused). Superdome
161 * and Keystone have one Diva chip with 3 UARTs. Some later machines have
162 * one Diva chip, but it has been expanded to 5 UARTs.
163 */
164static int pci_hp_diva_init(struct pci_dev *dev)
165{
166 int rc = 0;
167
168 switch (dev->subsystem_device) {
169 case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
170 case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
171 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
172 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
173 rc = 3;
174 break;
175 case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
176 rc = 2;
177 break;
178 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
179 rc = 4;
180 break;
181 case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
182 case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
183 rc = 1;
184 break;
185 }
186
187 return rc;
188}
189
190/*
191 * HP's Diva chip puts the 4th/5th serial port further out, and
192 * some serial ports are supposed to be hidden on certain models.
193 */
194static int
195pci_hp_diva_setup(struct serial_private *priv,
196 const struct pciserial_board *board,
197 struct uart_port *port, int idx)
198{
199 unsigned int offset = board->first_offset;
200 unsigned int bar = FL_GET_BASE(board->flags);
201
202 switch (priv->dev->subsystem_device) {
203 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
204 if (idx == 3)
205 idx++;
206 break;
207 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
208 if (idx > 0)
209 idx++;
210 if (idx > 2)
211 idx++;
212 break;
213 }
214 if (idx > 2)
215 offset = 0x18;
216
217 offset += idx * board->uart_offset;
218
219 return setup_port(priv, port, bar, offset, board->reg_shift);
220}
221
222/*
223 * Added for EKF Intel i960 serial boards
224 */
225static int pci_inteli960ni_init(struct pci_dev *dev)
226{
227 unsigned long oldval;
228
229 if (!(dev->subsystem_device & 0x1000))
230 return -ENODEV;
231
232 /* is firmware started? */
233 pci_read_config_dword(dev, 0x44, (void *)&oldval);
234 if (oldval == 0x00001000L) { /* RESET value */
235 printk(KERN_DEBUG "Local i960 firmware missing");
236 return -ENODEV;
237 }
238 return 0;
239}
240
241/*
242 * Some PCI serial cards using the PLX 9050 PCI interface chip require
243 * that the card interrupt be explicitly enabled or disabled. This
244 * seems to be mainly needed on card using the PLX which also use I/O
245 * mapped memory.
246 */
247static int pci_plx9050_init(struct pci_dev *dev)
248{
249 u8 irq_config;
250 void __iomem *p;
251
252 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
253 moan_device("no memory in bar 0", dev);
254 return 0;
255 }
256
257 irq_config = 0x41;
258 if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
259 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
260 irq_config = 0x43;
261
262 if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
263 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
264 /*
265 * As the megawolf cards have the int pins active
266 * high, and have 2 UART chips, both ints must be
267 * enabled on the 9050. Also, the UARTS are set in
268 * 16450 mode by default, so we have to enable the
269 * 16C950 'enhanced' mode so that we can use the
270 * deep FIFOs
271 */
272 irq_config = 0x5b;
273 /*
274 * enable/disable interrupts
275 */
276 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
277 if (p == NULL)
278 return -ENOMEM;
279 writel(irq_config, p + 0x4c);
280
281 /*
282 * Read the register back to ensure that it took effect.
283 */
284 readl(p + 0x4c);
285 iounmap(p);
286
287 return 0;
288}
289
290static void __devexit pci_plx9050_exit(struct pci_dev *dev)
291{
292 u8 __iomem *p;
293
294 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
295 return;
296
297 /*
298 * disable interrupts
299 */
300 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
301 if (p != NULL) {
302 writel(0, p + 0x4c);
303
304 /*
305 * Read the register back to ensure that it took effect.
306 */
307 readl(p + 0x4c);
308 iounmap(p);
309 }
310}
311
312#define NI8420_INT_ENABLE_REG 0x38
313#define NI8420_INT_ENABLE_BIT 0x2000
314
315static void __devexit pci_ni8420_exit(struct pci_dev *dev)
316{
317 void __iomem *p;
318 unsigned long base, len;
319 unsigned int bar = 0;
320
321 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
322 moan_device("no memory in bar", dev);
323 return;
324 }
325
326 base = pci_resource_start(dev, bar);
327 len = pci_resource_len(dev, bar);
328 p = ioremap_nocache(base, len);
329 if (p == NULL)
330 return;
331
332 /* Disable the CPU Interrupt */
333 writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
334 p + NI8420_INT_ENABLE_REG);
335 iounmap(p);
336}
337
338
339/* MITE registers */
340#define MITE_IOWBSR1 0xc4
341#define MITE_IOWCR1 0xf4
342#define MITE_LCIMR1 0x08
343#define MITE_LCIMR2 0x10
344
345#define MITE_LCIMR2_CLR_CPU_IE (1 << 30)
346
347static void __devexit pci_ni8430_exit(struct pci_dev *dev)
348{
349 void __iomem *p;
350 unsigned long base, len;
351 unsigned int bar = 0;
352
353 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
354 moan_device("no memory in bar", dev);
355 return;
356 }
357
358 base = pci_resource_start(dev, bar);
359 len = pci_resource_len(dev, bar);
360 p = ioremap_nocache(base, len);
361 if (p == NULL)
362 return;
363
364 /* Disable the CPU Interrupt */
365 writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
366 iounmap(p);
367}
368
369/* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
370static int
371sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
372 struct uart_port *port, int idx)
373{
374 unsigned int bar, offset = board->first_offset;
375
376 bar = 0;
377
378 if (idx < 4) {
379 /* first four channels map to 0, 0x100, 0x200, 0x300 */
380 offset += idx * board->uart_offset;
381 } else if (idx < 8) {
382 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
383 offset += idx * board->uart_offset + 0xC00;
384 } else /* we have only 8 ports on PMC-OCTALPRO */
385 return 1;
386
387 return setup_port(priv, port, bar, offset, board->reg_shift);
388}
389
390/*
391* This does initialization for PMC OCTALPRO cards:
392* maps the device memory, resets the UARTs (needed, bc
393* if the module is removed and inserted again, the card
394* is in the sleep mode) and enables global interrupt.
395*/
396
397/* global control register offset for SBS PMC-OctalPro */
398#define OCT_REG_CR_OFF 0x500
399
400static int sbs_init(struct pci_dev *dev)
401{
402 u8 __iomem *p;
403
404 p = pci_ioremap_bar(dev, 0);
405
406 if (p == NULL)
407 return -ENOMEM;
408 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
409 writeb(0x10, p + OCT_REG_CR_OFF);
410 udelay(50);
411 writeb(0x0, p + OCT_REG_CR_OFF);
412
413 /* Set bit-2 (INTENABLE) of Control Register */
414 writeb(0x4, p + OCT_REG_CR_OFF);
415 iounmap(p);
416
417 return 0;
418}
419
420/*
421 * Disables the global interrupt of PMC-OctalPro
422 */
423
424static void __devexit sbs_exit(struct pci_dev *dev)
425{
426 u8 __iomem *p;
427
428 p = pci_ioremap_bar(dev, 0);
429 /* FIXME: What if resource_len < OCT_REG_CR_OFF */
430 if (p != NULL)
431 writeb(0, p + OCT_REG_CR_OFF);
432 iounmap(p);
433}
434
435/*
436 * SIIG serial cards have an PCI interface chip which also controls
437 * the UART clocking frequency. Each UART can be clocked independently
438 * (except cards equipped with 4 UARTs) and initial clocking settings
439 * are stored in the EEPROM chip. It can cause problems because this
440 * version of serial driver doesn't support differently clocked UART's
441 * on single PCI card. To prevent this, initialization functions set
442 * high frequency clocking for all UART's on given card. It is safe (I
443 * hope) because it doesn't touch EEPROM settings to prevent conflicts
444 * with other OSes (like M$ DOS).
445 *
446 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
447 *
448 * There is two family of SIIG serial cards with different PCI
449 * interface chip and different configuration methods:
450 * - 10x cards have control registers in IO and/or memory space;
451 * - 20x cards have control registers in standard PCI configuration space.
452 *
453 * Note: all 10x cards have PCI device ids 0x10..
454 * all 20x cards have PCI device ids 0x20..
455 *
456 * There are also Quartet Serial cards which use Oxford Semiconductor
457 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
458 *
459 * Note: some SIIG cards are probed by the parport_serial object.
460 */
461
462#define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
463#define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
464
465static int pci_siig10x_init(struct pci_dev *dev)
466{
467 u16 data;
468 void __iomem *p;
469
470 switch (dev->device & 0xfff8) {
471 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
472 data = 0xffdf;
473 break;
474 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
475 data = 0xf7ff;
476 break;
477 default: /* 1S1P, 4S */
478 data = 0xfffb;
479 break;
480 }
481
482 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
483 if (p == NULL)
484 return -ENOMEM;
485
486 writew(readw(p + 0x28) & data, p + 0x28);
487 readw(p + 0x28);
488 iounmap(p);
489 return 0;
490}
491
492#define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
493#define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
494
495static int pci_siig20x_init(struct pci_dev *dev)
496{
497 u8 data;
498
499 /* Change clock frequency for the first UART. */
500 pci_read_config_byte(dev, 0x6f, &data);
501 pci_write_config_byte(dev, 0x6f, data & 0xef);
502
503 /* If this card has 2 UART, we have to do the same with second UART. */
504 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
505 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
506 pci_read_config_byte(dev, 0x73, &data);
507 pci_write_config_byte(dev, 0x73, data & 0xef);
508 }
509 return 0;
510}
511
512static int pci_siig_init(struct pci_dev *dev)
513{
514 unsigned int type = dev->device & 0xff00;
515
516 if (type == 0x1000)
517 return pci_siig10x_init(dev);
518 else if (type == 0x2000)
519 return pci_siig20x_init(dev);
520
521 moan_device("Unknown SIIG card", dev);
522 return -ENODEV;
523}
524
525static int pci_siig_setup(struct serial_private *priv,
526 const struct pciserial_board *board,
527 struct uart_port *port, int idx)
528{
529 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
530
531 if (idx > 3) {
532 bar = 4;
533 offset = (idx - 4) * 8;
534 }
535
536 return setup_port(priv, port, bar, offset, 0);
537}
538
539/*
540 * Timedia has an explosion of boards, and to avoid the PCI table from
541 * growing *huge*, we use this function to collapse some 70 entries
542 * in the PCI table into one, for sanity's and compactness's sake.
543 */
544static const unsigned short timedia_single_port[] = {
545 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
546};
547
548static const unsigned short timedia_dual_port[] = {
549 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
550 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
551 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
552 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
553 0xD079, 0
554};
555
556static const unsigned short timedia_quad_port[] = {
557 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
558 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
559 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
560 0xB157, 0
561};
562
563static const unsigned short timedia_eight_port[] = {
564 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
565 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
566};
567
568static const struct timedia_struct {
569 int num;
570 const unsigned short *ids;
571} timedia_data[] = {
572 { 1, timedia_single_port },
573 { 2, timedia_dual_port },
574 { 4, timedia_quad_port },
575 { 8, timedia_eight_port }
576};
577
578/*
579 * There are nearly 70 different Timedia/SUNIX PCI serial devices. Instead of
580 * listing them individually, this driver merely grabs them all with
581 * PCI_ANY_ID. Some of these devices, however, also feature a parallel port,
582 * and should be left free to be claimed by parport_serial instead.
583 */
584static int pci_timedia_probe(struct pci_dev *dev)
585{
586 /*
587 * Check the third digit of the subdevice ID
588 * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel)
589 */
590 if ((dev->subsystem_device & 0x00f0) >= 0x70) {
591 dev_info(&dev->dev,
592 "ignoring Timedia subdevice %04x for parport_serial\n",
593 dev->subsystem_device);
594 return -ENODEV;
595 }
596
597 return 0;
598}
599
600static int pci_timedia_init(struct pci_dev *dev)
601{
602 const unsigned short *ids;
603 int i, j;
604
605 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
606 ids = timedia_data[i].ids;
607 for (j = 0; ids[j]; j++)
608 if (dev->subsystem_device == ids[j])
609 return timedia_data[i].num;
610 }
611 return 0;
612}
613
614/*
615 * Timedia/SUNIX uses a mixture of BARs and offsets
616 * Ugh, this is ugly as all hell --- TYT
617 */
618static int
619pci_timedia_setup(struct serial_private *priv,
620 const struct pciserial_board *board,
621 struct uart_port *port, int idx)
622{
623 unsigned int bar = 0, offset = board->first_offset;
624
625 switch (idx) {
626 case 0:
627 bar = 0;
628 break;
629 case 1:
630 offset = board->uart_offset;
631 bar = 0;
632 break;
633 case 2:
634 bar = 1;
635 break;
636 case 3:
637 offset = board->uart_offset;
638 /* FALLTHROUGH */
639 case 4: /* BAR 2 */
640 case 5: /* BAR 3 */
641 case 6: /* BAR 4 */
642 case 7: /* BAR 5 */
643 bar = idx - 2;
644 }
645
646 return setup_port(priv, port, bar, offset, board->reg_shift);
647}
648
649/*
650 * Some Titan cards are also a little weird
651 */
652static int
653titan_400l_800l_setup(struct serial_private *priv,
654 const struct pciserial_board *board,
655 struct uart_port *port, int idx)
656{
657 unsigned int bar, offset = board->first_offset;
658
659 switch (idx) {
660 case 0:
661 bar = 1;
662 break;
663 case 1:
664 bar = 2;
665 break;
666 default:
667 bar = 4;
668 offset = (idx - 2) * board->uart_offset;
669 }
670
671 return setup_port(priv, port, bar, offset, board->reg_shift);
672}
673
674static int pci_xircom_init(struct pci_dev *dev)
675{
676 msleep(100);
677 return 0;
678}
679
680static int pci_ni8420_init(struct pci_dev *dev)
681{
682 void __iomem *p;
683 unsigned long base, len;
684 unsigned int bar = 0;
685
686 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
687 moan_device("no memory in bar", dev);
688 return 0;
689 }
690
691 base = pci_resource_start(dev, bar);
692 len = pci_resource_len(dev, bar);
693 p = ioremap_nocache(base, len);
694 if (p == NULL)
695 return -ENOMEM;
696
697 /* Enable CPU Interrupt */
698 writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
699 p + NI8420_INT_ENABLE_REG);
700
701 iounmap(p);
702 return 0;
703}
704
705#define MITE_IOWBSR1_WSIZE 0xa
706#define MITE_IOWBSR1_WIN_OFFSET 0x800
707#define MITE_IOWBSR1_WENAB (1 << 7)
708#define MITE_LCIMR1_IO_IE_0 (1 << 24)
709#define MITE_LCIMR2_SET_CPU_IE (1 << 31)
710#define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
711
712static int pci_ni8430_init(struct pci_dev *dev)
713{
714 void __iomem *p;
715 unsigned long base, len;
716 u32 device_window;
717 unsigned int bar = 0;
718
719 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
720 moan_device("no memory in bar", dev);
721 return 0;
722 }
723
724 base = pci_resource_start(dev, bar);
725 len = pci_resource_len(dev, bar);
726 p = ioremap_nocache(base, len);
727 if (p == NULL)
728 return -ENOMEM;
729
730 /* Set device window address and size in BAR0 */
731 device_window = ((base + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
732 | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
733 writel(device_window, p + MITE_IOWBSR1);
734
735 /* Set window access to go to RAMSEL IO address space */
736 writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
737 p + MITE_IOWCR1);
738
739 /* Enable IO Bus Interrupt 0 */
740 writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
741
742 /* Enable CPU Interrupt */
743 writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
744
745 iounmap(p);
746 return 0;
747}
748
749/* UART Port Control Register */
750#define NI8430_PORTCON 0x0f
751#define NI8430_PORTCON_TXVR_ENABLE (1 << 3)
752
753static int
754pci_ni8430_setup(struct serial_private *priv,
755 const struct pciserial_board *board,
756 struct uart_port *port, int idx)
757{
758 void __iomem *p;
759 unsigned long base, len;
760 unsigned int bar, offset = board->first_offset;
761
762 if (idx >= board->num_ports)
763 return 1;
764
765 bar = FL_GET_BASE(board->flags);
766 offset += idx * board->uart_offset;
767
768 base = pci_resource_start(priv->dev, bar);
769 len = pci_resource_len(priv->dev, bar);
770 p = ioremap_nocache(base, len);
771
772 /* enable the transceiver */
773 writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
774 p + offset + NI8430_PORTCON);
775
776 iounmap(p);
777
778 return setup_port(priv, port, bar, offset, board->reg_shift);
779}
780
781static int pci_netmos_9900_setup(struct serial_private *priv,
782 const struct pciserial_board *board,
783 struct uart_port *port, int idx)
784{
785 unsigned int bar;
786
787 if ((priv->dev->subsystem_device & 0xff00) == 0x3000) {
788 /* netmos apparently orders BARs by datasheet layout, so serial
789 * ports get BARs 0 and 3 (or 1 and 4 for memmapped)
790 */
791 bar = 3 * idx;
792
793 return setup_port(priv, port, bar, 0, board->reg_shift);
794 } else {
795 return pci_default_setup(priv, board, port, idx);
796 }
797}
798
799/* the 99xx series comes with a range of device IDs and a variety
800 * of capabilities:
801 *
802 * 9900 has varying capabilities and can cascade to sub-controllers
803 * (cascading should be purely internal)
804 * 9904 is hardwired with 4 serial ports
805 * 9912 and 9922 are hardwired with 2 serial ports
806 */
807static int pci_netmos_9900_numports(struct pci_dev *dev)
808{
809 unsigned int c = dev->class;
810 unsigned int pi;
811 unsigned short sub_serports;
812
813 pi = (c & 0xff);
814
815 if (pi == 2) {
816 return 1;
817 } else if ((pi == 0) &&
818 (dev->device == PCI_DEVICE_ID_NETMOS_9900)) {
819 /* two possibilities: 0x30ps encodes number of parallel and
820 * serial ports, or 0x1000 indicates *something*. This is not
821 * immediately obvious, since the 2s1p+4s configuration seems
822 * to offer all functionality on functions 0..2, while still
823 * advertising the same function 3 as the 4s+2s1p config.
824 */
825 sub_serports = dev->subsystem_device & 0xf;
826 if (sub_serports > 0) {
827 return sub_serports;
828 } else {
829 printk(KERN_NOTICE "NetMos/Mostech serial driver ignoring port on ambiguous config.\n");
830 return 0;
831 }
832 }
833
834 moan_device("unknown NetMos/Mostech program interface", dev);
835 return 0;
836}
837
838static int pci_netmos_init(struct pci_dev *dev)
839{
840 /* subdevice 0x00PS means <P> parallel, <S> serial */
841 unsigned int num_serial = dev->subsystem_device & 0xf;
842
843 if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) ||
844 (dev->device == PCI_DEVICE_ID_NETMOS_9865))
845 return 0;
846
847 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
848 dev->subsystem_device == 0x0299)
849 return 0;
850
851 switch (dev->device) { /* FALLTHROUGH on all */
852 case PCI_DEVICE_ID_NETMOS_9904:
853 case PCI_DEVICE_ID_NETMOS_9912:
854 case PCI_DEVICE_ID_NETMOS_9922:
855 case PCI_DEVICE_ID_NETMOS_9900:
856 num_serial = pci_netmos_9900_numports(dev);
857 break;
858
859 default:
860 if (num_serial == 0 ) {
861 moan_device("unknown NetMos/Mostech device", dev);
862 }
863 }
864
865 if (num_serial == 0)
866 return -ENODEV;
867
868 return num_serial;
869}
870
871/*
872 * These chips are available with optionally one parallel port and up to
873 * two serial ports. Unfortunately they all have the same product id.
874 *
875 * Basic configuration is done over a region of 32 I/O ports. The base
876 * ioport is called INTA or INTC, depending on docs/other drivers.
877 *
878 * The region of the 32 I/O ports is configured in POSIO0R...
879 */
880
881/* registers */
882#define ITE_887x_MISCR 0x9c
883#define ITE_887x_INTCBAR 0x78
884#define ITE_887x_UARTBAR 0x7c
885#define ITE_887x_PS0BAR 0x10
886#define ITE_887x_POSIO0 0x60
887
888/* I/O space size */
889#define ITE_887x_IOSIZE 32
890/* I/O space size (bits 26-24; 8 bytes = 011b) */
891#define ITE_887x_POSIO_IOSIZE_8 (3 << 24)
892/* I/O space size (bits 26-24; 32 bytes = 101b) */
893#define ITE_887x_POSIO_IOSIZE_32 (5 << 24)
894/* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
895#define ITE_887x_POSIO_SPEED (3 << 29)
896/* enable IO_Space bit */
897#define ITE_887x_POSIO_ENABLE (1 << 31)
898
899static int pci_ite887x_init(struct pci_dev *dev)
900{
901 /* inta_addr are the configuration addresses of the ITE */
902 static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
903 0x200, 0x280, 0 };
904 int ret, i, type;
905 struct resource *iobase = NULL;
906 u32 miscr, uartbar, ioport;
907
908 /* search for the base-ioport */
909 i = 0;
910 while (inta_addr[i] && iobase == NULL) {
911 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
912 "ite887x");
913 if (iobase != NULL) {
914 /* write POSIO0R - speed | size | ioport */
915 pci_write_config_dword(dev, ITE_887x_POSIO0,
916 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
917 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
918 /* write INTCBAR - ioport */
919 pci_write_config_dword(dev, ITE_887x_INTCBAR,
920 inta_addr[i]);
921 ret = inb(inta_addr[i]);
922 if (ret != 0xff) {
923 /* ioport connected */
924 break;
925 }
926 release_region(iobase->start, ITE_887x_IOSIZE);
927 iobase = NULL;
928 }
929 i++;
930 }
931
932 if (!inta_addr[i]) {
933 printk(KERN_ERR "ite887x: could not find iobase\n");
934 return -ENODEV;
935 }
936
937 /* start of undocumented type checking (see parport_pc.c) */
938 type = inb(iobase->start + 0x18) & 0x0f;
939
940 switch (type) {
941 case 0x2: /* ITE8871 (1P) */
942 case 0xa: /* ITE8875 (1P) */
943 ret = 0;
944 break;
945 case 0xe: /* ITE8872 (2S1P) */
946 ret = 2;
947 break;
948 case 0x6: /* ITE8873 (1S) */
949 ret = 1;
950 break;
951 case 0x8: /* ITE8874 (2S) */
952 ret = 2;
953 break;
954 default:
955 moan_device("Unknown ITE887x", dev);
956 ret = -ENODEV;
957 }
958
959 /* configure all serial ports */
960 for (i = 0; i < ret; i++) {
961 /* read the I/O port from the device */
962 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
963 &ioport);
964 ioport &= 0x0000FF00; /* the actual base address */
965 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
966 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
967 ITE_887x_POSIO_IOSIZE_8 | ioport);
968
969 /* write the ioport to the UARTBAR */
970 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
971 uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */
972 uartbar |= (ioport << (16 * i)); /* set the ioport */
973 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
974
975 /* get current config */
976 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
977 /* disable interrupts (UARTx_Routing[3:0]) */
978 miscr &= ~(0xf << (12 - 4 * i));
979 /* activate the UART (UARTx_En) */
980 miscr |= 1 << (23 - i);
981 /* write new config with activated UART */
982 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
983 }
984
985 if (ret <= 0) {
986 /* the device has no UARTs if we get here */
987 release_region(iobase->start, ITE_887x_IOSIZE);
988 }
989
990 return ret;
991}
992
993static void __devexit pci_ite887x_exit(struct pci_dev *dev)
994{
995 u32 ioport;
996 /* the ioport is bit 0-15 in POSIO0R */
997 pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
998 ioport &= 0xffff;
999 release_region(ioport, ITE_887x_IOSIZE);
1000}
1001
1002/*
1003 * Oxford Semiconductor Inc.
1004 * Check that device is part of the Tornado range of devices, then determine
1005 * the number of ports available on the device.
1006 */
1007static int pci_oxsemi_tornado_init(struct pci_dev *dev)
1008{
1009 u8 __iomem *p;
1010 unsigned long deviceID;
1011 unsigned int number_uarts = 0;
1012
1013 /* OxSemi Tornado devices are all 0xCxxx */
1014 if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
1015 (dev->device & 0xF000) != 0xC000)
1016 return 0;
1017
1018 p = pci_iomap(dev, 0, 5);
1019 if (p == NULL)
1020 return -ENOMEM;
1021
1022 deviceID = ioread32(p);
1023 /* Tornado device */
1024 if (deviceID == 0x07000200) {
1025 number_uarts = ioread8(p + 4);
1026 printk(KERN_DEBUG
1027 "%d ports detected on Oxford PCI Express device\n",
1028 number_uarts);
1029 }
1030 pci_iounmap(dev, p);
1031 return number_uarts;
1032}
1033
1034static int
1035pci_default_setup(struct serial_private *priv,
1036 const struct pciserial_board *board,
1037 struct uart_port *port, int idx)
1038{
1039 unsigned int bar, offset = board->first_offset, maxnr;
1040
1041 bar = FL_GET_BASE(board->flags);
1042 if (board->flags & FL_BASE_BARS)
1043 bar += idx;
1044 else
1045 offset += idx * board->uart_offset;
1046
1047 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1048 (board->reg_shift + 3);
1049
1050 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1051 return 1;
1052
1053 return setup_port(priv, port, bar, offset, board->reg_shift);
1054}
1055
1056static int
1057ce4100_serial_setup(struct serial_private *priv,
1058 const struct pciserial_board *board,
1059 struct uart_port *port, int idx)
1060{
1061 int ret;
1062
1063 ret = setup_port(priv, port, 0, 0, board->reg_shift);
1064 port->iotype = UPIO_MEM32;
1065 port->type = PORT_XSCALE;
1066 port->flags = (port->flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1067 port->regshift = 2;
1068
1069 return ret;
1070}
1071
1072static int
1073pci_omegapci_setup(struct serial_private *priv,
1074 const struct pciserial_board *board,
1075 struct uart_port *port, int idx)
1076{
1077 return setup_port(priv, port, 2, idx * 8, 0);
1078}
1079
1080static int skip_tx_en_setup(struct serial_private *priv,
1081 const struct pciserial_board *board,
1082 struct uart_port *port, int idx)
1083{
1084 port->flags |= UPF_NO_TXEN_TEST;
1085 printk(KERN_DEBUG "serial8250: skipping TxEn test for device "
1086 "[%04x:%04x] subsystem [%04x:%04x]\n",
1087 priv->dev->vendor,
1088 priv->dev->device,
1089 priv->dev->subsystem_vendor,
1090 priv->dev->subsystem_device);
1091
1092 return pci_default_setup(priv, board, port, idx);
1093}
1094
1095static int kt_serial_setup(struct serial_private *priv,
1096 const struct pciserial_board *board,
1097 struct uart_port *port, int idx)
1098{
1099 port->flags |= UPF_IIR_ONCE;
1100 return skip_tx_en_setup(priv, board, port, idx);
1101}
1102
1103static int pci_eg20t_init(struct pci_dev *dev)
1104{
1105#if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE)
1106 return -ENODEV;
1107#else
1108 return 0;
1109#endif
1110}
1111
1112static int
1113pci_xr17c154_setup(struct serial_private *priv,
1114 const struct pciserial_board *board,
1115 struct uart_port *port, int idx)
1116{
1117 port->flags |= UPF_EXAR_EFR;
1118 return pci_default_setup(priv, board, port, idx);
1119}
1120
1121static int try_enable_msi(struct pci_dev *dev)
1122{
1123 /* use msi if available, but fallback to legacy otherwise */
1124 pci_enable_msi(dev);
1125 return 0;
1126}
1127
1128static void disable_msi(struct pci_dev *dev)
1129{
1130 pci_disable_msi(dev);
1131}
1132
1133#define PCI_VENDOR_ID_SBSMODULARIO 0x124B
1134#define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
1135#define PCI_DEVICE_ID_OCTPRO 0x0001
1136#define PCI_SUBDEVICE_ID_OCTPRO232 0x0108
1137#define PCI_SUBDEVICE_ID_OCTPRO422 0x0208
1138#define PCI_SUBDEVICE_ID_POCTAL232 0x0308
1139#define PCI_SUBDEVICE_ID_POCTAL422 0x0408
1140#define PCI_VENDOR_ID_ADVANTECH 0x13fe
1141#define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66
1142#define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
1143#define PCI_DEVICE_ID_TITAN_200I 0x8028
1144#define PCI_DEVICE_ID_TITAN_400I 0x8048
1145#define PCI_DEVICE_ID_TITAN_800I 0x8088
1146#define PCI_DEVICE_ID_TITAN_800EH 0xA007
1147#define PCI_DEVICE_ID_TITAN_800EHB 0xA008
1148#define PCI_DEVICE_ID_TITAN_400EH 0xA009
1149#define PCI_DEVICE_ID_TITAN_100E 0xA010
1150#define PCI_DEVICE_ID_TITAN_200E 0xA012
1151#define PCI_DEVICE_ID_TITAN_400E 0xA013
1152#define PCI_DEVICE_ID_TITAN_800E 0xA014
1153#define PCI_DEVICE_ID_TITAN_200EI 0xA016
1154#define PCI_DEVICE_ID_TITAN_200EISI 0xA017
1155#define PCI_DEVICE_ID_TITAN_400V3 0xA310
1156#define PCI_DEVICE_ID_TITAN_410V3 0xA312
1157#define PCI_DEVICE_ID_TITAN_800V3 0xA314
1158#define PCI_DEVICE_ID_TITAN_800V3B 0xA315
1159#define PCI_DEVICE_ID_OXSEMI_16PCI958 0x9538
1160#define PCIE_DEVICE_ID_NEO_2_OX_IBM 0x00F6
1161#define PCI_DEVICE_ID_PLX_CRONYX_OMEGA 0xc001
1162#define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d
1163
1164/* Unknown vendors/cards - this should not be in linux/pci_ids.h */
1165#define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
1166
1167/*
1168 * Master list of serial port init/setup/exit quirks.
1169 * This does not describe the general nature of the port.
1170 * (ie, baud base, number and location of ports, etc)
1171 *
1172 * This list is ordered alphabetically by vendor then device.
1173 * Specific entries must come before more generic entries.
1174 */
1175static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
1176 /*
1177 * ADDI-DATA GmbH communication cards <info@addi-data.com>
1178 */
1179 {
1180 .vendor = PCI_VENDOR_ID_ADDIDATA_OLD,
1181 .device = PCI_DEVICE_ID_ADDIDATA_APCI7800,
1182 .subvendor = PCI_ANY_ID,
1183 .subdevice = PCI_ANY_ID,
1184 .setup = addidata_apci7800_setup,
1185 },
1186 /*
1187 * AFAVLAB cards - these may be called via parport_serial
1188 * It is not clear whether this applies to all products.
1189 */
1190 {
1191 .vendor = PCI_VENDOR_ID_AFAVLAB,
1192 .device = PCI_ANY_ID,
1193 .subvendor = PCI_ANY_ID,
1194 .subdevice = PCI_ANY_ID,
1195 .setup = afavlab_setup,
1196 },
1197 /*
1198 * HP Diva
1199 */
1200 {
1201 .vendor = PCI_VENDOR_ID_HP,
1202 .device = PCI_DEVICE_ID_HP_DIVA,
1203 .subvendor = PCI_ANY_ID,
1204 .subdevice = PCI_ANY_ID,
1205 .init = pci_hp_diva_init,
1206 .setup = pci_hp_diva_setup,
1207 },
1208 /*
1209 * Intel
1210 */
1211 {
1212 .vendor = PCI_VENDOR_ID_INTEL,
1213 .device = PCI_DEVICE_ID_INTEL_80960_RP,
1214 .subvendor = 0xe4bf,
1215 .subdevice = PCI_ANY_ID,
1216 .init = pci_inteli960ni_init,
1217 .setup = pci_default_setup,
1218 },
1219 {
1220 .vendor = PCI_VENDOR_ID_INTEL,
1221 .device = PCI_DEVICE_ID_INTEL_8257X_SOL,
1222 .subvendor = PCI_ANY_ID,
1223 .subdevice = PCI_ANY_ID,
1224 .setup = skip_tx_en_setup,
1225 },
1226 {
1227 .vendor = PCI_VENDOR_ID_INTEL,
1228 .device = PCI_DEVICE_ID_INTEL_82573L_SOL,
1229 .subvendor = PCI_ANY_ID,
1230 .subdevice = PCI_ANY_ID,
1231 .setup = skip_tx_en_setup,
1232 },
1233 {
1234 .vendor = PCI_VENDOR_ID_INTEL,
1235 .device = PCI_DEVICE_ID_INTEL_82573E_SOL,
1236 .subvendor = PCI_ANY_ID,
1237 .subdevice = PCI_ANY_ID,
1238 .setup = skip_tx_en_setup,
1239 },
1240 {
1241 .vendor = PCI_VENDOR_ID_INTEL,
1242 .device = PCI_DEVICE_ID_INTEL_CE4100_UART,
1243 .subvendor = PCI_ANY_ID,
1244 .subdevice = PCI_ANY_ID,
1245 .setup = ce4100_serial_setup,
1246 },
1247 {
1248 .vendor = PCI_VENDOR_ID_INTEL,
1249 .device = PCI_DEVICE_ID_INTEL_PATSBURG_KT,
1250 .subvendor = PCI_ANY_ID,
1251 .subdevice = PCI_ANY_ID,
1252 .init = try_enable_msi,
1253 .setup = kt_serial_setup,
1254 .exit = disable_msi,
1255 },
1256 /*
1257 * ITE
1258 */
1259 {
1260 .vendor = PCI_VENDOR_ID_ITE,
1261 .device = PCI_DEVICE_ID_ITE_8872,
1262 .subvendor = PCI_ANY_ID,
1263 .subdevice = PCI_ANY_ID,
1264 .init = pci_ite887x_init,
1265 .setup = pci_default_setup,
1266 .exit = __devexit_p(pci_ite887x_exit),
1267 },
1268 /*
1269 * National Instruments
1270 */
1271 {
1272 .vendor = PCI_VENDOR_ID_NI,
1273 .device = PCI_DEVICE_ID_NI_PCI23216,
1274 .subvendor = PCI_ANY_ID,
1275 .subdevice = PCI_ANY_ID,
1276 .init = pci_ni8420_init,
1277 .setup = pci_default_setup,
1278 .exit = __devexit_p(pci_ni8420_exit),
1279 },
1280 {
1281 .vendor = PCI_VENDOR_ID_NI,
1282 .device = PCI_DEVICE_ID_NI_PCI2328,
1283 .subvendor = PCI_ANY_ID,
1284 .subdevice = PCI_ANY_ID,
1285 .init = pci_ni8420_init,
1286 .setup = pci_default_setup,
1287 .exit = __devexit_p(pci_ni8420_exit),
1288 },
1289 {
1290 .vendor = PCI_VENDOR_ID_NI,
1291 .device = PCI_DEVICE_ID_NI_PCI2324,
1292 .subvendor = PCI_ANY_ID,
1293 .subdevice = PCI_ANY_ID,
1294 .init = pci_ni8420_init,
1295 .setup = pci_default_setup,
1296 .exit = __devexit_p(pci_ni8420_exit),
1297 },
1298 {
1299 .vendor = PCI_VENDOR_ID_NI,
1300 .device = PCI_DEVICE_ID_NI_PCI2322,
1301 .subvendor = PCI_ANY_ID,
1302 .subdevice = PCI_ANY_ID,
1303 .init = pci_ni8420_init,
1304 .setup = pci_default_setup,
1305 .exit = __devexit_p(pci_ni8420_exit),
1306 },
1307 {
1308 .vendor = PCI_VENDOR_ID_NI,
1309 .device = PCI_DEVICE_ID_NI_PCI2324I,
1310 .subvendor = PCI_ANY_ID,
1311 .subdevice = PCI_ANY_ID,
1312 .init = pci_ni8420_init,
1313 .setup = pci_default_setup,
1314 .exit = __devexit_p(pci_ni8420_exit),
1315 },
1316 {
1317 .vendor = PCI_VENDOR_ID_NI,
1318 .device = PCI_DEVICE_ID_NI_PCI2322I,
1319 .subvendor = PCI_ANY_ID,
1320 .subdevice = PCI_ANY_ID,
1321 .init = pci_ni8420_init,
1322 .setup = pci_default_setup,
1323 .exit = __devexit_p(pci_ni8420_exit),
1324 },
1325 {
1326 .vendor = PCI_VENDOR_ID_NI,
1327 .device = PCI_DEVICE_ID_NI_PXI8420_23216,
1328 .subvendor = PCI_ANY_ID,
1329 .subdevice = PCI_ANY_ID,
1330 .init = pci_ni8420_init,
1331 .setup = pci_default_setup,
1332 .exit = __devexit_p(pci_ni8420_exit),
1333 },
1334 {
1335 .vendor = PCI_VENDOR_ID_NI,
1336 .device = PCI_DEVICE_ID_NI_PXI8420_2328,
1337 .subvendor = PCI_ANY_ID,
1338 .subdevice = PCI_ANY_ID,
1339 .init = pci_ni8420_init,
1340 .setup = pci_default_setup,
1341 .exit = __devexit_p(pci_ni8420_exit),
1342 },
1343 {
1344 .vendor = PCI_VENDOR_ID_NI,
1345 .device = PCI_DEVICE_ID_NI_PXI8420_2324,
1346 .subvendor = PCI_ANY_ID,
1347 .subdevice = PCI_ANY_ID,
1348 .init = pci_ni8420_init,
1349 .setup = pci_default_setup,
1350 .exit = __devexit_p(pci_ni8420_exit),
1351 },
1352 {
1353 .vendor = PCI_VENDOR_ID_NI,
1354 .device = PCI_DEVICE_ID_NI_PXI8420_2322,
1355 .subvendor = PCI_ANY_ID,
1356 .subdevice = PCI_ANY_ID,
1357 .init = pci_ni8420_init,
1358 .setup = pci_default_setup,
1359 .exit = __devexit_p(pci_ni8420_exit),
1360 },
1361 {
1362 .vendor = PCI_VENDOR_ID_NI,
1363 .device = PCI_DEVICE_ID_NI_PXI8422_2324,
1364 .subvendor = PCI_ANY_ID,
1365 .subdevice = PCI_ANY_ID,
1366 .init = pci_ni8420_init,
1367 .setup = pci_default_setup,
1368 .exit = __devexit_p(pci_ni8420_exit),
1369 },
1370 {
1371 .vendor = PCI_VENDOR_ID_NI,
1372 .device = PCI_DEVICE_ID_NI_PXI8422_2322,
1373 .subvendor = PCI_ANY_ID,
1374 .subdevice = PCI_ANY_ID,
1375 .init = pci_ni8420_init,
1376 .setup = pci_default_setup,
1377 .exit = __devexit_p(pci_ni8420_exit),
1378 },
1379 {
1380 .vendor = PCI_VENDOR_ID_NI,
1381 .device = PCI_ANY_ID,
1382 .subvendor = PCI_ANY_ID,
1383 .subdevice = PCI_ANY_ID,
1384 .init = pci_ni8430_init,
1385 .setup = pci_ni8430_setup,
1386 .exit = __devexit_p(pci_ni8430_exit),
1387 },
1388 /*
1389 * Panacom
1390 */
1391 {
1392 .vendor = PCI_VENDOR_ID_PANACOM,
1393 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM,
1394 .subvendor = PCI_ANY_ID,
1395 .subdevice = PCI_ANY_ID,
1396 .init = pci_plx9050_init,
1397 .setup = pci_default_setup,
1398 .exit = __devexit_p(pci_plx9050_exit),
1399 },
1400 {
1401 .vendor = PCI_VENDOR_ID_PANACOM,
1402 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM,
1403 .subvendor = PCI_ANY_ID,
1404 .subdevice = PCI_ANY_ID,
1405 .init = pci_plx9050_init,
1406 .setup = pci_default_setup,
1407 .exit = __devexit_p(pci_plx9050_exit),
1408 },
1409 /*
1410 * PLX
1411 */
1412 {
1413 .vendor = PCI_VENDOR_ID_PLX,
1414 .device = PCI_DEVICE_ID_PLX_9030,
1415 .subvendor = PCI_SUBVENDOR_ID_PERLE,
1416 .subdevice = PCI_ANY_ID,
1417 .setup = pci_default_setup,
1418 },
1419 {
1420 .vendor = PCI_VENDOR_ID_PLX,
1421 .device = PCI_DEVICE_ID_PLX_9050,
1422 .subvendor = PCI_SUBVENDOR_ID_EXSYS,
1423 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055,
1424 .init = pci_plx9050_init,
1425 .setup = pci_default_setup,
1426 .exit = __devexit_p(pci_plx9050_exit),
1427 },
1428 {
1429 .vendor = PCI_VENDOR_ID_PLX,
1430 .device = PCI_DEVICE_ID_PLX_9050,
1431 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN,
1432 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
1433 .init = pci_plx9050_init,
1434 .setup = pci_default_setup,
1435 .exit = __devexit_p(pci_plx9050_exit),
1436 },
1437 {
1438 .vendor = PCI_VENDOR_ID_PLX,
1439 .device = PCI_DEVICE_ID_PLX_9050,
1440 .subvendor = PCI_VENDOR_ID_PLX,
1441 .subdevice = PCI_SUBDEVICE_ID_UNKNOWN_0x1584,
1442 .init = pci_plx9050_init,
1443 .setup = pci_default_setup,
1444 .exit = __devexit_p(pci_plx9050_exit),
1445 },
1446 {
1447 .vendor = PCI_VENDOR_ID_PLX,
1448 .device = PCI_DEVICE_ID_PLX_ROMULUS,
1449 .subvendor = PCI_VENDOR_ID_PLX,
1450 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS,
1451 .init = pci_plx9050_init,
1452 .setup = pci_default_setup,
1453 .exit = __devexit_p(pci_plx9050_exit),
1454 },
1455 /*
1456 * SBS Technologies, Inc., PMC-OCTALPRO 232
1457 */
1458 {
1459 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1460 .device = PCI_DEVICE_ID_OCTPRO,
1461 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1462 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232,
1463 .init = sbs_init,
1464 .setup = sbs_setup,
1465 .exit = __devexit_p(sbs_exit),
1466 },
1467 /*
1468 * SBS Technologies, Inc., PMC-OCTALPRO 422
1469 */
1470 {
1471 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1472 .device = PCI_DEVICE_ID_OCTPRO,
1473 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1474 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422,
1475 .init = sbs_init,
1476 .setup = sbs_setup,
1477 .exit = __devexit_p(sbs_exit),
1478 },
1479 /*
1480 * SBS Technologies, Inc., P-Octal 232
1481 */
1482 {
1483 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1484 .device = PCI_DEVICE_ID_OCTPRO,
1485 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1486 .subdevice = PCI_SUBDEVICE_ID_POCTAL232,
1487 .init = sbs_init,
1488 .setup = sbs_setup,
1489 .exit = __devexit_p(sbs_exit),
1490 },
1491 /*
1492 * SBS Technologies, Inc., P-Octal 422
1493 */
1494 {
1495 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1496 .device = PCI_DEVICE_ID_OCTPRO,
1497 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1498 .subdevice = PCI_SUBDEVICE_ID_POCTAL422,
1499 .init = sbs_init,
1500 .setup = sbs_setup,
1501 .exit = __devexit_p(sbs_exit),
1502 },
1503 /*
1504 * SIIG cards - these may be called via parport_serial
1505 */
1506 {
1507 .vendor = PCI_VENDOR_ID_SIIG,
1508 .device = PCI_ANY_ID,
1509 .subvendor = PCI_ANY_ID,
1510 .subdevice = PCI_ANY_ID,
1511 .init = pci_siig_init,
1512 .setup = pci_siig_setup,
1513 },
1514 /*
1515 * Titan cards
1516 */
1517 {
1518 .vendor = PCI_VENDOR_ID_TITAN,
1519 .device = PCI_DEVICE_ID_TITAN_400L,
1520 .subvendor = PCI_ANY_ID,
1521 .subdevice = PCI_ANY_ID,
1522 .setup = titan_400l_800l_setup,
1523 },
1524 {
1525 .vendor = PCI_VENDOR_ID_TITAN,
1526 .device = PCI_DEVICE_ID_TITAN_800L,
1527 .subvendor = PCI_ANY_ID,
1528 .subdevice = PCI_ANY_ID,
1529 .setup = titan_400l_800l_setup,
1530 },
1531 /*
1532 * Timedia cards
1533 */
1534 {
1535 .vendor = PCI_VENDOR_ID_TIMEDIA,
1536 .device = PCI_DEVICE_ID_TIMEDIA_1889,
1537 .subvendor = PCI_VENDOR_ID_TIMEDIA,
1538 .subdevice = PCI_ANY_ID,
1539 .probe = pci_timedia_probe,
1540 .init = pci_timedia_init,
1541 .setup = pci_timedia_setup,
1542 },
1543 {
1544 .vendor = PCI_VENDOR_ID_TIMEDIA,
1545 .device = PCI_ANY_ID,
1546 .subvendor = PCI_ANY_ID,
1547 .subdevice = PCI_ANY_ID,
1548 .setup = pci_timedia_setup,
1549 },
1550 /*
1551 * Exar cards
1552 */
1553 {
1554 .vendor = PCI_VENDOR_ID_EXAR,
1555 .device = PCI_DEVICE_ID_EXAR_XR17C152,
1556 .subvendor = PCI_ANY_ID,
1557 .subdevice = PCI_ANY_ID,
1558 .setup = pci_xr17c154_setup,
1559 },
1560 {
1561 .vendor = PCI_VENDOR_ID_EXAR,
1562 .device = PCI_DEVICE_ID_EXAR_XR17C154,
1563 .subvendor = PCI_ANY_ID,
1564 .subdevice = PCI_ANY_ID,
1565 .setup = pci_xr17c154_setup,
1566 },
1567 {
1568 .vendor = PCI_VENDOR_ID_EXAR,
1569 .device = PCI_DEVICE_ID_EXAR_XR17C158,
1570 .subvendor = PCI_ANY_ID,
1571 .subdevice = PCI_ANY_ID,
1572 .setup = pci_xr17c154_setup,
1573 },
1574 /*
1575 * Xircom cards
1576 */
1577 {
1578 .vendor = PCI_VENDOR_ID_XIRCOM,
1579 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
1580 .subvendor = PCI_ANY_ID,
1581 .subdevice = PCI_ANY_ID,
1582 .init = pci_xircom_init,
1583 .setup = pci_default_setup,
1584 },
1585 /*
1586 * Netmos cards - these may be called via parport_serial
1587 */
1588 {
1589 .vendor = PCI_VENDOR_ID_NETMOS,
1590 .device = PCI_ANY_ID,
1591 .subvendor = PCI_ANY_ID,
1592 .subdevice = PCI_ANY_ID,
1593 .init = pci_netmos_init,
1594 .setup = pci_netmos_9900_setup,
1595 },
1596 /*
1597 * For Oxford Semiconductor Tornado based devices
1598 */
1599 {
1600 .vendor = PCI_VENDOR_ID_OXSEMI,
1601 .device = PCI_ANY_ID,
1602 .subvendor = PCI_ANY_ID,
1603 .subdevice = PCI_ANY_ID,
1604 .init = pci_oxsemi_tornado_init,
1605 .setup = pci_default_setup,
1606 },
1607 {
1608 .vendor = PCI_VENDOR_ID_MAINPINE,
1609 .device = PCI_ANY_ID,
1610 .subvendor = PCI_ANY_ID,
1611 .subdevice = PCI_ANY_ID,
1612 .init = pci_oxsemi_tornado_init,
1613 .setup = pci_default_setup,
1614 },
1615 {
1616 .vendor = PCI_VENDOR_ID_DIGI,
1617 .device = PCIE_DEVICE_ID_NEO_2_OX_IBM,
1618 .subvendor = PCI_SUBVENDOR_ID_IBM,
1619 .subdevice = PCI_ANY_ID,
1620 .init = pci_oxsemi_tornado_init,
1621 .setup = pci_default_setup,
1622 },
1623 {
1624 .vendor = PCI_VENDOR_ID_INTEL,
1625 .device = 0x8811,
1626 .init = pci_eg20t_init,
1627 .setup = pci_default_setup,
1628 },
1629 {
1630 .vendor = PCI_VENDOR_ID_INTEL,
1631 .device = 0x8812,
1632 .init = pci_eg20t_init,
1633 .setup = pci_default_setup,
1634 },
1635 {
1636 .vendor = PCI_VENDOR_ID_INTEL,
1637 .device = 0x8813,
1638 .init = pci_eg20t_init,
1639 .setup = pci_default_setup,
1640 },
1641 {
1642 .vendor = PCI_VENDOR_ID_INTEL,
1643 .device = 0x8814,
1644 .init = pci_eg20t_init,
1645 .setup = pci_default_setup,
1646 },
1647 {
1648 .vendor = 0x10DB,
1649 .device = 0x8027,
1650 .init = pci_eg20t_init,
1651 .setup = pci_default_setup,
1652 },
1653 {
1654 .vendor = 0x10DB,
1655 .device = 0x8028,
1656 .init = pci_eg20t_init,
1657 .setup = pci_default_setup,
1658 },
1659 {
1660 .vendor = 0x10DB,
1661 .device = 0x8029,
1662 .init = pci_eg20t_init,
1663 .setup = pci_default_setup,
1664 },
1665 {
1666 .vendor = 0x10DB,
1667 .device = 0x800C,
1668 .init = pci_eg20t_init,
1669 .setup = pci_default_setup,
1670 },
1671 {
1672 .vendor = 0x10DB,
1673 .device = 0x800D,
1674 .init = pci_eg20t_init,
1675 .setup = pci_default_setup,
1676 },
1677 /*
1678 * Cronyx Omega PCI (PLX-chip based)
1679 */
1680 {
1681 .vendor = PCI_VENDOR_ID_PLX,
1682 .device = PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
1683 .subvendor = PCI_ANY_ID,
1684 .subdevice = PCI_ANY_ID,
1685 .setup = pci_omegapci_setup,
1686 },
1687 /*
1688 * Default "match everything" terminator entry
1689 */
1690 {
1691 .vendor = PCI_ANY_ID,
1692 .device = PCI_ANY_ID,
1693 .subvendor = PCI_ANY_ID,
1694 .subdevice = PCI_ANY_ID,
1695 .setup = pci_default_setup,
1696 }
1697};
1698
1699static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
1700{
1701 return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
1702}
1703
1704static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
1705{
1706 struct pci_serial_quirk *quirk;
1707
1708 for (quirk = pci_serial_quirks; ; quirk++)
1709 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
1710 quirk_id_matches(quirk->device, dev->device) &&
1711 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
1712 quirk_id_matches(quirk->subdevice, dev->subsystem_device))
1713 break;
1714 return quirk;
1715}
1716
1717static inline int get_pci_irq(struct pci_dev *dev,
1718 const struct pciserial_board *board)
1719{
1720 if (board->flags & FL_NOIRQ)
1721 return 0;
1722 else
1723 return dev->irq;
1724}
1725
1726/*
1727 * This is the configuration table for all of the PCI serial boards
1728 * which we support. It is directly indexed by the pci_board_num_t enum
1729 * value, which is encoded in the pci_device_id PCI probe table's
1730 * driver_data member.
1731 *
1732 * The makeup of these names are:
1733 * pbn_bn{_bt}_n_baud{_offsetinhex}
1734 *
1735 * bn = PCI BAR number
1736 * bt = Index using PCI BARs
1737 * n = number of serial ports
1738 * baud = baud rate
1739 * offsetinhex = offset for each sequential port (in hex)
1740 *
1741 * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
1742 *
1743 * Please note: in theory if n = 1, _bt infix should make no difference.
1744 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
1745 */
1746enum pci_board_num_t {
1747 pbn_default = 0,
1748
1749 pbn_b0_1_115200,
1750 pbn_b0_2_115200,
1751 pbn_b0_4_115200,
1752 pbn_b0_5_115200,
1753 pbn_b0_8_115200,
1754
1755 pbn_b0_1_921600,
1756 pbn_b0_2_921600,
1757 pbn_b0_4_921600,
1758
1759 pbn_b0_2_1130000,
1760
1761 pbn_b0_4_1152000,
1762
1763 pbn_b0_2_1843200,
1764 pbn_b0_4_1843200,
1765
1766 pbn_b0_2_1843200_200,
1767 pbn_b0_4_1843200_200,
1768 pbn_b0_8_1843200_200,
1769
1770 pbn_b0_1_4000000,
1771
1772 pbn_b0_bt_1_115200,
1773 pbn_b0_bt_2_115200,
1774 pbn_b0_bt_4_115200,
1775 pbn_b0_bt_8_115200,
1776
1777 pbn_b0_bt_1_460800,
1778 pbn_b0_bt_2_460800,
1779 pbn_b0_bt_4_460800,
1780
1781 pbn_b0_bt_1_921600,
1782 pbn_b0_bt_2_921600,
1783 pbn_b0_bt_4_921600,
1784 pbn_b0_bt_8_921600,
1785
1786 pbn_b1_1_115200,
1787 pbn_b1_2_115200,
1788 pbn_b1_4_115200,
1789 pbn_b1_8_115200,
1790 pbn_b1_16_115200,
1791
1792 pbn_b1_1_921600,
1793 pbn_b1_2_921600,
1794 pbn_b1_4_921600,
1795 pbn_b1_8_921600,
1796
1797 pbn_b1_2_1250000,
1798
1799 pbn_b1_bt_1_115200,
1800 pbn_b1_bt_2_115200,
1801 pbn_b1_bt_4_115200,
1802
1803 pbn_b1_bt_2_921600,
1804
1805 pbn_b1_1_1382400,
1806 pbn_b1_2_1382400,
1807 pbn_b1_4_1382400,
1808 pbn_b1_8_1382400,
1809
1810 pbn_b2_1_115200,
1811 pbn_b2_2_115200,
1812 pbn_b2_4_115200,
1813 pbn_b2_8_115200,
1814
1815 pbn_b2_1_460800,
1816 pbn_b2_4_460800,
1817 pbn_b2_8_460800,
1818 pbn_b2_16_460800,
1819
1820 pbn_b2_1_921600,
1821 pbn_b2_4_921600,
1822 pbn_b2_8_921600,
1823
1824 pbn_b2_8_1152000,
1825
1826 pbn_b2_bt_1_115200,
1827 pbn_b2_bt_2_115200,
1828 pbn_b2_bt_4_115200,
1829
1830 pbn_b2_bt_2_921600,
1831 pbn_b2_bt_4_921600,
1832
1833 pbn_b3_2_115200,
1834 pbn_b3_4_115200,
1835 pbn_b3_8_115200,
1836
1837 pbn_b4_bt_2_921600,
1838 pbn_b4_bt_4_921600,
1839 pbn_b4_bt_8_921600,
1840
1841 /*
1842 * Board-specific versions.
1843 */
1844 pbn_panacom,
1845 pbn_panacom2,
1846 pbn_panacom4,
1847 pbn_exsys_4055,
1848 pbn_plx_romulus,
1849 pbn_oxsemi,
1850 pbn_oxsemi_1_4000000,
1851 pbn_oxsemi_2_4000000,
1852 pbn_oxsemi_4_4000000,
1853 pbn_oxsemi_8_4000000,
1854 pbn_intel_i960,
1855 pbn_sgi_ioc3,
1856 pbn_computone_4,
1857 pbn_computone_6,
1858 pbn_computone_8,
1859 pbn_sbsxrsio,
1860 pbn_exar_XR17C152,
1861 pbn_exar_XR17C154,
1862 pbn_exar_XR17C158,
1863 pbn_exar_ibm_saturn,
1864 pbn_pasemi_1682M,
1865 pbn_ni8430_2,
1866 pbn_ni8430_4,
1867 pbn_ni8430_8,
1868 pbn_ni8430_16,
1869 pbn_ADDIDATA_PCIe_1_3906250,
1870 pbn_ADDIDATA_PCIe_2_3906250,
1871 pbn_ADDIDATA_PCIe_4_3906250,
1872 pbn_ADDIDATA_PCIe_8_3906250,
1873 pbn_ce4100_1_115200,
1874 pbn_omegapci,
1875 pbn_NETMOS9900_2s_115200,
1876};
1877
1878/*
1879 * uart_offset - the space between channels
1880 * reg_shift - describes how the UART registers are mapped
1881 * to PCI memory by the card.
1882 * For example IER register on SBS, Inc. PMC-OctPro is located at
1883 * offset 0x10 from the UART base, while UART_IER is defined as 1
1884 * in include/linux/serial_reg.h,
1885 * see first lines of serial_in() and serial_out() in 8250.c
1886*/
1887
1888static struct pciserial_board pci_boards[] __devinitdata = {
1889 [pbn_default] = {
1890 .flags = FL_BASE0,
1891 .num_ports = 1,
1892 .base_baud = 115200,
1893 .uart_offset = 8,
1894 },
1895 [pbn_b0_1_115200] = {
1896 .flags = FL_BASE0,
1897 .num_ports = 1,
1898 .base_baud = 115200,
1899 .uart_offset = 8,
1900 },
1901 [pbn_b0_2_115200] = {
1902 .flags = FL_BASE0,
1903 .num_ports = 2,
1904 .base_baud = 115200,
1905 .uart_offset = 8,
1906 },
1907 [pbn_b0_4_115200] = {
1908 .flags = FL_BASE0,
1909 .num_ports = 4,
1910 .base_baud = 115200,
1911 .uart_offset = 8,
1912 },
1913 [pbn_b0_5_115200] = {
1914 .flags = FL_BASE0,
1915 .num_ports = 5,
1916 .base_baud = 115200,
1917 .uart_offset = 8,
1918 },
1919 [pbn_b0_8_115200] = {
1920 .flags = FL_BASE0,
1921 .num_ports = 8,
1922 .base_baud = 115200,
1923 .uart_offset = 8,
1924 },
1925 [pbn_b0_1_921600] = {
1926 .flags = FL_BASE0,
1927 .num_ports = 1,
1928 .base_baud = 921600,
1929 .uart_offset = 8,
1930 },
1931 [pbn_b0_2_921600] = {
1932 .flags = FL_BASE0,
1933 .num_ports = 2,
1934 .base_baud = 921600,
1935 .uart_offset = 8,
1936 },
1937 [pbn_b0_4_921600] = {
1938 .flags = FL_BASE0,
1939 .num_ports = 4,
1940 .base_baud = 921600,
1941 .uart_offset = 8,
1942 },
1943
1944 [pbn_b0_2_1130000] = {
1945 .flags = FL_BASE0,
1946 .num_ports = 2,
1947 .base_baud = 1130000,
1948 .uart_offset = 8,
1949 },
1950
1951 [pbn_b0_4_1152000] = {
1952 .flags = FL_BASE0,
1953 .num_ports = 4,
1954 .base_baud = 1152000,
1955 .uart_offset = 8,
1956 },
1957
1958 [pbn_b0_2_1843200] = {
1959 .flags = FL_BASE0,
1960 .num_ports = 2,
1961 .base_baud = 1843200,
1962 .uart_offset = 8,
1963 },
1964 [pbn_b0_4_1843200] = {
1965 .flags = FL_BASE0,
1966 .num_ports = 4,
1967 .base_baud = 1843200,
1968 .uart_offset = 8,
1969 },
1970
1971 [pbn_b0_2_1843200_200] = {
1972 .flags = FL_BASE0,
1973 .num_ports = 2,
1974 .base_baud = 1843200,
1975 .uart_offset = 0x200,
1976 },
1977 [pbn_b0_4_1843200_200] = {
1978 .flags = FL_BASE0,
1979 .num_ports = 4,
1980 .base_baud = 1843200,
1981 .uart_offset = 0x200,
1982 },
1983 [pbn_b0_8_1843200_200] = {
1984 .flags = FL_BASE0,
1985 .num_ports = 8,
1986 .base_baud = 1843200,
1987 .uart_offset = 0x200,
1988 },
1989 [pbn_b0_1_4000000] = {
1990 .flags = FL_BASE0,
1991 .num_ports = 1,
1992 .base_baud = 4000000,
1993 .uart_offset = 8,
1994 },
1995
1996 [pbn_b0_bt_1_115200] = {
1997 .flags = FL_BASE0|FL_BASE_BARS,
1998 .num_ports = 1,
1999 .base_baud = 115200,
2000 .uart_offset = 8,
2001 },
2002 [pbn_b0_bt_2_115200] = {
2003 .flags = FL_BASE0|FL_BASE_BARS,
2004 .num_ports = 2,
2005 .base_baud = 115200,
2006 .uart_offset = 8,
2007 },
2008 [pbn_b0_bt_4_115200] = {
2009 .flags = FL_BASE0|FL_BASE_BARS,
2010 .num_ports = 4,
2011 .base_baud = 115200,
2012 .uart_offset = 8,
2013 },
2014 [pbn_b0_bt_8_115200] = {
2015 .flags = FL_BASE0|FL_BASE_BARS,
2016 .num_ports = 8,
2017 .base_baud = 115200,
2018 .uart_offset = 8,
2019 },
2020
2021 [pbn_b0_bt_1_460800] = {
2022 .flags = FL_BASE0|FL_BASE_BARS,
2023 .num_ports = 1,
2024 .base_baud = 460800,
2025 .uart_offset = 8,
2026 },
2027 [pbn_b0_bt_2_460800] = {
2028 .flags = FL_BASE0|FL_BASE_BARS,
2029 .num_ports = 2,
2030 .base_baud = 460800,
2031 .uart_offset = 8,
2032 },
2033 [pbn_b0_bt_4_460800] = {
2034 .flags = FL_BASE0|FL_BASE_BARS,
2035 .num_ports = 4,
2036 .base_baud = 460800,
2037 .uart_offset = 8,
2038 },
2039
2040 [pbn_b0_bt_1_921600] = {
2041 .flags = FL_BASE0|FL_BASE_BARS,
2042 .num_ports = 1,
2043 .base_baud = 921600,
2044 .uart_offset = 8,
2045 },
2046 [pbn_b0_bt_2_921600] = {
2047 .flags = FL_BASE0|FL_BASE_BARS,
2048 .num_ports = 2,
2049 .base_baud = 921600,
2050 .uart_offset = 8,
2051 },
2052 [pbn_b0_bt_4_921600] = {
2053 .flags = FL_BASE0|FL_BASE_BARS,
2054 .num_ports = 4,
2055 .base_baud = 921600,
2056 .uart_offset = 8,
2057 },
2058 [pbn_b0_bt_8_921600] = {
2059 .flags = FL_BASE0|FL_BASE_BARS,
2060 .num_ports = 8,
2061 .base_baud = 921600,
2062 .uart_offset = 8,
2063 },
2064
2065 [pbn_b1_1_115200] = {
2066 .flags = FL_BASE1,
2067 .num_ports = 1,
2068 .base_baud = 115200,
2069 .uart_offset = 8,
2070 },
2071 [pbn_b1_2_115200] = {
2072 .flags = FL_BASE1,
2073 .num_ports = 2,
2074 .base_baud = 115200,
2075 .uart_offset = 8,
2076 },
2077 [pbn_b1_4_115200] = {
2078 .flags = FL_BASE1,
2079 .num_ports = 4,
2080 .base_baud = 115200,
2081 .uart_offset = 8,
2082 },
2083 [pbn_b1_8_115200] = {
2084 .flags = FL_BASE1,
2085 .num_ports = 8,
2086 .base_baud = 115200,
2087 .uart_offset = 8,
2088 },
2089 [pbn_b1_16_115200] = {
2090 .flags = FL_BASE1,
2091 .num_ports = 16,
2092 .base_baud = 115200,
2093 .uart_offset = 8,
2094 },
2095
2096 [pbn_b1_1_921600] = {
2097 .flags = FL_BASE1,
2098 .num_ports = 1,
2099 .base_baud = 921600,
2100 .uart_offset = 8,
2101 },
2102 [pbn_b1_2_921600] = {
2103 .flags = FL_BASE1,
2104 .num_ports = 2,
2105 .base_baud = 921600,
2106 .uart_offset = 8,
2107 },
2108 [pbn_b1_4_921600] = {
2109 .flags = FL_BASE1,
2110 .num_ports = 4,
2111 .base_baud = 921600,
2112 .uart_offset = 8,
2113 },
2114 [pbn_b1_8_921600] = {
2115 .flags = FL_BASE1,
2116 .num_ports = 8,
2117 .base_baud = 921600,
2118 .uart_offset = 8,
2119 },
2120 [pbn_b1_2_1250000] = {
2121 .flags = FL_BASE1,
2122 .num_ports = 2,
2123 .base_baud = 1250000,
2124 .uart_offset = 8,
2125 },
2126
2127 [pbn_b1_bt_1_115200] = {
2128 .flags = FL_BASE1|FL_BASE_BARS,
2129 .num_ports = 1,
2130 .base_baud = 115200,
2131 .uart_offset = 8,
2132 },
2133 [pbn_b1_bt_2_115200] = {
2134 .flags = FL_BASE1|FL_BASE_BARS,
2135 .num_ports = 2,
2136 .base_baud = 115200,
2137 .uart_offset = 8,
2138 },
2139 [pbn_b1_bt_4_115200] = {
2140 .flags = FL_BASE1|FL_BASE_BARS,
2141 .num_ports = 4,
2142 .base_baud = 115200,
2143 .uart_offset = 8,
2144 },
2145
2146 [pbn_b1_bt_2_921600] = {
2147 .flags = FL_BASE1|FL_BASE_BARS,
2148 .num_ports = 2,
2149 .base_baud = 921600,
2150 .uart_offset = 8,
2151 },
2152
2153 [pbn_b1_1_1382400] = {
2154 .flags = FL_BASE1,
2155 .num_ports = 1,
2156 .base_baud = 1382400,
2157 .uart_offset = 8,
2158 },
2159 [pbn_b1_2_1382400] = {
2160 .flags = FL_BASE1,
2161 .num_ports = 2,
2162 .base_baud = 1382400,
2163 .uart_offset = 8,
2164 },
2165 [pbn_b1_4_1382400] = {
2166 .flags = FL_BASE1,
2167 .num_ports = 4,
2168 .base_baud = 1382400,
2169 .uart_offset = 8,
2170 },
2171 [pbn_b1_8_1382400] = {
2172 .flags = FL_BASE1,
2173 .num_ports = 8,
2174 .base_baud = 1382400,
2175 .uart_offset = 8,
2176 },
2177
2178 [pbn_b2_1_115200] = {
2179 .flags = FL_BASE2,
2180 .num_ports = 1,
2181 .base_baud = 115200,
2182 .uart_offset = 8,
2183 },
2184 [pbn_b2_2_115200] = {
2185 .flags = FL_BASE2,
2186 .num_ports = 2,
2187 .base_baud = 115200,
2188 .uart_offset = 8,
2189 },
2190 [pbn_b2_4_115200] = {
2191 .flags = FL_BASE2,
2192 .num_ports = 4,
2193 .base_baud = 115200,
2194 .uart_offset = 8,
2195 },
2196 [pbn_b2_8_115200] = {
2197 .flags = FL_BASE2,
2198 .num_ports = 8,
2199 .base_baud = 115200,
2200 .uart_offset = 8,
2201 },
2202
2203 [pbn_b2_1_460800] = {
2204 .flags = FL_BASE2,
2205 .num_ports = 1,
2206 .base_baud = 460800,
2207 .uart_offset = 8,
2208 },
2209 [pbn_b2_4_460800] = {
2210 .flags = FL_BASE2,
2211 .num_ports = 4,
2212 .base_baud = 460800,
2213 .uart_offset = 8,
2214 },
2215 [pbn_b2_8_460800] = {
2216 .flags = FL_BASE2,
2217 .num_ports = 8,
2218 .base_baud = 460800,
2219 .uart_offset = 8,
2220 },
2221 [pbn_b2_16_460800] = {
2222 .flags = FL_BASE2,
2223 .num_ports = 16,
2224 .base_baud = 460800,
2225 .uart_offset = 8,
2226 },
2227
2228 [pbn_b2_1_921600] = {
2229 .flags = FL_BASE2,
2230 .num_ports = 1,
2231 .base_baud = 921600,
2232 .uart_offset = 8,
2233 },
2234 [pbn_b2_4_921600] = {
2235 .flags = FL_BASE2,
2236 .num_ports = 4,
2237 .base_baud = 921600,
2238 .uart_offset = 8,
2239 },
2240 [pbn_b2_8_921600] = {
2241 .flags = FL_BASE2,
2242 .num_ports = 8,
2243 .base_baud = 921600,
2244 .uart_offset = 8,
2245 },
2246
2247 [pbn_b2_8_1152000] = {
2248 .flags = FL_BASE2,
2249 .num_ports = 8,
2250 .base_baud = 1152000,
2251 .uart_offset = 8,
2252 },
2253
2254 [pbn_b2_bt_1_115200] = {
2255 .flags = FL_BASE2|FL_BASE_BARS,
2256 .num_ports = 1,
2257 .base_baud = 115200,
2258 .uart_offset = 8,
2259 },
2260 [pbn_b2_bt_2_115200] = {
2261 .flags = FL_BASE2|FL_BASE_BARS,
2262 .num_ports = 2,
2263 .base_baud = 115200,
2264 .uart_offset = 8,
2265 },
2266 [pbn_b2_bt_4_115200] = {
2267 .flags = FL_BASE2|FL_BASE_BARS,
2268 .num_ports = 4,
2269 .base_baud = 115200,
2270 .uart_offset = 8,
2271 },
2272
2273 [pbn_b2_bt_2_921600] = {
2274 .flags = FL_BASE2|FL_BASE_BARS,
2275 .num_ports = 2,
2276 .base_baud = 921600,
2277 .uart_offset = 8,
2278 },
2279 [pbn_b2_bt_4_921600] = {
2280 .flags = FL_BASE2|FL_BASE_BARS,
2281 .num_ports = 4,
2282 .base_baud = 921600,
2283 .uart_offset = 8,
2284 },
2285
2286 [pbn_b3_2_115200] = {
2287 .flags = FL_BASE3,
2288 .num_ports = 2,
2289 .base_baud = 115200,
2290 .uart_offset = 8,
2291 },
2292 [pbn_b3_4_115200] = {
2293 .flags = FL_BASE3,
2294 .num_ports = 4,
2295 .base_baud = 115200,
2296 .uart_offset = 8,
2297 },
2298 [pbn_b3_8_115200] = {
2299 .flags = FL_BASE3,
2300 .num_ports = 8,
2301 .base_baud = 115200,
2302 .uart_offset = 8,
2303 },
2304
2305 [pbn_b4_bt_2_921600] = {
2306 .flags = FL_BASE4,
2307 .num_ports = 2,
2308 .base_baud = 921600,
2309 .uart_offset = 8,
2310 },
2311 [pbn_b4_bt_4_921600] = {
2312 .flags = FL_BASE4,
2313 .num_ports = 4,
2314 .base_baud = 921600,
2315 .uart_offset = 8,
2316 },
2317 [pbn_b4_bt_8_921600] = {
2318 .flags = FL_BASE4,
2319 .num_ports = 8,
2320 .base_baud = 921600,
2321 .uart_offset = 8,
2322 },
2323
2324 /*
2325 * Entries following this are board-specific.
2326 */
2327
2328 /*
2329 * Panacom - IOMEM
2330 */
2331 [pbn_panacom] = {
2332 .flags = FL_BASE2,
2333 .num_ports = 2,
2334 .base_baud = 921600,
2335 .uart_offset = 0x400,
2336 .reg_shift = 7,
2337 },
2338 [pbn_panacom2] = {
2339 .flags = FL_BASE2|FL_BASE_BARS,
2340 .num_ports = 2,
2341 .base_baud = 921600,
2342 .uart_offset = 0x400,
2343 .reg_shift = 7,
2344 },
2345 [pbn_panacom4] = {
2346 .flags = FL_BASE2|FL_BASE_BARS,
2347 .num_ports = 4,
2348 .base_baud = 921600,
2349 .uart_offset = 0x400,
2350 .reg_shift = 7,
2351 },
2352
2353 [pbn_exsys_4055] = {
2354 .flags = FL_BASE2,
2355 .num_ports = 4,
2356 .base_baud = 115200,
2357 .uart_offset = 8,
2358 },
2359
2360 /* I think this entry is broken - the first_offset looks wrong --rmk */
2361 [pbn_plx_romulus] = {
2362 .flags = FL_BASE2,
2363 .num_ports = 4,
2364 .base_baud = 921600,
2365 .uart_offset = 8 << 2,
2366 .reg_shift = 2,
2367 .first_offset = 0x03,
2368 },
2369
2370 /*
2371 * This board uses the size of PCI Base region 0 to
2372 * signal now many ports are available
2373 */
2374 [pbn_oxsemi] = {
2375 .flags = FL_BASE0|FL_REGION_SZ_CAP,
2376 .num_ports = 32,
2377 .base_baud = 115200,
2378 .uart_offset = 8,
2379 },
2380 [pbn_oxsemi_1_4000000] = {
2381 .flags = FL_BASE0,
2382 .num_ports = 1,
2383 .base_baud = 4000000,
2384 .uart_offset = 0x200,
2385 .first_offset = 0x1000,
2386 },
2387 [pbn_oxsemi_2_4000000] = {
2388 .flags = FL_BASE0,
2389 .num_ports = 2,
2390 .base_baud = 4000000,
2391 .uart_offset = 0x200,
2392 .first_offset = 0x1000,
2393 },
2394 [pbn_oxsemi_4_4000000] = {
2395 .flags = FL_BASE0,
2396 .num_ports = 4,
2397 .base_baud = 4000000,
2398 .uart_offset = 0x200,
2399 .first_offset = 0x1000,
2400 },
2401 [pbn_oxsemi_8_4000000] = {
2402 .flags = FL_BASE0,
2403 .num_ports = 8,
2404 .base_baud = 4000000,
2405 .uart_offset = 0x200,
2406 .first_offset = 0x1000,
2407 },
2408
2409
2410 /*
2411 * EKF addition for i960 Boards form EKF with serial port.
2412 * Max 256 ports.
2413 */
2414 [pbn_intel_i960] = {
2415 .flags = FL_BASE0,
2416 .num_ports = 32,
2417 .base_baud = 921600,
2418 .uart_offset = 8 << 2,
2419 .reg_shift = 2,
2420 .first_offset = 0x10000,
2421 },
2422 [pbn_sgi_ioc3] = {
2423 .flags = FL_BASE0|FL_NOIRQ,
2424 .num_ports = 1,
2425 .base_baud = 458333,
2426 .uart_offset = 8,
2427 .reg_shift = 0,
2428 .first_offset = 0x20178,
2429 },
2430
2431 /*
2432 * Computone - uses IOMEM.
2433 */
2434 [pbn_computone_4] = {
2435 .flags = FL_BASE0,
2436 .num_ports = 4,
2437 .base_baud = 921600,
2438 .uart_offset = 0x40,
2439 .reg_shift = 2,
2440 .first_offset = 0x200,
2441 },
2442 [pbn_computone_6] = {
2443 .flags = FL_BASE0,
2444 .num_ports = 6,
2445 .base_baud = 921600,
2446 .uart_offset = 0x40,
2447 .reg_shift = 2,
2448 .first_offset = 0x200,
2449 },
2450 [pbn_computone_8] = {
2451 .flags = FL_BASE0,
2452 .num_ports = 8,
2453 .base_baud = 921600,
2454 .uart_offset = 0x40,
2455 .reg_shift = 2,
2456 .first_offset = 0x200,
2457 },
2458 [pbn_sbsxrsio] = {
2459 .flags = FL_BASE0,
2460 .num_ports = 8,
2461 .base_baud = 460800,
2462 .uart_offset = 256,
2463 .reg_shift = 4,
2464 },
2465 /*
2466 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
2467 * Only basic 16550A support.
2468 * XR17C15[24] are not tested, but they should work.
2469 */
2470 [pbn_exar_XR17C152] = {
2471 .flags = FL_BASE0,
2472 .num_ports = 2,
2473 .base_baud = 921600,
2474 .uart_offset = 0x200,
2475 },
2476 [pbn_exar_XR17C154] = {
2477 .flags = FL_BASE0,
2478 .num_ports = 4,
2479 .base_baud = 921600,
2480 .uart_offset = 0x200,
2481 },
2482 [pbn_exar_XR17C158] = {
2483 .flags = FL_BASE0,
2484 .num_ports = 8,
2485 .base_baud = 921600,
2486 .uart_offset = 0x200,
2487 },
2488 [pbn_exar_ibm_saturn] = {
2489 .flags = FL_BASE0,
2490 .num_ports = 1,
2491 .base_baud = 921600,
2492 .uart_offset = 0x200,
2493 },
2494
2495 /*
2496 * PA Semi PWRficient PA6T-1682M on-chip UART
2497 */
2498 [pbn_pasemi_1682M] = {
2499 .flags = FL_BASE0,
2500 .num_ports = 1,
2501 .base_baud = 8333333,
2502 },
2503 /*
2504 * National Instruments 843x
2505 */
2506 [pbn_ni8430_16] = {
2507 .flags = FL_BASE0,
2508 .num_ports = 16,
2509 .base_baud = 3686400,
2510 .uart_offset = 0x10,
2511 .first_offset = 0x800,
2512 },
2513 [pbn_ni8430_8] = {
2514 .flags = FL_BASE0,
2515 .num_ports = 8,
2516 .base_baud = 3686400,
2517 .uart_offset = 0x10,
2518 .first_offset = 0x800,
2519 },
2520 [pbn_ni8430_4] = {
2521 .flags = FL_BASE0,
2522 .num_ports = 4,
2523 .base_baud = 3686400,
2524 .uart_offset = 0x10,
2525 .first_offset = 0x800,
2526 },
2527 [pbn_ni8430_2] = {
2528 .flags = FL_BASE0,
2529 .num_ports = 2,
2530 .base_baud = 3686400,
2531 .uart_offset = 0x10,
2532 .first_offset = 0x800,
2533 },
2534 /*
2535 * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com>
2536 */
2537 [pbn_ADDIDATA_PCIe_1_3906250] = {
2538 .flags = FL_BASE0,
2539 .num_ports = 1,
2540 .base_baud = 3906250,
2541 .uart_offset = 0x200,
2542 .first_offset = 0x1000,
2543 },
2544 [pbn_ADDIDATA_PCIe_2_3906250] = {
2545 .flags = FL_BASE0,
2546 .num_ports = 2,
2547 .base_baud = 3906250,
2548 .uart_offset = 0x200,
2549 .first_offset = 0x1000,
2550 },
2551 [pbn_ADDIDATA_PCIe_4_3906250] = {
2552 .flags = FL_BASE0,
2553 .num_ports = 4,
2554 .base_baud = 3906250,
2555 .uart_offset = 0x200,
2556 .first_offset = 0x1000,
2557 },
2558 [pbn_ADDIDATA_PCIe_8_3906250] = {
2559 .flags = FL_BASE0,
2560 .num_ports = 8,
2561 .base_baud = 3906250,
2562 .uart_offset = 0x200,
2563 .first_offset = 0x1000,
2564 },
2565 [pbn_ce4100_1_115200] = {
2566 .flags = FL_BASE0,
2567 .num_ports = 1,
2568 .base_baud = 921600,
2569 .reg_shift = 2,
2570 },
2571 [pbn_omegapci] = {
2572 .flags = FL_BASE0,
2573 .num_ports = 8,
2574 .base_baud = 115200,
2575 .uart_offset = 0x200,
2576 },
2577 [pbn_NETMOS9900_2s_115200] = {
2578 .flags = FL_BASE0,
2579 .num_ports = 2,
2580 .base_baud = 115200,
2581 },
2582};
2583
2584static const struct pci_device_id softmodem_blacklist[] = {
2585 { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
2586 { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */
2587 { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */
2588};
2589
2590/*
2591 * Given a complete unknown PCI device, try to use some heuristics to
2592 * guess what the configuration might be, based on the pitiful PCI
2593 * serial specs. Returns 0 on success, 1 on failure.
2594 */
2595static int __devinit
2596serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
2597{
2598 const struct pci_device_id *blacklist;
2599 int num_iomem, num_port, first_port = -1, i;
2600
2601 /*
2602 * If it is not a communications device or the programming
2603 * interface is greater than 6, give up.
2604 *
2605 * (Should we try to make guesses for multiport serial devices
2606 * later?)
2607 */
2608 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
2609 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
2610 (dev->class & 0xff) > 6)
2611 return -ENODEV;
2612
2613 /*
2614 * Do not access blacklisted devices that are known not to
2615 * feature serial ports.
2616 */
2617 for (blacklist = softmodem_blacklist;
2618 blacklist < softmodem_blacklist + ARRAY_SIZE(softmodem_blacklist);
2619 blacklist++) {
2620 if (dev->vendor == blacklist->vendor &&
2621 dev->device == blacklist->device)
2622 return -ENODEV;
2623 }
2624
2625 num_iomem = num_port = 0;
2626 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2627 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
2628 num_port++;
2629 if (first_port == -1)
2630 first_port = i;
2631 }
2632 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
2633 num_iomem++;
2634 }
2635
2636 /*
2637 * If there is 1 or 0 iomem regions, and exactly one port,
2638 * use it. We guess the number of ports based on the IO
2639 * region size.
2640 */
2641 if (num_iomem <= 1 && num_port == 1) {
2642 board->flags = first_port;
2643 board->num_ports = pci_resource_len(dev, first_port) / 8;
2644 return 0;
2645 }
2646
2647 /*
2648 * Now guess if we've got a board which indexes by BARs.
2649 * Each IO BAR should be 8 bytes, and they should follow
2650 * consecutively.
2651 */
2652 first_port = -1;
2653 num_port = 0;
2654 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2655 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
2656 pci_resource_len(dev, i) == 8 &&
2657 (first_port == -1 || (first_port + num_port) == i)) {
2658 num_port++;
2659 if (first_port == -1)
2660 first_port = i;
2661 }
2662 }
2663
2664 if (num_port > 1) {
2665 board->flags = first_port | FL_BASE_BARS;
2666 board->num_ports = num_port;
2667 return 0;
2668 }
2669
2670 return -ENODEV;
2671}
2672
2673static inline int
2674serial_pci_matches(const struct pciserial_board *board,
2675 const struct pciserial_board *guessed)
2676{
2677 return
2678 board->num_ports == guessed->num_ports &&
2679 board->base_baud == guessed->base_baud &&
2680 board->uart_offset == guessed->uart_offset &&
2681 board->reg_shift == guessed->reg_shift &&
2682 board->first_offset == guessed->first_offset;
2683}
2684
2685struct serial_private *
2686pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
2687{
2688 struct uart_port serial_port;
2689 struct serial_private *priv;
2690 struct pci_serial_quirk *quirk;
2691 int rc, nr_ports, i;
2692
2693 nr_ports = board->num_ports;
2694
2695 /*
2696 * Find an init and setup quirks.
2697 */
2698 quirk = find_quirk(dev);
2699
2700 /*
2701 * Run the new-style initialization function.
2702 * The initialization function returns:
2703 * <0 - error
2704 * 0 - use board->num_ports
2705 * >0 - number of ports
2706 */
2707 if (quirk->init) {
2708 rc = quirk->init(dev);
2709 if (rc < 0) {
2710 priv = ERR_PTR(rc);
2711 goto err_out;
2712 }
2713 if (rc)
2714 nr_ports = rc;
2715 }
2716
2717 priv = kzalloc(sizeof(struct serial_private) +
2718 sizeof(unsigned int) * nr_ports,
2719 GFP_KERNEL);
2720 if (!priv) {
2721 priv = ERR_PTR(-ENOMEM);
2722 goto err_deinit;
2723 }
2724
2725 priv->dev = dev;
2726 priv->quirk = quirk;
2727
2728 memset(&serial_port, 0, sizeof(struct uart_port));
2729 serial_port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
2730 serial_port.uartclk = board->base_baud * 16;
2731 serial_port.irq = get_pci_irq(dev, board);
2732 serial_port.dev = &dev->dev;
2733
2734 for (i = 0; i < nr_ports; i++) {
2735 if (quirk->setup(priv, board, &serial_port, i))
2736 break;
2737
2738#ifdef SERIAL_DEBUG_PCI
2739 printk(KERN_DEBUG "Setup PCI port: port %lx, irq %d, type %d\n",
2740 serial_port.iobase, serial_port.irq, serial_port.iotype);
2741#endif
2742
2743 priv->line[i] = serial8250_register_port(&serial_port);
2744 if (priv->line[i] < 0) {
2745 printk(KERN_WARNING "Couldn't register serial port %s: %d\n", pci_name(dev), priv->line[i]);
2746 break;
2747 }
2748 }
2749 priv->nr = i;
2750 return priv;
2751
2752err_deinit:
2753 if (quirk->exit)
2754 quirk->exit(dev);
2755err_out:
2756 return priv;
2757}
2758EXPORT_SYMBOL_GPL(pciserial_init_ports);
2759
2760void pciserial_remove_ports(struct serial_private *priv)
2761{
2762 struct pci_serial_quirk *quirk;
2763 int i;
2764
2765 for (i = 0; i < priv->nr; i++)
2766 serial8250_unregister_port(priv->line[i]);
2767
2768 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2769 if (priv->remapped_bar[i])
2770 iounmap(priv->remapped_bar[i]);
2771 priv->remapped_bar[i] = NULL;
2772 }
2773
2774 /*
2775 * Find the exit quirks.
2776 */
2777 quirk = find_quirk(priv->dev);
2778 if (quirk->exit)
2779 quirk->exit(priv->dev);
2780
2781 kfree(priv);
2782}
2783EXPORT_SYMBOL_GPL(pciserial_remove_ports);
2784
2785void pciserial_suspend_ports(struct serial_private *priv)
2786{
2787 int i;
2788
2789 for (i = 0; i < priv->nr; i++)
2790 if (priv->line[i] >= 0)
2791 serial8250_suspend_port(priv->line[i]);
2792}
2793EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
2794
2795void pciserial_resume_ports(struct serial_private *priv)
2796{
2797 int i;
2798
2799 /*
2800 * Ensure that the board is correctly configured.
2801 */
2802 if (priv->quirk->init)
2803 priv->quirk->init(priv->dev);
2804
2805 for (i = 0; i < priv->nr; i++)
2806 if (priv->line[i] >= 0)
2807 serial8250_resume_port(priv->line[i]);
2808}
2809EXPORT_SYMBOL_GPL(pciserial_resume_ports);
2810
2811/*
2812 * Probe one serial board. Unfortunately, there is no rhyme nor reason
2813 * to the arrangement of serial ports on a PCI card.
2814 */
2815static int __devinit
2816pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
2817{
2818 struct pci_serial_quirk *quirk;
2819 struct serial_private *priv;
2820 const struct pciserial_board *board;
2821 struct pciserial_board tmp;
2822 int rc;
2823
2824 quirk = find_quirk(dev);
2825 if (quirk->probe) {
2826 rc = quirk->probe(dev);
2827 if (rc)
2828 return rc;
2829 }
2830
2831 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
2832 printk(KERN_ERR "pci_init_one: invalid driver_data: %ld\n",
2833 ent->driver_data);
2834 return -EINVAL;
2835 }
2836
2837 board = &pci_boards[ent->driver_data];
2838
2839 rc = pci_enable_device(dev);
2840 pci_save_state(dev);
2841 if (rc)
2842 return rc;
2843
2844 if (ent->driver_data == pbn_default) {
2845 /*
2846 * Use a copy of the pci_board entry for this;
2847 * avoid changing entries in the table.
2848 */
2849 memcpy(&tmp, board, sizeof(struct pciserial_board));
2850 board = &tmp;
2851
2852 /*
2853 * We matched one of our class entries. Try to
2854 * determine the parameters of this board.
2855 */
2856 rc = serial_pci_guess_board(dev, &tmp);
2857 if (rc)
2858 goto disable;
2859 } else {
2860 /*
2861 * We matched an explicit entry. If we are able to
2862 * detect this boards settings with our heuristic,
2863 * then we no longer need this entry.
2864 */
2865 memcpy(&tmp, &pci_boards[pbn_default],
2866 sizeof(struct pciserial_board));
2867 rc = serial_pci_guess_board(dev, &tmp);
2868 if (rc == 0 && serial_pci_matches(board, &tmp))
2869 moan_device("Redundant entry in serial pci_table.",
2870 dev);
2871 }
2872
2873 priv = pciserial_init_ports(dev, board);
2874 if (!IS_ERR(priv)) {
2875 pci_set_drvdata(dev, priv);
2876 return 0;
2877 }
2878
2879 rc = PTR_ERR(priv);
2880
2881 disable:
2882 pci_disable_device(dev);
2883 return rc;
2884}
2885
2886static void __devexit pciserial_remove_one(struct pci_dev *dev)
2887{
2888 struct serial_private *priv = pci_get_drvdata(dev);
2889
2890 pci_set_drvdata(dev, NULL);
2891
2892 pciserial_remove_ports(priv);
2893
2894 pci_disable_device(dev);
2895}
2896
2897#ifdef CONFIG_PM
2898static int pciserial_suspend_one(struct pci_dev *dev, pm_message_t state)
2899{
2900 struct serial_private *priv = pci_get_drvdata(dev);
2901
2902 if (priv)
2903 pciserial_suspend_ports(priv);
2904
2905 pci_save_state(dev);
2906 pci_set_power_state(dev, pci_choose_state(dev, state));
2907 return 0;
2908}
2909
2910static int pciserial_resume_one(struct pci_dev *dev)
2911{
2912 int err;
2913 struct serial_private *priv = pci_get_drvdata(dev);
2914
2915 pci_set_power_state(dev, PCI_D0);
2916 pci_restore_state(dev);
2917
2918 if (priv) {
2919 /*
2920 * The device may have been disabled. Re-enable it.
2921 */
2922 err = pci_enable_device(dev);
2923 /* FIXME: We cannot simply error out here */
2924 if (err)
2925 printk(KERN_ERR "pciserial: Unable to re-enable ports, trying to continue.\n");
2926 pciserial_resume_ports(priv);
2927 }
2928 return 0;
2929}
2930#endif
2931
2932static struct pci_device_id serial_pci_tbl[] = {
2933 /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
2934 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
2935 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
2936 pbn_b2_8_921600 },
2937 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2938 PCI_SUBVENDOR_ID_CONNECT_TECH,
2939 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
2940 pbn_b1_8_1382400 },
2941 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2942 PCI_SUBVENDOR_ID_CONNECT_TECH,
2943 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
2944 pbn_b1_4_1382400 },
2945 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2946 PCI_SUBVENDOR_ID_CONNECT_TECH,
2947 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
2948 pbn_b1_2_1382400 },
2949 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2950 PCI_SUBVENDOR_ID_CONNECT_TECH,
2951 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
2952 pbn_b1_8_1382400 },
2953 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2954 PCI_SUBVENDOR_ID_CONNECT_TECH,
2955 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
2956 pbn_b1_4_1382400 },
2957 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2958 PCI_SUBVENDOR_ID_CONNECT_TECH,
2959 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
2960 pbn_b1_2_1382400 },
2961 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2962 PCI_SUBVENDOR_ID_CONNECT_TECH,
2963 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
2964 pbn_b1_8_921600 },
2965 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2966 PCI_SUBVENDOR_ID_CONNECT_TECH,
2967 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
2968 pbn_b1_8_921600 },
2969 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2970 PCI_SUBVENDOR_ID_CONNECT_TECH,
2971 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
2972 pbn_b1_4_921600 },
2973 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2974 PCI_SUBVENDOR_ID_CONNECT_TECH,
2975 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
2976 pbn_b1_4_921600 },
2977 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2978 PCI_SUBVENDOR_ID_CONNECT_TECH,
2979 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
2980 pbn_b1_2_921600 },
2981 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2982 PCI_SUBVENDOR_ID_CONNECT_TECH,
2983 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
2984 pbn_b1_8_921600 },
2985 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2986 PCI_SUBVENDOR_ID_CONNECT_TECH,
2987 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
2988 pbn_b1_8_921600 },
2989 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2990 PCI_SUBVENDOR_ID_CONNECT_TECH,
2991 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
2992 pbn_b1_4_921600 },
2993 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2994 PCI_SUBVENDOR_ID_CONNECT_TECH,
2995 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
2996 pbn_b1_2_1250000 },
2997 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2998 PCI_SUBVENDOR_ID_CONNECT_TECH,
2999 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
3000 pbn_b0_2_1843200 },
3001 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3002 PCI_SUBVENDOR_ID_CONNECT_TECH,
3003 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
3004 pbn_b0_4_1843200 },
3005 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3006 PCI_VENDOR_ID_AFAVLAB,
3007 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
3008 pbn_b0_4_1152000 },
3009 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3010 PCI_SUBVENDOR_ID_CONNECT_TECH,
3011 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
3012 pbn_b0_2_1843200_200 },
3013 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3014 PCI_SUBVENDOR_ID_CONNECT_TECH,
3015 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
3016 pbn_b0_4_1843200_200 },
3017 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3018 PCI_SUBVENDOR_ID_CONNECT_TECH,
3019 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
3020 pbn_b0_8_1843200_200 },
3021 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3022 PCI_SUBVENDOR_ID_CONNECT_TECH,
3023 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
3024 pbn_b0_2_1843200_200 },
3025 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3026 PCI_SUBVENDOR_ID_CONNECT_TECH,
3027 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
3028 pbn_b0_4_1843200_200 },
3029 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3030 PCI_SUBVENDOR_ID_CONNECT_TECH,
3031 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
3032 pbn_b0_8_1843200_200 },
3033 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3034 PCI_SUBVENDOR_ID_CONNECT_TECH,
3035 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
3036 pbn_b0_2_1843200_200 },
3037 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3038 PCI_SUBVENDOR_ID_CONNECT_TECH,
3039 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
3040 pbn_b0_4_1843200_200 },
3041 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3042 PCI_SUBVENDOR_ID_CONNECT_TECH,
3043 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
3044 pbn_b0_8_1843200_200 },
3045 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3046 PCI_SUBVENDOR_ID_CONNECT_TECH,
3047 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
3048 pbn_b0_2_1843200_200 },
3049 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3050 PCI_SUBVENDOR_ID_CONNECT_TECH,
3051 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
3052 pbn_b0_4_1843200_200 },
3053 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3054 PCI_SUBVENDOR_ID_CONNECT_TECH,
3055 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
3056 pbn_b0_8_1843200_200 },
3057 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3058 PCI_VENDOR_ID_IBM, PCI_SUBDEVICE_ID_IBM_SATURN_SERIAL_ONE_PORT,
3059 0, 0, pbn_exar_ibm_saturn },
3060
3061 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
3062 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3063 pbn_b2_bt_1_115200 },
3064 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
3065 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3066 pbn_b2_bt_2_115200 },
3067 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
3068 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3069 pbn_b2_bt_4_115200 },
3070 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
3071 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3072 pbn_b2_bt_2_115200 },
3073 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
3074 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3075 pbn_b2_bt_4_115200 },
3076 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
3077 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3078 pbn_b2_8_115200 },
3079 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
3080 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3081 pbn_b2_8_460800 },
3082 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
3083 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3084 pbn_b2_8_115200 },
3085
3086 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
3087 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3088 pbn_b2_bt_2_115200 },
3089 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
3090 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3091 pbn_b2_bt_2_921600 },
3092 /*
3093 * VScom SPCOM800, from sl@s.pl
3094 */
3095 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
3096 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3097 pbn_b2_8_921600 },
3098 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
3099 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3100 pbn_b2_4_921600 },
3101 /* Unknown card - subdevice 0x1584 */
3102 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3103 PCI_VENDOR_ID_PLX,
3104 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
3105 pbn_b0_4_115200 },
3106 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3107 PCI_SUBVENDOR_ID_KEYSPAN,
3108 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
3109 pbn_panacom },
3110 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
3111 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3112 pbn_panacom4 },
3113 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
3114 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3115 pbn_panacom2 },
3116 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
3117 PCI_VENDOR_ID_ESDGMBH,
3118 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
3119 pbn_b2_4_115200 },
3120 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3121 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
3122 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
3123 pbn_b2_4_460800 },
3124 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3125 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
3126 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
3127 pbn_b2_8_460800 },
3128 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3129 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
3130 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
3131 pbn_b2_16_460800 },
3132 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3133 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
3134 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
3135 pbn_b2_16_460800 },
3136 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3137 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
3138 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
3139 pbn_b2_4_460800 },
3140 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3141 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
3142 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
3143 pbn_b2_8_460800 },
3144 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3145 PCI_SUBVENDOR_ID_EXSYS,
3146 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
3147 pbn_exsys_4055 },
3148 /*
3149 * Megawolf Romulus PCI Serial Card, from Mike Hudson
3150 * (Exoray@isys.ca)
3151 */
3152 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
3153 0x10b5, 0x106a, 0, 0,
3154 pbn_plx_romulus },
3155 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
3156 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3157 pbn_b1_4_115200 },
3158 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
3159 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3160 pbn_b1_2_115200 },
3161 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
3162 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3163 pbn_b1_8_115200 },
3164 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
3165 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3166 pbn_b1_8_115200 },
3167 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
3168 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
3169 0, 0,
3170 pbn_b0_4_921600 },
3171 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3172 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
3173 0, 0,
3174 pbn_b0_4_1152000 },
3175 { PCI_VENDOR_ID_OXSEMI, 0x9505,
3176 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3177 pbn_b0_bt_2_921600 },
3178
3179 /*
3180 * The below card is a little controversial since it is the
3181 * subject of a PCI vendor/device ID clash. (See
3182 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
3183 * For now just used the hex ID 0x950a.
3184 */
3185 { PCI_VENDOR_ID_OXSEMI, 0x950a,
3186 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_SERIAL, 0, 0,
3187 pbn_b0_2_115200 },
3188 { PCI_VENDOR_ID_OXSEMI, 0x950a,
3189 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3190 pbn_b0_2_1130000 },
3191 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950,
3192 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0,
3193 pbn_b0_1_921600 },
3194 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3195 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3196 pbn_b0_4_115200 },
3197 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
3198 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3199 pbn_b0_bt_2_921600 },
3200 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958,
3201 PCI_ANY_ID , PCI_ANY_ID, 0, 0,
3202 pbn_b2_8_1152000 },
3203
3204 /*
3205 * Oxford Semiconductor Inc. Tornado PCI express device range.
3206 */
3207 { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */
3208 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3209 pbn_b0_1_4000000 },
3210 { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */
3211 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3212 pbn_b0_1_4000000 },
3213 { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */
3214 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3215 pbn_oxsemi_1_4000000 },
3216 { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */
3217 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3218 pbn_oxsemi_1_4000000 },
3219 { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */
3220 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3221 pbn_b0_1_4000000 },
3222 { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */
3223 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3224 pbn_b0_1_4000000 },
3225 { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */
3226 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3227 pbn_oxsemi_1_4000000 },
3228 { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */
3229 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3230 pbn_oxsemi_1_4000000 },
3231 { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */
3232 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3233 pbn_b0_1_4000000 },
3234 { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */
3235 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3236 pbn_b0_1_4000000 },
3237 { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */
3238 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3239 pbn_b0_1_4000000 },
3240 { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */
3241 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3242 pbn_b0_1_4000000 },
3243 { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */
3244 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3245 pbn_oxsemi_2_4000000 },
3246 { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */
3247 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3248 pbn_oxsemi_2_4000000 },
3249 { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */
3250 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3251 pbn_oxsemi_4_4000000 },
3252 { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */
3253 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3254 pbn_oxsemi_4_4000000 },
3255 { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */
3256 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3257 pbn_oxsemi_8_4000000 },
3258 { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */
3259 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3260 pbn_oxsemi_8_4000000 },
3261 { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */
3262 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3263 pbn_oxsemi_1_4000000 },
3264 { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */
3265 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3266 pbn_oxsemi_1_4000000 },
3267 { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */
3268 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3269 pbn_oxsemi_1_4000000 },
3270 { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */
3271 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3272 pbn_oxsemi_1_4000000 },
3273 { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */
3274 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3275 pbn_oxsemi_1_4000000 },
3276 { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */
3277 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3278 pbn_oxsemi_1_4000000 },
3279 { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */
3280 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3281 pbn_oxsemi_1_4000000 },
3282 { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */
3283 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3284 pbn_oxsemi_1_4000000 },
3285 { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */
3286 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3287 pbn_oxsemi_1_4000000 },
3288 { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */
3289 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3290 pbn_oxsemi_1_4000000 },
3291 { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */
3292 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3293 pbn_oxsemi_1_4000000 },
3294 { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */
3295 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3296 pbn_oxsemi_1_4000000 },
3297 { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */
3298 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3299 pbn_oxsemi_1_4000000 },
3300 { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */
3301 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3302 pbn_oxsemi_1_4000000 },
3303 { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */
3304 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3305 pbn_oxsemi_1_4000000 },
3306 { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */
3307 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3308 pbn_oxsemi_1_4000000 },
3309 { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */
3310 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3311 pbn_oxsemi_1_4000000 },
3312 { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */
3313 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3314 pbn_oxsemi_1_4000000 },
3315 { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */
3316 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3317 pbn_oxsemi_1_4000000 },
3318 { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */
3319 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3320 pbn_oxsemi_1_4000000 },
3321 { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */
3322 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3323 pbn_oxsemi_1_4000000 },
3324 { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */
3325 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3326 pbn_oxsemi_1_4000000 },
3327 { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */
3328 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3329 pbn_oxsemi_1_4000000 },
3330 { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */
3331 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3332 pbn_oxsemi_1_4000000 },
3333 { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */
3334 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3335 pbn_oxsemi_1_4000000 },
3336 { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */
3337 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3338 pbn_oxsemi_1_4000000 },
3339 /*
3340 * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
3341 */
3342 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
3343 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
3344 pbn_oxsemi_1_4000000 },
3345 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
3346 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
3347 pbn_oxsemi_2_4000000 },
3348 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
3349 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
3350 pbn_oxsemi_4_4000000 },
3351 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
3352 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
3353 pbn_oxsemi_8_4000000 },
3354
3355 /*
3356 * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado
3357 */
3358 { PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM,
3359 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0,
3360 pbn_oxsemi_2_4000000 },
3361
3362 /*
3363 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
3364 * from skokodyn@yahoo.com
3365 */
3366 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3367 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
3368 pbn_sbsxrsio },
3369 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3370 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
3371 pbn_sbsxrsio },
3372 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3373 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
3374 pbn_sbsxrsio },
3375 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3376 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
3377 pbn_sbsxrsio },
3378
3379 /*
3380 * Digitan DS560-558, from jimd@esoft.com
3381 */
3382 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
3383 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3384 pbn_b1_1_115200 },
3385
3386 /*
3387 * Titan Electronic cards
3388 * The 400L and 800L have a custom setup quirk.
3389 */
3390 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
3391 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3392 pbn_b0_1_921600 },
3393 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
3394 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3395 pbn_b0_2_921600 },
3396 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
3397 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3398 pbn_b0_4_921600 },
3399 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
3400 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3401 pbn_b0_4_921600 },
3402 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
3403 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3404 pbn_b1_1_921600 },
3405 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
3406 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3407 pbn_b1_bt_2_921600 },
3408 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
3409 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3410 pbn_b0_bt_4_921600 },
3411 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
3412 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3413 pbn_b0_bt_8_921600 },
3414 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I,
3415 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3416 pbn_b4_bt_2_921600 },
3417 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I,
3418 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3419 pbn_b4_bt_4_921600 },
3420 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I,
3421 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3422 pbn_b4_bt_8_921600 },
3423 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH,
3424 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3425 pbn_b0_4_921600 },
3426 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH,
3427 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3428 pbn_b0_4_921600 },
3429 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB,
3430 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3431 pbn_b0_4_921600 },
3432 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E,
3433 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3434 pbn_oxsemi_1_4000000 },
3435 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E,
3436 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3437 pbn_oxsemi_2_4000000 },
3438 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E,
3439 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3440 pbn_oxsemi_4_4000000 },
3441 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E,
3442 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3443 pbn_oxsemi_8_4000000 },
3444 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI,
3445 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3446 pbn_oxsemi_2_4000000 },
3447 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI,
3448 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3449 pbn_oxsemi_2_4000000 },
3450 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3,
3451 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3452 pbn_b0_4_921600 },
3453 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3,
3454 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3455 pbn_b0_4_921600 },
3456 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3,
3457 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3458 pbn_b0_4_921600 },
3459 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B,
3460 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3461 pbn_b0_4_921600 },
3462
3463 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
3464 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3465 pbn_b2_1_460800 },
3466 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
3467 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3468 pbn_b2_1_460800 },
3469 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
3470 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3471 pbn_b2_1_460800 },
3472 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
3473 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3474 pbn_b2_bt_2_921600 },
3475 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
3476 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3477 pbn_b2_bt_2_921600 },
3478 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
3479 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3480 pbn_b2_bt_2_921600 },
3481 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
3482 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3483 pbn_b2_bt_4_921600 },
3484 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
3485 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3486 pbn_b2_bt_4_921600 },
3487 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
3488 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3489 pbn_b2_bt_4_921600 },
3490 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
3491 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3492 pbn_b0_1_921600 },
3493 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
3494 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3495 pbn_b0_1_921600 },
3496 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
3497 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3498 pbn_b0_1_921600 },
3499 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
3500 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3501 pbn_b0_bt_2_921600 },
3502 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
3503 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3504 pbn_b0_bt_2_921600 },
3505 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
3506 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3507 pbn_b0_bt_2_921600 },
3508 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
3509 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3510 pbn_b0_bt_4_921600 },
3511 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
3512 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3513 pbn_b0_bt_4_921600 },
3514 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
3515 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3516 pbn_b0_bt_4_921600 },
3517 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
3518 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3519 pbn_b0_bt_8_921600 },
3520 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
3521 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3522 pbn_b0_bt_8_921600 },
3523 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
3524 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3525 pbn_b0_bt_8_921600 },
3526
3527 /*
3528 * Computone devices submitted by Doug McNash dmcnash@computone.com
3529 */
3530 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
3531 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
3532 0, 0, pbn_computone_4 },
3533 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
3534 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
3535 0, 0, pbn_computone_8 },
3536 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
3537 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
3538 0, 0, pbn_computone_6 },
3539
3540 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
3541 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3542 pbn_oxsemi },
3543 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
3544 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
3545 pbn_b0_bt_1_921600 },
3546
3547 /*
3548 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
3549 */
3550 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
3551 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3552 pbn_b0_bt_8_115200 },
3553 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
3554 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3555 pbn_b0_bt_8_115200 },
3556
3557 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
3558 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3559 pbn_b0_bt_2_115200 },
3560 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
3561 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3562 pbn_b0_bt_2_115200 },
3563 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
3564 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3565 pbn_b0_bt_2_115200 },
3566 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A,
3567 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3568 pbn_b0_bt_2_115200 },
3569 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B,
3570 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3571 pbn_b0_bt_2_115200 },
3572 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
3573 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3574 pbn_b0_bt_4_460800 },
3575 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
3576 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3577 pbn_b0_bt_4_460800 },
3578 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
3579 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3580 pbn_b0_bt_2_460800 },
3581 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
3582 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3583 pbn_b0_bt_2_460800 },
3584 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
3585 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3586 pbn_b0_bt_2_460800 },
3587 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
3588 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3589 pbn_b0_bt_1_115200 },
3590 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
3591 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3592 pbn_b0_bt_1_460800 },
3593
3594 /*
3595 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
3596 * Cards are identified by their subsystem vendor IDs, which
3597 * (in hex) match the model number.
3598 *
3599 * Note that JC140x are RS422/485 cards which require ox950
3600 * ACR = 0x10, and as such are not currently fully supported.
3601 */
3602 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3603 0x1204, 0x0004, 0, 0,
3604 pbn_b0_4_921600 },
3605 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3606 0x1208, 0x0004, 0, 0,
3607 pbn_b0_4_921600 },
3608/* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3609 0x1402, 0x0002, 0, 0,
3610 pbn_b0_2_921600 }, */
3611/* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3612 0x1404, 0x0004, 0, 0,
3613 pbn_b0_4_921600 }, */
3614 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
3615 0x1208, 0x0004, 0, 0,
3616 pbn_b0_4_921600 },
3617
3618 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
3619 0x1204, 0x0004, 0, 0,
3620 pbn_b0_4_921600 },
3621 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
3622 0x1208, 0x0004, 0, 0,
3623 pbn_b0_4_921600 },
3624 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3,
3625 0x1208, 0x0004, 0, 0,
3626 pbn_b0_4_921600 },
3627 /*
3628 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
3629 */
3630 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
3631 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3632 pbn_b1_1_1382400 },
3633
3634 /*
3635 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
3636 */
3637 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
3638 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3639 pbn_b1_1_1382400 },
3640
3641 /*
3642 * RAStel 2 port modem, gerg@moreton.com.au
3643 */
3644 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
3645 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3646 pbn_b2_bt_2_115200 },
3647
3648 /*
3649 * EKF addition for i960 Boards form EKF with serial port
3650 */
3651 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
3652 0xE4BF, PCI_ANY_ID, 0, 0,
3653 pbn_intel_i960 },
3654
3655 /*
3656 * Xircom Cardbus/Ethernet combos
3657 */
3658 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
3659 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3660 pbn_b0_1_115200 },
3661 /*
3662 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
3663 */
3664 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
3665 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3666 pbn_b0_1_115200 },
3667
3668 /*
3669 * Untested PCI modems, sent in from various folks...
3670 */
3671
3672 /*
3673 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
3674 */
3675 { PCI_VENDOR_ID_ROCKWELL, 0x1004,
3676 0x1048, 0x1500, 0, 0,
3677 pbn_b1_1_115200 },
3678
3679 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
3680 0xFF00, 0, 0, 0,
3681 pbn_sgi_ioc3 },
3682
3683 /*
3684 * HP Diva card
3685 */
3686 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
3687 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
3688 pbn_b1_1_115200 },
3689 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
3690 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3691 pbn_b0_5_115200 },
3692 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
3693 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3694 pbn_b2_1_115200 },
3695
3696 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
3697 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3698 pbn_b3_2_115200 },
3699 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
3700 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3701 pbn_b3_4_115200 },
3702 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
3703 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3704 pbn_b3_8_115200 },
3705
3706 /*
3707 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
3708 */
3709 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3710 PCI_ANY_ID, PCI_ANY_ID,
3711 0,
3712 0, pbn_exar_XR17C152 },
3713 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3714 PCI_ANY_ID, PCI_ANY_ID,
3715 0,
3716 0, pbn_exar_XR17C154 },
3717 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3718 PCI_ANY_ID, PCI_ANY_ID,
3719 0,
3720 0, pbn_exar_XR17C158 },
3721
3722 /*
3723 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
3724 */
3725 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
3726 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3727 pbn_b0_1_115200 },
3728 /*
3729 * ITE
3730 */
3731 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
3732 PCI_ANY_ID, PCI_ANY_ID,
3733 0, 0,
3734 pbn_b1_bt_1_115200 },
3735
3736 /*
3737 * IntaShield IS-200
3738 */
3739 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
3740 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0811 */
3741 pbn_b2_2_115200 },
3742 /*
3743 * IntaShield IS-400
3744 */
3745 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
3746 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */
3747 pbn_b2_4_115200 },
3748 /*
3749 * Perle PCI-RAS cards
3750 */
3751 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
3752 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
3753 0, 0, pbn_b2_4_921600 },
3754 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
3755 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
3756 0, 0, pbn_b2_8_921600 },
3757
3758 /*
3759 * Mainpine series cards: Fairly standard layout but fools
3760 * parts of the autodetect in some cases and uses otherwise
3761 * unmatched communications subclasses in the PCI Express case
3762 */
3763
3764 { /* RockForceDUO */
3765 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3766 PCI_VENDOR_ID_MAINPINE, 0x0200,
3767 0, 0, pbn_b0_2_115200 },
3768 { /* RockForceQUATRO */
3769 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3770 PCI_VENDOR_ID_MAINPINE, 0x0300,
3771 0, 0, pbn_b0_4_115200 },
3772 { /* RockForceDUO+ */
3773 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3774 PCI_VENDOR_ID_MAINPINE, 0x0400,
3775 0, 0, pbn_b0_2_115200 },
3776 { /* RockForceQUATRO+ */
3777 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3778 PCI_VENDOR_ID_MAINPINE, 0x0500,
3779 0, 0, pbn_b0_4_115200 },
3780 { /* RockForce+ */
3781 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3782 PCI_VENDOR_ID_MAINPINE, 0x0600,
3783 0, 0, pbn_b0_2_115200 },
3784 { /* RockForce+ */
3785 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3786 PCI_VENDOR_ID_MAINPINE, 0x0700,
3787 0, 0, pbn_b0_4_115200 },
3788 { /* RockForceOCTO+ */
3789 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3790 PCI_VENDOR_ID_MAINPINE, 0x0800,
3791 0, 0, pbn_b0_8_115200 },
3792 { /* RockForceDUO+ */
3793 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3794 PCI_VENDOR_ID_MAINPINE, 0x0C00,
3795 0, 0, pbn_b0_2_115200 },
3796 { /* RockForceQUARTRO+ */
3797 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3798 PCI_VENDOR_ID_MAINPINE, 0x0D00,
3799 0, 0, pbn_b0_4_115200 },
3800 { /* RockForceOCTO+ */
3801 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3802 PCI_VENDOR_ID_MAINPINE, 0x1D00,
3803 0, 0, pbn_b0_8_115200 },
3804 { /* RockForceD1 */
3805 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3806 PCI_VENDOR_ID_MAINPINE, 0x2000,
3807 0, 0, pbn_b0_1_115200 },
3808 { /* RockForceF1 */
3809 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3810 PCI_VENDOR_ID_MAINPINE, 0x2100,
3811 0, 0, pbn_b0_1_115200 },
3812 { /* RockForceD2 */
3813 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3814 PCI_VENDOR_ID_MAINPINE, 0x2200,
3815 0, 0, pbn_b0_2_115200 },
3816 { /* RockForceF2 */
3817 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3818 PCI_VENDOR_ID_MAINPINE, 0x2300,
3819 0, 0, pbn_b0_2_115200 },
3820 { /* RockForceD4 */
3821 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3822 PCI_VENDOR_ID_MAINPINE, 0x2400,
3823 0, 0, pbn_b0_4_115200 },
3824 { /* RockForceF4 */
3825 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3826 PCI_VENDOR_ID_MAINPINE, 0x2500,
3827 0, 0, pbn_b0_4_115200 },
3828 { /* RockForceD8 */
3829 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3830 PCI_VENDOR_ID_MAINPINE, 0x2600,
3831 0, 0, pbn_b0_8_115200 },
3832 { /* RockForceF8 */
3833 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3834 PCI_VENDOR_ID_MAINPINE, 0x2700,
3835 0, 0, pbn_b0_8_115200 },
3836 { /* IQ Express D1 */
3837 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3838 PCI_VENDOR_ID_MAINPINE, 0x3000,
3839 0, 0, pbn_b0_1_115200 },
3840 { /* IQ Express F1 */
3841 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3842 PCI_VENDOR_ID_MAINPINE, 0x3100,
3843 0, 0, pbn_b0_1_115200 },
3844 { /* IQ Express D2 */
3845 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3846 PCI_VENDOR_ID_MAINPINE, 0x3200,
3847 0, 0, pbn_b0_2_115200 },
3848 { /* IQ Express F2 */
3849 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3850 PCI_VENDOR_ID_MAINPINE, 0x3300,
3851 0, 0, pbn_b0_2_115200 },
3852 { /* IQ Express D4 */
3853 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3854 PCI_VENDOR_ID_MAINPINE, 0x3400,
3855 0, 0, pbn_b0_4_115200 },
3856 { /* IQ Express F4 */
3857 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3858 PCI_VENDOR_ID_MAINPINE, 0x3500,
3859 0, 0, pbn_b0_4_115200 },
3860 { /* IQ Express D8 */
3861 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3862 PCI_VENDOR_ID_MAINPINE, 0x3C00,
3863 0, 0, pbn_b0_8_115200 },
3864 { /* IQ Express F8 */
3865 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3866 PCI_VENDOR_ID_MAINPINE, 0x3D00,
3867 0, 0, pbn_b0_8_115200 },
3868
3869
3870 /*
3871 * PA Semi PA6T-1682M on-chip UART
3872 */
3873 { PCI_VENDOR_ID_PASEMI, 0xa004,
3874 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3875 pbn_pasemi_1682M },
3876
3877 /*
3878 * National Instruments
3879 */
3880 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216,
3881 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3882 pbn_b1_16_115200 },
3883 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328,
3884 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3885 pbn_b1_8_115200 },
3886 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324,
3887 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3888 pbn_b1_bt_4_115200 },
3889 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322,
3890 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3891 pbn_b1_bt_2_115200 },
3892 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I,
3893 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3894 pbn_b1_bt_4_115200 },
3895 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I,
3896 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3897 pbn_b1_bt_2_115200 },
3898 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216,
3899 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3900 pbn_b1_16_115200 },
3901 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328,
3902 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3903 pbn_b1_8_115200 },
3904 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324,
3905 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3906 pbn_b1_bt_4_115200 },
3907 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322,
3908 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3909 pbn_b1_bt_2_115200 },
3910 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324,
3911 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3912 pbn_b1_bt_4_115200 },
3913 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322,
3914 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3915 pbn_b1_bt_2_115200 },
3916 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
3917 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3918 pbn_ni8430_2 },
3919 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
3920 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3921 pbn_ni8430_2 },
3922 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
3923 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3924 pbn_ni8430_4 },
3925 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
3926 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3927 pbn_ni8430_4 },
3928 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
3929 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3930 pbn_ni8430_8 },
3931 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
3932 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3933 pbn_ni8430_8 },
3934 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
3935 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3936 pbn_ni8430_16 },
3937 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
3938 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3939 pbn_ni8430_16 },
3940 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
3941 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3942 pbn_ni8430_2 },
3943 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
3944 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3945 pbn_ni8430_2 },
3946 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
3947 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3948 pbn_ni8430_4 },
3949 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
3950 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3951 pbn_ni8430_4 },
3952
3953 /*
3954 * ADDI-DATA GmbH communication cards <info@addi-data.com>
3955 */
3956 { PCI_VENDOR_ID_ADDIDATA,
3957 PCI_DEVICE_ID_ADDIDATA_APCI7500,
3958 PCI_ANY_ID,
3959 PCI_ANY_ID,
3960 0,
3961 0,
3962 pbn_b0_4_115200 },
3963
3964 { PCI_VENDOR_ID_ADDIDATA,
3965 PCI_DEVICE_ID_ADDIDATA_APCI7420,
3966 PCI_ANY_ID,
3967 PCI_ANY_ID,
3968 0,
3969 0,
3970 pbn_b0_2_115200 },
3971
3972 { PCI_VENDOR_ID_ADDIDATA,
3973 PCI_DEVICE_ID_ADDIDATA_APCI7300,
3974 PCI_ANY_ID,
3975 PCI_ANY_ID,
3976 0,
3977 0,
3978 pbn_b0_1_115200 },
3979
3980 { PCI_VENDOR_ID_ADDIDATA_OLD,
3981 PCI_DEVICE_ID_ADDIDATA_APCI7800,
3982 PCI_ANY_ID,
3983 PCI_ANY_ID,
3984 0,
3985 0,
3986 pbn_b1_8_115200 },
3987
3988 { PCI_VENDOR_ID_ADDIDATA,
3989 PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
3990 PCI_ANY_ID,
3991 PCI_ANY_ID,
3992 0,
3993 0,
3994 pbn_b0_4_115200 },
3995
3996 { PCI_VENDOR_ID_ADDIDATA,
3997 PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
3998 PCI_ANY_ID,
3999 PCI_ANY_ID,
4000 0,
4001 0,
4002 pbn_b0_2_115200 },
4003
4004 { PCI_VENDOR_ID_ADDIDATA,
4005 PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
4006 PCI_ANY_ID,
4007 PCI_ANY_ID,
4008 0,
4009 0,
4010 pbn_b0_1_115200 },
4011
4012 { PCI_VENDOR_ID_ADDIDATA,
4013 PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
4014 PCI_ANY_ID,
4015 PCI_ANY_ID,
4016 0,
4017 0,
4018 pbn_b0_4_115200 },
4019
4020 { PCI_VENDOR_ID_ADDIDATA,
4021 PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
4022 PCI_ANY_ID,
4023 PCI_ANY_ID,
4024 0,
4025 0,
4026 pbn_b0_2_115200 },
4027
4028 { PCI_VENDOR_ID_ADDIDATA,
4029 PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
4030 PCI_ANY_ID,
4031 PCI_ANY_ID,
4032 0,
4033 0,
4034 pbn_b0_1_115200 },
4035
4036 { PCI_VENDOR_ID_ADDIDATA,
4037 PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
4038 PCI_ANY_ID,
4039 PCI_ANY_ID,
4040 0,
4041 0,
4042 pbn_b0_8_115200 },
4043
4044 { PCI_VENDOR_ID_ADDIDATA,
4045 PCI_DEVICE_ID_ADDIDATA_APCIe7500,
4046 PCI_ANY_ID,
4047 PCI_ANY_ID,
4048 0,
4049 0,
4050 pbn_ADDIDATA_PCIe_4_3906250 },
4051
4052 { PCI_VENDOR_ID_ADDIDATA,
4053 PCI_DEVICE_ID_ADDIDATA_APCIe7420,
4054 PCI_ANY_ID,
4055 PCI_ANY_ID,
4056 0,
4057 0,
4058 pbn_ADDIDATA_PCIe_2_3906250 },
4059
4060 { PCI_VENDOR_ID_ADDIDATA,
4061 PCI_DEVICE_ID_ADDIDATA_APCIe7300,
4062 PCI_ANY_ID,
4063 PCI_ANY_ID,
4064 0,
4065 0,
4066 pbn_ADDIDATA_PCIe_1_3906250 },
4067
4068 { PCI_VENDOR_ID_ADDIDATA,
4069 PCI_DEVICE_ID_ADDIDATA_APCIe7800,
4070 PCI_ANY_ID,
4071 PCI_ANY_ID,
4072 0,
4073 0,
4074 pbn_ADDIDATA_PCIe_8_3906250 },
4075
4076 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
4077 PCI_VENDOR_ID_IBM, 0x0299,
4078 0, 0, pbn_b0_bt_2_115200 },
4079
4080 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
4081 0xA000, 0x1000,
4082 0, 0, pbn_b0_1_115200 },
4083
4084 /* the 9901 is a rebranded 9912 */
4085 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
4086 0xA000, 0x1000,
4087 0, 0, pbn_b0_1_115200 },
4088
4089 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
4090 0xA000, 0x1000,
4091 0, 0, pbn_b0_1_115200 },
4092
4093 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904,
4094 0xA000, 0x1000,
4095 0, 0, pbn_b0_1_115200 },
4096
4097 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
4098 0xA000, 0x1000,
4099 0, 0, pbn_b0_1_115200 },
4100
4101 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
4102 0xA000, 0x3002,
4103 0, 0, pbn_NETMOS9900_2s_115200 },
4104
4105 /*
4106 * Best Connectivity and Rosewill PCI Multi I/O cards
4107 */
4108
4109 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
4110 0xA000, 0x1000,
4111 0, 0, pbn_b0_1_115200 },
4112
4113 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
4114 0xA000, 0x3002,
4115 0, 0, pbn_b0_bt_2_115200 },
4116
4117 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
4118 0xA000, 0x3004,
4119 0, 0, pbn_b0_bt_4_115200 },
4120 /* Intel CE4100 */
4121 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART,
4122 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4123 pbn_ce4100_1_115200 },
4124
4125 /*
4126 * Cronyx Omega PCI
4127 */
4128 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
4129 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4130 pbn_omegapci },
4131
4132 /*
4133 * These entries match devices with class COMMUNICATION_SERIAL,
4134 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
4135 */
4136 { PCI_ANY_ID, PCI_ANY_ID,
4137 PCI_ANY_ID, PCI_ANY_ID,
4138 PCI_CLASS_COMMUNICATION_SERIAL << 8,
4139 0xffff00, pbn_default },
4140 { PCI_ANY_ID, PCI_ANY_ID,
4141 PCI_ANY_ID, PCI_ANY_ID,
4142 PCI_CLASS_COMMUNICATION_MODEM << 8,
4143 0xffff00, pbn_default },
4144 { PCI_ANY_ID, PCI_ANY_ID,
4145 PCI_ANY_ID, PCI_ANY_ID,
4146 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
4147 0xffff00, pbn_default },
4148 { 0, }
4149};
4150
4151static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev,
4152 pci_channel_state_t state)
4153{
4154 struct serial_private *priv = pci_get_drvdata(dev);
4155
4156 if (state == pci_channel_io_perm_failure)
4157 return PCI_ERS_RESULT_DISCONNECT;
4158
4159 if (priv)
4160 pciserial_suspend_ports(priv);
4161
4162 pci_disable_device(dev);
4163
4164 return PCI_ERS_RESULT_NEED_RESET;
4165}
4166
4167static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev)
4168{
4169 int rc;
4170
4171 rc = pci_enable_device(dev);
4172
4173 if (rc)
4174 return PCI_ERS_RESULT_DISCONNECT;
4175
4176 pci_restore_state(dev);
4177 pci_save_state(dev);
4178
4179 return PCI_ERS_RESULT_RECOVERED;
4180}
4181
4182static void serial8250_io_resume(struct pci_dev *dev)
4183{
4184 struct serial_private *priv = pci_get_drvdata(dev);
4185
4186 if (priv)
4187 pciserial_resume_ports(priv);
4188}
4189
4190static struct pci_error_handlers serial8250_err_handler = {
4191 .error_detected = serial8250_io_error_detected,
4192 .slot_reset = serial8250_io_slot_reset,
4193 .resume = serial8250_io_resume,
4194};
4195
4196static struct pci_driver serial_pci_driver = {
4197 .name = "serial",
4198 .probe = pciserial_init_one,
4199 .remove = __devexit_p(pciserial_remove_one),
4200#ifdef CONFIG_PM
4201 .suspend = pciserial_suspend_one,
4202 .resume = pciserial_resume_one,
4203#endif
4204 .id_table = serial_pci_tbl,
4205 .err_handler = &serial8250_err_handler,
4206};
4207
4208static int __init serial8250_pci_init(void)
4209{
4210 return pci_register_driver(&serial_pci_driver);
4211}
4212
4213static void __exit serial8250_pci_exit(void)
4214{
4215 pci_unregister_driver(&serial_pci_driver);
4216}
4217
4218module_init(serial8250_pci_init);
4219module_exit(serial8250_pci_exit);
4220
4221MODULE_LICENSE("GPL");
4222MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
4223MODULE_DEVICE_TABLE(pci, serial_pci_tbl);
diff --git a/drivers/tty/serial/8250/8250_pnp.c b/drivers/tty/serial/8250/8250_pnp.c
new file mode 100644
index 000000000000..a2f236510ff1
--- /dev/null
+++ b/drivers/tty/serial/8250/8250_pnp.c
@@ -0,0 +1,524 @@
1/*
2 * Probe module for 8250/16550-type ISAPNP serial ports.
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Copyright (C) 2001 Russell King, All Rights Reserved.
7 *
8 * Ported to the Linux PnP Layer - (C) Adam Belay.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License.
13 */
14#include <linux/module.h>
15#include <linux/init.h>
16#include <linux/pci.h>
17#include <linux/pnp.h>
18#include <linux/string.h>
19#include <linux/kernel.h>
20#include <linux/serial_core.h>
21#include <linux/bitops.h>
22
23#include <asm/byteorder.h>
24
25#include "8250.h"
26
27#define UNKNOWN_DEV 0x3000
28
29
30static const struct pnp_device_id pnp_dev_table[] = {
31 /* Archtek America Corp. */
32 /* Archtek SmartLink Modem 3334BT Plug & Play */
33 { "AAC000F", 0 },
34 /* Anchor Datacomm BV */
35 /* SXPro 144 External Data Fax Modem Plug & Play */
36 { "ADC0001", 0 },
37 /* SXPro 288 External Data Fax Modem Plug & Play */
38 { "ADC0002", 0 },
39 /* PROLiNK 1456VH ISA PnP K56flex Fax Modem */
40 { "AEI0250", 0 },
41 /* Actiontec ISA PNP 56K X2 Fax Modem */
42 { "AEI1240", 0 },
43 /* Rockwell 56K ACF II Fax+Data+Voice Modem */
44 { "AKY1021", 0 /*SPCI_FL_NO_SHIRQ*/ },
45 /* AZT3005 PnP SOUND DEVICE */
46 { "AZT4001", 0 },
47 /* Best Data Products Inc. Smart One 336F PnP Modem */
48 { "BDP3336", 0 },
49 /* Boca Research */
50 /* Boca Complete Ofc Communicator 14.4 Data-FAX */
51 { "BRI0A49", 0 },
52 /* Boca Research 33,600 ACF Modem */
53 { "BRI1400", 0 },
54 /* Boca 33.6 Kbps Internal FD34FSVD */
55 { "BRI3400", 0 },
56 /* Boca 33.6 Kbps Internal FD34FSVD */
57 { "BRI0A49", 0 },
58 /* Best Data Products Inc. Smart One 336F PnP Modem */
59 { "BDP3336", 0 },
60 /* Computer Peripherals Inc */
61 /* EuroViVa CommCenter-33.6 SP PnP */
62 { "CPI4050", 0 },
63 /* Creative Labs */
64 /* Creative Labs Phone Blaster 28.8 DSVD PnP Voice */
65 { "CTL3001", 0 },
66 /* Creative Labs Modem Blaster 28.8 DSVD PnP Voice */
67 { "CTL3011", 0 },
68 /* Davicom ISA 33.6K Modem */
69 { "DAV0336", 0 },
70 /* Creative */
71 /* Creative Modem Blaster Flash56 DI5601-1 */
72 { "DMB1032", 0 },
73 /* Creative Modem Blaster V.90 DI5660 */
74 { "DMB2001", 0 },
75 /* E-Tech */
76 /* E-Tech CyberBULLET PC56RVP */
77 { "ETT0002", 0 },
78 /* FUJITSU */
79 /* Fujitsu 33600 PnP-I2 R Plug & Play */
80 { "FUJ0202", 0 },
81 /* Fujitsu FMV-FX431 Plug & Play */
82 { "FUJ0205", 0 },
83 /* Fujitsu 33600 PnP-I4 R Plug & Play */
84 { "FUJ0206", 0 },
85 /* Fujitsu Fax Voice 33600 PNP-I5 R Plug & Play */
86 { "FUJ0209", 0 },
87 /* Archtek America Corp. */
88 /* Archtek SmartLink Modem 3334BT Plug & Play */
89 { "GVC000F", 0 },
90 /* Archtek SmartLink Modem 3334BRV 33.6K Data Fax Voice */
91 { "GVC0303", 0 },
92 /* Hayes */
93 /* Hayes Optima 288 V.34-V.FC + FAX + Voice Plug & Play */
94 { "HAY0001", 0 },
95 /* Hayes Optima 336 V.34 + FAX + Voice PnP */
96 { "HAY000C", 0 },
97 /* Hayes Optima 336B V.34 + FAX + Voice PnP */
98 { "HAY000D", 0 },
99 /* Hayes Accura 56K Ext Fax Modem PnP */
100 { "HAY5670", 0 },
101 /* Hayes Accura 56K Ext Fax Modem PnP */
102 { "HAY5674", 0 },
103 /* Hayes Accura 56K Fax Modem PnP */
104 { "HAY5675", 0 },
105 /* Hayes 288, V.34 + FAX */
106 { "HAYF000", 0 },
107 /* Hayes Optima 288 V.34 + FAX + Voice, Plug & Play */
108 { "HAYF001", 0 },
109 /* IBM */
110 /* IBM Thinkpad 701 Internal Modem Voice */
111 { "IBM0033", 0 },
112 /* Intermec */
113 /* Intermec CV60 touchscreen port */
114 { "PNP4972", 0 },
115 /* Intertex */
116 /* Intertex 28k8 33k6 Voice EXT PnP */
117 { "IXDC801", 0 },
118 /* Intertex 33k6 56k Voice EXT PnP */
119 { "IXDC901", 0 },
120 /* Intertex 28k8 33k6 Voice SP EXT PnP */
121 { "IXDD801", 0 },
122 /* Intertex 33k6 56k Voice SP EXT PnP */
123 { "IXDD901", 0 },
124 /* Intertex 28k8 33k6 Voice SP INT PnP */
125 { "IXDF401", 0 },
126 /* Intertex 28k8 33k6 Voice SP EXT PnP */
127 { "IXDF801", 0 },
128 /* Intertex 33k6 56k Voice SP EXT PnP */
129 { "IXDF901", 0 },
130 /* Kortex International */
131 /* KORTEX 28800 Externe PnP */
132 { "KOR4522", 0 },
133 /* KXPro 33.6 Vocal ASVD PnP */
134 { "KORF661", 0 },
135 /* Lasat */
136 /* LASAT Internet 33600 PnP */
137 { "LAS4040", 0 },
138 /* Lasat Safire 560 PnP */
139 { "LAS4540", 0 },
140 /* Lasat Safire 336 PnP */
141 { "LAS5440", 0 },
142 /* Microcom, Inc. */
143 /* Microcom TravelPorte FAST V.34 Plug & Play */
144 { "MNP0281", 0 },
145 /* Microcom DeskPorte V.34 FAST or FAST+ Plug & Play */
146 { "MNP0336", 0 },
147 /* Microcom DeskPorte FAST EP 28.8 Plug & Play */
148 { "MNP0339", 0 },
149 /* Microcom DeskPorte 28.8P Plug & Play */
150 { "MNP0342", 0 },
151 /* Microcom DeskPorte FAST ES 28.8 Plug & Play */
152 { "MNP0500", 0 },
153 /* Microcom DeskPorte FAST ES 28.8 Plug & Play */
154 { "MNP0501", 0 },
155 /* Microcom DeskPorte 28.8S Internal Plug & Play */
156 { "MNP0502", 0 },
157 /* Motorola */
158 /* Motorola BitSURFR Plug & Play */
159 { "MOT1105", 0 },
160 /* Motorola TA210 Plug & Play */
161 { "MOT1111", 0 },
162 /* Motorola HMTA 200 (ISDN) Plug & Play */
163 { "MOT1114", 0 },
164 /* Motorola BitSURFR Plug & Play */
165 { "MOT1115", 0 },
166 /* Motorola Lifestyle 28.8 Internal */
167 { "MOT1190", 0 },
168 /* Motorola V.3400 Plug & Play */
169 { "MOT1501", 0 },
170 /* Motorola Lifestyle 28.8 V.34 Plug & Play */
171 { "MOT1502", 0 },
172 /* Motorola Power 28.8 V.34 Plug & Play */
173 { "MOT1505", 0 },
174 /* Motorola ModemSURFR External 28.8 Plug & Play */
175 { "MOT1509", 0 },
176 /* Motorola Premier 33.6 Desktop Plug & Play */
177 { "MOT150A", 0 },
178 /* Motorola VoiceSURFR 56K External PnP */
179 { "MOT150F", 0 },
180 /* Motorola ModemSURFR 56K External PnP */
181 { "MOT1510", 0 },
182 /* Motorola ModemSURFR 56K Internal PnP */
183 { "MOT1550", 0 },
184 /* Motorola ModemSURFR Internal 28.8 Plug & Play */
185 { "MOT1560", 0 },
186 /* Motorola Premier 33.6 Internal Plug & Play */
187 { "MOT1580", 0 },
188 /* Motorola OnlineSURFR 28.8 Internal Plug & Play */
189 { "MOT15B0", 0 },
190 /* Motorola VoiceSURFR 56K Internal PnP */
191 { "MOT15F0", 0 },
192 /* Com 1 */
193 /* Deskline K56 Phone System PnP */
194 { "MVX00A1", 0 },
195 /* PC Rider K56 Phone System PnP */
196 { "MVX00F2", 0 },
197 /* NEC 98NOTE SPEAKER PHONE FAX MODEM(33600bps) */
198 { "nEC8241", 0 },
199 /* Pace 56 Voice Internal Plug & Play Modem */
200 { "PMC2430", 0 },
201 /* Generic */
202 /* Generic standard PC COM port */
203 { "PNP0500", 0 },
204 /* Generic 16550A-compatible COM port */
205 { "PNP0501", 0 },
206 /* Compaq 14400 Modem */
207 { "PNPC000", 0 },
208 /* Compaq 2400/9600 Modem */
209 { "PNPC001", 0 },
210 /* Dial-Up Networking Serial Cable between 2 PCs */
211 { "PNPC031", 0 },
212 /* Dial-Up Networking Parallel Cable between 2 PCs */
213 { "PNPC032", 0 },
214 /* Standard 9600 bps Modem */
215 { "PNPC100", 0 },
216 /* Standard 14400 bps Modem */
217 { "PNPC101", 0 },
218 /* Standard 28800 bps Modem*/
219 { "PNPC102", 0 },
220 /* Standard Modem*/
221 { "PNPC103", 0 },
222 /* Standard 9600 bps Modem*/
223 { "PNPC104", 0 },
224 /* Standard 14400 bps Modem*/
225 { "PNPC105", 0 },
226 /* Standard 28800 bps Modem*/
227 { "PNPC106", 0 },
228 /* Standard Modem */
229 { "PNPC107", 0 },
230 /* Standard 9600 bps Modem */
231 { "PNPC108", 0 },
232 /* Standard 14400 bps Modem */
233 { "PNPC109", 0 },
234 /* Standard 28800 bps Modem */
235 { "PNPC10A", 0 },
236 /* Standard Modem */
237 { "PNPC10B", 0 },
238 /* Standard 9600 bps Modem */
239 { "PNPC10C", 0 },
240 /* Standard 14400 bps Modem */
241 { "PNPC10D", 0 },
242 /* Standard 28800 bps Modem */
243 { "PNPC10E", 0 },
244 /* Standard Modem */
245 { "PNPC10F", 0 },
246 /* Standard PCMCIA Card Modem */
247 { "PNP2000", 0 },
248 /* Rockwell */
249 /* Modular Technology */
250 /* Rockwell 33.6 DPF Internal PnP */
251 /* Modular Technology 33.6 Internal PnP */
252 { "ROK0030", 0 },
253 /* Kortex International */
254 /* KORTEX 14400 Externe PnP */
255 { "ROK0100", 0 },
256 /* Rockwell 28.8 */
257 { "ROK4120", 0 },
258 /* Viking Components, Inc */
259 /* Viking 28.8 INTERNAL Fax+Data+Voice PnP */
260 { "ROK4920", 0 },
261 /* Rockwell */
262 /* British Telecom */
263 /* Modular Technology */
264 /* Rockwell 33.6 DPF External PnP */
265 /* BT Prologue 33.6 External PnP */
266 /* Modular Technology 33.6 External PnP */
267 { "RSS00A0", 0 },
268 /* Viking 56K FAX INT */
269 { "RSS0262", 0 },
270 /* K56 par,VV,Voice,Speakphone,AudioSpan,PnP */
271 { "RSS0250", 0 },
272 /* SupraExpress 28.8 Data/Fax PnP modem */
273 { "SUP1310", 0 },
274 /* SupraExpress 336i PnP Voice Modem */
275 { "SUP1381", 0 },
276 /* SupraExpress 33.6 Data/Fax PnP modem */
277 { "SUP1421", 0 },
278 /* SupraExpress 33.6 Data/Fax PnP modem */
279 { "SUP1590", 0 },
280 /* SupraExpress 336i Sp ASVD */
281 { "SUP1620", 0 },
282 /* SupraExpress 33.6 Data/Fax PnP modem */
283 { "SUP1760", 0 },
284 /* SupraExpress 56i Sp Intl */
285 { "SUP2171", 0 },
286 /* Phoebe Micro */
287 /* Phoebe Micro 33.6 Data Fax 1433VQH Plug & Play */
288 { "TEX0011", 0 },
289 /* Archtek America Corp. */
290 /* Archtek SmartLink Modem 3334BT Plug & Play */
291 { "UAC000F", 0 },
292 /* 3Com Corp. */
293 /* Gateway Telepath IIvi 33.6 */
294 { "USR0000", 0 },
295 /* U.S. Robotics Sporster 33.6K Fax INT PnP */
296 { "USR0002", 0 },
297 /* Sportster Vi 14.4 PnP FAX Voicemail */
298 { "USR0004", 0 },
299 /* U.S. Robotics 33.6K Voice INT PnP */
300 { "USR0006", 0 },
301 /* U.S. Robotics 33.6K Voice EXT PnP */
302 { "USR0007", 0 },
303 /* U.S. Robotics Courier V.Everything INT PnP */
304 { "USR0009", 0 },
305 /* U.S. Robotics 33.6K Voice INT PnP */
306 { "USR2002", 0 },
307 /* U.S. Robotics 56K Voice INT PnP */
308 { "USR2070", 0 },
309 /* U.S. Robotics 56K Voice EXT PnP */
310 { "USR2080", 0 },
311 /* U.S. Robotics 56K FAX INT */
312 { "USR3031", 0 },
313 /* U.S. Robotics 56K FAX INT */
314 { "USR3050", 0 },
315 /* U.S. Robotics 56K Voice INT PnP */
316 { "USR3070", 0 },
317 /* U.S. Robotics 56K Voice EXT PnP */
318 { "USR3080", 0 },
319 /* U.S. Robotics 56K Voice INT PnP */
320 { "USR3090", 0 },
321 /* U.S. Robotics 56K Message */
322 { "USR9100", 0 },
323 /* U.S. Robotics 56K FAX EXT PnP*/
324 { "USR9160", 0 },
325 /* U.S. Robotics 56K FAX INT PnP*/
326 { "USR9170", 0 },
327 /* U.S. Robotics 56K Voice EXT PnP*/
328 { "USR9180", 0 },
329 /* U.S. Robotics 56K Voice INT PnP*/
330 { "USR9190", 0 },
331 /* Wacom tablets */
332 { "WACFXXX", 0 },
333 /* Compaq touchscreen */
334 { "FPI2002", 0 },
335 /* Fujitsu Stylistic touchscreens */
336 { "FUJ02B2", 0 },
337 { "FUJ02B3", 0 },
338 /* Fujitsu Stylistic LT touchscreens */
339 { "FUJ02B4", 0 },
340 /* Passive Fujitsu Stylistic touchscreens */
341 { "FUJ02B6", 0 },
342 { "FUJ02B7", 0 },
343 { "FUJ02B8", 0 },
344 { "FUJ02B9", 0 },
345 { "FUJ02BC", 0 },
346 /* Fujitsu Wacom Tablet PC device */
347 { "FUJ02E5", 0 },
348 /* Fujitsu P-series tablet PC device */
349 { "FUJ02E6", 0 },
350 /* Fujitsu Wacom 2FGT Tablet PC device */
351 { "FUJ02E7", 0 },
352 /* Fujitsu Wacom 1FGT Tablet PC device */
353 { "FUJ02E9", 0 },
354 /*
355 * LG C1 EXPRESS DUAL (C1-PB11A3) touch screen (actually a FUJ02E6 in
356 * disguise)
357 */
358 { "LTS0001", 0 },
359 /* Rockwell's (PORALiNK) 33600 INT PNP */
360 { "WCI0003", 0 },
361 /* Unknown PnP modems */
362 { "PNPCXXX", UNKNOWN_DEV },
363 /* More unknown PnP modems */
364 { "PNPDXXX", UNKNOWN_DEV },
365 { "", 0 }
366};
367
368MODULE_DEVICE_TABLE(pnp, pnp_dev_table);
369
370static char *modem_names[] __devinitdata = {
371 "MODEM", "Modem", "modem", "FAX", "Fax", "fax",
372 "56K", "56k", "K56", "33.6", "28.8", "14.4",
373 "33,600", "28,800", "14,400", "33.600", "28.800", "14.400",
374 "33600", "28800", "14400", "V.90", "V.34", "V.32", NULL
375};
376
377static int __devinit check_name(char *name)
378{
379 char **tmp;
380
381 for (tmp = modem_names; *tmp; tmp++)
382 if (strstr(name, *tmp))
383 return 1;
384
385 return 0;
386}
387
388static int __devinit check_resources(struct pnp_dev *dev)
389{
390 resource_size_t base[] = {0x2f8, 0x3f8, 0x2e8, 0x3e8};
391 int i;
392
393 for (i = 0; i < ARRAY_SIZE(base); i++) {
394 if (pnp_possible_config(dev, IORESOURCE_IO, base[i], 8))
395 return 1;
396 }
397
398 return 0;
399}
400
401/*
402 * Given a complete unknown PnP device, try to use some heuristics to
403 * detect modems. Currently use such heuristic set:
404 * - dev->name or dev->bus->name must contain "modem" substring;
405 * - device must have only one IO region (8 byte long) with base address
406 * 0x2e8, 0x3e8, 0x2f8 or 0x3f8.
407 *
408 * Such detection looks very ugly, but can detect at least some of numerous
409 * PnP modems, alternatively we must hardcode all modems in pnp_devices[]
410 * table.
411 */
412static int __devinit serial_pnp_guess_board(struct pnp_dev *dev, int *flags)
413{
414 if (!(check_name(pnp_dev_name(dev)) ||
415 (dev->card && check_name(dev->card->name))))
416 return -ENODEV;
417
418 if (check_resources(dev))
419 return 0;
420
421 return -ENODEV;
422}
423
424static int __devinit
425serial_pnp_probe(struct pnp_dev *dev, const struct pnp_device_id *dev_id)
426{
427 struct uart_port port;
428 int ret, line, flags = dev_id->driver_data;
429
430 if (flags & UNKNOWN_DEV) {
431 ret = serial_pnp_guess_board(dev, &flags);
432 if (ret < 0)
433 return ret;
434 }
435
436 memset(&port, 0, sizeof(struct uart_port));
437 if (pnp_irq_valid(dev, 0))
438 port.irq = pnp_irq(dev, 0);
439 if (pnp_port_valid(dev, 0)) {
440 port.iobase = pnp_port_start(dev, 0);
441 port.iotype = UPIO_PORT;
442 } else if (pnp_mem_valid(dev, 0)) {
443 port.mapbase = pnp_mem_start(dev, 0);
444 port.iotype = UPIO_MEM;
445 port.flags = UPF_IOREMAP;
446 } else
447 return -ENODEV;
448
449#ifdef SERIAL_DEBUG_PNP
450 printk(KERN_DEBUG
451 "Setup PNP port: port %x, mem 0x%lx, irq %d, type %d\n",
452 port.iobase, port.mapbase, port.irq, port.iotype);
453#endif
454
455 port.flags |= UPF_SKIP_TEST | UPF_BOOT_AUTOCONF;
456 if (pnp_irq_flags(dev, 0) & IORESOURCE_IRQ_SHAREABLE)
457 port.flags |= UPF_SHARE_IRQ;
458 port.uartclk = 1843200;
459 port.dev = &dev->dev;
460
461 line = serial8250_register_port(&port);
462 if (line < 0)
463 return -ENODEV;
464
465 pnp_set_drvdata(dev, (void *)((long)line + 1));
466 return 0;
467}
468
469static void __devexit serial_pnp_remove(struct pnp_dev *dev)
470{
471 long line = (long)pnp_get_drvdata(dev);
472 if (line)
473 serial8250_unregister_port(line - 1);
474}
475
476#ifdef CONFIG_PM
477static int serial_pnp_suspend(struct pnp_dev *dev, pm_message_t state)
478{
479 long line = (long)pnp_get_drvdata(dev);
480
481 if (!line)
482 return -ENODEV;
483 serial8250_suspend_port(line - 1);
484 return 0;
485}
486
487static int serial_pnp_resume(struct pnp_dev *dev)
488{
489 long line = (long)pnp_get_drvdata(dev);
490
491 if (!line)
492 return -ENODEV;
493 serial8250_resume_port(line - 1);
494 return 0;
495}
496#else
497#define serial_pnp_suspend NULL
498#define serial_pnp_resume NULL
499#endif /* CONFIG_PM */
500
501static struct pnp_driver serial_pnp_driver = {
502 .name = "serial",
503 .probe = serial_pnp_probe,
504 .remove = __devexit_p(serial_pnp_remove),
505 .suspend = serial_pnp_suspend,
506 .resume = serial_pnp_resume,
507 .id_table = pnp_dev_table,
508};
509
510static int __init serial8250_pnp_init(void)
511{
512 return pnp_register_driver(&serial_pnp_driver);
513}
514
515static void __exit serial8250_pnp_exit(void)
516{
517 pnp_unregister_driver(&serial_pnp_driver);
518}
519
520module_init(serial8250_pnp_init);
521module_exit(serial8250_pnp_exit);
522
523MODULE_LICENSE("GPL");
524MODULE_DESCRIPTION("Generic 8250/16x50 PnP serial driver");
diff --git a/drivers/tty/serial/8250/Kconfig b/drivers/tty/serial/8250/Kconfig
new file mode 100644
index 000000000000..591f8018e7dd
--- /dev/null
+++ b/drivers/tty/serial/8250/Kconfig
@@ -0,0 +1,280 @@
1#
2# The 8250/16550 serial drivers. You shouldn't be in this list unless
3# you somehow have an implicit or explicit dependency on SERIAL_8250.
4#
5
6config SERIAL_8250
7 tristate "8250/16550 and compatible serial support"
8 select SERIAL_CORE
9 ---help---
10 This selects whether you want to include the driver for the standard
11 serial ports. The standard answer is Y. People who might say N
12 here are those that are setting up dedicated Ethernet WWW/FTP
13 servers, or users that have one of the various bus mice instead of a
14 serial mouse and don't intend to use their machine's standard serial
15 port for anything. (Note that the Cyclades and Stallion multi
16 serial port drivers do not need this driver built in for them to
17 work.)
18
19 To compile this driver as a module, choose M here: the
20 module will be called 8250.
21 [WARNING: Do not compile this driver as a module if you are using
22 non-standard serial ports, since the configuration information will
23 be lost when the driver is unloaded. This limitation may be lifted
24 in the future.]
25
26 BTW1: If you have a mouseman serial mouse which is not recognized by
27 the X window system, try running gpm first.
28
29 BTW2: If you intend to use a software modem (also called Winmodem)
30 under Linux, forget it. These modems are crippled and require
31 proprietary drivers which are only available under Windows.
32
33 Most people will say Y or M here, so that they can use serial mice,
34 modems and similar devices connecting to the standard serial ports.
35
36config SERIAL_8250_CONSOLE
37 bool "Console on 8250/16550 and compatible serial port"
38 depends on SERIAL_8250=y
39 select SERIAL_CORE_CONSOLE
40 ---help---
41 If you say Y here, it will be possible to use a serial port as the
42 system console (the system console is the device which receives all
43 kernel messages and warnings and which allows logins in single user
44 mode). This could be useful if some terminal or printer is connected
45 to that serial port.
46
47 Even if you say Y here, the currently visible virtual console
48 (/dev/tty0) will still be used as the system console by default, but
49 you can alter that using a kernel command line option such as
50 "console=ttyS1". (Try "man bootparam" or see the documentation of
51 your boot loader (grub or lilo or loadlin) about how to pass options
52 to the kernel at boot time.)
53
54 If you don't have a VGA card installed and you say Y here, the
55 kernel will automatically use the first serial line, /dev/ttyS0, as
56 system console.
57
58 You can set that using a kernel command line option such as
59 "console=uart8250,io,0x3f8,9600n8"
60 "console=uart8250,mmio,0xff5e0000,115200n8".
61 and it will switch to normal serial console when the corresponding
62 port is ready.
63 "earlycon=uart8250,io,0x3f8,9600n8"
64 "earlycon=uart8250,mmio,0xff5e0000,115200n8".
65 it will not only setup early console.
66
67 If unsure, say N.
68
69config FIX_EARLYCON_MEM
70 bool
71 depends on X86
72 default y
73
74config SERIAL_8250_GSC
75 tristate
76 depends on SERIAL_8250 && GSC
77 default SERIAL_8250
78
79config SERIAL_8250_PCI
80 tristate "8250/16550 PCI device support" if EXPERT
81 depends on SERIAL_8250 && PCI
82 default SERIAL_8250
83 help
84 This builds standard PCI serial support. You may be able to
85 disable this feature if you only need legacy serial support.
86 Saves about 9K.
87
88config SERIAL_8250_PNP
89 tristate "8250/16550 PNP device support" if EXPERT
90 depends on SERIAL_8250 && PNP
91 default SERIAL_8250
92 help
93 This builds standard PNP serial support. You may be able to
94 disable this feature if you only need legacy serial support.
95
96config SERIAL_8250_HP300
97 tristate
98 depends on SERIAL_8250 && HP300
99 default SERIAL_8250
100
101config SERIAL_8250_CS
102 tristate "8250/16550 PCMCIA device support"
103 depends on PCMCIA && SERIAL_8250
104 ---help---
105 Say Y here to enable support for 16-bit PCMCIA serial devices,
106 including serial port cards, modems, and the modem functions of
107 multi-function Ethernet/modem cards. (PCMCIA- or PC-cards are
108 credit-card size devices often used with laptops.)
109
110 To compile this driver as a module, choose M here: the
111 module will be called serial_cs.
112
113 If unsure, say N.
114
115config SERIAL_8250_NR_UARTS
116 int "Maximum number of 8250/16550 serial ports"
117 depends on SERIAL_8250
118 default "4"
119 help
120 Set this to the number of serial ports you want the driver
121 to support. This includes any ports discovered via ACPI or
122 PCI enumeration and any ports that may be added at run-time
123 via hot-plug, or any ISA multi-port serial cards.
124
125config SERIAL_8250_RUNTIME_UARTS
126 int "Number of 8250/16550 serial ports to register at runtime"
127 depends on SERIAL_8250
128 range 0 SERIAL_8250_NR_UARTS
129 default "4"
130 help
131 Set this to the maximum number of serial ports you want
132 the kernel to register at boot time. This can be overridden
133 with the module parameter "nr_uarts", or boot-time parameter
134 8250.nr_uarts
135
136config SERIAL_8250_EXTENDED
137 bool "Extended 8250/16550 serial driver options"
138 depends on SERIAL_8250
139 help
140 If you wish to use any non-standard features of the standard "dumb"
141 driver, say Y here. This includes HUB6 support, shared serial
142 interrupts, special multiport support, support for more than the
143 four COM 1/2/3/4 boards, etc.
144
145 Note that the answer to this question won't directly affect the
146 kernel: saying N will just cause the configurator to skip all
147 the questions about serial driver options. If unsure, say N.
148
149config SERIAL_8250_MANY_PORTS
150 bool "Support more than 4 legacy serial ports"
151 depends on SERIAL_8250_EXTENDED && !IA64
152 help
153 Say Y here if you have dumb serial boards other than the four
154 standard COM 1/2/3/4 ports. This may happen if you have an AST
155 FourPort, Accent Async, Boca (read the Boca mini-HOWTO, available
156 from <http://www.tldp.org/docs.html#howto>), or other custom
157 serial port hardware which acts similar to standard serial port
158 hardware. If you only use the standard COM 1/2/3/4 ports, you can
159 say N here to save some memory. You can also say Y if you have an
160 "intelligent" multiport card such as Cyclades, Digiboards, etc.
161
162#
163# Multi-port serial cards
164#
165
166config SERIAL_8250_FOURPORT
167 tristate "Support Fourport cards"
168 depends on SERIAL_8250 != n && ISA && SERIAL_8250_MANY_PORTS
169 help
170 Say Y here if you have an AST FourPort serial board.
171
172 To compile this driver as a module, choose M here: the module
173 will be called 8250_fourport.
174
175config SERIAL_8250_ACCENT
176 tristate "Support Accent cards"
177 depends on SERIAL_8250 != n && ISA && SERIAL_8250_MANY_PORTS
178 help
179 Say Y here if you have an Accent Async serial board.
180
181 To compile this driver as a module, choose M here: the module
182 will be called 8250_accent.
183
184config SERIAL_8250_BOCA
185 tristate "Support Boca cards"
186 depends on SERIAL_8250 != n && ISA && SERIAL_8250_MANY_PORTS
187 help
188 Say Y here if you have a Boca serial board. Please read the Boca
189 mini-HOWTO, available from <http://www.tldp.org/docs.html#howto>
190
191 To compile this driver as a module, choose M here: the module
192 will be called 8250_boca.
193
194config SERIAL_8250_EXAR_ST16C554
195 tristate "Support Exar ST16C554/554D Quad UART"
196 depends on SERIAL_8250 != n && ISA && SERIAL_8250_MANY_PORTS
197 help
198 The Uplogix Envoy TU301 uses this Exar Quad UART. If you are
199 tinkering with your Envoy TU301, or have a machine with this UART,
200 say Y here.
201
202 To compile this driver as a module, choose M here: the module
203 will be called 8250_exar_st16c554.
204
205config SERIAL_8250_HUB6
206 tristate "Support Hub6 cards"
207 depends on SERIAL_8250 != n && ISA && SERIAL_8250_MANY_PORTS
208 help
209 Say Y here if you have a HUB6 serial board.
210
211 To compile this driver as a module, choose M here: the module
212 will be called 8250_hub6.
213
214#
215# Misc. options/drivers.
216#
217
218config SERIAL_8250_SHARE_IRQ
219 bool "Support for sharing serial interrupts"
220 depends on SERIAL_8250_EXTENDED
221 help
222 Some serial boards have hardware support which allows multiple dumb
223 serial ports on the same board to share a single IRQ. To enable
224 support for this in the serial driver, say Y here.
225
226config SERIAL_8250_DETECT_IRQ
227 bool "Autodetect IRQ on standard ports (unsafe)"
228 depends on SERIAL_8250_EXTENDED
229 help
230 Say Y here if you want the kernel to try to guess which IRQ
231 to use for your serial port.
232
233 This is considered unsafe; it is far better to configure the IRQ in
234 a boot script using the setserial command.
235
236 If unsure, say N.
237
238config SERIAL_8250_RSA
239 bool "Support RSA serial ports"
240 depends on SERIAL_8250_EXTENDED
241 help
242 ::: To be written :::
243
244config SERIAL_8250_MCA
245 tristate "Support 8250-type ports on MCA buses"
246 depends on SERIAL_8250 != n && MCA
247 help
248 Say Y here if you have a MCA serial ports.
249
250 To compile this driver as a module, choose M here: the module
251 will be called 8250_mca.
252
253config SERIAL_8250_ACORN
254 tristate "Acorn expansion card serial port support"
255 depends on ARCH_ACORN && SERIAL_8250
256 help
257 If you have an Atomwide Serial card or Serial Port card for an Acorn
258 system, say Y to this option. The driver can handle 1, 2, or 3 port
259 cards. If unsure, say N.
260
261config SERIAL_8250_RM9K
262 bool "Support for MIPS RM9xxx integrated serial port"
263 depends on SERIAL_8250 != n && SERIAL_RM9000
264 select SERIAL_8250_SHARE_IRQ
265 help
266 Selecting this option will add support for the integrated serial
267 port hardware found on MIPS RM9122 and similar processors.
268 If unsure, say N.
269
270config SERIAL_8250_FSL
271 bool
272 depends on SERIAL_8250_CONSOLE && PPC_UDBG_16550
273 default PPC
274
275config SERIAL_8250_DW
276 tristate "Support for Synopsys DesignWare 8250 quirks"
277 depends on SERIAL_8250 && OF
278 help
279 Selecting this option will enable handling of the extra features
280 present in the Synopsys DesignWare APB UART.
diff --git a/drivers/tty/serial/8250/Makefile b/drivers/tty/serial/8250/Makefile
new file mode 100644
index 000000000000..867bba738908
--- /dev/null
+++ b/drivers/tty/serial/8250/Makefile
@@ -0,0 +1,20 @@
1#
2# Makefile for the 8250 serial device drivers.
3#
4
5obj-$(CONFIG_SERIAL_8250) += 8250.o
6obj-$(CONFIG_SERIAL_8250_PNP) += 8250_pnp.o
7obj-$(CONFIG_SERIAL_8250_GSC) += 8250_gsc.o
8obj-$(CONFIG_SERIAL_8250_PCI) += 8250_pci.o
9obj-$(CONFIG_SERIAL_8250_HP300) += 8250_hp300.o
10obj-$(CONFIG_SERIAL_8250_CS) += serial_cs.o
11obj-$(CONFIG_SERIAL_8250_ACORN) += 8250_acorn.o
12obj-$(CONFIG_SERIAL_8250_CONSOLE) += 8250_early.o
13obj-$(CONFIG_SERIAL_8250_FOURPORT) += 8250_fourport.o
14obj-$(CONFIG_SERIAL_8250_ACCENT) += 8250_accent.o
15obj-$(CONFIG_SERIAL_8250_BOCA) += 8250_boca.o
16obj-$(CONFIG_SERIAL_8250_EXAR_ST16C554) += 8250_exar_st16c554.o
17obj-$(CONFIG_SERIAL_8250_HUB6) += 8250_hub6.o
18obj-$(CONFIG_SERIAL_8250_MCA) += 8250_mca.o
19obj-$(CONFIG_SERIAL_8250_FSL) += 8250_fsl.o
20obj-$(CONFIG_SERIAL_8250_DW) += 8250_dw.o
diff --git a/drivers/tty/serial/8250/m32r_sio.c b/drivers/tty/serial/8250/m32r_sio.c
new file mode 100644
index 000000000000..94a6792bf97b
--- /dev/null
+++ b/drivers/tty/serial/8250/m32r_sio.c
@@ -0,0 +1,1191 @@
1/*
2 * m32r_sio.c
3 *
4 * Driver for M32R serial ports
5 *
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 * Based on drivers/serial/8250.c.
8 *
9 * Copyright (C) 2001 Russell King.
10 * Copyright (C) 2004 Hirokazu Takata <takata at linux-m32r.org>
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 */
17
18/*
19 * A note about mapbase / membase
20 *
21 * mapbase is the physical address of the IO port. Currently, we don't
22 * support this very well, and it may well be dropped from this driver
23 * in future. As such, mapbase should be NULL.
24 *
25 * membase is an 'ioremapped' cookie. This is compatible with the old
26 * serial.c driver, and is currently the preferred form.
27 */
28
29#if defined(CONFIG_SERIAL_M32R_SIO_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
30#define SUPPORT_SYSRQ
31#endif
32
33#include <linux/module.h>
34#include <linux/tty.h>
35#include <linux/tty_flip.h>
36#include <linux/ioport.h>
37#include <linux/init.h>
38#include <linux/console.h>
39#include <linux/sysrq.h>
40#include <linux/serial.h>
41#include <linux/serialP.h>
42#include <linux/delay.h>
43
44#include <asm/m32r.h>
45#include <asm/io.h>
46#include <asm/irq.h>
47
48#define PORT_M32R_BASE PORT_M32R_SIO
49#define PORT_INDEX(x) (x - PORT_M32R_BASE + 1)
50#define BAUD_RATE 115200
51
52#include <linux/serial_core.h>
53#include "m32r_sio.h"
54#include "m32r_sio_reg.h"
55
56/*
57 * Debugging.
58 */
59#if 0
60#define DEBUG_AUTOCONF(fmt...) printk(fmt)
61#else
62#define DEBUG_AUTOCONF(fmt...) do { } while (0)
63#endif
64
65#if 0
66#define DEBUG_INTR(fmt...) printk(fmt)
67#else
68#define DEBUG_INTR(fmt...) do { } while (0)
69#endif
70
71#define PASS_LIMIT 256
72
73/*
74 * We default to IRQ0 for the "no irq" hack. Some
75 * machine types want others as well - they're free
76 * to redefine this in their header file.
77 */
78#define is_real_interrupt(irq) ((irq) != 0)
79
80#define BASE_BAUD 115200
81
82/* Standard COM flags */
83#define STD_COM_FLAGS (UPF_BOOT_AUTOCONF | UPF_SKIP_TEST)
84
85/*
86 * SERIAL_PORT_DFNS tells us about built-in ports that have no
87 * standard enumeration mechanism. Platforms that can find all
88 * serial ports via mechanisms like ACPI or PCI need not supply it.
89 */
90#if defined(CONFIG_PLAT_USRV)
91
92#define SERIAL_PORT_DFNS \
93 /* UART CLK PORT IRQ FLAGS */ \
94 { 0, BASE_BAUD, 0x3F8, PLD_IRQ_UART0, STD_COM_FLAGS }, /* ttyS0 */ \
95 { 0, BASE_BAUD, 0x2F8, PLD_IRQ_UART1, STD_COM_FLAGS }, /* ttyS1 */
96
97#else /* !CONFIG_PLAT_USRV */
98
99#if defined(CONFIG_SERIAL_M32R_PLDSIO)
100#define SERIAL_PORT_DFNS \
101 { 0, BASE_BAUD, ((unsigned long)PLD_ESIO0CR), PLD_IRQ_SIO0_RCV, \
102 STD_COM_FLAGS }, /* ttyS0 */
103#else
104#define SERIAL_PORT_DFNS \
105 { 0, BASE_BAUD, M32R_SIO_OFFSET, M32R_IRQ_SIO0_R, \
106 STD_COM_FLAGS }, /* ttyS0 */
107#endif
108
109#endif /* !CONFIG_PLAT_USRV */
110
111static struct old_serial_port old_serial_port[] = {
112 SERIAL_PORT_DFNS
113};
114
115#define UART_NR ARRAY_SIZE(old_serial_port)
116
117struct uart_sio_port {
118 struct uart_port port;
119 struct timer_list timer; /* "no irq" timer */
120 struct list_head list; /* ports on this IRQ */
121 unsigned short rev;
122 unsigned char acr;
123 unsigned char ier;
124 unsigned char lcr;
125 unsigned char mcr_mask; /* mask of user bits */
126 unsigned char mcr_force; /* mask of forced bits */
127 unsigned char lsr_break_flag;
128
129 /*
130 * We provide a per-port pm hook.
131 */
132 void (*pm)(struct uart_port *port,
133 unsigned int state, unsigned int old);
134};
135
136struct irq_info {
137 spinlock_t lock;
138 struct list_head *head;
139};
140
141static struct irq_info irq_lists[NR_IRQS];
142
143/*
144 * Here we define the default xmit fifo size used for each type of UART.
145 */
146static const struct serial_uart_config uart_config[] = {
147 [PORT_UNKNOWN] = {
148 .name = "unknown",
149 .dfl_xmit_fifo_size = 1,
150 .flags = 0,
151 },
152 [PORT_INDEX(PORT_M32R_SIO)] = {
153 .name = "M32RSIO",
154 .dfl_xmit_fifo_size = 1,
155 .flags = 0,
156 },
157};
158
159#ifdef CONFIG_SERIAL_M32R_PLDSIO
160
161#define __sio_in(x) inw((unsigned long)(x))
162#define __sio_out(v,x) outw((v),(unsigned long)(x))
163
164static inline void sio_set_baud_rate(unsigned long baud)
165{
166 unsigned short sbaud;
167 sbaud = (boot_cpu_data.bus_clock / (baud * 4))-1;
168 __sio_out(sbaud, PLD_ESIO0BAUR);
169}
170
171static void sio_reset(void)
172{
173 unsigned short tmp;
174
175 tmp = __sio_in(PLD_ESIO0RXB);
176 tmp = __sio_in(PLD_ESIO0RXB);
177 tmp = __sio_in(PLD_ESIO0CR);
178 sio_set_baud_rate(BAUD_RATE);
179 __sio_out(0x0300, PLD_ESIO0CR);
180 __sio_out(0x0003, PLD_ESIO0CR);
181}
182
183static void sio_init(void)
184{
185 unsigned short tmp;
186
187 tmp = __sio_in(PLD_ESIO0RXB);
188 tmp = __sio_in(PLD_ESIO0RXB);
189 tmp = __sio_in(PLD_ESIO0CR);
190 __sio_out(0x0300, PLD_ESIO0CR);
191 __sio_out(0x0003, PLD_ESIO0CR);
192}
193
194static void sio_error(int *status)
195{
196 printk("SIO0 error[%04x]\n", *status);
197 do {
198 sio_init();
199 } while ((*status = __sio_in(PLD_ESIO0CR)) != 3);
200}
201
202#else /* not CONFIG_SERIAL_M32R_PLDSIO */
203
204#define __sio_in(x) inl(x)
205#define __sio_out(v,x) outl((v),(x))
206
207static inline void sio_set_baud_rate(unsigned long baud)
208{
209 unsigned long i, j;
210
211 i = boot_cpu_data.bus_clock / (baud * 16);
212 j = (boot_cpu_data.bus_clock - (i * baud * 16)) / baud;
213 i -= 1;
214 j = (j + 1) >> 1;
215
216 __sio_out(i, M32R_SIO0_BAUR_PORTL);
217 __sio_out(j, M32R_SIO0_RBAUR_PORTL);
218}
219
220static void sio_reset(void)
221{
222 __sio_out(0x00000300, M32R_SIO0_CR_PORTL); /* init status */
223 __sio_out(0x00000800, M32R_SIO0_MOD1_PORTL); /* 8bit */
224 __sio_out(0x00000080, M32R_SIO0_MOD0_PORTL); /* 1stop non */
225 sio_set_baud_rate(BAUD_RATE);
226 __sio_out(0x00000000, M32R_SIO0_TRCR_PORTL);
227 __sio_out(0x00000003, M32R_SIO0_CR_PORTL); /* RXCEN */
228}
229
230static void sio_init(void)
231{
232 unsigned int tmp;
233
234 tmp = __sio_in(M32R_SIO0_RXB_PORTL);
235 tmp = __sio_in(M32R_SIO0_RXB_PORTL);
236 tmp = __sio_in(M32R_SIO0_STS_PORTL);
237 __sio_out(0x00000003, M32R_SIO0_CR_PORTL);
238}
239
240static void sio_error(int *status)
241{
242 printk("SIO0 error[%04x]\n", *status);
243 do {
244 sio_init();
245 } while ((*status = __sio_in(M32R_SIO0_CR_PORTL)) != 3);
246}
247
248#endif /* CONFIG_SERIAL_M32R_PLDSIO */
249
250static unsigned int sio_in(struct uart_sio_port *up, int offset)
251{
252 return __sio_in(up->port.iobase + offset);
253}
254
255static void sio_out(struct uart_sio_port *up, int offset, int value)
256{
257 __sio_out(value, up->port.iobase + offset);
258}
259
260static unsigned int serial_in(struct uart_sio_port *up, int offset)
261{
262 if (!offset)
263 return 0;
264
265 return __sio_in(offset);
266}
267
268static void serial_out(struct uart_sio_port *up, int offset, int value)
269{
270 if (!offset)
271 return;
272
273 __sio_out(value, offset);
274}
275
276static void m32r_sio_stop_tx(struct uart_port *port)
277{
278 struct uart_sio_port *up = (struct uart_sio_port *)port;
279
280 if (up->ier & UART_IER_THRI) {
281 up->ier &= ~UART_IER_THRI;
282 serial_out(up, UART_IER, up->ier);
283 }
284}
285
286static void m32r_sio_start_tx(struct uart_port *port)
287{
288#ifdef CONFIG_SERIAL_M32R_PLDSIO
289 struct uart_sio_port *up = (struct uart_sio_port *)port;
290 struct circ_buf *xmit = &up->port.state->xmit;
291
292 if (!(up->ier & UART_IER_THRI)) {
293 up->ier |= UART_IER_THRI;
294 serial_out(up, UART_IER, up->ier);
295 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
296 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
297 up->port.icount.tx++;
298 }
299 while((serial_in(up, UART_LSR) & UART_EMPTY) != UART_EMPTY);
300#else
301 struct uart_sio_port *up = (struct uart_sio_port *)port;
302
303 if (!(up->ier & UART_IER_THRI)) {
304 up->ier |= UART_IER_THRI;
305 serial_out(up, UART_IER, up->ier);
306 }
307#endif
308}
309
310static void m32r_sio_stop_rx(struct uart_port *port)
311{
312 struct uart_sio_port *up = (struct uart_sio_port *)port;
313
314 up->ier &= ~UART_IER_RLSI;
315 up->port.read_status_mask &= ~UART_LSR_DR;
316 serial_out(up, UART_IER, up->ier);
317}
318
319static void m32r_sio_enable_ms(struct uart_port *port)
320{
321 struct uart_sio_port *up = (struct uart_sio_port *)port;
322
323 up->ier |= UART_IER_MSI;
324 serial_out(up, UART_IER, up->ier);
325}
326
327static void receive_chars(struct uart_sio_port *up, int *status)
328{
329 struct tty_struct *tty = up->port.state->port.tty;
330 unsigned char ch;
331 unsigned char flag;
332 int max_count = 256;
333
334 do {
335 ch = sio_in(up, SIORXB);
336 flag = TTY_NORMAL;
337 up->port.icount.rx++;
338
339 if (unlikely(*status & (UART_LSR_BI | UART_LSR_PE |
340 UART_LSR_FE | UART_LSR_OE))) {
341 /*
342 * For statistics only
343 */
344 if (*status & UART_LSR_BI) {
345 *status &= ~(UART_LSR_FE | UART_LSR_PE);
346 up->port.icount.brk++;
347 /*
348 * We do the SysRQ and SAK checking
349 * here because otherwise the break
350 * may get masked by ignore_status_mask
351 * or read_status_mask.
352 */
353 if (uart_handle_break(&up->port))
354 goto ignore_char;
355 } else if (*status & UART_LSR_PE)
356 up->port.icount.parity++;
357 else if (*status & UART_LSR_FE)
358 up->port.icount.frame++;
359 if (*status & UART_LSR_OE)
360 up->port.icount.overrun++;
361
362 /*
363 * Mask off conditions which should be ingored.
364 */
365 *status &= up->port.read_status_mask;
366
367 if (up->port.line == up->port.cons->index) {
368 /* Recover the break flag from console xmit */
369 *status |= up->lsr_break_flag;
370 up->lsr_break_flag = 0;
371 }
372
373 if (*status & UART_LSR_BI) {
374 DEBUG_INTR("handling break....");
375 flag = TTY_BREAK;
376 } else if (*status & UART_LSR_PE)
377 flag = TTY_PARITY;
378 else if (*status & UART_LSR_FE)
379 flag = TTY_FRAME;
380 }
381 if (uart_handle_sysrq_char(&up->port, ch))
382 goto ignore_char;
383 if ((*status & up->port.ignore_status_mask) == 0)
384 tty_insert_flip_char(tty, ch, flag);
385
386 if (*status & UART_LSR_OE) {
387 /*
388 * Overrun is special, since it's reported
389 * immediately, and doesn't affect the current
390 * character.
391 */
392 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
393 }
394 ignore_char:
395 *status = serial_in(up, UART_LSR);
396 } while ((*status & UART_LSR_DR) && (max_count-- > 0));
397 tty_flip_buffer_push(tty);
398}
399
400static void transmit_chars(struct uart_sio_port *up)
401{
402 struct circ_buf *xmit = &up->port.state->xmit;
403 int count;
404
405 if (up->port.x_char) {
406#ifndef CONFIG_SERIAL_M32R_PLDSIO /* XXX */
407 serial_out(up, UART_TX, up->port.x_char);
408#endif
409 up->port.icount.tx++;
410 up->port.x_char = 0;
411 return;
412 }
413 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
414 m32r_sio_stop_tx(&up->port);
415 return;
416 }
417
418 count = up->port.fifosize;
419 do {
420 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
421 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
422 up->port.icount.tx++;
423 if (uart_circ_empty(xmit))
424 break;
425 while (!(serial_in(up, UART_LSR) & UART_LSR_THRE));
426
427 } while (--count > 0);
428
429 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
430 uart_write_wakeup(&up->port);
431
432 DEBUG_INTR("THRE...");
433
434 if (uart_circ_empty(xmit))
435 m32r_sio_stop_tx(&up->port);
436}
437
438/*
439 * This handles the interrupt from one port.
440 */
441static inline void m32r_sio_handle_port(struct uart_sio_port *up,
442 unsigned int status)
443{
444 DEBUG_INTR("status = %x...", status);
445
446 if (status & 0x04)
447 receive_chars(up, &status);
448 if (status & 0x01)
449 transmit_chars(up);
450}
451
452/*
453 * This is the serial driver's interrupt routine.
454 *
455 * Arjan thinks the old way was overly complex, so it got simplified.
456 * Alan disagrees, saying that need the complexity to handle the weird
457 * nature of ISA shared interrupts. (This is a special exception.)
458 *
459 * In order to handle ISA shared interrupts properly, we need to check
460 * that all ports have been serviced, and therefore the ISA interrupt
461 * line has been de-asserted.
462 *
463 * This means we need to loop through all ports. checking that they
464 * don't have an interrupt pending.
465 */
466static irqreturn_t m32r_sio_interrupt(int irq, void *dev_id)
467{
468 struct irq_info *i = dev_id;
469 struct list_head *l, *end = NULL;
470 int pass_counter = 0;
471
472 DEBUG_INTR("m32r_sio_interrupt(%d)...", irq);
473
474#ifdef CONFIG_SERIAL_M32R_PLDSIO
475// if (irq == PLD_IRQ_SIO0_SND)
476// irq = PLD_IRQ_SIO0_RCV;
477#else
478 if (irq == M32R_IRQ_SIO0_S)
479 irq = M32R_IRQ_SIO0_R;
480#endif
481
482 spin_lock(&i->lock);
483
484 l = i->head;
485 do {
486 struct uart_sio_port *up;
487 unsigned int sts;
488
489 up = list_entry(l, struct uart_sio_port, list);
490
491 sts = sio_in(up, SIOSTS);
492 if (sts & 0x5) {
493 spin_lock(&up->port.lock);
494 m32r_sio_handle_port(up, sts);
495 spin_unlock(&up->port.lock);
496
497 end = NULL;
498 } else if (end == NULL)
499 end = l;
500
501 l = l->next;
502
503 if (l == i->head && pass_counter++ > PASS_LIMIT) {
504 if (sts & 0xe0)
505 sio_error(&sts);
506 break;
507 }
508 } while (l != end);
509
510 spin_unlock(&i->lock);
511
512 DEBUG_INTR("end.\n");
513
514 return IRQ_HANDLED;
515}
516
517/*
518 * To support ISA shared interrupts, we need to have one interrupt
519 * handler that ensures that the IRQ line has been deasserted
520 * before returning. Failing to do this will result in the IRQ
521 * line being stuck active, and, since ISA irqs are edge triggered,
522 * no more IRQs will be seen.
523 */
524static void serial_do_unlink(struct irq_info *i, struct uart_sio_port *up)
525{
526 spin_lock_irq(&i->lock);
527
528 if (!list_empty(i->head)) {
529 if (i->head == &up->list)
530 i->head = i->head->next;
531 list_del(&up->list);
532 } else {
533 BUG_ON(i->head != &up->list);
534 i->head = NULL;
535 }
536
537 spin_unlock_irq(&i->lock);
538}
539
540static int serial_link_irq_chain(struct uart_sio_port *up)
541{
542 struct irq_info *i = irq_lists + up->port.irq;
543 int ret, irq_flags = 0;
544
545 spin_lock_irq(&i->lock);
546
547 if (i->head) {
548 list_add(&up->list, i->head);
549 spin_unlock_irq(&i->lock);
550
551 ret = 0;
552 } else {
553 INIT_LIST_HEAD(&up->list);
554 i->head = &up->list;
555 spin_unlock_irq(&i->lock);
556
557 ret = request_irq(up->port.irq, m32r_sio_interrupt,
558 irq_flags, "SIO0-RX", i);
559 ret |= request_irq(up->port.irq + 1, m32r_sio_interrupt,
560 irq_flags, "SIO0-TX", i);
561 if (ret < 0)
562 serial_do_unlink(i, up);
563 }
564
565 return ret;
566}
567
568static void serial_unlink_irq_chain(struct uart_sio_port *up)
569{
570 struct irq_info *i = irq_lists + up->port.irq;
571
572 BUG_ON(i->head == NULL);
573
574 if (list_empty(i->head)) {
575 free_irq(up->port.irq, i);
576 free_irq(up->port.irq + 1, i);
577 }
578
579 serial_do_unlink(i, up);
580}
581
582/*
583 * This function is used to handle ports that do not have an interrupt.
584 */
585static void m32r_sio_timeout(unsigned long data)
586{
587 struct uart_sio_port *up = (struct uart_sio_port *)data;
588 unsigned int timeout;
589 unsigned int sts;
590
591 sts = sio_in(up, SIOSTS);
592 if (sts & 0x5) {
593 spin_lock(&up->port.lock);
594 m32r_sio_handle_port(up, sts);
595 spin_unlock(&up->port.lock);
596 }
597
598 timeout = up->port.timeout;
599 timeout = timeout > 6 ? (timeout / 2 - 2) : 1;
600 mod_timer(&up->timer, jiffies + timeout);
601}
602
603static unsigned int m32r_sio_tx_empty(struct uart_port *port)
604{
605 struct uart_sio_port *up = (struct uart_sio_port *)port;
606 unsigned long flags;
607 unsigned int ret;
608
609 spin_lock_irqsave(&up->port.lock, flags);
610 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
611 spin_unlock_irqrestore(&up->port.lock, flags);
612
613 return ret;
614}
615
616static unsigned int m32r_sio_get_mctrl(struct uart_port *port)
617{
618 return 0;
619}
620
621static void m32r_sio_set_mctrl(struct uart_port *port, unsigned int mctrl)
622{
623
624}
625
626static void m32r_sio_break_ctl(struct uart_port *port, int break_state)
627{
628
629}
630
631static int m32r_sio_startup(struct uart_port *port)
632{
633 struct uart_sio_port *up = (struct uart_sio_port *)port;
634 int retval;
635
636 sio_init();
637
638 /*
639 * If the "interrupt" for this port doesn't correspond with any
640 * hardware interrupt, we use a timer-based system. The original
641 * driver used to do this with IRQ0.
642 */
643 if (!is_real_interrupt(up->port.irq)) {
644 unsigned int timeout = up->port.timeout;
645
646 timeout = timeout > 6 ? (timeout / 2 - 2) : 1;
647
648 up->timer.data = (unsigned long)up;
649 mod_timer(&up->timer, jiffies + timeout);
650 } else {
651 retval = serial_link_irq_chain(up);
652 if (retval)
653 return retval;
654 }
655
656 /*
657 * Finally, enable interrupts. Note: Modem status interrupts
658 * are set via set_termios(), which will be occurring imminently
659 * anyway, so we don't enable them here.
660 * - M32R_SIO: 0x0c
661 * - M32R_PLDSIO: 0x04
662 */
663 up->ier = UART_IER_MSI | UART_IER_RLSI | UART_IER_RDI;
664 sio_out(up, SIOTRCR, up->ier);
665
666 /*
667 * And clear the interrupt registers again for luck.
668 */
669 sio_reset();
670
671 return 0;
672}
673
674static void m32r_sio_shutdown(struct uart_port *port)
675{
676 struct uart_sio_port *up = (struct uart_sio_port *)port;
677
678 /*
679 * Disable interrupts from this port
680 */
681 up->ier = 0;
682 sio_out(up, SIOTRCR, 0);
683
684 /*
685 * Disable break condition and FIFOs
686 */
687
688 sio_init();
689
690 if (!is_real_interrupt(up->port.irq))
691 del_timer_sync(&up->timer);
692 else
693 serial_unlink_irq_chain(up);
694}
695
696static unsigned int m32r_sio_get_divisor(struct uart_port *port,
697 unsigned int baud)
698{
699 return uart_get_divisor(port, baud);
700}
701
702static void m32r_sio_set_termios(struct uart_port *port,
703 struct ktermios *termios, struct ktermios *old)
704{
705 struct uart_sio_port *up = (struct uart_sio_port *)port;
706 unsigned char cval = 0;
707 unsigned long flags;
708 unsigned int baud, quot;
709
710 switch (termios->c_cflag & CSIZE) {
711 case CS5:
712 cval = UART_LCR_WLEN5;
713 break;
714 case CS6:
715 cval = UART_LCR_WLEN6;
716 break;
717 case CS7:
718 cval = UART_LCR_WLEN7;
719 break;
720 default:
721 case CS8:
722 cval = UART_LCR_WLEN8;
723 break;
724 }
725
726 if (termios->c_cflag & CSTOPB)
727 cval |= UART_LCR_STOP;
728 if (termios->c_cflag & PARENB)
729 cval |= UART_LCR_PARITY;
730 if (!(termios->c_cflag & PARODD))
731 cval |= UART_LCR_EPAR;
732#ifdef CMSPAR
733 if (termios->c_cflag & CMSPAR)
734 cval |= UART_LCR_SPAR;
735#endif
736
737 /*
738 * Ask the core to calculate the divisor for us.
739 */
740#ifdef CONFIG_SERIAL_M32R_PLDSIO
741 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/4);
742#else
743 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
744#endif
745 quot = m32r_sio_get_divisor(port, baud);
746
747 /*
748 * Ok, we're now changing the port state. Do it with
749 * interrupts disabled.
750 */
751 spin_lock_irqsave(&up->port.lock, flags);
752
753 sio_set_baud_rate(baud);
754
755 /*
756 * Update the per-port timeout.
757 */
758 uart_update_timeout(port, termios->c_cflag, baud);
759
760 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
761 if (termios->c_iflag & INPCK)
762 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
763 if (termios->c_iflag & (BRKINT | PARMRK))
764 up->port.read_status_mask |= UART_LSR_BI;
765
766 /*
767 * Characteres to ignore
768 */
769 up->port.ignore_status_mask = 0;
770 if (termios->c_iflag & IGNPAR)
771 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
772 if (termios->c_iflag & IGNBRK) {
773 up->port.ignore_status_mask |= UART_LSR_BI;
774 /*
775 * If we're ignoring parity and break indicators,
776 * ignore overruns too (for real raw support).
777 */
778 if (termios->c_iflag & IGNPAR)
779 up->port.ignore_status_mask |= UART_LSR_OE;
780 }
781
782 /*
783 * ignore all characters if CREAD is not set
784 */
785 if ((termios->c_cflag & CREAD) == 0)
786 up->port.ignore_status_mask |= UART_LSR_DR;
787
788 /*
789 * CTS flow control flag and modem status interrupts
790 */
791 up->ier &= ~UART_IER_MSI;
792 if (UART_ENABLE_MS(&up->port, termios->c_cflag))
793 up->ier |= UART_IER_MSI;
794
795 serial_out(up, UART_IER, up->ier);
796
797 up->lcr = cval; /* Save LCR */
798 spin_unlock_irqrestore(&up->port.lock, flags);
799}
800
801static void m32r_sio_pm(struct uart_port *port, unsigned int state,
802 unsigned int oldstate)
803{
804 struct uart_sio_port *up = (struct uart_sio_port *)port;
805
806 if (up->pm)
807 up->pm(port, state, oldstate);
808}
809
810/*
811 * Resource handling. This is complicated by the fact that resources
812 * depend on the port type. Maybe we should be claiming the standard
813 * 8250 ports, and then trying to get other resources as necessary?
814 */
815static int
816m32r_sio_request_std_resource(struct uart_sio_port *up, struct resource **res)
817{
818 unsigned int size = 8 << up->port.regshift;
819#ifndef CONFIG_SERIAL_M32R_PLDSIO
820 unsigned long start;
821#endif
822 int ret = 0;
823
824 switch (up->port.iotype) {
825 case UPIO_MEM:
826 if (up->port.mapbase) {
827#ifdef CONFIG_SERIAL_M32R_PLDSIO
828 *res = request_mem_region(up->port.mapbase, size, "serial");
829#else
830 start = up->port.mapbase;
831 *res = request_mem_region(start, size, "serial");
832#endif
833 if (!*res)
834 ret = -EBUSY;
835 }
836 break;
837
838 case UPIO_PORT:
839 *res = request_region(up->port.iobase, size, "serial");
840 if (!*res)
841 ret = -EBUSY;
842 break;
843 }
844 return ret;
845}
846
847static void m32r_sio_release_port(struct uart_port *port)
848{
849 struct uart_sio_port *up = (struct uart_sio_port *)port;
850 unsigned long start, offset = 0, size = 0;
851
852 size <<= up->port.regshift;
853
854 switch (up->port.iotype) {
855 case UPIO_MEM:
856 if (up->port.mapbase) {
857 /*
858 * Unmap the area.
859 */
860 iounmap(up->port.membase);
861 up->port.membase = NULL;
862
863 start = up->port.mapbase;
864
865 if (size)
866 release_mem_region(start + offset, size);
867 release_mem_region(start, 8 << up->port.regshift);
868 }
869 break;
870
871 case UPIO_PORT:
872 start = up->port.iobase;
873
874 if (size)
875 release_region(start + offset, size);
876 release_region(start + offset, 8 << up->port.regshift);
877 break;
878
879 default:
880 break;
881 }
882}
883
884static int m32r_sio_request_port(struct uart_port *port)
885{
886 struct uart_sio_port *up = (struct uart_sio_port *)port;
887 struct resource *res = NULL;
888 int ret = 0;
889
890 ret = m32r_sio_request_std_resource(up, &res);
891
892 /*
893 * If we have a mapbase, then request that as well.
894 */
895 if (ret == 0 && up->port.flags & UPF_IOREMAP) {
896 int size = resource_size(res);
897
898 up->port.membase = ioremap(up->port.mapbase, size);
899 if (!up->port.membase)
900 ret = -ENOMEM;
901 }
902
903 if (ret < 0) {
904 if (res)
905 release_resource(res);
906 }
907
908 return ret;
909}
910
911static void m32r_sio_config_port(struct uart_port *port, int unused)
912{
913 struct uart_sio_port *up = (struct uart_sio_port *)port;
914 unsigned long flags;
915
916 spin_lock_irqsave(&up->port.lock, flags);
917
918 up->port.type = (PORT_M32R_SIO - PORT_M32R_BASE + 1);
919 up->port.fifosize = uart_config[up->port.type].dfl_xmit_fifo_size;
920
921 spin_unlock_irqrestore(&up->port.lock, flags);
922}
923
924static int
925m32r_sio_verify_port(struct uart_port *port, struct serial_struct *ser)
926{
927 if (ser->irq >= nr_irqs || ser->irq < 0 ||
928 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
929 ser->type >= ARRAY_SIZE(uart_config))
930 return -EINVAL;
931 return 0;
932}
933
934static const char *
935m32r_sio_type(struct uart_port *port)
936{
937 int type = port->type;
938
939 if (type >= ARRAY_SIZE(uart_config))
940 type = 0;
941 return uart_config[type].name;
942}
943
944static struct uart_ops m32r_sio_pops = {
945 .tx_empty = m32r_sio_tx_empty,
946 .set_mctrl = m32r_sio_set_mctrl,
947 .get_mctrl = m32r_sio_get_mctrl,
948 .stop_tx = m32r_sio_stop_tx,
949 .start_tx = m32r_sio_start_tx,
950 .stop_rx = m32r_sio_stop_rx,
951 .enable_ms = m32r_sio_enable_ms,
952 .break_ctl = m32r_sio_break_ctl,
953 .startup = m32r_sio_startup,
954 .shutdown = m32r_sio_shutdown,
955 .set_termios = m32r_sio_set_termios,
956 .pm = m32r_sio_pm,
957 .type = m32r_sio_type,
958 .release_port = m32r_sio_release_port,
959 .request_port = m32r_sio_request_port,
960 .config_port = m32r_sio_config_port,
961 .verify_port = m32r_sio_verify_port,
962};
963
964static struct uart_sio_port m32r_sio_ports[UART_NR];
965
966static void __init m32r_sio_init_ports(void)
967{
968 struct uart_sio_port *up;
969 static int first = 1;
970 int i;
971
972 if (!first)
973 return;
974 first = 0;
975
976 for (i = 0, up = m32r_sio_ports; i < ARRAY_SIZE(old_serial_port);
977 i++, up++) {
978 up->port.iobase = old_serial_port[i].port;
979 up->port.irq = irq_canonicalize(old_serial_port[i].irq);
980 up->port.uartclk = old_serial_port[i].baud_base * 16;
981 up->port.flags = old_serial_port[i].flags;
982 up->port.membase = old_serial_port[i].iomem_base;
983 up->port.iotype = old_serial_port[i].io_type;
984 up->port.regshift = old_serial_port[i].iomem_reg_shift;
985 up->port.ops = &m32r_sio_pops;
986 }
987}
988
989static void __init m32r_sio_register_ports(struct uart_driver *drv)
990{
991 int i;
992
993 m32r_sio_init_ports();
994
995 for (i = 0; i < UART_NR; i++) {
996 struct uart_sio_port *up = &m32r_sio_ports[i];
997
998 up->port.line = i;
999 up->port.ops = &m32r_sio_pops;
1000 init_timer(&up->timer);
1001 up->timer.function = m32r_sio_timeout;
1002
1003 up->mcr_mask = ~0;
1004 up->mcr_force = 0;
1005
1006 uart_add_one_port(drv, &up->port);
1007 }
1008}
1009
1010#ifdef CONFIG_SERIAL_M32R_SIO_CONSOLE
1011
1012/*
1013 * Wait for transmitter & holding register to empty
1014 */
1015static inline void wait_for_xmitr(struct uart_sio_port *up)
1016{
1017 unsigned int status, tmout = 10000;
1018
1019 /* Wait up to 10ms for the character(s) to be sent. */
1020 do {
1021 status = sio_in(up, SIOSTS);
1022
1023 if (--tmout == 0)
1024 break;
1025 udelay(1);
1026 } while ((status & UART_EMPTY) != UART_EMPTY);
1027
1028 /* Wait up to 1s for flow control if necessary */
1029 if (up->port.flags & UPF_CONS_FLOW) {
1030 tmout = 1000000;
1031 while (--tmout)
1032 udelay(1);
1033 }
1034}
1035
1036static void m32r_sio_console_putchar(struct uart_port *port, int ch)
1037{
1038 struct uart_sio_port *up = (struct uart_sio_port *)port;
1039
1040 wait_for_xmitr(up);
1041 sio_out(up, SIOTXB, ch);
1042}
1043
1044/*
1045 * Print a string to the serial port trying not to disturb
1046 * any possible real use of the port...
1047 *
1048 * The console_lock must be held when we get here.
1049 */
1050static void m32r_sio_console_write(struct console *co, const char *s,
1051 unsigned int count)
1052{
1053 struct uart_sio_port *up = &m32r_sio_ports[co->index];
1054 unsigned int ier;
1055
1056 /*
1057 * First save the UER then disable the interrupts
1058 */
1059 ier = sio_in(up, SIOTRCR);
1060 sio_out(up, SIOTRCR, 0);
1061
1062 uart_console_write(&up->port, s, count, m32r_sio_console_putchar);
1063
1064 /*
1065 * Finally, wait for transmitter to become empty
1066 * and restore the IER
1067 */
1068 wait_for_xmitr(up);
1069 sio_out(up, SIOTRCR, ier);
1070}
1071
1072static int __init m32r_sio_console_setup(struct console *co, char *options)
1073{
1074 struct uart_port *port;
1075 int baud = 9600;
1076 int bits = 8;
1077 int parity = 'n';
1078 int flow = 'n';
1079
1080 /*
1081 * Check whether an invalid uart number has been specified, and
1082 * if so, search for the first available port that does have
1083 * console support.
1084 */
1085 if (co->index >= UART_NR)
1086 co->index = 0;
1087 port = &m32r_sio_ports[co->index].port;
1088
1089 /*
1090 * Temporary fix.
1091 */
1092 spin_lock_init(&port->lock);
1093
1094 if (options)
1095 uart_parse_options(options, &baud, &parity, &bits, &flow);
1096
1097 return uart_set_options(port, co, baud, parity, bits, flow);
1098}
1099
1100static struct uart_driver m32r_sio_reg;
1101static struct console m32r_sio_console = {
1102 .name = "ttyS",
1103 .write = m32r_sio_console_write,
1104 .device = uart_console_device,
1105 .setup = m32r_sio_console_setup,
1106 .flags = CON_PRINTBUFFER,
1107 .index = -1,
1108 .data = &m32r_sio_reg,
1109};
1110
1111static int __init m32r_sio_console_init(void)
1112{
1113 sio_reset();
1114 sio_init();
1115 m32r_sio_init_ports();
1116 register_console(&m32r_sio_console);
1117 return 0;
1118}
1119console_initcall(m32r_sio_console_init);
1120
1121#define M32R_SIO_CONSOLE &m32r_sio_console
1122#else
1123#define M32R_SIO_CONSOLE NULL
1124#endif
1125
1126static struct uart_driver m32r_sio_reg = {
1127 .owner = THIS_MODULE,
1128 .driver_name = "sio",
1129 .dev_name = "ttyS",
1130 .major = TTY_MAJOR,
1131 .minor = 64,
1132 .nr = UART_NR,
1133 .cons = M32R_SIO_CONSOLE,
1134};
1135
1136/**
1137 * m32r_sio_suspend_port - suspend one serial port
1138 * @line: serial line number
1139 *
1140 * Suspend one serial port.
1141 */
1142void m32r_sio_suspend_port(int line)
1143{
1144 uart_suspend_port(&m32r_sio_reg, &m32r_sio_ports[line].port);
1145}
1146
1147/**
1148 * m32r_sio_resume_port - resume one serial port
1149 * @line: serial line number
1150 *
1151 * Resume one serial port.
1152 */
1153void m32r_sio_resume_port(int line)
1154{
1155 uart_resume_port(&m32r_sio_reg, &m32r_sio_ports[line].port);
1156}
1157
1158static int __init m32r_sio_init(void)
1159{
1160 int ret, i;
1161
1162 printk(KERN_INFO "Serial: M32R SIO driver\n");
1163
1164 for (i = 0; i < nr_irqs; i++)
1165 spin_lock_init(&irq_lists[i].lock);
1166
1167 ret = uart_register_driver(&m32r_sio_reg);
1168 if (ret >= 0)
1169 m32r_sio_register_ports(&m32r_sio_reg);
1170
1171 return ret;
1172}
1173
1174static void __exit m32r_sio_exit(void)
1175{
1176 int i;
1177
1178 for (i = 0; i < UART_NR; i++)
1179 uart_remove_one_port(&m32r_sio_reg, &m32r_sio_ports[i].port);
1180
1181 uart_unregister_driver(&m32r_sio_reg);
1182}
1183
1184module_init(m32r_sio_init);
1185module_exit(m32r_sio_exit);
1186
1187EXPORT_SYMBOL(m32r_sio_suspend_port);
1188EXPORT_SYMBOL(m32r_sio_resume_port);
1189
1190MODULE_LICENSE("GPL");
1191MODULE_DESCRIPTION("Generic M32R SIO serial driver");
diff --git a/drivers/tty/serial/8250/m32r_sio.h b/drivers/tty/serial/8250/m32r_sio.h
new file mode 100644
index 000000000000..e9b7e11793b1
--- /dev/null
+++ b/drivers/tty/serial/8250/m32r_sio.h
@@ -0,0 +1,48 @@
1/*
2 * m32r_sio.h
3 *
4 * Driver for M32R serial ports
5 *
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 * Based on drivers/serial/8250.h.
8 *
9 * Copyright (C) 2001 Russell King.
10 * Copyright (C) 2004 Hirokazu Takata <takata at linux-m32r.org>
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 */
17
18
19struct m32r_sio_probe {
20 struct module *owner;
21 int (*pci_init_one)(struct pci_dev *dev);
22 void (*pci_remove_one)(struct pci_dev *dev);
23 void (*pnp_init)(void);
24};
25
26int m32r_sio_register_probe(struct m32r_sio_probe *probe);
27void m32r_sio_unregister_probe(struct m32r_sio_probe *probe);
28void m32r_sio_get_irq_map(unsigned int *map);
29void m32r_sio_suspend_port(int line);
30void m32r_sio_resume_port(int line);
31
32struct old_serial_port {
33 unsigned int uart;
34 unsigned int baud_base;
35 unsigned int port;
36 unsigned int irq;
37 unsigned int flags;
38 unsigned char io_type;
39 unsigned char __iomem *iomem_base;
40 unsigned short iomem_reg_shift;
41};
42
43#define _INLINE_ inline
44
45#define PROBE_RSA (1 << 0)
46#define PROBE_ANY (~0)
47
48#define HIGH_BITS_OFFSET ((sizeof(long)-sizeof(int))*8)
diff --git a/drivers/tty/serial/8250/m32r_sio_reg.h b/drivers/tty/serial/8250/m32r_sio_reg.h
new file mode 100644
index 000000000000..4671473793e3
--- /dev/null
+++ b/drivers/tty/serial/8250/m32r_sio_reg.h
@@ -0,0 +1,152 @@
1/*
2 * m32r_sio_reg.h
3 *
4 * Copyright (C) 1992, 1994 by Theodore Ts'o.
5 * Copyright (C) 2004 Hirokazu Takata <takata at linux-m32r.org>
6 *
7 * Redistribution of this file is permitted under the terms of the GNU
8 * Public License (GPL)
9 *
10 * These are the UART port assignments, expressed as offsets from the base
11 * register. These assignments should hold for any serial port based on
12 * a 8250, 16450, or 16550(A).
13 */
14
15#ifndef _M32R_SIO_REG_H
16#define _M32R_SIO_REG_H
17
18
19#ifdef CONFIG_SERIAL_M32R_PLDSIO
20
21#define SIOCR 0x000
22#define SIOMOD0 0x002
23#define SIOMOD1 0x004
24#define SIOSTS 0x006
25#define SIOTRCR 0x008
26#define SIOBAUR 0x00a
27// #define SIORBAUR 0x018
28#define SIOTXB 0x00c
29#define SIORXB 0x00e
30
31#define UART_RX ((unsigned long) PLD_ESIO0RXB)
32 /* In: Receive buffer (DLAB=0) */
33#define UART_TX ((unsigned long) PLD_ESIO0TXB)
34 /* Out: Transmit buffer (DLAB=0) */
35#define UART_DLL 0 /* Out: Divisor Latch Low (DLAB=1) */
36#define UART_TRG 0 /* (LCR=BF) FCTR bit 7 selects Rx or Tx
37 * In: Fifo count
38 * Out: Fifo custom trigger levels
39 * XR16C85x only */
40
41#define UART_DLM 0 /* Out: Divisor Latch High (DLAB=1) */
42#define UART_IER ((unsigned long) PLD_ESIO0INTCR)
43 /* Out: Interrupt Enable Register */
44#define UART_FCTR 0 /* (LCR=BF) Feature Control Register
45 * XR16C85x only */
46
47#define UART_IIR 0 /* In: Interrupt ID Register */
48#define UART_FCR 0 /* Out: FIFO Control Register */
49#define UART_EFR 0 /* I/O: Extended Features Register */
50 /* (DLAB=1, 16C660 only) */
51
52#define UART_LCR 0 /* Out: Line Control Register */
53#define UART_MCR 0 /* Out: Modem Control Register */
54#define UART_LSR ((unsigned long) PLD_ESIO0STS)
55 /* In: Line Status Register */
56#define UART_MSR 0 /* In: Modem Status Register */
57#define UART_SCR 0 /* I/O: Scratch Register */
58#define UART_EMSR 0 /* (LCR=BF) Extended Mode Select Register
59 * FCTR bit 6 selects SCR or EMSR
60 * XR16c85x only */
61
62#else /* not CONFIG_SERIAL_M32R_PLDSIO */
63
64#define SIOCR 0x000
65#define SIOMOD0 0x004
66#define SIOMOD1 0x008
67#define SIOSTS 0x00c
68#define SIOTRCR 0x010
69#define SIOBAUR 0x014
70#define SIORBAUR 0x018
71#define SIOTXB 0x01c
72#define SIORXB 0x020
73
74#define UART_RX M32R_SIO0_RXB_PORTL /* In: Receive buffer (DLAB=0) */
75#define UART_TX M32R_SIO0_TXB_PORTL /* Out: Transmit buffer (DLAB=0) */
76#define UART_DLL 0 /* Out: Divisor Latch Low (DLAB=1) */
77#define UART_TRG 0 /* (LCR=BF) FCTR bit 7 selects Rx or Tx
78 * In: Fifo count
79 * Out: Fifo custom trigger levels
80 * XR16C85x only */
81
82#define UART_DLM 0 /* Out: Divisor Latch High (DLAB=1) */
83#define UART_IER M32R_SIO0_TRCR_PORTL /* Out: Interrupt Enable Register */
84#define UART_FCTR 0 /* (LCR=BF) Feature Control Register
85 * XR16C85x only */
86
87#define UART_IIR 0 /* In: Interrupt ID Register */
88#define UART_FCR 0 /* Out: FIFO Control Register */
89#define UART_EFR 0 /* I/O: Extended Features Register */
90 /* (DLAB=1, 16C660 only) */
91
92#define UART_LCR 0 /* Out: Line Control Register */
93#define UART_MCR 0 /* Out: Modem Control Register */
94#define UART_LSR M32R_SIO0_STS_PORTL /* In: Line Status Register */
95#define UART_MSR 0 /* In: Modem Status Register */
96#define UART_SCR 0 /* I/O: Scratch Register */
97#define UART_EMSR 0 /* (LCR=BF) Extended Mode Select Register
98 * FCTR bit 6 selects SCR or EMSR
99 * XR16c85x only */
100
101#endif /* CONFIG_SERIAL_M32R_PLDSIO */
102
103#define UART_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
104
105/*
106 * These are the definitions for the Line Control Register
107 *
108 * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting
109 * UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits.
110 */
111#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
112#define UART_LCR_SBC 0x40 /* Set break control */
113#define UART_LCR_SPAR 0x20 /* Stick parity (?) */
114#define UART_LCR_EPAR 0x10 /* Even parity select */
115#define UART_LCR_PARITY 0x08 /* Parity Enable */
116#define UART_LCR_STOP 0x04 /* Stop bits: 0=1 stop bit, 1= 2 stop bits */
117#define UART_LCR_WLEN5 0x00 /* Wordlength: 5 bits */
118#define UART_LCR_WLEN6 0x01 /* Wordlength: 6 bits */
119#define UART_LCR_WLEN7 0x02 /* Wordlength: 7 bits */
120#define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */
121
122/*
123 * These are the definitions for the Line Status Register
124 */
125#define UART_LSR_TEMT 0x02 /* Transmitter empty */
126#define UART_LSR_THRE 0x01 /* Transmit-hold-register empty */
127#define UART_LSR_BI 0x00 /* Break interrupt indicator */
128#define UART_LSR_FE 0x80 /* Frame error indicator */
129#define UART_LSR_PE 0x40 /* Parity error indicator */
130#define UART_LSR_OE 0x20 /* Overrun error indicator */
131#define UART_LSR_DR 0x04 /* Receiver data ready */
132
133/*
134 * These are the definitions for the Interrupt Identification Register
135 */
136#define UART_IIR_NO_INT 0x01 /* No interrupts pending */
137#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
138
139#define UART_IIR_MSI 0x00 /* Modem status interrupt */
140#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
141#define UART_IIR_RDI 0x04 /* Receiver data interrupt */
142#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
143
144/*
145 * These are the definitions for the Interrupt Enable Register
146 */
147#define UART_IER_MSI 0x00 /* Enable Modem status interrupt */
148#define UART_IER_RLSI 0x08 /* Enable receiver line status interrupt */
149#define UART_IER_THRI 0x03 /* Enable Transmitter holding register int. */
150#define UART_IER_RDI 0x04 /* Enable receiver data interrupt */
151
152#endif /* _M32R_SIO_REG_H */
diff --git a/drivers/tty/serial/8250/serial_cs.c b/drivers/tty/serial/8250/serial_cs.c
new file mode 100644
index 000000000000..86090605a84e
--- /dev/null
+++ b/drivers/tty/serial/8250/serial_cs.c
@@ -0,0 +1,870 @@
1/*======================================================================
2
3 A driver for PCMCIA serial devices
4
5 serial_cs.c 1.134 2002/05/04 05:48:53
6
7 The contents of this file are subject to the Mozilla Public
8 License Version 1.1 (the "License"); you may not use this file
9 except in compliance with the License. You may obtain a copy of
10 the License at http://www.mozilla.org/MPL/
11
12 Software distributed under the License is distributed on an "AS
13 IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
14 implied. See the License for the specific language governing
15 rights and limitations under the License.
16
17 The initial developer of the original code is David A. Hinds
18 <dahinds@users.sourceforge.net>. Portions created by David A. Hinds
19 are Copyright (C) 1999 David A. Hinds. All Rights Reserved.
20
21 Alternatively, the contents of this file may be used under the
22 terms of the GNU General Public License version 2 (the "GPL"), in which
23 case the provisions of the GPL are applicable instead of the
24 above. If you wish to allow the use of your version of this file
25 only under the terms of the GPL and not to allow others to use
26 your version of this file under the MPL, indicate your decision
27 by deleting the provisions above and replace them with the notice
28 and other provisions required by the GPL. If you do not delete
29 the provisions above, a recipient may use your version of this
30 file under either the MPL or the GPL.
31
32======================================================================*/
33
34#include <linux/module.h>
35#include <linux/moduleparam.h>
36#include <linux/kernel.h>
37#include <linux/init.h>
38#include <linux/ptrace.h>
39#include <linux/slab.h>
40#include <linux/string.h>
41#include <linux/timer.h>
42#include <linux/serial_core.h>
43#include <linux/delay.h>
44#include <linux/major.h>
45#include <asm/io.h>
46#include <asm/system.h>
47
48#include <pcmcia/cistpl.h>
49#include <pcmcia/ciscode.h>
50#include <pcmcia/ds.h>
51#include <pcmcia/cisreg.h>
52
53#include "8250.h"
54
55
56/*====================================================================*/
57
58/* Parameters that can be set with 'insmod' */
59
60/* Enable the speaker? */
61static int do_sound = 1;
62/* Skip strict UART tests? */
63static int buggy_uart;
64
65module_param(do_sound, int, 0444);
66module_param(buggy_uart, int, 0444);
67
68/*====================================================================*/
69
70/* Table of multi-port card ID's */
71
72struct serial_quirk {
73 unsigned int manfid;
74 unsigned int prodid;
75 int multi; /* 1 = multifunction, > 1 = # ports */
76 void (*config)(struct pcmcia_device *);
77 void (*setup)(struct pcmcia_device *, struct uart_port *);
78 void (*wakeup)(struct pcmcia_device *);
79 int (*post)(struct pcmcia_device *);
80};
81
82struct serial_info {
83 struct pcmcia_device *p_dev;
84 int ndev;
85 int multi;
86 int slave;
87 int manfid;
88 int prodid;
89 int c950ctrl;
90 int line[4];
91 const struct serial_quirk *quirk;
92};
93
94struct serial_cfg_mem {
95 tuple_t tuple;
96 cisparse_t parse;
97 u_char buf[256];
98};
99
100/*
101 * vers_1 5.0, "Brain Boxes", "2-Port RS232 card", "r6"
102 * manfid 0x0160, 0x0104
103 * This card appears to have a 14.7456MHz clock.
104 */
105/* Generic Modem: MD55x (GPRS/EDGE) have
106 * Elan VPU16551 UART with 14.7456MHz oscillator
107 * manfid 0x015D, 0x4C45
108 */
109static void quirk_setup_brainboxes_0104(struct pcmcia_device *link, struct uart_port *port)
110{
111 port->uartclk = 14745600;
112}
113
114static int quirk_post_ibm(struct pcmcia_device *link)
115{
116 u8 val;
117 int ret;
118
119 ret = pcmcia_read_config_byte(link, 0x800, &val);
120 if (ret)
121 goto failed;
122
123 ret = pcmcia_write_config_byte(link, 0x800, val | 1);
124 if (ret)
125 goto failed;
126 return 0;
127
128 failed:
129 return -ENODEV;
130}
131
132/*
133 * Nokia cards are not really multiport cards. Shouldn't this
134 * be handled by setting the quirk entry .multi = 0 | 1 ?
135 */
136static void quirk_config_nokia(struct pcmcia_device *link)
137{
138 struct serial_info *info = link->priv;
139
140 if (info->multi > 1)
141 info->multi = 1;
142}
143
144static void quirk_wakeup_oxsemi(struct pcmcia_device *link)
145{
146 struct serial_info *info = link->priv;
147
148 if (info->c950ctrl)
149 outb(12, info->c950ctrl + 1);
150}
151
152/* request_region? oxsemi branch does no request_region too... */
153/*
154 * This sequence is needed to properly initialize MC45 attached to OXCF950.
155 * I tried decreasing these msleep()s, but it worked properly (survived
156 * 1000 stop/start operations) with these timeouts (or bigger).
157 */
158static void quirk_wakeup_possio_gcc(struct pcmcia_device *link)
159{
160 struct serial_info *info = link->priv;
161 unsigned int ctrl = info->c950ctrl;
162
163 outb(0xA, ctrl + 1);
164 msleep(100);
165 outb(0xE, ctrl + 1);
166 msleep(300);
167 outb(0xC, ctrl + 1);
168 msleep(100);
169 outb(0xE, ctrl + 1);
170 msleep(200);
171 outb(0xF, ctrl + 1);
172 msleep(100);
173 outb(0xE, ctrl + 1);
174 msleep(100);
175 outb(0xC, ctrl + 1);
176}
177
178/*
179 * Socket Dual IO: this enables irq's for second port
180 */
181static void quirk_config_socket(struct pcmcia_device *link)
182{
183 struct serial_info *info = link->priv;
184
185 if (info->multi)
186 link->config_flags |= CONF_ENABLE_ESR;
187}
188
189static const struct serial_quirk quirks[] = {
190 {
191 .manfid = 0x0160,
192 .prodid = 0x0104,
193 .multi = -1,
194 .setup = quirk_setup_brainboxes_0104,
195 }, {
196 .manfid = 0x015D,
197 .prodid = 0x4C45,
198 .multi = -1,
199 .setup = quirk_setup_brainboxes_0104,
200 }, {
201 .manfid = MANFID_IBM,
202 .prodid = ~0,
203 .multi = -1,
204 .post = quirk_post_ibm,
205 }, {
206 .manfid = MANFID_INTEL,
207 .prodid = PRODID_INTEL_DUAL_RS232,
208 .multi = 2,
209 }, {
210 .manfid = MANFID_NATINST,
211 .prodid = PRODID_NATINST_QUAD_RS232,
212 .multi = 4,
213 }, {
214 .manfid = MANFID_NOKIA,
215 .prodid = ~0,
216 .multi = -1,
217 .config = quirk_config_nokia,
218 }, {
219 .manfid = MANFID_OMEGA,
220 .prodid = PRODID_OMEGA_QSP_100,
221 .multi = 4,
222 }, {
223 .manfid = MANFID_OXSEMI,
224 .prodid = ~0,
225 .multi = -1,
226 .wakeup = quirk_wakeup_oxsemi,
227 }, {
228 .manfid = MANFID_POSSIO,
229 .prodid = PRODID_POSSIO_GCC,
230 .multi = -1,
231 .wakeup = quirk_wakeup_possio_gcc,
232 }, {
233 .manfid = MANFID_QUATECH,
234 .prodid = PRODID_QUATECH_DUAL_RS232,
235 .multi = 2,
236 }, {
237 .manfid = MANFID_QUATECH,
238 .prodid = PRODID_QUATECH_DUAL_RS232_D1,
239 .multi = 2,
240 }, {
241 .manfid = MANFID_QUATECH,
242 .prodid = PRODID_QUATECH_DUAL_RS232_G,
243 .multi = 2,
244 }, {
245 .manfid = MANFID_QUATECH,
246 .prodid = PRODID_QUATECH_QUAD_RS232,
247 .multi = 4,
248 }, {
249 .manfid = MANFID_SOCKET,
250 .prodid = PRODID_SOCKET_DUAL_RS232,
251 .multi = 2,
252 .config = quirk_config_socket,
253 }, {
254 .manfid = MANFID_SOCKET,
255 .prodid = ~0,
256 .multi = -1,
257 .config = quirk_config_socket,
258 }
259};
260
261
262static int serial_config(struct pcmcia_device * link);
263
264
265static void serial_remove(struct pcmcia_device *link)
266{
267 struct serial_info *info = link->priv;
268 int i;
269
270 dev_dbg(&link->dev, "serial_release\n");
271
272 /*
273 * Recheck to see if the device is still configured.
274 */
275 for (i = 0; i < info->ndev; i++)
276 serial8250_unregister_port(info->line[i]);
277
278 if (!info->slave)
279 pcmcia_disable_device(link);
280}
281
282static int serial_suspend(struct pcmcia_device *link)
283{
284 struct serial_info *info = link->priv;
285 int i;
286
287 for (i = 0; i < info->ndev; i++)
288 serial8250_suspend_port(info->line[i]);
289
290 return 0;
291}
292
293static int serial_resume(struct pcmcia_device *link)
294{
295 struct serial_info *info = link->priv;
296 int i;
297
298 for (i = 0; i < info->ndev; i++)
299 serial8250_resume_port(info->line[i]);
300
301 if (info->quirk && info->quirk->wakeup)
302 info->quirk->wakeup(link);
303
304 return 0;
305}
306
307static int serial_probe(struct pcmcia_device *link)
308{
309 struct serial_info *info;
310
311 dev_dbg(&link->dev, "serial_attach()\n");
312
313 /* Create new serial device */
314 info = kzalloc(sizeof (*info), GFP_KERNEL);
315 if (!info)
316 return -ENOMEM;
317 info->p_dev = link;
318 link->priv = info;
319
320 link->config_flags |= CONF_ENABLE_IRQ | CONF_AUTO_SET_IO;
321 if (do_sound)
322 link->config_flags |= CONF_ENABLE_SPKR;
323
324 return serial_config(link);
325}
326
327static void serial_detach(struct pcmcia_device *link)
328{
329 struct serial_info *info = link->priv;
330
331 dev_dbg(&link->dev, "serial_detach\n");
332
333 /*
334 * Ensure that the ports have been released.
335 */
336 serial_remove(link);
337
338 /* free bits */
339 kfree(info);
340}
341
342/*====================================================================*/
343
344static int setup_serial(struct pcmcia_device *handle, struct serial_info * info,
345 unsigned int iobase, int irq)
346{
347 struct uart_port port;
348 int line;
349
350 memset(&port, 0, sizeof (struct uart_port));
351 port.iobase = iobase;
352 port.irq = irq;
353 port.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_SHARE_IRQ;
354 port.uartclk = 1843200;
355 port.dev = &handle->dev;
356 if (buggy_uart)
357 port.flags |= UPF_BUGGY_UART;
358
359 if (info->quirk && info->quirk->setup)
360 info->quirk->setup(handle, &port);
361
362 line = serial8250_register_port(&port);
363 if (line < 0) {
364 printk(KERN_NOTICE "serial_cs: serial8250_register_port() at "
365 "0x%04lx, irq %d failed\n", (u_long)iobase, irq);
366 return -EINVAL;
367 }
368
369 info->line[info->ndev] = line;
370 info->ndev++;
371
372 return 0;
373}
374
375/*====================================================================*/
376
377static int pfc_config(struct pcmcia_device *p_dev)
378{
379 unsigned int port = 0;
380 struct serial_info *info = p_dev->priv;
381
382 if ((p_dev->resource[1]->end != 0) &&
383 (resource_size(p_dev->resource[1]) == 8)) {
384 port = p_dev->resource[1]->start;
385 info->slave = 1;
386 } else if ((info->manfid == MANFID_OSITECH) &&
387 (resource_size(p_dev->resource[0]) == 0x40)) {
388 port = p_dev->resource[0]->start + 0x28;
389 info->slave = 1;
390 }
391 if (info->slave)
392 return setup_serial(p_dev, info, port, p_dev->irq);
393
394 dev_warn(&p_dev->dev, "no usable port range found, giving up\n");
395 return -ENODEV;
396}
397
398static int simple_config_check(struct pcmcia_device *p_dev, void *priv_data)
399{
400 static const int size_table[2] = { 8, 16 };
401 int *try = priv_data;
402
403 if (p_dev->resource[0]->start == 0)
404 return -ENODEV;
405
406 if ((*try & 0x1) == 0)
407 p_dev->io_lines = 16;
408
409 if (p_dev->resource[0]->end != size_table[(*try >> 1)])
410 return -ENODEV;
411
412 p_dev->resource[0]->end = 8;
413 p_dev->resource[0]->flags &= ~IO_DATA_PATH_WIDTH;
414 p_dev->resource[0]->flags |= IO_DATA_PATH_WIDTH_8;
415
416 return pcmcia_request_io(p_dev);
417}
418
419static int simple_config_check_notpicky(struct pcmcia_device *p_dev,
420 void *priv_data)
421{
422 static const unsigned int base[5] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8, 0x0 };
423 int j;
424
425 if (p_dev->io_lines > 3)
426 return -ENODEV;
427
428 p_dev->resource[0]->flags &= ~IO_DATA_PATH_WIDTH;
429 p_dev->resource[0]->flags |= IO_DATA_PATH_WIDTH_8;
430 p_dev->resource[0]->end = 8;
431
432 for (j = 0; j < 5; j++) {
433 p_dev->resource[0]->start = base[j];
434 p_dev->io_lines = base[j] ? 16 : 3;
435 if (!pcmcia_request_io(p_dev))
436 return 0;
437 }
438 return -ENODEV;
439}
440
441static int simple_config(struct pcmcia_device *link)
442{
443 struct serial_info *info = link->priv;
444 int i = -ENODEV, try;
445
446 /* First pass: look for a config entry that looks normal.
447 * Two tries: without IO aliases, then with aliases */
448 link->config_flags |= CONF_AUTO_SET_VPP;
449 for (try = 0; try < 4; try++)
450 if (!pcmcia_loop_config(link, simple_config_check, &try))
451 goto found_port;
452
453 /* Second pass: try to find an entry that isn't picky about
454 its base address, then try to grab any standard serial port
455 address, and finally try to get any free port. */
456 if (!pcmcia_loop_config(link, simple_config_check_notpicky, NULL))
457 goto found_port;
458
459 dev_warn(&link->dev, "no usable port range found, giving up\n");
460 return -1;
461
462found_port:
463 if (info->multi && (info->manfid == MANFID_3COM))
464 link->config_index &= ~(0x08);
465
466 /*
467 * Apply any configuration quirks.
468 */
469 if (info->quirk && info->quirk->config)
470 info->quirk->config(link);
471
472 i = pcmcia_enable_device(link);
473 if (i != 0)
474 return -1;
475 return setup_serial(link, info, link->resource[0]->start, link->irq);
476}
477
478static int multi_config_check(struct pcmcia_device *p_dev, void *priv_data)
479{
480 int *multi = priv_data;
481
482 if (p_dev->resource[1]->end)
483 return -EINVAL;
484
485 /* The quad port cards have bad CIS's, so just look for a
486 window larger than 8 ports and assume it will be right */
487 if (p_dev->resource[0]->end <= 8)
488 return -EINVAL;
489
490 p_dev->resource[0]->flags &= ~IO_DATA_PATH_WIDTH;
491 p_dev->resource[0]->flags |= IO_DATA_PATH_WIDTH_8;
492 p_dev->resource[0]->end = *multi * 8;
493
494 if (pcmcia_request_io(p_dev))
495 return -ENODEV;
496 return 0;
497}
498
499static int multi_config_check_notpicky(struct pcmcia_device *p_dev,
500 void *priv_data)
501{
502 int *base2 = priv_data;
503
504 if (!p_dev->resource[0]->end || !p_dev->resource[1]->end ||
505 p_dev->resource[0]->start + 8 != p_dev->resource[1]->start)
506 return -ENODEV;
507
508 p_dev->resource[0]->end = p_dev->resource[1]->end = 8;
509 p_dev->resource[0]->flags &= ~IO_DATA_PATH_WIDTH;
510 p_dev->resource[0]->flags |= IO_DATA_PATH_WIDTH_8;
511
512 if (pcmcia_request_io(p_dev))
513 return -ENODEV;
514
515 *base2 = p_dev->resource[0]->start + 8;
516 return 0;
517}
518
519static int multi_config(struct pcmcia_device *link)
520{
521 struct serial_info *info = link->priv;
522 int i, base2 = 0;
523
524 /* First, look for a generic full-sized window */
525 if (!pcmcia_loop_config(link, multi_config_check, &info->multi))
526 base2 = link->resource[0]->start + 8;
527 else {
528 /* If that didn't work, look for two windows */
529 info->multi = 2;
530 if (pcmcia_loop_config(link, multi_config_check_notpicky,
531 &base2)) {
532 dev_warn(&link->dev, "no usable port range "
533 "found, giving up\n");
534 return -ENODEV;
535 }
536 }
537
538 if (!link->irq)
539 dev_warn(&link->dev, "no usable IRQ found, continuing...\n");
540
541 /*
542 * Apply any configuration quirks.
543 */
544 if (info->quirk && info->quirk->config)
545 info->quirk->config(link);
546
547 i = pcmcia_enable_device(link);
548 if (i != 0)
549 return -ENODEV;
550
551 /* The Oxford Semiconductor OXCF950 cards are in fact single-port:
552 * 8 registers are for the UART, the others are extra registers.
553 * Siemen's MC45 PCMCIA (Possio's GCC) is OXCF950 based too.
554 */
555 if (info->manfid == MANFID_OXSEMI || (info->manfid == MANFID_POSSIO &&
556 info->prodid == PRODID_POSSIO_GCC)) {
557 int err;
558
559 if (link->config_index == 1 ||
560 link->config_index == 3) {
561 err = setup_serial(link, info, base2,
562 link->irq);
563 base2 = link->resource[0]->start;
564 } else {
565 err = setup_serial(link, info, link->resource[0]->start,
566 link->irq);
567 }
568 info->c950ctrl = base2;
569
570 /*
571 * FIXME: We really should wake up the port prior to
572 * handing it over to the serial layer.
573 */
574 if (info->quirk && info->quirk->wakeup)
575 info->quirk->wakeup(link);
576
577 return 0;
578 }
579
580 setup_serial(link, info, link->resource[0]->start, link->irq);
581 for (i = 0; i < info->multi - 1; i++)
582 setup_serial(link, info, base2 + (8 * i),
583 link->irq);
584 return 0;
585}
586
587static int serial_check_for_multi(struct pcmcia_device *p_dev, void *priv_data)
588{
589 struct serial_info *info = p_dev->priv;
590
591 if (!p_dev->resource[0]->end)
592 return -EINVAL;
593
594 if ((!p_dev->resource[1]->end) && (p_dev->resource[0]->end % 8 == 0))
595 info->multi = p_dev->resource[0]->end >> 3;
596
597 if ((p_dev->resource[1]->end) && (p_dev->resource[0]->end == 8)
598 && (p_dev->resource[1]->end == 8))
599 info->multi = 2;
600
601 return 0; /* break */
602}
603
604
605static int serial_config(struct pcmcia_device * link)
606{
607 struct serial_info *info = link->priv;
608 int i;
609
610 dev_dbg(&link->dev, "serial_config\n");
611
612 /* Is this a compliant multifunction card? */
613 info->multi = (link->socket->functions > 1);
614
615 /* Is this a multiport card? */
616 info->manfid = link->manf_id;
617 info->prodid = link->card_id;
618
619 for (i = 0; i < ARRAY_SIZE(quirks); i++)
620 if ((quirks[i].manfid == ~0 ||
621 quirks[i].manfid == info->manfid) &&
622 (quirks[i].prodid == ~0 ||
623 quirks[i].prodid == info->prodid)) {
624 info->quirk = &quirks[i];
625 break;
626 }
627
628 /* Another check for dual-serial cards: look for either serial or
629 multifunction cards that ask for appropriate IO port ranges */
630 if ((info->multi == 0) &&
631 (link->has_func_id) &&
632 (link->socket->pcmcia_pfc == 0) &&
633 ((link->func_id == CISTPL_FUNCID_MULTI) ||
634 (link->func_id == CISTPL_FUNCID_SERIAL)))
635 pcmcia_loop_config(link, serial_check_for_multi, info);
636
637 /*
638 * Apply any multi-port quirk.
639 */
640 if (info->quirk && info->quirk->multi != -1)
641 info->multi = info->quirk->multi;
642
643 dev_info(&link->dev,
644 "trying to set up [0x%04x:0x%04x] (pfc: %d, multi: %d, quirk: %p)\n",
645 link->manf_id, link->card_id,
646 link->socket->pcmcia_pfc, info->multi, info->quirk);
647 if (link->socket->pcmcia_pfc)
648 i = pfc_config(link);
649 else if (info->multi > 1)
650 i = multi_config(link);
651 else
652 i = simple_config(link);
653
654 if (i || info->ndev == 0)
655 goto failed;
656
657 /*
658 * Apply any post-init quirk. FIXME: This should really happen
659 * before we register the port, since it might already be in use.
660 */
661 if (info->quirk && info->quirk->post)
662 if (info->quirk->post(link))
663 goto failed;
664
665 return 0;
666
667failed:
668 dev_warn(&link->dev, "failed to initialize\n");
669 serial_remove(link);
670 return -ENODEV;
671}
672
673static const struct pcmcia_device_id serial_ids[] = {
674 PCMCIA_PFC_DEVICE_MANF_CARD(1, 0x0057, 0x0021),
675 PCMCIA_PFC_DEVICE_MANF_CARD(1, 0x0089, 0x110a),
676 PCMCIA_PFC_DEVICE_MANF_CARD(1, 0x0104, 0x000a),
677 PCMCIA_PFC_DEVICE_MANF_CARD(1, 0x0105, 0x0d0a),
678 PCMCIA_PFC_DEVICE_MANF_CARD(1, 0x0105, 0x0e0a),
679 PCMCIA_PFC_DEVICE_MANF_CARD(1, 0x0105, 0xea15),
680 PCMCIA_PFC_DEVICE_MANF_CARD(1, 0x0109, 0x0501),
681 PCMCIA_PFC_DEVICE_MANF_CARD(1, 0x0138, 0x110a),
682 PCMCIA_PFC_DEVICE_MANF_CARD(1, 0x0140, 0x000a),
683 PCMCIA_PFC_DEVICE_MANF_CARD(1, 0x0143, 0x3341),
684 PCMCIA_PFC_DEVICE_MANF_CARD(1, 0x0143, 0xc0ab),
685 PCMCIA_PFC_DEVICE_MANF_CARD(1, 0x016c, 0x0081),
686 PCMCIA_PFC_DEVICE_MANF_CARD(1, 0x021b, 0x0101),
687 PCMCIA_PFC_DEVICE_MANF_CARD(1, 0x08a1, 0xc0ab),
688 PCMCIA_PFC_DEVICE_PROD_ID123(1, "MEGAHERTZ", "CC/XJEM3288", "DATA/FAX/CELL ETHERNET MODEM", 0xf510db04, 0x04cd2988, 0x46a52d63),
689 PCMCIA_PFC_DEVICE_PROD_ID123(1, "MEGAHERTZ", "CC/XJEM3336", "DATA/FAX/CELL ETHERNET MODEM", 0xf510db04, 0x0143b773, 0x46a52d63),
690 PCMCIA_PFC_DEVICE_PROD_ID123(1, "MEGAHERTZ", "EM1144T", "PCMCIA MODEM", 0xf510db04, 0x856d66c8, 0xbd6c43ef),
691 PCMCIA_PFC_DEVICE_PROD_ID123(1, "MEGAHERTZ", "XJEM1144/CCEM1144", "PCMCIA MODEM", 0xf510db04, 0x52d21e1e, 0xbd6c43ef),
692 PCMCIA_PFC_DEVICE_PROD_ID13(1, "Xircom", "CEM28", 0x2e3ee845, 0x0ea978ea),
693 PCMCIA_PFC_DEVICE_PROD_ID13(1, "Xircom", "CEM33", 0x2e3ee845, 0x80609023),
694 PCMCIA_PFC_DEVICE_PROD_ID13(1, "Xircom", "CEM56", 0x2e3ee845, 0xa650c32a),
695 PCMCIA_PFC_DEVICE_PROD_ID13(1, "Xircom", "REM10", 0x2e3ee845, 0x76df1d29),
696 PCMCIA_PFC_DEVICE_PROD_ID13(1, "Xircom", "XEM5600", 0x2e3ee845, 0xf1403719),
697 PCMCIA_PFC_DEVICE_PROD_ID12(1, "AnyCom", "Fast Ethernet + 56K COMBO", 0x578ba6e7, 0xb0ac62c4),
698 PCMCIA_PFC_DEVICE_PROD_ID12(1, "ATKK", "LM33-PCM-T", 0xba9eb7e2, 0x077c174e),
699 PCMCIA_PFC_DEVICE_PROD_ID12(1, "D-Link", "DME336T", 0x1a424a1c, 0xb23897ff),
700 PCMCIA_PFC_DEVICE_PROD_ID12(1, "Gateway 2000", "XJEM3336", 0xdd9989be, 0x662c394c),
701 PCMCIA_PFC_DEVICE_PROD_ID12(1, "Grey Cell", "GCS3000", 0x2a151fac, 0x48b932ae),
702 PCMCIA_PFC_DEVICE_PROD_ID12(1, "Linksys", "EtherFast 10&100 + 56K PC Card (PCMLM56)", 0x0733cc81, 0xb3765033),
703 PCMCIA_PFC_DEVICE_PROD_ID12(1, "LINKSYS", "PCMLM336", 0xf7cb0b07, 0x7a821b58),
704 PCMCIA_PFC_DEVICE_PROD_ID12(1, "MEGAHERTZ", "XJEM1144/CCEM1144", 0xf510db04, 0x52d21e1e),
705 PCMCIA_PFC_DEVICE_PROD_ID12(1, "MICRO RESEARCH", "COMBO-L/M-336", 0xb2ced065, 0x3ced0555),
706 PCMCIA_PFC_DEVICE_PROD_ID12(1, "NEC", "PK-UG-J001" ,0x18df0ba0 ,0x831b1064),
707 PCMCIA_PFC_DEVICE_PROD_ID12(1, "Ositech", "Trumpcard:Jack of Diamonds Modem+Ethernet", 0xc2f80cd, 0x656947b9),
708 PCMCIA_PFC_DEVICE_PROD_ID12(1, "Ositech", "Trumpcard:Jack of Hearts Modem+Ethernet", 0xc2f80cd, 0xdc9ba5ed),
709 PCMCIA_PFC_DEVICE_PROD_ID12(1, "PCMCIAs", "ComboCard", 0xdcfe12d3, 0xcd8906cc),
710 PCMCIA_PFC_DEVICE_PROD_ID12(1, "PCMCIAs", "LanModem", 0xdcfe12d3, 0xc67c648f),
711 PCMCIA_PFC_DEVICE_PROD_ID12(1, "TDK", "GlobalNetworker 3410/3412", 0x1eae9475, 0xd9a93bed),
712 PCMCIA_PFC_DEVICE_PROD_ID12(1, "Xircom", "CreditCard Ethernet+Modem II", 0x2e3ee845, 0xeca401bf),
713 PCMCIA_PFC_DEVICE_MANF_CARD(1, 0x0032, 0x0e01),
714 PCMCIA_PFC_DEVICE_MANF_CARD(1, 0x0032, 0x0a05),
715 PCMCIA_PFC_DEVICE_MANF_CARD(1, 0x0032, 0x0b05),
716 PCMCIA_PFC_DEVICE_MANF_CARD(1, 0x0032, 0x1101),
717 PCMCIA_MFC_DEVICE_MANF_CARD(0, 0x0104, 0x0070),
718 PCMCIA_MFC_DEVICE_MANF_CARD(1, 0x0101, 0x0562),
719 PCMCIA_MFC_DEVICE_MANF_CARD(1, 0x0104, 0x0070),
720 PCMCIA_MFC_DEVICE_MANF_CARD(1, 0x016c, 0x0020),
721 PCMCIA_MFC_DEVICE_PROD_ID123(1, "APEX DATA", "MULTICARD", "ETHERNET-MODEM", 0x11c2da09, 0x7289dc5d, 0xaad95e1f),
722 PCMCIA_MFC_DEVICE_PROD_ID12(1, "IBM", "Home and Away 28.8 PC Card ", 0xb569a6e5, 0x5bd4ff2c),
723 PCMCIA_MFC_DEVICE_PROD_ID12(1, "IBM", "Home and Away Credit Card Adapter", 0xb569a6e5, 0x4bdf15c3),
724 PCMCIA_MFC_DEVICE_PROD_ID12(1, "IBM", "w95 Home and Away Credit Card ", 0xb569a6e5, 0xae911c15),
725 PCMCIA_MFC_DEVICE_PROD_ID1(1, "Motorola MARQUIS", 0xf03e4e77),
726 PCMCIA_MFC_DEVICE_PROD_ID2(1, "FAX/Modem/Ethernet Combo Card ", 0x1ed59302),
727 PCMCIA_DEVICE_MANF_CARD(0x0089, 0x0301),
728 PCMCIA_DEVICE_MANF_CARD(0x00a4, 0x0276),
729 PCMCIA_DEVICE_MANF_CARD(0x0101, 0x0039),
730 PCMCIA_DEVICE_MANF_CARD(0x0104, 0x0006),
731 PCMCIA_DEVICE_MANF_CARD(0x0105, 0x0101), /* TDK DF2814 */
732 PCMCIA_DEVICE_MANF_CARD(0x0105, 0x100a), /* Xircom CM-56G */
733 PCMCIA_DEVICE_MANF_CARD(0x0105, 0x3e0a), /* TDK DF5660 */
734 PCMCIA_DEVICE_MANF_CARD(0x0105, 0x410a),
735 PCMCIA_DEVICE_MANF_CARD(0x0107, 0x0002), /* USRobotics 14,400 */
736 PCMCIA_DEVICE_MANF_CARD(0x010b, 0x0d50),
737 PCMCIA_DEVICE_MANF_CARD(0x010b, 0x0d51),
738 PCMCIA_DEVICE_MANF_CARD(0x010b, 0x0d52),
739 PCMCIA_DEVICE_MANF_CARD(0x010b, 0x0d53),
740 PCMCIA_DEVICE_MANF_CARD(0x010b, 0xd180),
741 PCMCIA_DEVICE_MANF_CARD(0x0115, 0x3330), /* USRobotics/SUN 14,400 */
742 PCMCIA_DEVICE_MANF_CARD(0x0124, 0x0100), /* Nokia DTP-2 ver II */
743 PCMCIA_DEVICE_MANF_CARD(0x0134, 0x5600), /* LASAT COMMUNICATIONS A/S */
744 PCMCIA_DEVICE_MANF_CARD(0x0137, 0x000e),
745 PCMCIA_DEVICE_MANF_CARD(0x0137, 0x001b),
746 PCMCIA_DEVICE_MANF_CARD(0x0137, 0x0025),
747 PCMCIA_DEVICE_MANF_CARD(0x0137, 0x0045),
748 PCMCIA_DEVICE_MANF_CARD(0x0137, 0x0052),
749 PCMCIA_DEVICE_MANF_CARD(0x016c, 0x0006), /* Psion 56K+Fax */
750 PCMCIA_DEVICE_MANF_CARD(0x0200, 0x0001), /* MultiMobile */
751 PCMCIA_DEVICE_PROD_ID134("ADV", "TECH", "COMpad-32/85", 0x67459937, 0x916d02ba, 0x8fbe92ae),
752 PCMCIA_DEVICE_PROD_ID124("GATEWAY2000", "CC3144", "PCMCIA MODEM", 0x506bccae, 0xcb3685f1, 0xbd6c43ef),
753 PCMCIA_DEVICE_PROD_ID14("MEGAHERTZ", "PCMCIA MODEM", 0xf510db04, 0xbd6c43ef),
754 PCMCIA_DEVICE_PROD_ID124("TOSHIBA", "T144PF", "PCMCIA MODEM", 0xb4585a1a, 0x7271409c, 0xbd6c43ef),
755 PCMCIA_DEVICE_PROD_ID123("FUJITSU", "FC14F ", "MBH10213", 0x6ee5a3d8, 0x30ead12b, 0xb00f05a0),
756 PCMCIA_DEVICE_PROD_ID123("Novatel Wireless", "Merlin UMTS Modem", "U630", 0x32607776, 0xd9e73b13, 0xe87332e),
757 PCMCIA_DEVICE_PROD_ID13("MEGAHERTZ", "V.34 PCMCIA MODEM", 0xf510db04, 0xbb2cce4a),
758 PCMCIA_DEVICE_PROD_ID12("Brain Boxes", "Bluetooth PC Card", 0xee138382, 0xd4ce9b02),
759 PCMCIA_DEVICE_PROD_ID12("CIRRUS LOGIC", "FAX MODEM", 0xe625f451, 0xcecd6dfa),
760 PCMCIA_DEVICE_PROD_ID12("COMPAQ", "PCMCIA 28800 FAX/DATA MODEM", 0xa3a3062c, 0x8cbd7c76),
761 PCMCIA_DEVICE_PROD_ID12("COMPAQ", "PCMCIA 33600 FAX/DATA MODEM", 0xa3a3062c, 0x5a00ce95),
762 PCMCIA_DEVICE_PROD_ID12("Computerboards, Inc.", "PCM-COM422", 0xd0b78f51, 0x7e2d49ed),
763 PCMCIA_DEVICE_PROD_ID12("Dr. Neuhaus", "FURY CARD 14K4", 0x76942813, 0x8b96ce65),
764 PCMCIA_DEVICE_PROD_ID12("IBM", "ISDN/56K/GSM", 0xb569a6e5, 0xfee5297b),
765 PCMCIA_DEVICE_PROD_ID12("Intelligent", "ANGIA FAX/MODEM", 0xb496e65e, 0xf31602a6),
766 PCMCIA_DEVICE_PROD_ID12("Intel", "MODEM 2400+", 0x816cc815, 0x412729fb),
767 PCMCIA_DEVICE_PROD_ID12("Intertex", "IX34-PCMCIA", 0xf8a097e3, 0x97880447),
768 PCMCIA_DEVICE_PROD_ID12("IOTech Inc ", "PCMCIA Dual RS-232 Serial Port Card", 0x3bd2d898, 0x92abc92f),
769 PCMCIA_DEVICE_PROD_ID12("MACRONIX", "FAX/MODEM", 0x668388b3, 0x3f9bdf2f),
770 PCMCIA_DEVICE_PROD_ID12("Multi-Tech", "MT1432LT", 0x5f73be51, 0x0b3e2383),
771 PCMCIA_DEVICE_PROD_ID12("Multi-Tech", "MT2834LT", 0x5f73be51, 0x4cd7c09e),
772 PCMCIA_DEVICE_PROD_ID12("OEM ", "C288MX ", 0xb572d360, 0xd2385b7a),
773 PCMCIA_DEVICE_PROD_ID12("Option International", "V34bis GSM/PSTN Data/Fax Modem", 0x9d7cd6f5, 0x5cb8bf41),
774 PCMCIA_DEVICE_PROD_ID12("PCMCIA ", "C336MX ", 0x99bcafe9, 0xaa25bcab),
775 PCMCIA_DEVICE_PROD_ID12("Quatech Inc", "PCMCIA Dual RS-232 Serial Port Card", 0xc4420b35, 0x92abc92f),
776 PCMCIA_DEVICE_PROD_ID12("Quatech Inc", "Dual RS-232 Serial Port PC Card", 0xc4420b35, 0x031a380d),
777 PCMCIA_DEVICE_PROD_ID12("Telia", "SurfinBird 560P/A+", 0xe2cdd5e, 0xc9314b38),
778 PCMCIA_DEVICE_PROD_ID1("Smart Serial Port", 0x2d8ce292),
779 PCMCIA_PFC_DEVICE_CIS_PROD_ID12(1, "PCMCIA", "EN2218-LAN/MODEM", 0x281f1c5d, 0x570f348e, "cis/PCMLM28.cis"),
780 PCMCIA_PFC_DEVICE_CIS_PROD_ID12(1, "PCMCIA", "UE2218-LAN/MODEM", 0x281f1c5d, 0x6fdcacee, "cis/PCMLM28.cis"),
781 PCMCIA_PFC_DEVICE_CIS_PROD_ID12(1, "Psion Dacom", "Gold Card V34 Ethernet", 0xf5f025c2, 0x338e8155, "cis/PCMLM28.cis"),
782 PCMCIA_PFC_DEVICE_CIS_PROD_ID12(1, "Psion Dacom", "Gold Card V34 Ethernet GSM", 0xf5f025c2, 0x4ae85d35, "cis/PCMLM28.cis"),
783 PCMCIA_PFC_DEVICE_CIS_PROD_ID12(1, "LINKSYS", "PCMLM28", 0xf7cb0b07, 0x66881874, "cis/PCMLM28.cis"),
784 PCMCIA_PFC_DEVICE_CIS_PROD_ID12(1, "TOSHIBA", "Modem/LAN Card", 0xb4585a1a, 0x53f922f8, "cis/PCMLM28.cis"),
785 PCMCIA_MFC_DEVICE_CIS_PROD_ID12(1, "DAYNA COMMUNICATIONS", "LAN AND MODEM MULTIFUNCTION", 0x8fdf8f89, 0xdd5ed9e8, "cis/DP83903.cis"),
786 PCMCIA_MFC_DEVICE_CIS_PROD_ID4(1, "NSC MF LAN/Modem", 0x58fc6056, "cis/DP83903.cis"),
787 PCMCIA_MFC_DEVICE_CIS_MANF_CARD(1, 0x0101, 0x0556, "cis/3CCFEM556.cis"),
788 PCMCIA_MFC_DEVICE_CIS_MANF_CARD(1, 0x0175, 0x0000, "cis/DP83903.cis"),
789 PCMCIA_MFC_DEVICE_CIS_MANF_CARD(1, 0x0101, 0x0035, "cis/3CXEM556.cis"),
790 PCMCIA_MFC_DEVICE_CIS_MANF_CARD(1, 0x0101, 0x003d, "cis/3CXEM556.cis"),
791 PCMCIA_DEVICE_CIS_PROD_ID12("Sierra Wireless", "AC850", 0xd85f6206, 0x42a2c018, "cis/SW_8xx_SER.cis"), /* Sierra Wireless AC850 3G Network Adapter R1 */
792 PCMCIA_DEVICE_CIS_PROD_ID12("Sierra Wireless", "AC860", 0xd85f6206, 0x698f93db, "cis/SW_8xx_SER.cis"), /* Sierra Wireless AC860 3G Network Adapter R1 */
793 PCMCIA_DEVICE_CIS_PROD_ID12("Sierra Wireless", "AC710/AC750", 0xd85f6206, 0x761b11e0, "cis/SW_7xx_SER.cis"), /* Sierra Wireless AC710/AC750 GPRS Network Adapter R1 */
794 PCMCIA_DEVICE_CIS_MANF_CARD(0x0192, 0xa555, "cis/SW_555_SER.cis"), /* Sierra Aircard 555 CDMA 1xrtt Modem -- pre update */
795 PCMCIA_DEVICE_CIS_MANF_CARD(0x013f, 0xa555, "cis/SW_555_SER.cis"), /* Sierra Aircard 555 CDMA 1xrtt Modem -- post update */
796 PCMCIA_DEVICE_CIS_PROD_ID12("MultiTech", "PCMCIA 56K DataFax", 0x842047ee, 0xc2efcf03, "cis/MT5634ZLX.cis"),
797 PCMCIA_DEVICE_CIS_PROD_ID12("ADVANTECH", "COMpad-32/85B-2", 0x96913a85, 0x27ab5437, "cis/COMpad2.cis"),
798 PCMCIA_DEVICE_CIS_PROD_ID12("ADVANTECH", "COMpad-32/85B-4", 0x96913a85, 0xcec8f102, "cis/COMpad4.cis"),
799 PCMCIA_DEVICE_CIS_PROD_ID123("ADVANTECH", "COMpad-32/85", "1.0", 0x96913a85, 0x8fbe92ae, 0x0877b627, "cis/COMpad2.cis"),
800 PCMCIA_DEVICE_CIS_PROD_ID2("RS-COM 2P", 0xad20b156, "cis/RS-COM-2P.cis"),
801 PCMCIA_DEVICE_CIS_MANF_CARD(0x0013, 0x0000, "cis/GLOBETROTTER.cis"),
802 PCMCIA_DEVICE_PROD_ID12("ELAN DIGITAL SYSTEMS LTD, c1997.","SERIAL CARD: SL100 1.00.",0x19ca78af,0xf964f42b),
803 PCMCIA_DEVICE_PROD_ID12("ELAN DIGITAL SYSTEMS LTD, c1997.","SERIAL CARD: SL100",0x19ca78af,0x71d98e83),
804 PCMCIA_DEVICE_PROD_ID12("ELAN DIGITAL SYSTEMS LTD, c1997.","SERIAL CARD: SL232 1.00.",0x19ca78af,0x69fb7490),
805 PCMCIA_DEVICE_PROD_ID12("ELAN DIGITAL SYSTEMS LTD, c1997.","SERIAL CARD: SL232",0x19ca78af,0xb6bc0235),
806 PCMCIA_DEVICE_PROD_ID12("ELAN DIGITAL SYSTEMS LTD, c2000.","SERIAL CARD: CF232",0x63f2e0bd,0xb9e175d3),
807 PCMCIA_DEVICE_PROD_ID12("ELAN DIGITAL SYSTEMS LTD, c2000.","SERIAL CARD: CF232-5",0x63f2e0bd,0xfce33442),
808 PCMCIA_DEVICE_PROD_ID12("Elan","Serial Port: CF232",0x3beb8cf2,0x171e7190),
809 PCMCIA_DEVICE_PROD_ID12("Elan","Serial Port: CF232-5",0x3beb8cf2,0x20da4262),
810 PCMCIA_DEVICE_PROD_ID12("Elan","Serial Port: CF428",0x3beb8cf2,0xea5dd57d),
811 PCMCIA_DEVICE_PROD_ID12("Elan","Serial Port: CF500",0x3beb8cf2,0xd77255fa),
812 PCMCIA_DEVICE_PROD_ID12("Elan","Serial Port: IC232",0x3beb8cf2,0x6a709903),
813 PCMCIA_DEVICE_PROD_ID12("Elan","Serial Port: SL232",0x3beb8cf2,0x18430676),
814 PCMCIA_DEVICE_PROD_ID12("Elan","Serial Port: XL232",0x3beb8cf2,0x6f933767),
815 PCMCIA_MFC_DEVICE_PROD_ID12(0,"Elan","Serial Port: CF332",0x3beb8cf2,0x16dc1ba7),
816 PCMCIA_MFC_DEVICE_PROD_ID12(0,"Elan","Serial Port: SL332",0x3beb8cf2,0x19816c41),
817 PCMCIA_MFC_DEVICE_PROD_ID12(0,"Elan","Serial Port: SL385",0x3beb8cf2,0x64112029),
818 PCMCIA_MFC_DEVICE_PROD_ID12(0,"Elan","Serial Port: SL432",0x3beb8cf2,0x1cce7ac4),
819 PCMCIA_MFC_DEVICE_PROD_ID12(0,"Elan","Serial+Parallel Port: SP230",0x3beb8cf2,0xdb9e58bc),
820 PCMCIA_MFC_DEVICE_PROD_ID12(1,"Elan","Serial Port: CF332",0x3beb8cf2,0x16dc1ba7),
821 PCMCIA_MFC_DEVICE_PROD_ID12(1,"Elan","Serial Port: SL332",0x3beb8cf2,0x19816c41),
822 PCMCIA_MFC_DEVICE_PROD_ID12(1,"Elan","Serial Port: SL385",0x3beb8cf2,0x64112029),
823 PCMCIA_MFC_DEVICE_PROD_ID12(1,"Elan","Serial Port: SL432",0x3beb8cf2,0x1cce7ac4),
824 PCMCIA_MFC_DEVICE_PROD_ID12(2,"Elan","Serial Port: SL432",0x3beb8cf2,0x1cce7ac4),
825 PCMCIA_MFC_DEVICE_PROD_ID12(3,"Elan","Serial Port: SL432",0x3beb8cf2,0x1cce7ac4),
826 PCMCIA_DEVICE_MANF_CARD(0x0279, 0x950b),
827 /* too generic */
828 /* PCMCIA_MFC_DEVICE_MANF_CARD(0, 0x0160, 0x0002), */
829 /* PCMCIA_MFC_DEVICE_MANF_CARD(1, 0x0160, 0x0002), */
830 PCMCIA_DEVICE_FUNC_ID(2),
831 PCMCIA_DEVICE_NULL,
832};
833MODULE_DEVICE_TABLE(pcmcia, serial_ids);
834
835MODULE_FIRMWARE("cis/PCMLM28.cis");
836MODULE_FIRMWARE("cis/DP83903.cis");
837MODULE_FIRMWARE("cis/3CCFEM556.cis");
838MODULE_FIRMWARE("cis/3CXEM556.cis");
839MODULE_FIRMWARE("cis/SW_8xx_SER.cis");
840MODULE_FIRMWARE("cis/SW_7xx_SER.cis");
841MODULE_FIRMWARE("cis/SW_555_SER.cis");
842MODULE_FIRMWARE("cis/MT5634ZLX.cis");
843MODULE_FIRMWARE("cis/COMpad2.cis");
844MODULE_FIRMWARE("cis/COMpad4.cis");
845MODULE_FIRMWARE("cis/RS-COM-2P.cis");
846
847static struct pcmcia_driver serial_cs_driver = {
848 .owner = THIS_MODULE,
849 .name = "serial_cs",
850 .probe = serial_probe,
851 .remove = serial_detach,
852 .id_table = serial_ids,
853 .suspend = serial_suspend,
854 .resume = serial_resume,
855};
856
857static int __init init_serial_cs(void)
858{
859 return pcmcia_register_driver(&serial_cs_driver);
860}
861
862static void __exit exit_serial_cs(void)
863{
864 pcmcia_unregister_driver(&serial_cs_driver);
865}
866
867module_init(init_serial_cs);
868module_exit(exit_serial_cs);
869
870MODULE_LICENSE("GPL");
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-01 17:17:32 -0500