diff options
author | Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> | 2014-11-13 10:00:59 -0500 |
---|---|---|
committer | Eduardo Valentin <edubezval@gmail.com> | 2014-11-20 09:52:35 -0500 |
commit | 32f9520569ed6bf75673063b8b1c4f2e46a75c48 (patch) | |
tree | d9addbb87d4637992e7b388900e2a51896a4747b /drivers/thermal | |
parent | 6b1fbbdebae2016fa8a7505021ff2924e75d9e82 (diff) |
thermal: exynos: remove needless triminfo_ctrl abstraction
reg->triminfo_ctrl[] is used in only exynos_tmu_initialize() and
accessed only if TMU_SUPPORT_TRIM_RELOAD flag is set. This flag
is set only on Exynos3250, Exynos4412 and Exynos5250 (other SoC
types don't even have triminfo_ctrl[] entries assigned in their
struct exynos_tmu_registers instances) so the register abstraction
is not needed and can be removed.
There should be no functional changes caused by this patch.
Cc: Amit Daniel Kachhap <amit.daniel@samsung.com>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Eduardo Valentin <edubezval@gmail.com>
Cc: Zhang Rui <rui.zhang@intel.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
Tested-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Eduardo Valentin <edubezval@gmail.com>
Diffstat (limited to 'drivers/thermal')
-rw-r--r-- | drivers/thermal/samsung/exynos_thermal_common.h | 1 | ||||
-rw-r--r-- | drivers/thermal/samsung/exynos_tmu.c | 15 | ||||
-rw-r--r-- | drivers/thermal/samsung/exynos_tmu.h | 7 | ||||
-rw-r--r-- | drivers/thermal/samsung/exynos_tmu_data.c | 8 |
4 files changed, 7 insertions, 24 deletions
diff --git a/drivers/thermal/samsung/exynos_thermal_common.h b/drivers/thermal/samsung/exynos_thermal_common.h index 158f5aa8dc5d..cd4471925cdd 100644 --- a/drivers/thermal/samsung/exynos_thermal_common.h +++ b/drivers/thermal/samsung/exynos_thermal_common.h | |||
@@ -27,7 +27,6 @@ | |||
27 | #define SENSOR_NAME_LEN 16 | 27 | #define SENSOR_NAME_LEN 16 |
28 | #define MAX_TRIP_COUNT 8 | 28 | #define MAX_TRIP_COUNT 8 |
29 | #define MAX_COOLING_DEVICE 4 | 29 | #define MAX_COOLING_DEVICE 4 |
30 | #define MAX_TRIMINFO_CTRL_REG 2 | ||
31 | 30 | ||
32 | #define ACTIVE_INTERVAL 500 | 31 | #define ACTIVE_INTERVAL 500 |
33 | #define IDLE_INTERVAL 10000 | 32 | #define IDLE_INTERVAL 10000 |
diff --git a/drivers/thermal/samsung/exynos_tmu.c b/drivers/thermal/samsung/exynos_tmu.c index 12e6f16d75c7..160e7fa5e1bc 100644 --- a/drivers/thermal/samsung/exynos_tmu.c +++ b/drivers/thermal/samsung/exynos_tmu.c | |||
@@ -162,15 +162,14 @@ static int exynos_tmu_initialize(struct platform_device *pdev) | |||
162 | } | 162 | } |
163 | 163 | ||
164 | if (TMU_SUPPORTS(pdata, TRIM_RELOAD)) { | 164 | if (TMU_SUPPORTS(pdata, TRIM_RELOAD)) { |
165 | for (i = 0; i < reg->triminfo_ctrl_count; i++) { | 165 | if (data->soc == SOC_ARCH_EXYNOS3250) { |
166 | if (pdata->triminfo_reload[i]) { | 166 | ctrl = readl(data->base + EXYNOS_TMU_TRIMINFO_CON1); |
167 | ctrl = readl(data->base + | 167 | ctrl |= EXYNOS_TRIMINFO_RELOAD_ENABLE; |
168 | reg->triminfo_ctrl[i]); | 168 | writel(ctrl, data->base + EXYNOS_TMU_TRIMINFO_CON1); |
169 | ctrl |= pdata->triminfo_reload[i]; | ||
170 | writel(ctrl, data->base + | ||
171 | reg->triminfo_ctrl[i]); | ||
172 | } | ||
173 | } | 169 | } |
170 | ctrl = readl(data->base + EXYNOS_TMU_TRIMINFO_CON2); | ||
171 | ctrl |= EXYNOS_TRIMINFO_RELOAD_ENABLE; | ||
172 | writel(ctrl, data->base + EXYNOS_TMU_TRIMINFO_CON2); | ||
174 | } | 173 | } |
175 | 174 | ||
176 | /* Save trimming info in order to perform calibration */ | 175 | /* Save trimming info in order to perform calibration */ |
diff --git a/drivers/thermal/samsung/exynos_tmu.h b/drivers/thermal/samsung/exynos_tmu.h index d69321579140..cee81a1de8e3 100644 --- a/drivers/thermal/samsung/exynos_tmu.h +++ b/drivers/thermal/samsung/exynos_tmu.h | |||
@@ -76,8 +76,6 @@ enum soc_type { | |||
76 | * struct exynos_tmu_register - register descriptors to access registers and | 76 | * struct exynos_tmu_register - register descriptors to access registers and |
77 | * bitfields. The register validity, offsets and bitfield values may vary | 77 | * bitfields. The register validity, offsets and bitfield values may vary |
78 | * slightly across different exynos SOC's. | 78 | * slightly across different exynos SOC's. |
79 | * @triminfo_ctrl: trim info controller register. | ||
80 | * @triminfo_ctrl_count: the number of trim info controller register. | ||
81 | * @tmu_ctrl: TMU main controller register. | 79 | * @tmu_ctrl: TMU main controller register. |
82 | * @test_mux_addr_shift: shift bits of test mux address. | 80 | * @test_mux_addr_shift: shift bits of test mux address. |
83 | * @therm_trip_mode_shift: shift bits of tripping mode in tmu_ctrl register. | 81 | * @therm_trip_mode_shift: shift bits of tripping mode in tmu_ctrl register. |
@@ -104,9 +102,6 @@ enum soc_type { | |||
104 | * @tmu_pmin: register to get/set the Pmin value. | 102 | * @tmu_pmin: register to get/set the Pmin value. |
105 | */ | 103 | */ |
106 | struct exynos_tmu_registers { | 104 | struct exynos_tmu_registers { |
107 | u32 triminfo_ctrl[MAX_TRIMINFO_CTRL_REG]; | ||
108 | u32 triminfo_ctrl_count; | ||
109 | |||
110 | u32 tmu_ctrl; | 105 | u32 tmu_ctrl; |
111 | u32 test_mux_addr_shift; | 106 | u32 test_mux_addr_shift; |
112 | u32 therm_trip_mode_shift; | 107 | u32 therm_trip_mode_shift; |
@@ -184,7 +179,6 @@ struct exynos_tmu_registers { | |||
184 | * @second_point_trim: temp value of the second point trimming | 179 | * @second_point_trim: temp value of the second point trimming |
185 | * @default_temp_offset: default temperature offset in case of no trimming | 180 | * @default_temp_offset: default temperature offset in case of no trimming |
186 | * @test_mux; information if SoC supports test MUX | 181 | * @test_mux; information if SoC supports test MUX |
187 | * @triminfo_reload: reload value to read TRIMINFO register | ||
188 | * @cal_type: calibration type for temperature | 182 | * @cal_type: calibration type for temperature |
189 | * @freq_clip_table: Table representing frequency reduction percentage. | 183 | * @freq_clip_table: Table representing frequency reduction percentage. |
190 | * @freq_tab_count: Count of the above table as frequency reduction may | 184 | * @freq_tab_count: Count of the above table as frequency reduction may |
@@ -215,7 +209,6 @@ struct exynos_tmu_platform_data { | |||
215 | u8 second_point_trim; | 209 | u8 second_point_trim; |
216 | u8 default_temp_offset; | 210 | u8 default_temp_offset; |
217 | u8 test_mux; | 211 | u8 test_mux; |
218 | u8 triminfo_reload[MAX_TRIMINFO_CTRL_REG]; | ||
219 | 212 | ||
220 | enum calibration_type cal_type; | 213 | enum calibration_type cal_type; |
221 | enum soc_type type; | 214 | enum soc_type type; |
diff --git a/drivers/thermal/samsung/exynos_tmu_data.c b/drivers/thermal/samsung/exynos_tmu_data.c index 8153c41b9725..d4b9a68e803d 100644 --- a/drivers/thermal/samsung/exynos_tmu_data.c +++ b/drivers/thermal/samsung/exynos_tmu_data.c | |||
@@ -82,9 +82,6 @@ struct exynos_tmu_init_data const exynos4210_default_tmu_data = { | |||
82 | 82 | ||
83 | #if defined(CONFIG_SOC_EXYNOS3250) | 83 | #if defined(CONFIG_SOC_EXYNOS3250) |
84 | static const struct exynos_tmu_registers exynos3250_tmu_registers = { | 84 | static const struct exynos_tmu_registers exynos3250_tmu_registers = { |
85 | .triminfo_ctrl[0] = EXYNOS_TMU_TRIMINFO_CON1, | ||
86 | .triminfo_ctrl[1] = EXYNOS_TMU_TRIMINFO_CON2, | ||
87 | .triminfo_ctrl_count = 2, | ||
88 | .tmu_ctrl = EXYNOS_TMU_REG_CONTROL, | 85 | .tmu_ctrl = EXYNOS_TMU_REG_CONTROL, |
89 | .test_mux_addr_shift = EXYNOS4412_MUX_ADDR_SHIFT, | 86 | .test_mux_addr_shift = EXYNOS4412_MUX_ADDR_SHIFT, |
90 | .therm_trip_mode_shift = EXYNOS_TMU_TRIP_MODE_SHIFT, | 87 | .therm_trip_mode_shift = EXYNOS_TMU_TRIP_MODE_SHIFT, |
@@ -140,8 +137,6 @@ static const struct exynos_tmu_registers exynos3250_tmu_registers = { | |||
140 | .temp_level = 95, \ | 137 | .temp_level = 95, \ |
141 | }, \ | 138 | }, \ |
142 | .freq_tab_count = 2, \ | 139 | .freq_tab_count = 2, \ |
143 | .triminfo_reload[0] = EXYNOS_TRIMINFO_RELOAD_ENABLE, \ | ||
144 | .triminfo_reload[1] = EXYNOS_TRIMINFO_RELOAD_ENABLE, \ | ||
145 | .registers = &exynos3250_tmu_registers, \ | 140 | .registers = &exynos3250_tmu_registers, \ |
146 | .features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_TRIM_RELOAD | \ | 141 | .features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_TRIM_RELOAD | \ |
147 | TMU_SUPPORT_FALLING_TRIP | TMU_SUPPORT_READY_STATUS | \ | 142 | TMU_SUPPORT_FALLING_TRIP | TMU_SUPPORT_READY_STATUS | \ |
@@ -163,8 +158,6 @@ struct exynos_tmu_init_data const exynos3250_default_tmu_data = { | |||
163 | 158 | ||
164 | #if defined(CONFIG_SOC_EXYNOS4412) || defined(CONFIG_SOC_EXYNOS5250) | 159 | #if defined(CONFIG_SOC_EXYNOS4412) || defined(CONFIG_SOC_EXYNOS5250) |
165 | static const struct exynos_tmu_registers exynos4412_tmu_registers = { | 160 | static const struct exynos_tmu_registers exynos4412_tmu_registers = { |
166 | .triminfo_ctrl[0] = EXYNOS_TMU_TRIMINFO_CON2, | ||
167 | .triminfo_ctrl_count = 1, | ||
168 | .tmu_ctrl = EXYNOS_TMU_REG_CONTROL, | 161 | .tmu_ctrl = EXYNOS_TMU_REG_CONTROL, |
169 | .test_mux_addr_shift = EXYNOS4412_MUX_ADDR_SHIFT, | 162 | .test_mux_addr_shift = EXYNOS4412_MUX_ADDR_SHIFT, |
170 | .therm_trip_mode_shift = EXYNOS_TMU_TRIP_MODE_SHIFT, | 163 | .therm_trip_mode_shift = EXYNOS_TMU_TRIP_MODE_SHIFT, |
@@ -221,7 +214,6 @@ static const struct exynos_tmu_registers exynos4412_tmu_registers = { | |||
221 | .temp_level = 95, \ | 214 | .temp_level = 95, \ |
222 | }, \ | 215 | }, \ |
223 | .freq_tab_count = 2, \ | 216 | .freq_tab_count = 2, \ |
224 | .triminfo_reload[0] = EXYNOS_TRIMINFO_RELOAD_ENABLE, \ | ||
225 | .registers = &exynos4412_tmu_registers, \ | 217 | .registers = &exynos4412_tmu_registers, \ |
226 | .features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_TRIM_RELOAD | \ | 218 | .features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_TRIM_RELOAD | \ |
227 | TMU_SUPPORT_FALLING_TRIP | TMU_SUPPORT_READY_STATUS | \ | 219 | TMU_SUPPORT_FALLING_TRIP | TMU_SUPPORT_READY_STATUS | \ |