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authorEduardo Valentin <eduardo.valentin@ti.com>2013-06-03 16:31:55 -0400
committerZhang Rui <rui.zhang@intel.com>2013-06-12 22:15:52 -0400
commit8926fa4f9b6160b1953ca44852d6044b58a829e1 (patch)
tree92cb275108b323e650a96dc1693a0cb66cbeb0a4 /drivers/thermal
parent0c12b5ac82fbae6903237997677c228089569ace (diff)
thermal: ti-soc-thermal: add thermal data for DRA752 chips
This patch adds the thermal data for TI DRA752 chips. In this change it includes (autogen): . Register offset definitions . Bitfields and masks for all registers . Conversion table Also, the thermal limits, thresholds and extrapolation rules are included. The extrapolation rule is simply add +2C as margin. All 5 sensors, MPU, GPU, CORE, DSPEVE and IVA, are defined and exposed. Only MPU has cooling device. Cc: Zhang Rui <rui.zhang@intel.com> Cc: linux-pm@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Eduardo Valentin <eduardo.valentin@ti.com> Signed-off-by: Zhang Rui <rui.zhang@intel.com>
Diffstat (limited to 'drivers/thermal')
-rw-r--r--drivers/thermal/ti-soc-thermal/Kconfig12
-rw-r--r--drivers/thermal/ti-soc-thermal/Makefile1
-rw-r--r--drivers/thermal/ti-soc-thermal/dra752-bandgap.h280
-rw-r--r--drivers/thermal/ti-soc-thermal/dra752-thermal-data.c476
-rw-r--r--drivers/thermal/ti-soc-thermal/ti-thermal.h6
5 files changed, 775 insertions, 0 deletions
diff --git a/drivers/thermal/ti-soc-thermal/Kconfig b/drivers/thermal/ti-soc-thermal/Kconfig
index e81375fb2155..bd4c7beba679 100644
--- a/drivers/thermal/ti-soc-thermal/Kconfig
+++ b/drivers/thermal/ti-soc-thermal/Kconfig
@@ -46,3 +46,15 @@ config OMAP5_THERMAL
46 46
47 This includes alert interrupts generation and also the TSHUT 47 This includes alert interrupts generation and also the TSHUT
48 support. 48 support.
49
50config DRA752_THERMAL
51 bool "Texas Instruments DRA752 thermal support"
52 depends on TI_SOC_THERMAL
53 depends on SOC_DRA7XX
54 help
55 If you say yes here you get thermal support for the Texas Instruments
56 DRA752 SoC family. The current chip supported are:
57 - DRA752
58
59 This includes alert interrupts generation and also the TSHUT
60 support.
diff --git a/drivers/thermal/ti-soc-thermal/Makefile b/drivers/thermal/ti-soc-thermal/Makefile
index 0ca034fb419d..1226b2484e55 100644
--- a/drivers/thermal/ti-soc-thermal/Makefile
+++ b/drivers/thermal/ti-soc-thermal/Makefile
@@ -1,5 +1,6 @@
1obj-$(CONFIG_TI_SOC_THERMAL) += ti-soc-thermal.o 1obj-$(CONFIG_TI_SOC_THERMAL) += ti-soc-thermal.o
2ti-soc-thermal-y := ti-bandgap.o 2ti-soc-thermal-y := ti-bandgap.o
3ti-soc-thermal-$(CONFIG_TI_THERMAL) += ti-thermal-common.o 3ti-soc-thermal-$(CONFIG_TI_THERMAL) += ti-thermal-common.o
4ti-soc-thermal-$(CONFIG_DRA752_THERMAL) += dra752-thermal-data.o
4ti-soc-thermal-$(CONFIG_OMAP4_THERMAL) += omap4-thermal-data.o 5ti-soc-thermal-$(CONFIG_OMAP4_THERMAL) += omap4-thermal-data.o
5ti-soc-thermal-$(CONFIG_OMAP5_THERMAL) += omap5-thermal-data.o 6ti-soc-thermal-$(CONFIG_OMAP5_THERMAL) += omap5-thermal-data.o
diff --git a/drivers/thermal/ti-soc-thermal/dra752-bandgap.h b/drivers/thermal/ti-soc-thermal/dra752-bandgap.h
new file mode 100644
index 000000000000..6b0f2b1160f7
--- /dev/null
+++ b/drivers/thermal/ti-soc-thermal/dra752-bandgap.h
@@ -0,0 +1,280 @@
1/*
2 * DRA752 bandgap registers, bitfields and temperature definitions
3 *
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
5 * Contact:
6 * Eduardo Valentin <eduardo.valentin@ti.com>
7 * Tero Kristo <t-kristo@ti.com>
8 *
9 * This is an auto generated file.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * version 2 as published by the Free Software Foundation.
14 *
15 * This program is distributed in the hope that it will be useful, but
16 * WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
23 * 02110-1301 USA
24 *
25 */
26#ifndef __DRA752_BANDGAP_H
27#define __DRA752_BANDGAP_H
28
29/**
30 * *** DRA752 ***
31 *
32 * Below, in sequence, are the Register definitions,
33 * the bitfields and the temperature definitions for DRA752.
34 */
35
36/**
37 * DRA752 register definitions
38 *
39 * Registers are defined as offsets. The offsets are
40 * relative to FUSE_OPP_BGAP_GPU on DRA752.
41 * DRA752_BANDGAP_BASE 0x4a0021e0
42 *
43 * Register below are grouped by domain (not necessarily in offset order)
44 */
45
46
47/* DRA752.common register offsets */
48#define DRA752_BANDGAP_CTRL_1_OFFSET 0x1a0
49#define DRA752_BANDGAP_STATUS_1_OFFSET 0x1c8
50#define DRA752_BANDGAP_CTRL_2_OFFSET 0x39c
51#define DRA752_BANDGAP_STATUS_2_OFFSET 0x3b8
52
53/* DRA752.core register offsets */
54#define DRA752_STD_FUSE_OPP_BGAP_CORE_OFFSET 0x8
55#define DRA752_TEMP_SENSOR_CORE_OFFSET 0x154
56#define DRA752_BANDGAP_THRESHOLD_CORE_OFFSET 0x1ac
57#define DRA752_BANDGAP_TSHUT_CORE_OFFSET 0x1b8
58#define DRA752_BANDGAP_CUMUL_DTEMP_CORE_OFFSET 0x1c4
59#define DRA752_DTEMP_CORE_0_OFFSET 0x208
60#define DRA752_DTEMP_CORE_1_OFFSET 0x20c
61#define DRA752_DTEMP_CORE_2_OFFSET 0x210
62#define DRA752_DTEMP_CORE_3_OFFSET 0x214
63#define DRA752_DTEMP_CORE_4_OFFSET 0x218
64
65/* DRA752.iva register offsets */
66#define DRA752_STD_FUSE_OPP_BGAP_IVA_OFFSET 0x388
67#define DRA752_TEMP_SENSOR_IVA_OFFSET 0x398
68#define DRA752_BANDGAP_THRESHOLD_IVA_OFFSET 0x3a4
69#define DRA752_BANDGAP_TSHUT_IVA_OFFSET 0x3ac
70#define DRA752_BANDGAP_CUMUL_DTEMP_IVA_OFFSET 0x3b4
71#define DRA752_DTEMP_IVA_0_OFFSET 0x3d0
72#define DRA752_DTEMP_IVA_1_OFFSET 0x3d4
73#define DRA752_DTEMP_IVA_2_OFFSET 0x3d8
74#define DRA752_DTEMP_IVA_3_OFFSET 0x3dc
75#define DRA752_DTEMP_IVA_4_OFFSET 0x3e0
76
77/* DRA752.mpu register offsets */
78#define DRA752_STD_FUSE_OPP_BGAP_MPU_OFFSET 0x4
79#define DRA752_TEMP_SENSOR_MPU_OFFSET 0x14c
80#define DRA752_BANDGAP_THRESHOLD_MPU_OFFSET 0x1a4
81#define DRA752_BANDGAP_TSHUT_MPU_OFFSET 0x1b0
82#define DRA752_BANDGAP_CUMUL_DTEMP_MPU_OFFSET 0x1bc
83#define DRA752_DTEMP_MPU_0_OFFSET 0x1e0
84#define DRA752_DTEMP_MPU_1_OFFSET 0x1e4
85#define DRA752_DTEMP_MPU_2_OFFSET 0x1e8
86#define DRA752_DTEMP_MPU_3_OFFSET 0x1ec
87#define DRA752_DTEMP_MPU_4_OFFSET 0x1f0
88
89/* DRA752.dspeve register offsets */
90#define DRA752_STD_FUSE_OPP_BGAP_DSPEVE_OFFSET 0x384
91#define DRA752_TEMP_SENSOR_DSPEVE_OFFSET 0x394
92#define DRA752_BANDGAP_THRESHOLD_DSPEVE_OFFSET 0x3a0
93#define DRA752_BANDGAP_TSHUT_DSPEVE_OFFSET 0x3a8
94#define DRA752_BANDGAP_CUMUL_DTEMP_DSPEVE_OFFSET 0x3b0
95#define DRA752_DTEMP_DSPEVE_0_OFFSET 0x3bc
96#define DRA752_DTEMP_DSPEVE_1_OFFSET 0x3c0
97#define DRA752_DTEMP_DSPEVE_2_OFFSET 0x3c4
98#define DRA752_DTEMP_DSPEVE_3_OFFSET 0x3c8
99#define DRA752_DTEMP_DSPEVE_4_OFFSET 0x3cc
100
101/* DRA752.gpu register offsets */
102#define DRA752_STD_FUSE_OPP_BGAP_GPU_OFFSET 0x0
103#define DRA752_TEMP_SENSOR_GPU_OFFSET 0x150
104#define DRA752_BANDGAP_THRESHOLD_GPU_OFFSET 0x1a8
105#define DRA752_BANDGAP_TSHUT_GPU_OFFSET 0x1b4
106#define DRA752_BANDGAP_CUMUL_DTEMP_GPU_OFFSET 0x1c0
107#define DRA752_DTEMP_GPU_0_OFFSET 0x1f4
108#define DRA752_DTEMP_GPU_1_OFFSET 0x1f8
109#define DRA752_DTEMP_GPU_2_OFFSET 0x1fc
110#define DRA752_DTEMP_GPU_3_OFFSET 0x200
111#define DRA752_DTEMP_GPU_4_OFFSET 0x204
112
113/**
114 * Register bitfields for DRA752
115 *
116 * All the macros bellow define the required bits for
117 * controlling temperature on DRA752. Bit defines are
118 * grouped by register.
119 */
120
121/* DRA752.BANDGAP_STATUS_1 */
122#define DRA752_BANDGAP_STATUS_1_ALERT_MASK BIT(31)
123#define DRA752_BANDGAP_STATUS_1_HOT_CORE_MASK BIT(5)
124#define DRA752_BANDGAP_STATUS_1_COLD_CORE_MASK BIT(4)
125#define DRA752_BANDGAP_STATUS_1_HOT_GPU_MASK BIT(3)
126#define DRA752_BANDGAP_STATUS_1_COLD_GPU_MASK BIT(2)
127#define DRA752_BANDGAP_STATUS_1_HOT_MPU_MASK BIT(1)
128#define DRA752_BANDGAP_STATUS_1_COLD_MPU_MASK BIT(0)
129
130/* DRA752.BANDGAP_CTRL_2 */
131#define DRA752_BANDGAP_CTRL_2_FREEZE_IVA_MASK BIT(22)
132#define DRA752_BANDGAP_CTRL_2_FREEZE_DSPEVE_MASK BIT(21)
133#define DRA752_BANDGAP_CTRL_2_CLEAR_IVA_MASK BIT(19)
134#define DRA752_BANDGAP_CTRL_2_CLEAR_DSPEVE_MASK BIT(18)
135#define DRA752_BANDGAP_CTRL_2_CLEAR_ACCUM_IVA_MASK BIT(16)
136#define DRA752_BANDGAP_CTRL_2_CLEAR_ACCUM_DSPEVE_MASK BIT(15)
137#define DRA752_BANDGAP_CTRL_2_MASK_HOT_IVA_MASK BIT(3)
138#define DRA752_BANDGAP_CTRL_2_MASK_COLD_IVA_MASK BIT(2)
139#define DRA752_BANDGAP_CTRL_2_MASK_HOT_DSPEVE_MASK BIT(1)
140#define DRA752_BANDGAP_CTRL_2_MASK_COLD_DSPEVE_MASK BIT(0)
141
142/* DRA752.BANDGAP_STATUS_2 */
143#define DRA752_BANDGAP_STATUS_2_HOT_IVA_MASK BIT(3)
144#define DRA752_BANDGAP_STATUS_2_COLD_IVA_MASK BIT(2)
145#define DRA752_BANDGAP_STATUS_2_HOT_DSPEVE_MASK BIT(1)
146#define DRA752_BANDGAP_STATUS_2_COLD_DSPEVE_MASK BIT(0)
147
148/* DRA752.BANDGAP_CTRL_1 */
149#define DRA752_BANDGAP_CTRL_1_SIDLEMODE_MASK (0x3 << 30)
150#define DRA752_BANDGAP_CTRL_1_COUNTER_DELAY_MASK (0x7 << 27)
151#define DRA752_BANDGAP_CTRL_1_FREEZE_CORE_MASK BIT(23)
152#define DRA752_BANDGAP_CTRL_1_FREEZE_GPU_MASK BIT(22)
153#define DRA752_BANDGAP_CTRL_1_FREEZE_MPU_MASK BIT(21)
154#define DRA752_BANDGAP_CTRL_1_CLEAR_CORE_MASK BIT(20)
155#define DRA752_BANDGAP_CTRL_1_CLEAR_GPU_MASK BIT(19)
156#define DRA752_BANDGAP_CTRL_1_CLEAR_MPU_MASK BIT(18)
157#define DRA752_BANDGAP_CTRL_1_CLEAR_ACCUM_CORE_MASK BIT(17)
158#define DRA752_BANDGAP_CTRL_1_CLEAR_ACCUM_GPU_MASK BIT(16)
159#define DRA752_BANDGAP_CTRL_1_CLEAR_ACCUM_MPU_MASK BIT(15)
160#define DRA752_BANDGAP_CTRL_1_MASK_HOT_CORE_MASK BIT(5)
161#define DRA752_BANDGAP_CTRL_1_MASK_COLD_CORE_MASK BIT(4)
162#define DRA752_BANDGAP_CTRL_1_MASK_HOT_GPU_MASK BIT(3)
163#define DRA752_BANDGAP_CTRL_1_MASK_COLD_GPU_MASK BIT(2)
164#define DRA752_BANDGAP_CTRL_1_MASK_HOT_MPU_MASK BIT(1)
165#define DRA752_BANDGAP_CTRL_1_MASK_COLD_MPU_MASK BIT(0)
166
167/* DRA752.TEMP_SENSOR */
168#define DRA752_TEMP_SENSOR_TMPSOFF_MASK BIT(11)
169#define DRA752_TEMP_SENSOR_EOCZ_MASK BIT(10)
170#define DRA752_TEMP_SENSOR_DTEMP_MASK (0x3ff << 0)
171
172/* DRA752.BANDGAP_THRESHOLD */
173#define DRA752_BANDGAP_THRESHOLD_HOT_MASK (0x3ff << 16)
174#define DRA752_BANDGAP_THRESHOLD_COLD_MASK (0x3ff << 0)
175
176/* DRA752.TSHUT_THRESHOLD */
177#define DRA752_TSHUT_THRESHOLD_MUXCTRL_MASK BIT(31)
178#define DRA752_TSHUT_THRESHOLD_HOT_MASK (0x3ff << 16)
179#define DRA752_TSHUT_THRESHOLD_COLD_MASK (0x3ff << 0)
180
181/* DRA752.BANDGAP_CUMUL_DTEMP_CORE */
182#define DRA752_BANDGAP_CUMUL_DTEMP_CORE_MASK (0xffffffff << 0)
183
184/* DRA752.BANDGAP_CUMUL_DTEMP_IVA */
185#define DRA752_BANDGAP_CUMUL_DTEMP_IVA_MASK (0xffffffff << 0)
186
187/* DRA752.BANDGAP_CUMUL_DTEMP_MPU */
188#define DRA752_BANDGAP_CUMUL_DTEMP_MPU_MASK (0xffffffff << 0)
189
190/* DRA752.BANDGAP_CUMUL_DTEMP_DSPEVE */
191#define DRA752_BANDGAP_CUMUL_DTEMP_DSPEVE_MASK (0xffffffff << 0)
192
193/* DRA752.BANDGAP_CUMUL_DTEMP_GPU */
194#define DRA752_BANDGAP_CUMUL_DTEMP_GPU_MASK (0xffffffff << 0)
195
196/**
197 * Temperature limits and thresholds for DRA752
198 *
199 * All the macros bellow are definitions for handling the
200 * ADC conversions and representation of temperature limits
201 * and thresholds for DRA752. Definitions are grouped
202 * by temperature domain.
203 */
204
205/* DRA752.common temperature definitions */
206/* ADC conversion table limits */
207#define DRA752_ADC_START_VALUE 540
208#define DRA752_ADC_END_VALUE 945
209
210/* DRA752.GPU temperature definitions */
211/* bandgap clock limits */
212#define DRA752_GPU_MAX_FREQ 1500000
213#define DRA752_GPU_MIN_FREQ 1000000
214/* sensor limits */
215#define DRA752_GPU_MIN_TEMP -40000
216#define DRA752_GPU_MAX_TEMP 125000
217#define DRA752_GPU_HYST_VAL 5000
218/* interrupts thresholds */
219#define DRA752_GPU_TSHUT_HOT 915
220#define DRA752_GPU_TSHUT_COLD 900
221#define DRA752_GPU_T_HOT 800
222#define DRA752_GPU_T_COLD 795
223
224/* DRA752.MPU temperature definitions */
225/* bandgap clock limits */
226#define DRA752_MPU_MAX_FREQ 1500000
227#define DRA752_MPU_MIN_FREQ 1000000
228/* sensor limits */
229#define DRA752_MPU_MIN_TEMP -40000
230#define DRA752_MPU_MAX_TEMP 125000
231#define DRA752_MPU_HYST_VAL 5000
232/* interrupts thresholds */
233#define DRA752_MPU_TSHUT_HOT 915
234#define DRA752_MPU_TSHUT_COLD 900
235#define DRA752_MPU_T_HOT 800
236#define DRA752_MPU_T_COLD 795
237
238/* DRA752.CORE temperature definitions */
239/* bandgap clock limits */
240#define DRA752_CORE_MAX_FREQ 1500000
241#define DRA752_CORE_MIN_FREQ 1000000
242/* sensor limits */
243#define DRA752_CORE_MIN_TEMP -40000
244#define DRA752_CORE_MAX_TEMP 125000
245#define DRA752_CORE_HYST_VAL 5000
246/* interrupts thresholds */
247#define DRA752_CORE_TSHUT_HOT 915
248#define DRA752_CORE_TSHUT_COLD 900
249#define DRA752_CORE_T_HOT 800
250#define DRA752_CORE_T_COLD 795
251
252/* DRA752.DSPEVE temperature definitions */
253/* bandgap clock limits */
254#define DRA752_DSPEVE_MAX_FREQ 1500000
255#define DRA752_DSPEVE_MIN_FREQ 1000000
256/* sensor limits */
257#define DRA752_DSPEVE_MIN_TEMP -40000
258#define DRA752_DSPEVE_MAX_TEMP 125000
259#define DRA752_DSPEVE_HYST_VAL 5000
260/* interrupts thresholds */
261#define DRA752_DSPEVE_TSHUT_HOT 915
262#define DRA752_DSPEVE_TSHUT_COLD 900
263#define DRA752_DSPEVE_T_HOT 800
264#define DRA752_DSPEVE_T_COLD 795
265
266/* DRA752.IVA temperature definitions */
267/* bandgap clock limits */
268#define DRA752_IVA_MAX_FREQ 1500000
269#define DRA752_IVA_MIN_FREQ 1000000
270/* sensor limits */
271#define DRA752_IVA_MIN_TEMP -40000
272#define DRA752_IVA_MAX_TEMP 125000
273#define DRA752_IVA_HYST_VAL 5000
274/* interrupts thresholds */
275#define DRA752_IVA_TSHUT_HOT 915
276#define DRA752_IVA_TSHUT_COLD 900
277#define DRA752_IVA_T_HOT 800
278#define DRA752_IVA_T_COLD 795
279
280#endif /* __DRA752_BANDGAP_H */
diff --git a/drivers/thermal/ti-soc-thermal/dra752-thermal-data.c b/drivers/thermal/ti-soc-thermal/dra752-thermal-data.c
new file mode 100644
index 000000000000..e5d8326a54d6
--- /dev/null
+++ b/drivers/thermal/ti-soc-thermal/dra752-thermal-data.c
@@ -0,0 +1,476 @@
1/*
2 * DRA752 thermal data.
3 *
4 * Copyright (C) 2013 Texas Instruments Inc.
5 * Contact:
6 * Eduardo Valentin <eduardo.valentin@ti.com>
7 * Tero Kristo <t-kristo@ti.com>
8 *
9 * This file is partially autogenerated.
10 *
11 * This software is licensed under the terms of the GNU General Public
12 * License version 2, as published by the Free Software Foundation, and
13 * may be copied, distributed, and modified under those terms.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 */
21
22#include "ti-thermal.h"
23#include "ti-bandgap.h"
24#include "dra752-bandgap.h"
25
26/*
27 * DRA752 has five instances of thermal sensor: MPU, GPU, CORE,
28 * IVA and DSPEVE need to describe the individual registers and
29 * bit fields.
30 */
31
32/*
33 * DRA752 CORE thermal sensor register offsets and bit-fields
34 */
35static struct temp_sensor_registers
36dra752_core_temp_sensor_registers = {
37 .temp_sensor_ctrl = DRA752_TEMP_SENSOR_CORE_OFFSET,
38 .bgap_tempsoff_mask = DRA752_TEMP_SENSOR_TMPSOFF_MASK,
39 .bgap_eocz_mask = DRA752_TEMP_SENSOR_EOCZ_MASK,
40 .bgap_dtemp_mask = DRA752_TEMP_SENSOR_DTEMP_MASK,
41 .bgap_mask_ctrl = DRA752_BANDGAP_CTRL_1_OFFSET,
42 .mask_hot_mask = DRA752_BANDGAP_CTRL_1_MASK_HOT_CORE_MASK,
43 .mask_cold_mask = DRA752_BANDGAP_CTRL_1_MASK_COLD_CORE_MASK,
44 .mask_sidlemode_mask = DRA752_BANDGAP_CTRL_1_SIDLEMODE_MASK,
45 .mask_freeze_mask = DRA752_BANDGAP_CTRL_1_FREEZE_CORE_MASK,
46 .mask_clear_mask = DRA752_BANDGAP_CTRL_1_CLEAR_CORE_MASK,
47 .mask_clear_accum_mask = DRA752_BANDGAP_CTRL_1_CLEAR_ACCUM_CORE_MASK,
48 .bgap_threshold = DRA752_BANDGAP_THRESHOLD_CORE_OFFSET,
49 .threshold_thot_mask = DRA752_BANDGAP_THRESHOLD_HOT_MASK,
50 .threshold_tcold_mask = DRA752_BANDGAP_THRESHOLD_COLD_MASK,
51 .tshut_threshold = DRA752_BANDGAP_TSHUT_CORE_OFFSET,
52 .tshut_hot_mask = DRA752_TSHUT_THRESHOLD_HOT_MASK,
53 .tshut_cold_mask = DRA752_TSHUT_THRESHOLD_COLD_MASK,
54 .bgap_status = DRA752_BANDGAP_STATUS_1_OFFSET,
55 .status_bgap_alert_mask = DRA752_BANDGAP_STATUS_1_ALERT_MASK,
56 .status_hot_mask = DRA752_BANDGAP_STATUS_1_HOT_CORE_MASK,
57 .status_cold_mask = DRA752_BANDGAP_STATUS_1_COLD_CORE_MASK,
58 .bgap_cumul_dtemp = DRA752_BANDGAP_CUMUL_DTEMP_CORE_OFFSET,
59 .ctrl_dtemp_0 = DRA752_DTEMP_CORE_0_OFFSET,
60 .ctrl_dtemp_1 = DRA752_DTEMP_CORE_1_OFFSET,
61 .ctrl_dtemp_2 = DRA752_DTEMP_CORE_2_OFFSET,
62 .ctrl_dtemp_3 = DRA752_DTEMP_CORE_3_OFFSET,
63 .ctrl_dtemp_4 = DRA752_DTEMP_CORE_4_OFFSET,
64 .bgap_efuse = DRA752_STD_FUSE_OPP_BGAP_CORE_OFFSET,
65};
66
67/*
68 * DRA752 IVA thermal sensor register offsets and bit-fields
69 */
70static struct temp_sensor_registers
71dra752_iva_temp_sensor_registers = {
72 .temp_sensor_ctrl = DRA752_TEMP_SENSOR_IVA_OFFSET,
73 .bgap_tempsoff_mask = DRA752_TEMP_SENSOR_TMPSOFF_MASK,
74 .bgap_eocz_mask = DRA752_TEMP_SENSOR_EOCZ_MASK,
75 .bgap_dtemp_mask = DRA752_TEMP_SENSOR_DTEMP_MASK,
76 .bgap_mask_ctrl = DRA752_BANDGAP_CTRL_2_OFFSET,
77 .mask_hot_mask = DRA752_BANDGAP_CTRL_2_MASK_HOT_IVA_MASK,
78 .mask_cold_mask = DRA752_BANDGAP_CTRL_2_MASK_COLD_IVA_MASK,
79 .mask_sidlemode_mask = DRA752_BANDGAP_CTRL_1_SIDLEMODE_MASK,
80 .mask_freeze_mask = DRA752_BANDGAP_CTRL_2_FREEZE_IVA_MASK,
81 .mask_clear_mask = DRA752_BANDGAP_CTRL_2_CLEAR_IVA_MASK,
82 .mask_clear_accum_mask = DRA752_BANDGAP_CTRL_2_CLEAR_ACCUM_IVA_MASK,
83 .bgap_threshold = DRA752_BANDGAP_THRESHOLD_IVA_OFFSET,
84 .threshold_thot_mask = DRA752_BANDGAP_THRESHOLD_HOT_MASK,
85 .threshold_tcold_mask = DRA752_BANDGAP_THRESHOLD_COLD_MASK,
86 .tshut_threshold = DRA752_BANDGAP_TSHUT_IVA_OFFSET,
87 .tshut_hot_mask = DRA752_TSHUT_THRESHOLD_HOT_MASK,
88 .tshut_cold_mask = DRA752_TSHUT_THRESHOLD_COLD_MASK,
89 .bgap_status = DRA752_BANDGAP_STATUS_2_OFFSET,
90 .status_bgap_alert_mask = DRA752_BANDGAP_STATUS_1_ALERT_MASK,
91 .status_hot_mask = DRA752_BANDGAP_STATUS_2_HOT_IVA_MASK,
92 .status_cold_mask = DRA752_BANDGAP_STATUS_2_COLD_IVA_MASK,
93 .bgap_cumul_dtemp = DRA752_BANDGAP_CUMUL_DTEMP_IVA_OFFSET,
94 .ctrl_dtemp_0 = DRA752_DTEMP_IVA_0_OFFSET,
95 .ctrl_dtemp_1 = DRA752_DTEMP_IVA_1_OFFSET,
96 .ctrl_dtemp_2 = DRA752_DTEMP_IVA_2_OFFSET,
97 .ctrl_dtemp_3 = DRA752_DTEMP_IVA_3_OFFSET,
98 .ctrl_dtemp_4 = DRA752_DTEMP_IVA_4_OFFSET,
99 .bgap_efuse = DRA752_STD_FUSE_OPP_BGAP_IVA_OFFSET,
100};
101
102/*
103 * DRA752 MPU thermal sensor register offsets and bit-fields
104 */
105static struct temp_sensor_registers
106dra752_mpu_temp_sensor_registers = {
107 .temp_sensor_ctrl = DRA752_TEMP_SENSOR_MPU_OFFSET,
108 .bgap_tempsoff_mask = DRA752_TEMP_SENSOR_TMPSOFF_MASK,
109 .bgap_eocz_mask = DRA752_TEMP_SENSOR_EOCZ_MASK,
110 .bgap_dtemp_mask = DRA752_TEMP_SENSOR_DTEMP_MASK,
111 .bgap_mask_ctrl = DRA752_BANDGAP_CTRL_1_OFFSET,
112 .mask_hot_mask = DRA752_BANDGAP_CTRL_1_MASK_HOT_MPU_MASK,
113 .mask_cold_mask = DRA752_BANDGAP_CTRL_1_MASK_COLD_MPU_MASK,
114 .mask_sidlemode_mask = DRA752_BANDGAP_CTRL_1_SIDLEMODE_MASK,
115 .mask_freeze_mask = DRA752_BANDGAP_CTRL_1_FREEZE_MPU_MASK,
116 .mask_clear_mask = DRA752_BANDGAP_CTRL_1_CLEAR_MPU_MASK,
117 .mask_clear_accum_mask = DRA752_BANDGAP_CTRL_1_CLEAR_ACCUM_MPU_MASK,
118 .bgap_threshold = DRA752_BANDGAP_THRESHOLD_MPU_OFFSET,
119 .threshold_thot_mask = DRA752_BANDGAP_THRESHOLD_HOT_MASK,
120 .threshold_tcold_mask = DRA752_BANDGAP_THRESHOLD_COLD_MASK,
121 .tshut_threshold = DRA752_BANDGAP_TSHUT_MPU_OFFSET,
122 .tshut_hot_mask = DRA752_TSHUT_THRESHOLD_HOT_MASK,
123 .tshut_cold_mask = DRA752_TSHUT_THRESHOLD_COLD_MASK,
124 .bgap_status = DRA752_BANDGAP_STATUS_1_OFFSET,
125 .status_bgap_alert_mask = DRA752_BANDGAP_STATUS_1_ALERT_MASK,
126 .status_hot_mask = DRA752_BANDGAP_STATUS_1_HOT_MPU_MASK,
127 .status_cold_mask = DRA752_BANDGAP_STATUS_1_COLD_MPU_MASK,
128 .bgap_cumul_dtemp = DRA752_BANDGAP_CUMUL_DTEMP_MPU_OFFSET,
129 .ctrl_dtemp_0 = DRA752_DTEMP_MPU_0_OFFSET,
130 .ctrl_dtemp_1 = DRA752_DTEMP_MPU_1_OFFSET,
131 .ctrl_dtemp_2 = DRA752_DTEMP_MPU_2_OFFSET,
132 .ctrl_dtemp_3 = DRA752_DTEMP_MPU_3_OFFSET,
133 .ctrl_dtemp_4 = DRA752_DTEMP_MPU_4_OFFSET,
134 .bgap_efuse = DRA752_STD_FUSE_OPP_BGAP_MPU_OFFSET,
135};
136
137/*
138 * DRA752 DSPEVE thermal sensor register offsets and bit-fields
139 */
140static struct temp_sensor_registers
141dra752_dspeve_temp_sensor_registers = {
142 .temp_sensor_ctrl = DRA752_TEMP_SENSOR_DSPEVE_OFFSET,
143 .bgap_tempsoff_mask = DRA752_TEMP_SENSOR_TMPSOFF_MASK,
144 .bgap_eocz_mask = DRA752_TEMP_SENSOR_EOCZ_MASK,
145 .bgap_dtemp_mask = DRA752_TEMP_SENSOR_DTEMP_MASK,
146 .bgap_mask_ctrl = DRA752_BANDGAP_CTRL_2_OFFSET,
147 .mask_hot_mask = DRA752_BANDGAP_CTRL_2_MASK_HOT_DSPEVE_MASK,
148 .mask_cold_mask = DRA752_BANDGAP_CTRL_2_MASK_COLD_DSPEVE_MASK,
149 .mask_sidlemode_mask = DRA752_BANDGAP_CTRL_1_SIDLEMODE_MASK,
150 .mask_freeze_mask = DRA752_BANDGAP_CTRL_2_FREEZE_DSPEVE_MASK,
151 .mask_clear_mask = DRA752_BANDGAP_CTRL_2_CLEAR_DSPEVE_MASK,
152 .mask_clear_accum_mask = DRA752_BANDGAP_CTRL_2_CLEAR_ACCUM_DSPEVE_MASK,
153 .bgap_threshold = DRA752_BANDGAP_THRESHOLD_DSPEVE_OFFSET,
154 .threshold_thot_mask = DRA752_BANDGAP_THRESHOLD_HOT_MASK,
155 .threshold_tcold_mask = DRA752_BANDGAP_THRESHOLD_COLD_MASK,
156 .tshut_threshold = DRA752_BANDGAP_TSHUT_DSPEVE_OFFSET,
157 .tshut_hot_mask = DRA752_TSHUT_THRESHOLD_HOT_MASK,
158 .tshut_cold_mask = DRA752_TSHUT_THRESHOLD_COLD_MASK,
159 .bgap_status = DRA752_BANDGAP_STATUS_2_OFFSET,
160 .status_bgap_alert_mask = DRA752_BANDGAP_STATUS_1_ALERT_MASK,
161 .status_hot_mask = DRA752_BANDGAP_STATUS_2_HOT_DSPEVE_MASK,
162 .status_cold_mask = DRA752_BANDGAP_STATUS_2_COLD_DSPEVE_MASK,
163 .bgap_cumul_dtemp = DRA752_BANDGAP_CUMUL_DTEMP_DSPEVE_OFFSET,
164 .ctrl_dtemp_0 = DRA752_DTEMP_DSPEVE_0_OFFSET,
165 .ctrl_dtemp_1 = DRA752_DTEMP_DSPEVE_1_OFFSET,
166 .ctrl_dtemp_2 = DRA752_DTEMP_DSPEVE_2_OFFSET,
167 .ctrl_dtemp_3 = DRA752_DTEMP_DSPEVE_3_OFFSET,
168 .ctrl_dtemp_4 = DRA752_DTEMP_DSPEVE_4_OFFSET,
169 .bgap_efuse = DRA752_STD_FUSE_OPP_BGAP_DSPEVE_OFFSET,
170};
171
172/*
173 * DRA752 GPU thermal sensor register offsets and bit-fields
174 */
175static struct temp_sensor_registers
176dra752_gpu_temp_sensor_registers = {
177 .temp_sensor_ctrl = DRA752_TEMP_SENSOR_GPU_OFFSET,
178 .bgap_tempsoff_mask = DRA752_TEMP_SENSOR_TMPSOFF_MASK,
179 .bgap_eocz_mask = DRA752_TEMP_SENSOR_EOCZ_MASK,
180 .bgap_dtemp_mask = DRA752_TEMP_SENSOR_DTEMP_MASK,
181 .bgap_mask_ctrl = DRA752_BANDGAP_CTRL_1_OFFSET,
182 .mask_hot_mask = DRA752_BANDGAP_CTRL_1_MASK_HOT_GPU_MASK,
183 .mask_cold_mask = DRA752_BANDGAP_CTRL_1_MASK_COLD_GPU_MASK,
184 .mask_sidlemode_mask = DRA752_BANDGAP_CTRL_1_SIDLEMODE_MASK,
185 .mask_freeze_mask = DRA752_BANDGAP_CTRL_1_FREEZE_GPU_MASK,
186 .mask_clear_mask = DRA752_BANDGAP_CTRL_1_CLEAR_GPU_MASK,
187 .mask_clear_accum_mask = DRA752_BANDGAP_CTRL_1_CLEAR_ACCUM_GPU_MASK,
188 .bgap_threshold = DRA752_BANDGAP_THRESHOLD_GPU_OFFSET,
189 .threshold_thot_mask = DRA752_BANDGAP_THRESHOLD_HOT_MASK,
190 .threshold_tcold_mask = DRA752_BANDGAP_THRESHOLD_COLD_MASK,
191 .tshut_threshold = DRA752_BANDGAP_TSHUT_GPU_OFFSET,
192 .tshut_hot_mask = DRA752_TSHUT_THRESHOLD_HOT_MASK,
193 .tshut_cold_mask = DRA752_TSHUT_THRESHOLD_COLD_MASK,
194 .bgap_status = DRA752_BANDGAP_STATUS_1_OFFSET,
195 .status_bgap_alert_mask = DRA752_BANDGAP_STATUS_1_ALERT_MASK,
196 .status_hot_mask = DRA752_BANDGAP_STATUS_1_HOT_GPU_MASK,
197 .status_cold_mask = DRA752_BANDGAP_STATUS_1_COLD_GPU_MASK,
198 .bgap_cumul_dtemp = DRA752_BANDGAP_CUMUL_DTEMP_GPU_OFFSET,
199 .ctrl_dtemp_0 = DRA752_DTEMP_GPU_0_OFFSET,
200 .ctrl_dtemp_1 = DRA752_DTEMP_GPU_1_OFFSET,
201 .ctrl_dtemp_2 = DRA752_DTEMP_GPU_2_OFFSET,
202 .ctrl_dtemp_3 = DRA752_DTEMP_GPU_3_OFFSET,
203 .ctrl_dtemp_4 = DRA752_DTEMP_GPU_4_OFFSET,
204 .bgap_efuse = DRA752_STD_FUSE_OPP_BGAP_GPU_OFFSET,
205};
206
207/* Thresholds and limits for DRA752 MPU temperature sensor */
208static struct temp_sensor_data dra752_mpu_temp_sensor_data = {
209 .tshut_hot = DRA752_MPU_TSHUT_HOT,
210 .tshut_cold = DRA752_MPU_TSHUT_COLD,
211 .t_hot = DRA752_MPU_T_HOT,
212 .t_cold = DRA752_MPU_T_COLD,
213 .min_freq = DRA752_MPU_MIN_FREQ,
214 .max_freq = DRA752_MPU_MAX_FREQ,
215 .max_temp = DRA752_MPU_MAX_TEMP,
216 .min_temp = DRA752_MPU_MIN_TEMP,
217 .hyst_val = DRA752_MPU_HYST_VAL,
218 .update_int1 = 1000,
219 .update_int2 = 2000,
220};
221
222/* Thresholds and limits for DRA752 GPU temperature sensor */
223static struct temp_sensor_data dra752_gpu_temp_sensor_data = {
224 .tshut_hot = DRA752_GPU_TSHUT_HOT,
225 .tshut_cold = DRA752_GPU_TSHUT_COLD,
226 .t_hot = DRA752_GPU_T_HOT,
227 .t_cold = DRA752_GPU_T_COLD,
228 .min_freq = DRA752_GPU_MIN_FREQ,
229 .max_freq = DRA752_GPU_MAX_FREQ,
230 .max_temp = DRA752_GPU_MAX_TEMP,
231 .min_temp = DRA752_GPU_MIN_TEMP,
232 .hyst_val = DRA752_GPU_HYST_VAL,
233 .update_int1 = 1000,
234 .update_int2 = 2000,
235};
236
237/* Thresholds and limits for DRA752 CORE temperature sensor */
238static struct temp_sensor_data dra752_core_temp_sensor_data = {
239 .tshut_hot = DRA752_CORE_TSHUT_HOT,
240 .tshut_cold = DRA752_CORE_TSHUT_COLD,
241 .t_hot = DRA752_CORE_T_HOT,
242 .t_cold = DRA752_CORE_T_COLD,
243 .min_freq = DRA752_CORE_MIN_FREQ,
244 .max_freq = DRA752_CORE_MAX_FREQ,
245 .max_temp = DRA752_CORE_MAX_TEMP,
246 .min_temp = DRA752_CORE_MIN_TEMP,
247 .hyst_val = DRA752_CORE_HYST_VAL,
248 .update_int1 = 1000,
249 .update_int2 = 2000,
250};
251
252/* Thresholds and limits for DRA752 DSPEVE temperature sensor */
253static struct temp_sensor_data dra752_dspeve_temp_sensor_data = {
254 .tshut_hot = DRA752_DSPEVE_TSHUT_HOT,
255 .tshut_cold = DRA752_DSPEVE_TSHUT_COLD,
256 .t_hot = DRA752_DSPEVE_T_HOT,
257 .t_cold = DRA752_DSPEVE_T_COLD,
258 .min_freq = DRA752_DSPEVE_MIN_FREQ,
259 .max_freq = DRA752_DSPEVE_MAX_FREQ,
260 .max_temp = DRA752_DSPEVE_MAX_TEMP,
261 .min_temp = DRA752_DSPEVE_MIN_TEMP,
262 .hyst_val = DRA752_DSPEVE_HYST_VAL,
263 .update_int1 = 1000,
264 .update_int2 = 2000,
265};
266
267/* Thresholds and limits for DRA752 IVA temperature sensor */
268static struct temp_sensor_data dra752_iva_temp_sensor_data = {
269 .tshut_hot = DRA752_IVA_TSHUT_HOT,
270 .tshut_cold = DRA752_IVA_TSHUT_COLD,
271 .t_hot = DRA752_IVA_T_HOT,
272 .t_cold = DRA752_IVA_T_COLD,
273 .min_freq = DRA752_IVA_MIN_FREQ,
274 .max_freq = DRA752_IVA_MAX_FREQ,
275 .max_temp = DRA752_IVA_MAX_TEMP,
276 .min_temp = DRA752_IVA_MIN_TEMP,
277 .hyst_val = DRA752_IVA_HYST_VAL,
278 .update_int1 = 1000,
279 .update_int2 = 2000,
280};
281
282/*
283 * DRA752 : Temperature values in milli degree celsius
284 * ADC code values from 540 to 945
285 */
286static
287int dra752_adc_to_temp[DRA752_ADC_END_VALUE - DRA752_ADC_START_VALUE + 1] = {
288 /* Index 540 - 549 */
289 -40000, -40000, -40000, -40000, -39800, -39400, -39000, -38600, -38200,
290 -37800,
291 /* Index 550 - 559 */
292 -37400, -37000, -36600, -36200, -35800, -35300, -34700, -34200, -33800,
293 -33400,
294 /* Index 560 - 569 */
295 -33000, -32600, -32200, -31800, -31400, -31000, -30600, -30200, -29800,
296 -29400,
297 /* Index 570 - 579 */
298 -29000, -28600, -28200, -27700, -27100, -26600, -26200, -25800, -25400,
299 -25000,
300 /* Index 580 - 589 */
301 -24600, -24200, -23800, -23400, -23000, -22600, -22200, -21800, -21400,
302 -21000,
303 /* Index 590 - 599 */
304 -20500, -19900, -19400, -19000, -18600, -18200, -17800, -17400, -17000,
305 -16600,
306 /* Index 600 - 609 */
307 -16200, -15800, -15400, -15000, -14600, -14200, -13800, -13400, -13000,
308 -12500,
309 /* Index 610 - 619 */
310 -11900, -11400, -11000, -10600, -10200, -9800, -9400, -9000, -8600,
311 -8200,
312 /* Index 620 - 629 */
313 -7800, -7400, -7000, -6600, -6200, -5800, -5400, -5000, -4500,
314 -3900,
315 /* Index 630 - 639 */
316 -3400, -3000, -2600, -2200, -1800, -1400, -1000, -600, -200,
317 200,
318 /* Index 640 - 649 */
319 600, 1000, 1400, 1800, 2200, 2600, 3000, 3400, 3900,
320 4500,
321 /* Index 650 - 659 */
322 5000, 5400, 5800, 6200, 6600, 7000, 7400, 7800, 8200,
323 8600,
324 /* Index 660 - 669 */
325 9000, 9400, 9800, 10200, 10600, 11000, 11400, 11800, 12200,
326 12700,
327 /* Index 670 - 679 */
328 13300, 13800, 14200, 14600, 15000, 15400, 15800, 16200, 16600,
329 17000,
330 /* Index 680 - 689 */
331 17400, 17800, 18200, 18600, 19000, 19400, 19800, 20200, 20600,
332 21000,
333 /* Index 690 - 699 */
334 21400, 21900, 22500, 23000, 23400, 23800, 24200, 24600, 25000,
335 25400,
336 /* Index 700 - 709 */
337 25800, 26200, 26600, 27000, 27400, 27800, 28200, 28600, 29000,
338 29400,
339 /* Index 710 - 719 */
340 29800, 30200, 30600, 31000, 31400, 31900, 32500, 33000, 33400,
341 33800,
342 /* Index 720 - 729 */
343 34200, 34600, 35000, 35400, 35800, 36200, 36600, 37000, 37400,
344 37800,
345 /* Index 730 - 739 */
346 38200, 38600, 39000, 39400, 39800, 40200, 40600, 41000, 41400,
347 41800,
348 /* Index 740 - 749 */
349 42200, 42600, 43100, 43700, 44200, 44600, 45000, 45400, 45800,
350 46200,
351 /* Index 750 - 759 */
352 46600, 47000, 47400, 47800, 48200, 48600, 49000, 49400, 49800,
353 50200,
354 /* Index 760 - 769 */
355 50600, 51000, 51400, 51800, 52200, 52600, 53000, 53400, 53800,
356 54200,
357 /* Index 770 - 779 */
358 54600, 55000, 55400, 55900, 56500, 57000, 57400, 57800, 58200,
359 58600,
360 /* Index 780 - 789 */
361 59000, 59400, 59800, 60200, 60600, 61000, 61400, 61800, 62200,
362 62600,
363 /* Index 790 - 799 */
364 63000, 63400, 63800, 64200, 64600, 65000, 65400, 65800, 66200,
365 66600,
366 /* Index 800 - 809 */
367 67000, 67400, 67800, 68200, 68600, 69000, 69400, 69800, 70200,
368 70600,
369 /* Index 810 - 819 */
370 71000, 71500, 72100, 72600, 73000, 73400, 73800, 74200, 74600,
371 75000,
372 /* Index 820 - 829 */
373 75400, 75800, 76200, 76600, 77000, 77400, 77800, 78200, 78600,
374 79000,
375 /* Index 830 - 839 */
376 79400, 79800, 80200, 80600, 81000, 81400, 81800, 82200, 82600,
377 83000,
378 /* Index 840 - 849 */
379 83400, 83800, 84200, 84600, 85000, 85400, 85800, 86200, 86600,
380 87000,
381 /* Index 850 - 859 */
382 87400, 87800, 88200, 88600, 89000, 89400, 89800, 90200, 90600,
383 91000,
384 /* Index 860 - 869 */
385 91400, 91800, 92200, 92600, 93000, 93400, 93800, 94200, 94600,
386 95000,
387 /* Index 870 - 879 */
388 95400, 95800, 96200, 96600, 97000, 97500, 98100, 98600, 99000,
389 99400,
390 /* Index 880 - 889 */
391 99800, 100200, 100600, 101000, 101400, 101800, 102200, 102600, 103000,
392 103400,
393 /* Index 890 - 899 */
394 103800, 104200, 104600, 105000, 105400, 105800, 106200, 106600, 107000,
395 107400,
396 /* Index 900 - 909 */
397 107800, 108200, 108600, 109000, 109400, 109800, 110200, 110600, 111000,
398 111400,
399 /* Index 910 - 919 */
400 111800, 112200, 112600, 113000, 113400, 113800, 114200, 114600, 115000,
401 115400,
402 /* Index 920 - 929 */
403 115800, 116200, 116600, 117000, 117400, 117800, 118200, 118600, 119000,
404 119400,
405 /* Index 930 - 939 */
406 119800, 120200, 120600, 121000, 121400, 121800, 122200, 122600, 123000,
407 123400,
408 /* Index 940 - 945 */
409 123800, 124200, 124600, 124900, 125000, 125000,
410};
411
412/* DRA752 data */
413const struct ti_bandgap_data dra752_data = {
414 .features = TI_BANDGAP_FEATURE_TSHUT_CONFIG |
415 TI_BANDGAP_FEATURE_FREEZE_BIT |
416 TI_BANDGAP_FEATURE_TALERT |
417 TI_BANDGAP_FEATURE_COUNTER_DELAY |
418 TI_BANDGAP_FEATURE_HISTORY_BUFFER,
419 .fclock_name = "l3instr_ts_gclk_div",
420 .div_ck_name = "l3instr_ts_gclk_div",
421 .conv_table = dra752_adc_to_temp,
422 .adc_start_val = DRA752_ADC_START_VALUE,
423 .adc_end_val = DRA752_ADC_END_VALUE,
424 .expose_sensor = ti_thermal_expose_sensor,
425 .remove_sensor = ti_thermal_remove_sensor,
426 .sensors = {
427 {
428 .registers = &dra752_mpu_temp_sensor_registers,
429 .ts_data = &dra752_mpu_temp_sensor_data,
430 .domain = "cpu",
431 .register_cooling = ti_thermal_register_cpu_cooling,
432 .unregister_cooling = ti_thermal_unregister_cpu_cooling,
433 .slope = DRA752_GRADIENT_SLOPE,
434 .constant = DRA752_GRADIENT_CONST,
435 .slope_pcb = DRA752_GRADIENT_SLOPE_W_PCB,
436 .constant_pcb = DRA752_GRADIENT_CONST_W_PCB,
437 },
438 {
439 .registers = &dra752_gpu_temp_sensor_registers,
440 .ts_data = &dra752_gpu_temp_sensor_data,
441 .domain = "gpu",
442 .slope = DRA752_GRADIENT_SLOPE,
443 .constant = DRA752_GRADIENT_CONST,
444 .slope_pcb = DRA752_GRADIENT_SLOPE_W_PCB,
445 .constant_pcb = DRA752_GRADIENT_CONST_W_PCB,
446 },
447 {
448 .registers = &dra752_core_temp_sensor_registers,
449 .ts_data = &dra752_core_temp_sensor_data,
450 .domain = "core",
451 .slope = DRA752_GRADIENT_SLOPE,
452 .constant = DRA752_GRADIENT_CONST,
453 .slope_pcb = DRA752_GRADIENT_SLOPE_W_PCB,
454 .constant_pcb = DRA752_GRADIENT_CONST_W_PCB,
455 },
456 {
457 .registers = &dra752_dspeve_temp_sensor_registers,
458 .ts_data = &dra752_dspeve_temp_sensor_data,
459 .domain = "dspeve",
460 .slope = DRA752_GRADIENT_SLOPE,
461 .constant = DRA752_GRADIENT_CONST,
462 .slope_pcb = DRA752_GRADIENT_SLOPE_W_PCB,
463 .constant_pcb = DRA752_GRADIENT_CONST_W_PCB,
464 },
465 {
466 .registers = &dra752_iva_temp_sensor_registers,
467 .ts_data = &dra752_iva_temp_sensor_data,
468 .domain = "iva",
469 .slope = DRA752_GRADIENT_SLOPE,
470 .constant = DRA752_GRADIENT_CONST,
471 .slope_pcb = DRA752_GRADIENT_SLOPE_W_PCB,
472 .constant_pcb = DRA752_GRADIENT_CONST_W_PCB,
473 },
474 },
475 .sensor_count = 5,
476};
diff --git a/drivers/thermal/ti-soc-thermal/ti-thermal.h b/drivers/thermal/ti-soc-thermal/ti-thermal.h
index 5055777727cc..f8b7ffea6194 100644
--- a/drivers/thermal/ti-soc-thermal/ti-thermal.h
+++ b/drivers/thermal/ti-soc-thermal/ti-thermal.h
@@ -38,6 +38,9 @@
38#define OMAP_GRADIENT_SLOPE_5430_GPU 117 38#define OMAP_GRADIENT_SLOPE_5430_GPU 117
39#define OMAP_GRADIENT_CONST_5430_GPU -2992 39#define OMAP_GRADIENT_CONST_5430_GPU -2992
40 40
41#define DRA752_GRADIENT_SLOPE 0
42#define DRA752_GRADIENT_CONST 2000
43
41/* PCB sensor calculation constants */ 44/* PCB sensor calculation constants */
42#define OMAP_GRADIENT_SLOPE_W_PCB_4430 0 45#define OMAP_GRADIENT_SLOPE_W_PCB_4430 0
43#define OMAP_GRADIENT_CONST_W_PCB_4430 20000 46#define OMAP_GRADIENT_CONST_W_PCB_4430 20000
@@ -51,6 +54,9 @@
51#define OMAP_GRADIENT_SLOPE_W_PCB_5430_GPU 464 54#define OMAP_GRADIENT_SLOPE_W_PCB_5430_GPU 464
52#define OMAP_GRADIENT_CONST_W_PCB_5430_GPU -5102 55#define OMAP_GRADIENT_CONST_W_PCB_5430_GPU -5102
53 56
57#define DRA752_GRADIENT_SLOPE_W_PCB 0
58#define DRA752_GRADIENT_CONST_W_PCB 2000
59
54/* trip points of interest in milicelsius (at hotspot level) */ 60/* trip points of interest in milicelsius (at hotspot level) */
55#define OMAP_TRIP_COLD 100000 61#define OMAP_TRIP_COLD 100000
56#define OMAP_TRIP_HOT 110000 62#define OMAP_TRIP_HOT 110000
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-30 02:05:04 -0500