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authorBartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>2014-11-13 10:01:26 -0500
committerEduardo Valentin <edubezval@gmail.com>2014-11-20 09:54:42 -0500
commit4c4680a16716ef77826eb11fe8d7c1e70e4eb78d (patch)
tree67fa4baca751fc310a69a4607e3adb93c8555983 /drivers/thermal/samsung/exynos_tmu_data.c
parent7575983c577c724425d11361acb1fc45834633f3 (diff)
thermal: exynos: remove SoC type ifdefs
Maximum theoretical size saving (i.e. with only Exynos5410 SoC support enabled in kernel config so all SoC dependend Exynos thermal driver code was dropped) is 4096 bytes so there is no much sense in keeping these ifdefs (especially given that they are useless once the driver gets updated to use device tree). While at it remove needless 'void *' casts. There should be no functional changes caused by this patch. Cc: Amit Daniel Kachhap <amit.daniel@samsung.com> Cc: Lukasz Majewski <l.majewski@samsung.com> Cc: Eduardo Valentin <edubezval@gmail.com> Cc: Zhang Rui <rui.zhang@intel.com> Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Acked-by: Kyungmin Park <kyungmin.park@samsung.com> Tested-by: Lukasz Majewski <l.majewski@samsung.com> Signed-off-by: Eduardo Valentin <edubezval@gmail.com>
Diffstat (limited to 'drivers/thermal/samsung/exynos_tmu_data.c')
-rw-r--r--drivers/thermal/samsung/exynos_tmu_data.c18
1 files changed, 0 insertions, 18 deletions
diff --git a/drivers/thermal/samsung/exynos_tmu_data.c b/drivers/thermal/samsung/exynos_tmu_data.c
index 708c3e146e89..02a1c342db4c 100644
--- a/drivers/thermal/samsung/exynos_tmu_data.c
+++ b/drivers/thermal/samsung/exynos_tmu_data.c
@@ -24,7 +24,6 @@
24#include "exynos_tmu.h" 24#include "exynos_tmu.h"
25#include "exynos_tmu_data.h" 25#include "exynos_tmu_data.h"
26 26
27#if defined(CONFIG_CPU_EXYNOS4210)
28struct exynos_tmu_init_data const exynos4210_default_tmu_data = { 27struct exynos_tmu_init_data const exynos4210_default_tmu_data = {
29 .tmu_data = { 28 .tmu_data = {
30 { 29 {
@@ -63,9 +62,7 @@ struct exynos_tmu_init_data const exynos4210_default_tmu_data = {
63 }, 62 },
64 .tmu_count = 1, 63 .tmu_count = 1,
65}; 64};
66#endif
67 65
68#if defined(CONFIG_SOC_EXYNOS3250)
69#define EXYNOS3250_TMU_DATA \ 66#define EXYNOS3250_TMU_DATA \
70 .threshold_falling = 10, \ 67 .threshold_falling = 10, \
71 .trigger_levels[0] = 70, \ 68 .trigger_levels[0] = 70, \
@@ -101,9 +98,7 @@ struct exynos_tmu_init_data const exynos4210_default_tmu_data = {
101 .temp_level = 95, \ 98 .temp_level = 95, \
102 }, \ 99 }, \
103 .freq_tab_count = 2 100 .freq_tab_count = 2
104#endif
105 101
106#if defined(CONFIG_SOC_EXYNOS3250)
107struct exynos_tmu_init_data const exynos3250_default_tmu_data = { 102struct exynos_tmu_init_data const exynos3250_default_tmu_data = {
108 .tmu_data = { 103 .tmu_data = {
109 { 104 {
@@ -113,9 +108,7 @@ struct exynos_tmu_init_data const exynos3250_default_tmu_data = {
113 }, 108 },
114 .tmu_count = 1, 109 .tmu_count = 1,
115}; 110};
116#endif
117 111
118#if defined(CONFIG_SOC_EXYNOS4412) || defined(CONFIG_SOC_EXYNOS5250)
119#define EXYNOS4412_TMU_DATA \ 112#define EXYNOS4412_TMU_DATA \
120 .threshold_falling = 10, \ 113 .threshold_falling = 10, \
121 .trigger_levels[0] = 70, \ 114 .trigger_levels[0] = 70, \
@@ -151,9 +144,7 @@ struct exynos_tmu_init_data const exynos3250_default_tmu_data = {
151 .temp_level = 95, \ 144 .temp_level = 95, \
152 }, \ 145 }, \
153 .freq_tab_count = 2 146 .freq_tab_count = 2
154#endif
155 147
156#if defined(CONFIG_SOC_EXYNOS4412)
157struct exynos_tmu_init_data const exynos4412_default_tmu_data = { 148struct exynos_tmu_init_data const exynos4412_default_tmu_data = {
158 .tmu_data = { 149 .tmu_data = {
159 { 150 {
@@ -163,9 +154,7 @@ struct exynos_tmu_init_data const exynos4412_default_tmu_data = {
163 }, 154 },
164 .tmu_count = 1, 155 .tmu_count = 1,
165}; 156};
166#endif
167 157
168#if defined(CONFIG_SOC_EXYNOS5250)
169struct exynos_tmu_init_data const exynos5250_default_tmu_data = { 158struct exynos_tmu_init_data const exynos5250_default_tmu_data = {
170 .tmu_data = { 159 .tmu_data = {
171 { 160 {
@@ -175,9 +164,7 @@ struct exynos_tmu_init_data const exynos5250_default_tmu_data = {
175 }, 164 },
176 .tmu_count = 1, 165 .tmu_count = 1,
177}; 166};
178#endif
179 167
180#if defined(CONFIG_SOC_EXYNOS5260)
181#define __EXYNOS5260_TMU_DATA \ 168#define __EXYNOS5260_TMU_DATA \
182 .threshold_falling = 10, \ 169 .threshold_falling = 10, \
183 .trigger_levels[0] = 85, \ 170 .trigger_levels[0] = 85, \
@@ -228,9 +215,7 @@ struct exynos_tmu_init_data const exynos5260_default_tmu_data = {
228 }, 215 },
229 .tmu_count = 5, 216 .tmu_count = 5,
230}; 217};
231#endif
232 218
233#if defined(CONFIG_SOC_EXYNOS5420)
234#define __EXYNOS5420_TMU_DATA \ 219#define __EXYNOS5420_TMU_DATA \
235 .threshold_falling = 10, \ 220 .threshold_falling = 10, \
236 .trigger_levels[0] = 85, \ 221 .trigger_levels[0] = 85, \
@@ -285,9 +270,7 @@ struct exynos_tmu_init_data const exynos5420_default_tmu_data = {
285 }, 270 },
286 .tmu_count = 5, 271 .tmu_count = 5,
287}; 272};
288#endif
289 273
290#if defined(CONFIG_SOC_EXYNOS5440)
291#define EXYNOS5440_TMU_DATA \ 274#define EXYNOS5440_TMU_DATA \
292 .trigger_levels[0] = 100, \ 275 .trigger_levels[0] = 100, \
293 .trigger_levels[4] = 105, \ 276 .trigger_levels[4] = 105, \
@@ -316,4 +299,3 @@ struct exynos_tmu_init_data const exynos5440_default_tmu_data = {
316 }, 299 },
317 .tmu_count = 3, 300 .tmu_count = 3,
318}; 301};
319#endif