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authorMaciej W. Rozycki <macro@linux-mips.org>2007-07-18 03:49:11 -0400
committerLinus Torvalds <torvalds@woody.linux-foundation.org>2007-07-18 11:38:22 -0400
commit8b4a40809e5330c9da5d20107d693d92d73b31dc (patch)
tree14de7320d32a7e72dc2cddf4833405db0f49a7ba /drivers/tc/zs.h
parentb187f180cc942e50007aa039f8e3a620ee5f3171 (diff)
zs: move to the serial subsystem
This is a reimplementation of the zs driver for the serial subsystem. Any resemblance to the old driver is purely coincidential. ;-) I do hope I got the handling of modem lines right -- better do not tackle me about the issue unless you feel too good... Any users of the old driver: please note the numbers of the serial lines have now been swapped, i.e. ttyS0 <-> ttyS1 and ttyS2 <-> ttyS3. It has to do with the modem lines mentioned above; basically the port A in a given chip has to be initialised before the port B if you want to use the latter as the serial console (which is usually the case), as operations on modem lines of the serial line associated with the port B access both ports (see the comment at the top of the driver for the details of wiring used). Please update your scripts. This is also the reason each SCC now requests an IRQ once only (as seen in "/proc/interrupts") -- the handler takes care of both ports at once as the line associated with the port B has to take status update interrupts from both ports (and yet the line of the port A takes its own for itself too). The old driver never got it right... Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: Ralf Baechle <ralf@linux-mips.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Diffstat (limited to 'drivers/tc/zs.h')
-rw-r--r--drivers/tc/zs.h404
1 files changed, 0 insertions, 404 deletions
diff --git a/drivers/tc/zs.h b/drivers/tc/zs.h
deleted file mode 100644
index 13512200ceba..000000000000
--- a/drivers/tc/zs.h
+++ /dev/null
@@ -1,404 +0,0 @@
1/*
2 * drivers/tc/zs.h: Definitions for the DECstation Z85C30 serial driver.
3 *
4 * Adapted from drivers/sbus/char/sunserial.h by Paul Mackerras.
5 * Adapted from drivers/macintosh/macserial.h by Harald Koerfgen.
6 *
7 * Copyright (C) 1996 Paul Mackerras (Paul.Mackerras@cs.anu.edu.au)
8 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
9 * Copyright (C) 2004, 2005 Maciej W. Rozycki
10 */
11#ifndef _DECSERIAL_H
12#define _DECSERIAL_H
13
14#include <asm/dec/serial.h>
15
16#define NUM_ZSREGS 16
17
18struct serial_struct {
19 int type;
20 int line;
21 int port;
22 int irq;
23 int flags;
24 int xmit_fifo_size;
25 int custom_divisor;
26 int baud_base;
27 unsigned short close_delay;
28 char reserved_char[2];
29 int hub6;
30 unsigned short closing_wait; /* time to wait before closing */
31 unsigned short closing_wait2; /* no longer used... */
32 int reserved[4];
33};
34
35/*
36 * For the close wait times, 0 means wait forever for serial port to
37 * flush its output. 65535 means don't wait at all.
38 */
39#define ZILOG_CLOSING_WAIT_INF 0
40#define ZILOG_CLOSING_WAIT_NONE 65535
41
42/*
43 * Definitions for ZILOG_struct (and serial_struct) flags field
44 */
45#define ZILOG_HUP_NOTIFY 0x0001 /* Notify getty on hangups and closes
46 on the callout port */
47#define ZILOG_FOURPORT 0x0002 /* Set OU1, OUT2 per AST Fourport settings */
48#define ZILOG_SAK 0x0004 /* Secure Attention Key (Orange book) */
49#define ZILOG_SPLIT_TERMIOS 0x0008 /* Separate termios for dialin/callout */
50
51#define ZILOG_SPD_MASK 0x0030
52#define ZILOG_SPD_HI 0x0010 /* Use 56000 instead of 38400 bps */
53
54#define ZILOG_SPD_VHI 0x0020 /* Use 115200 instead of 38400 bps */
55#define ZILOG_SPD_CUST 0x0030 /* Use user-specified divisor */
56
57#define ZILOG_SKIP_TEST 0x0040 /* Skip UART test during autoconfiguration */
58#define ZILOG_AUTO_IRQ 0x0080 /* Do automatic IRQ during autoconfiguration */
59#define ZILOG_SESSION_LOCKOUT 0x0100 /* Lock out cua opens based on session */
60#define ZILOG_PGRP_LOCKOUT 0x0200 /* Lock out cua opens based on pgrp */
61#define ZILOG_CALLOUT_NOHUP 0x0400 /* Don't do hangups for cua device */
62
63#define ZILOG_FLAGS 0x0FFF /* Possible legal ZILOG flags */
64#define ZILOG_USR_MASK 0x0430 /* Legal flags that non-privileged
65 * users can set or reset */
66
67/* Internal flags used only by kernel/chr_drv/serial.c */
68#define ZILOG_INITIALIZED 0x80000000 /* Serial port was initialized */
69#define ZILOG_CALLOUT_ACTIVE 0x40000000 /* Call out device is active */
70#define ZILOG_NORMAL_ACTIVE 0x20000000 /* Normal device is active */
71#define ZILOG_BOOT_AUTOCONF 0x10000000 /* Autoconfigure port on bootup */
72#define ZILOG_CLOSING 0x08000000 /* Serial port is closing */
73#define ZILOG_CTS_FLOW 0x04000000 /* Do CTS flow control */
74#define ZILOG_CHECK_CD 0x02000000 /* i.e., CLOCAL */
75
76/* Software state per channel */
77
78#ifdef __KERNEL__
79/*
80 * This is our internal structure for each serial port's state.
81 *
82 * Many fields are paralleled by the structure used by the serial_struct
83 * structure.
84 *
85 * For definitions of the flags field, see tty.h
86 */
87
88struct dec_zschannel {
89 volatile unsigned char *control;
90 volatile unsigned char *data;
91
92 /* Current write register values */
93 unsigned char curregs[NUM_ZSREGS];
94};
95
96struct dec_serial {
97 struct dec_serial *zs_next; /* For IRQ servicing chain. */
98 struct dec_zschannel *zs_channel; /* Channel registers. */
99 struct dec_zschannel *zs_chan_a; /* A side registers. */
100 unsigned char read_reg_zero;
101
102 struct dec_serial_hook *hook; /* Hook on this channel. */
103 int tty_break; /* Set on BREAK condition. */
104 int is_cons; /* Is this our console. */
105 int tx_active; /* Char is being xmitted. */
106 int tx_stopped; /* Output is suspended. */
107
108 /*
109 * We need to know the current clock divisor
110 * to read the bps rate the chip has currently loaded.
111 */
112 int clk_divisor; /* May be 1, 16, 32, or 64. */
113 int zs_baud;
114
115 char change_needed;
116
117 int magic;
118 int baud_base;
119 int port;
120 int irq;
121 int flags; /* Defined in tty.h. */
122 int type; /* UART type. */
123 struct tty_struct *tty;
124 int read_status_mask;
125 int ignore_status_mask;
126 int timeout;
127 int xmit_fifo_size;
128 int custom_divisor;
129 int x_char; /* XON/XOFF character. */
130 int close_delay;
131 unsigned short closing_wait;
132 unsigned short closing_wait2;
133 unsigned long event;
134 unsigned long last_active;
135 int line;
136 int count; /* # of fds on device. */
137 int blocked_open; /* # of blocked opens. */
138 unsigned char *xmit_buf;
139 int xmit_head;
140 int xmit_tail;
141 int xmit_cnt;
142 struct tasklet_struct tlet;
143 wait_queue_head_t open_wait;
144 wait_queue_head_t close_wait;
145};
146
147
148#define SERIAL_MAGIC 0x5301
149
150/*
151 * The size of the serial xmit buffer is 1 page, or 4096 bytes
152 */
153#define SERIAL_XMIT_SIZE 4096
154
155/*
156 * Events are used to schedule things to happen at timer-interrupt
157 * time, instead of at rs interrupt time.
158 */
159#define RS_EVENT_WRITE_WAKEUP 0
160
161#endif /* __KERNEL__ */
162
163/* Conversion routines to/from brg time constants from/to bits
164 * per second.
165 */
166#define BRG_TO_BPS(brg, freq) ((freq) / 2 / ((brg) + 2))
167#define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
168
169/* The Zilog register set */
170
171#define FLAG 0x7e
172
173/* Write Register 0 */
174#define R0 0 /* Register selects */
175#define R1 1
176#define R2 2
177#define R3 3
178#define R4 4
179#define R5 5
180#define R6 6
181#define R7 7
182#define R8 8
183#define R9 9
184#define R10 10
185#define R11 11
186#define R12 12
187#define R13 13
188#define R14 14
189#define R15 15
190
191#define NULLCODE 0 /* Null Code */
192#define POINT_HIGH 0x8 /* Select upper half of registers */
193#define RES_EXT_INT 0x10 /* Reset Ext. Status Interrupts */
194#define SEND_ABORT 0x18 /* HDLC Abort */
195#define RES_RxINT_FC 0x20 /* Reset RxINT on First Character */
196#define RES_Tx_P 0x28 /* Reset TxINT Pending */
197#define ERR_RES 0x30 /* Error Reset */
198#define RES_H_IUS 0x38 /* Reset highest IUS */
199
200#define RES_Rx_CRC 0x40 /* Reset Rx CRC Checker */
201#define RES_Tx_CRC 0x80 /* Reset Tx CRC Checker */
202#define RES_EOM_L 0xC0 /* Reset EOM latch */
203
204/* Write Register 1 */
205
206#define EXT_INT_ENAB 0x1 /* Ext Int Enable */
207#define TxINT_ENAB 0x2 /* Tx Int Enable */
208#define PAR_SPEC 0x4 /* Parity is special condition */
209
210#define RxINT_DISAB 0 /* Rx Int Disable */
211#define RxINT_FCERR 0x8 /* Rx Int on First Character Only or Error */
212#define RxINT_ALL 0x10 /* Int on all Rx Characters or error */
213#define RxINT_ERR 0x18 /* Int on error only */
214#define RxINT_MASK 0x18
215
216#define WT_RDY_RT 0x20 /* Wait/Ready on R/T */
217#define WT_FN_RDYFN 0x40 /* Wait/FN/Ready FN */
218#define WT_RDY_ENAB 0x80 /* Wait/Ready Enable */
219
220/* Write Register #2 (Interrupt Vector) */
221
222/* Write Register 3 */
223
224#define RxENABLE 0x1 /* Rx Enable */
225#define SYNC_L_INH 0x2 /* Sync Character Load Inhibit */
226#define ADD_SM 0x4 /* Address Search Mode (SDLC) */
227#define RxCRC_ENAB 0x8 /* Rx CRC Enable */
228#define ENT_HM 0x10 /* Enter Hunt Mode */
229#define AUTO_ENAB 0x20 /* Auto Enables */
230#define Rx5 0x0 /* Rx 5 Bits/Character */
231#define Rx7 0x40 /* Rx 7 Bits/Character */
232#define Rx6 0x80 /* Rx 6 Bits/Character */
233#define Rx8 0xc0 /* Rx 8 Bits/Character */
234#define RxNBITS_MASK 0xc0
235
236/* Write Register 4 */
237
238#define PAR_ENA 0x1 /* Parity Enable */
239#define PAR_EVEN 0x2 /* Parity Even/Odd* */
240
241#define SYNC_ENAB 0 /* Sync Modes Enable */
242#define SB1 0x4 /* 1 stop bit/char */
243#define SB15 0x8 /* 1.5 stop bits/char */
244#define SB2 0xc /* 2 stop bits/char */
245#define SB_MASK 0xc
246
247#define MONSYNC 0 /* 8 Bit Sync character */
248#define BISYNC 0x10 /* 16 bit sync character */
249#define SDLC 0x20 /* SDLC Mode (01111110 Sync Flag) */
250#define EXTSYNC 0x30 /* External Sync Mode */
251
252#define X1CLK 0x0 /* x1 clock mode */
253#define X16CLK 0x40 /* x16 clock mode */
254#define X32CLK 0x80 /* x32 clock mode */
255#define X64CLK 0xC0 /* x64 clock mode */
256#define XCLK_MASK 0xC0
257
258/* Write Register 5 */
259
260#define TxCRC_ENAB 0x1 /* Tx CRC Enable */
261#define RTS 0x2 /* RTS */
262#define SDLC_CRC 0x4 /* SDLC/CRC-16 */
263#define TxENAB 0x8 /* Tx Enable */
264#define SND_BRK 0x10 /* Send Break */
265#define Tx5 0x0 /* Tx 5 bits (or less)/character */
266#define Tx7 0x20 /* Tx 7 bits/character */
267#define Tx6 0x40 /* Tx 6 bits/character */
268#define Tx8 0x60 /* Tx 8 bits/character */
269#define TxNBITS_MASK 0x60
270#define DTR 0x80 /* DTR */
271
272/* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
273
274/* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
275
276/* Write Register 8 (transmit buffer) */
277
278/* Write Register 9 (Master interrupt control) */
279#define VIS 1 /* Vector Includes Status */
280#define NV 2 /* No Vector */
281#define DLC 4 /* Disable Lower Chain */
282#define MIE 8 /* Master Interrupt Enable */
283#define STATHI 0x10 /* Status high */
284#define SOFTACK 0x20 /* Software Interrupt Acknowledge */
285#define NORESET 0 /* No reset on write to R9 */
286#define CHRB 0x40 /* Reset channel B */
287#define CHRA 0x80 /* Reset channel A */
288#define FHWRES 0xc0 /* Force hardware reset */
289
290/* Write Register 10 (misc control bits) */
291#define BIT6 1 /* 6 bit/8bit sync */
292#define LOOPMODE 2 /* SDLC Loop mode */
293#define ABUNDER 4 /* Abort/flag on SDLC xmit underrun */
294#define MARKIDLE 8 /* Mark/flag on idle */
295#define GAOP 0x10 /* Go active on poll */
296#define NRZ 0 /* NRZ mode */
297#define NRZI 0x20 /* NRZI mode */
298#define FM1 0x40 /* FM1 (transition = 1) */
299#define FM0 0x60 /* FM0 (transition = 0) */
300#define CRCPS 0x80 /* CRC Preset I/O */
301
302/* Write Register 11 (Clock Mode control) */
303#define TRxCXT 0 /* TRxC = Xtal output */
304#define TRxCTC 1 /* TRxC = Transmit clock */
305#define TRxCBR 2 /* TRxC = BR Generator Output */
306#define TRxCDP 3 /* TRxC = DPLL output */
307#define TRxCOI 4 /* TRxC O/I */
308#define TCRTxCP 0 /* Transmit clock = RTxC pin */
309#define TCTRxCP 8 /* Transmit clock = TRxC pin */
310#define TCBR 0x10 /* Transmit clock = BR Generator output */
311#define TCDPLL 0x18 /* Transmit clock = DPLL output */
312#define RCRTxCP 0 /* Receive clock = RTxC pin */
313#define RCTRxCP 0x20 /* Receive clock = TRxC pin */
314#define RCBR 0x40 /* Receive clock = BR Generator output */
315#define RCDPLL 0x60 /* Receive clock = DPLL output */
316#define RTxCX 0x80 /* RTxC Xtal/No Xtal */
317
318/* Write Register 12 (lower byte of baud rate generator time constant) */
319
320/* Write Register 13 (upper byte of baud rate generator time constant) */
321
322/* Write Register 14 (Misc control bits) */
323#define BRENABL 1 /* Baud rate generator enable */
324#define BRSRC 2 /* Baud rate generator source */
325#define DTRREQ 4 /* DTR/Request function */
326#define AUTOECHO 8 /* Auto Echo */
327#define LOOPBAK 0x10 /* Local loopback */
328#define SEARCH 0x20 /* Enter search mode */
329#define RMC 0x40 /* Reset missing clock */
330#define DISDPLL 0x60 /* Disable DPLL */
331#define SSBR 0x80 /* Set DPLL source = BR generator */
332#define SSRTxC 0xa0 /* Set DPLL source = RTxC */
333#define SFMM 0xc0 /* Set FM mode */
334#define SNRZI 0xe0 /* Set NRZI mode */
335
336/* Write Register 15 (external/status interrupt control) */
337#define ZCIE 2 /* Zero count IE */
338#define DCDIE 8 /* DCD IE */
339#define SYNCIE 0x10 /* Sync/hunt IE */
340#define CTSIE 0x20 /* CTS IE */
341#define TxUIE 0x40 /* Tx Underrun/EOM IE */
342#define BRKIE 0x80 /* Break/Abort IE */
343
344
345/* Read Register 0 */
346#define Rx_CH_AV 0x1 /* Rx Character Available */
347#define ZCOUNT 0x2 /* Zero count */
348#define Tx_BUF_EMP 0x4 /* Tx Buffer empty */
349#define DCD 0x8 /* DCD */
350#define SYNC_HUNT 0x10 /* Sync/hunt */
351#define CTS 0x20 /* CTS */
352#define TxEOM 0x40 /* Tx underrun */
353#define BRK_ABRT 0x80 /* Break/Abort */
354
355/* Read Register 1 */
356#define ALL_SNT 0x1 /* All sent */
357/* Residue Data for 8 Rx bits/char programmed */
358#define RES3 0x8 /* 0/3 */
359#define RES4 0x4 /* 0/4 */
360#define RES5 0xc /* 0/5 */
361#define RES6 0x2 /* 0/6 */
362#define RES7 0xa /* 0/7 */
363#define RES8 0x6 /* 0/8 */
364#define RES18 0xe /* 1/8 */
365#define RES28 0x0 /* 2/8 */
366/* Special Rx Condition Interrupts */
367#define PAR_ERR 0x10 /* Parity error */
368#define Rx_OVR 0x20 /* Rx Overrun Error */
369#define FRM_ERR 0x40 /* CRC/Framing Error */
370#define END_FR 0x80 /* End of Frame (SDLC) */
371
372/* Read Register 2 (channel b only) - Interrupt vector */
373
374/* Read Register 3 (interrupt pending register) ch a only */
375#define CHBEXT 0x1 /* Channel B Ext/Stat IP */
376#define CHBTxIP 0x2 /* Channel B Tx IP */
377#define CHBRxIP 0x4 /* Channel B Rx IP */
378#define CHAEXT 0x8 /* Channel A Ext/Stat IP */
379#define CHATxIP 0x10 /* Channel A Tx IP */
380#define CHARxIP 0x20 /* Channel A Rx IP */
381
382/* Read Register 8 (receive data register) */
383
384/* Read Register 10 (misc status bits) */
385#define ONLOOP 2 /* On loop */
386#define LOOPSEND 0x10 /* Loop sending */
387#define CLK2MIS 0x40 /* Two clocks missing */
388#define CLK1MIS 0x80 /* One clock missing */
389
390/* Read Register 12 (lower byte of baud rate generator constant) */
391
392/* Read Register 13 (upper byte of baud rate generator constant) */
393
394/* Read Register 15 (value of WR 15) */
395
396/* Misc macros */
397#define ZS_CLEARERR(channel) (write_zsreg(channel, 0, ERR_RES))
398#define ZS_CLEARFIFO(channel) do { volatile unsigned char garbage; \
399 garbage = read_zsdata(channel); \
400 garbage = read_zsdata(channel); \
401 garbage = read_zsdata(channel); \
402 } while(0)
403
404#endif /* !(_DECSERIAL_H) */
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