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authorMaciej W. Rozycki <macro@linux-mips.org>2005-06-13 15:58:50 -0400
committerRalf Baechle <ralf@linux-mips.org>2005-11-17 11:23:39 -0500
commit0905780aae58ea69f2dafea9716ee2ea78dbe4e2 (patch)
tree8285d824fce3959edb64af5fbc2511cd549321e4 /drivers/tc/zs.h
parente0c9b7973021ea4baa1ed76ff25ceb80f75edd8f (diff)
[MIPS] zs.c: Resurrect the deceased zs.c for now.
Not that it's meant to be sustained for long, but from time to time it's useful to have some console... Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'drivers/tc/zs.h')
-rw-r--r--drivers/tc/zs.h13
1 files changed, 6 insertions, 7 deletions
diff --git a/drivers/tc/zs.h b/drivers/tc/zs.h
index c52edffa6049..13512200ceba 100644
--- a/drivers/tc/zs.h
+++ b/drivers/tc/zs.h
@@ -6,14 +6,14 @@
6 * 6 *
7 * Copyright (C) 1996 Paul Mackerras (Paul.Mackerras@cs.anu.edu.au) 7 * Copyright (C) 1996 Paul Mackerras (Paul.Mackerras@cs.anu.edu.au)
8 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu) 8 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
9 * Copyright (C) 2004 Maciej W. Rozycki 9 * Copyright (C) 2004, 2005 Maciej W. Rozycki
10 */ 10 */
11#ifndef _DECSERIAL_H 11#ifndef _DECSERIAL_H
12#define _DECSERIAL_H 12#define _DECSERIAL_H
13 13
14#include <asm/dec/serial.h> 14#include <asm/dec/serial.h>
15 15
16#define NUM_ZSREGS 16 16#define NUM_ZSREGS 16
17 17
18struct serial_struct { 18struct serial_struct {
19 int type; 19 int type;
@@ -139,8 +139,7 @@ struct dec_serial {
139 int xmit_head; 139 int xmit_head;
140 int xmit_tail; 140 int xmit_tail;
141 int xmit_cnt; 141 int xmit_cnt;
142 struct tq_struct tqueue; 142 struct tasklet_struct tlet;
143 struct tq_struct tqueue_hangup;
144 wait_queue_head_t open_wait; 143 wait_queue_head_t open_wait;
145 wait_queue_head_t close_wait; 144 wait_queue_head_t close_wait;
146}; 145};
@@ -282,7 +281,7 @@ struct dec_serial {
282#define DLC 4 /* Disable Lower Chain */ 281#define DLC 4 /* Disable Lower Chain */
283#define MIE 8 /* Master Interrupt Enable */ 282#define MIE 8 /* Master Interrupt Enable */
284#define STATHI 0x10 /* Status high */ 283#define STATHI 0x10 /* Status high */
285#define SOFTACK 0x20 /* Software Interrupt Acknowledge */ 284#define SOFTACK 0x20 /* Software Interrupt Acknowledge */
286#define NORESET 0 /* No reset on write to R9 */ 285#define NORESET 0 /* No reset on write to R9 */
287#define CHRB 0x40 /* Reset channel B */ 286#define CHRB 0x40 /* Reset channel B */
288#define CHRA 0x80 /* Reset channel A */ 287#define CHRA 0x80 /* Reset channel A */
@@ -395,8 +394,8 @@ struct dec_serial {
395/* Read Register 15 (value of WR 15) */ 394/* Read Register 15 (value of WR 15) */
396 395
397/* Misc macros */ 396/* Misc macros */
398#define ZS_CLEARERR(channel) (write_zsreg(channel, 0, ERR_RES)) 397#define ZS_CLEARERR(channel) (write_zsreg(channel, 0, ERR_RES))
399#define ZS_CLEARFIFO(channel) do { volatile unsigned char garbage; \ 398#define ZS_CLEARFIFO(channel) do { volatile unsigned char garbage; \
400 garbage = read_zsdata(channel); \ 399 garbage = read_zsdata(channel); \
401 garbage = read_zsdata(channel); \ 400 garbage = read_zsdata(channel); \
402 garbage = read_zsdata(channel); \ 401 garbage = read_zsdata(channel); \