diff options
author | Rafał Miłecki <zajec5@gmail.com> | 2011-05-10 20:10:58 -0400 |
---|---|---|
committer | John W. Linville <linville@tuxdriver.com> | 2011-05-11 14:50:41 -0400 |
commit | 8576f815d5c8beb8b10f96abe31831b90af3d352 (patch) | |
tree | 5c600a151f8a508434e20d8ade1579c0c4cec696 /drivers/ssb | |
parent | 1073e4ee595265086a592a056d903bf4fcc8885a (diff) |
ssb: move ssb_commit_settings and export it
Commiting settings is possible on devices without PCI core (but with CC
core). Export it for usage in drivers supporting other cores.
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/ssb')
-rw-r--r-- | drivers/ssb/driver_pcicore.c | 26 | ||||
-rw-r--r-- | drivers/ssb/main.c | 25 |
2 files changed, 25 insertions, 26 deletions
diff --git a/drivers/ssb/driver_pcicore.c b/drivers/ssb/driver_pcicore.c index 8fde1220bc89..82feb348c8bb 100644 --- a/drivers/ssb/driver_pcicore.c +++ b/drivers/ssb/driver_pcicore.c | |||
@@ -21,8 +21,6 @@ static u16 ssb_pcie_mdio_read(struct ssb_pcicore *pc, u8 device, u8 address); | |||
21 | static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device, | 21 | static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device, |
22 | u8 address, u16 data); | 22 | u8 address, u16 data); |
23 | 23 | ||
24 | static void ssb_commit_settings(struct ssb_bus *bus); | ||
25 | |||
26 | static inline | 24 | static inline |
27 | u32 pcicore_read32(struct ssb_pcicore *pc, u16 offset) | 25 | u32 pcicore_read32(struct ssb_pcicore *pc, u16 offset) |
28 | { | 26 | { |
@@ -659,30 +657,6 @@ static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device, | |||
659 | pcicore_write32(pc, mdio_control, 0); | 657 | pcicore_write32(pc, mdio_control, 0); |
660 | } | 658 | } |
661 | 659 | ||
662 | static void ssb_broadcast_value(struct ssb_device *dev, | ||
663 | u32 address, u32 data) | ||
664 | { | ||
665 | /* This is used for both, PCI and ChipCommon core, so be careful. */ | ||
666 | BUILD_BUG_ON(SSB_PCICORE_BCAST_ADDR != SSB_CHIPCO_BCAST_ADDR); | ||
667 | BUILD_BUG_ON(SSB_PCICORE_BCAST_DATA != SSB_CHIPCO_BCAST_DATA); | ||
668 | |||
669 | ssb_write32(dev, SSB_PCICORE_BCAST_ADDR, address); | ||
670 | ssb_read32(dev, SSB_PCICORE_BCAST_ADDR); /* flush */ | ||
671 | ssb_write32(dev, SSB_PCICORE_BCAST_DATA, data); | ||
672 | ssb_read32(dev, SSB_PCICORE_BCAST_DATA); /* flush */ | ||
673 | } | ||
674 | |||
675 | static void ssb_commit_settings(struct ssb_bus *bus) | ||
676 | { | ||
677 | struct ssb_device *dev; | ||
678 | |||
679 | dev = bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev; | ||
680 | if (WARN_ON(!dev)) | ||
681 | return; | ||
682 | /* This forces an update of the cached registers. */ | ||
683 | ssb_broadcast_value(dev, 0xFD8, 0); | ||
684 | } | ||
685 | |||
686 | int ssb_pcicore_dev_irqvecs_enable(struct ssb_pcicore *pc, | 660 | int ssb_pcicore_dev_irqvecs_enable(struct ssb_pcicore *pc, |
687 | struct ssb_device *dev) | 661 | struct ssb_device *dev) |
688 | { | 662 | { |
diff --git a/drivers/ssb/main.c b/drivers/ssb/main.c index ad3da93a428c..ee2937c41424 100644 --- a/drivers/ssb/main.c +++ b/drivers/ssb/main.c | |||
@@ -1329,6 +1329,31 @@ error: | |||
1329 | } | 1329 | } |
1330 | EXPORT_SYMBOL(ssb_bus_powerup); | 1330 | EXPORT_SYMBOL(ssb_bus_powerup); |
1331 | 1331 | ||
1332 | static void ssb_broadcast_value(struct ssb_device *dev, | ||
1333 | u32 address, u32 data) | ||
1334 | { | ||
1335 | /* This is used for both, PCI and ChipCommon core, so be careful. */ | ||
1336 | BUILD_BUG_ON(SSB_PCICORE_BCAST_ADDR != SSB_CHIPCO_BCAST_ADDR); | ||
1337 | BUILD_BUG_ON(SSB_PCICORE_BCAST_DATA != SSB_CHIPCO_BCAST_DATA); | ||
1338 | |||
1339 | ssb_write32(dev, SSB_PCICORE_BCAST_ADDR, address); | ||
1340 | ssb_read32(dev, SSB_PCICORE_BCAST_ADDR); /* flush */ | ||
1341 | ssb_write32(dev, SSB_PCICORE_BCAST_DATA, data); | ||
1342 | ssb_read32(dev, SSB_PCICORE_BCAST_DATA); /* flush */ | ||
1343 | } | ||
1344 | |||
1345 | void ssb_commit_settings(struct ssb_bus *bus) | ||
1346 | { | ||
1347 | struct ssb_device *dev; | ||
1348 | |||
1349 | dev = bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev; | ||
1350 | if (WARN_ON(!dev)) | ||
1351 | return; | ||
1352 | /* This forces an update of the cached registers. */ | ||
1353 | ssb_broadcast_value(dev, 0xFD8, 0); | ||
1354 | } | ||
1355 | EXPORT_SYMBOL(ssb_commit_settings); | ||
1356 | |||
1332 | u32 ssb_admatch_base(u32 adm) | 1357 | u32 ssb_admatch_base(u32 adm) |
1333 | { | 1358 | { |
1334 | u32 base = 0; | 1359 | u32 base = 0; |