ssb: move ssb_commit_settings and export it

Commiting settings is possible on devices without PCI core (but with CC
core). Export it for usage in drivers supporting other cores.

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>

1 files changed, 25 insertions, 0 deletions

diff --git a/drivers/ssb/main.c b/drivers/ssb/main.c
index ad3da93a428c..ee2937c41424 100644
--- a/drivers/ssb/main.c
+++ b/drivers/ssb/main.c
@@ -1329,6 +1329,31 @@ error:
 }
 EXPORT_SYMBOL(ssb_bus_powerup);
 
+static void ssb_broadcast_value(struct ssb_device *dev,
+                                u32 address, u32 data)
+{
+        /* This is used for both, PCI and ChipCommon core, so be careful. */
+        BUILD_BUG_ON(SSB_PCICORE_BCAST_ADDR != SSB_CHIPCO_BCAST_ADDR);
+        BUILD_BUG_ON(SSB_PCICORE_BCAST_DATA != SSB_CHIPCO_BCAST_DATA);
+
+        ssb_write32(dev, SSB_PCICORE_BCAST_ADDR, address);
+        ssb_read32(dev, SSB_PCICORE_BCAST_ADDR); /* flush */
+        ssb_write32(dev, SSB_PCICORE_BCAST_DATA, data);
+        ssb_read32(dev, SSB_PCICORE_BCAST_DATA); /* flush */
+}
+
+void ssb_commit_settings(struct ssb_bus *bus)
+{
+        struct ssb_device *dev;
+
+        dev = bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev;
+        if (WARN_ON(!dev))
+                return;
+        /* This forces an update of the cached registers. */
+        ssb_broadcast_value(dev, 0xFD8, 0);
+}
+EXPORT_SYMBOL(ssb_commit_settings);
+
 u32 ssb_admatch_base(u32 adm)
 {
         u32 base = 0;