diff options
author | Michael Buesch <mb@bu3sch.de> | 2008-02-19 08:53:35 -0500 |
---|---|---|
committer | John W. Linville <linville@tuxdriver.com> | 2008-02-20 20:11:49 -0500 |
commit | c2bcbe65fc88d61f9a806367ff6eab76c9eabb3a (patch) | |
tree | c882d3016ed4a273b8e7e8fb9b86c1bcb6d6836a /drivers/ssb/driver_chipcommon.c | |
parent | 42bfad4f71637c4eb4791aa8062063c4a8526522 (diff) |
ssb: Fix the GPIO API
This fixes the GPIO API to be usable.
Signed-off-by: Michael Buesch <mb@bu3sch.de>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/ssb/driver_chipcommon.c')
-rw-r--r-- | drivers/ssb/driver_chipcommon.c | 35 |
1 files changed, 29 insertions, 6 deletions
diff --git a/drivers/ssb/driver_chipcommon.c b/drivers/ssb/driver_chipcommon.c index 7cc03f2dd5a6..7ea0c0faa9ab 100644 --- a/drivers/ssb/driver_chipcommon.c +++ b/drivers/ssb/driver_chipcommon.c | |||
@@ -39,12 +39,14 @@ static inline void chipco_write32(struct ssb_chipcommon *cc, | |||
39 | ssb_write32(cc->dev, offset, value); | 39 | ssb_write32(cc->dev, offset, value); |
40 | } | 40 | } |
41 | 41 | ||
42 | static inline void chipco_write32_masked(struct ssb_chipcommon *cc, u16 offset, | 42 | static inline u32 chipco_write32_masked(struct ssb_chipcommon *cc, u16 offset, |
43 | u32 mask, u32 value) | 43 | u32 mask, u32 value) |
44 | { | 44 | { |
45 | value &= mask; | 45 | value &= mask; |
46 | value |= chipco_read32(cc, offset) & ~mask; | 46 | value |= chipco_read32(cc, offset) & ~mask; |
47 | chipco_write32(cc, offset, value); | 47 | chipco_write32(cc, offset, value); |
48 | |||
49 | return value; | ||
48 | } | 50 | } |
49 | 51 | ||
50 | void ssb_chipco_set_clockmode(struct ssb_chipcommon *cc, | 52 | void ssb_chipco_set_clockmode(struct ssb_chipcommon *cc, |
@@ -355,16 +357,37 @@ u32 ssb_chipco_gpio_in(struct ssb_chipcommon *cc, u32 mask) | |||
355 | { | 357 | { |
356 | return chipco_read32(cc, SSB_CHIPCO_GPIOIN) & mask; | 358 | return chipco_read32(cc, SSB_CHIPCO_GPIOIN) & mask; |
357 | } | 359 | } |
360 | EXPORT_SYMBOL(ssb_chipco_gpio_in); | ||
361 | |||
362 | u32 ssb_chipco_gpio_out(struct ssb_chipcommon *cc, u32 mask, u32 value) | ||
363 | { | ||
364 | return chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUT, mask, value); | ||
365 | } | ||
366 | EXPORT_SYMBOL(ssb_chipco_gpio_out); | ||
367 | |||
368 | u32 ssb_chipco_gpio_outen(struct ssb_chipcommon *cc, u32 mask, u32 value) | ||
369 | { | ||
370 | return chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUTEN, mask, value); | ||
371 | } | ||
372 | EXPORT_SYMBOL(ssb_chipco_gpio_outen); | ||
373 | |||
374 | u32 ssb_chipco_gpio_control(struct ssb_chipcommon *cc, u32 mask, u32 value) | ||
375 | { | ||
376 | return chipco_write32_masked(cc, SSB_CHIPCO_GPIOCTL, mask, value); | ||
377 | } | ||
378 | EXPORT_SYMBOL(ssb_chipco_gpio_control); | ||
358 | 379 | ||
359 | void ssb_chipco_gpio_out(struct ssb_chipcommon *cc, u32 mask, u32 value) | 380 | u32 ssb_chipco_gpio_intmask(struct ssb_chipcommon *cc, u32 mask, u32 value) |
360 | { | 381 | { |
361 | chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUT, mask, value); | 382 | return chipco_write32_masked(cc, SSB_CHIPCO_GPIOIRQ, mask, value); |
362 | } | 383 | } |
384 | EXPORT_SYMBOL(ssb_chipco_gpio_intmask); | ||
363 | 385 | ||
364 | void ssb_chipco_gpio_outen(struct ssb_chipcommon *cc, u32 mask, u32 value) | 386 | u32 ssb_chipco_gpio_polarity(struct ssb_chipcommon *cc, u32 mask, u32 value) |
365 | { | 387 | { |
366 | chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUTEN, mask, value); | 388 | return chipco_write32_masked(cc, SSB_CHIPCO_GPIOPOL, mask, value); |
367 | } | 389 | } |
390 | EXPORT_SYMBOL(ssb_chipco_gpio_polarity); | ||
368 | 391 | ||
369 | #ifdef CONFIG_SSB_SERIAL | 392 | #ifdef CONFIG_SSB_SERIAL |
370 | int ssb_chipco_serial_init(struct ssb_chipcommon *cc, | 393 | int ssb_chipco_serial_init(struct ssb_chipcommon *cc, |