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authorMichael Buesch <mb@bu3sch.de>2008-02-18 15:44:39 -0500
committerJohn W. Linville <linville@tuxdriver.com>2008-02-20 20:11:48 -0500
commit58ff70d4feae29cbb7ace410fa6585ef3afb44b6 (patch)
tree298ddfd64df8fbab670538202f93cf0bc028605a /drivers/ssb/driver_chipcommon.c
parent04f93a87a2db84e7214a4ec56fccd2289e973ce5 (diff)
ssb: Fix serial console on new bcm47xx devices
This fixes the baud settings for new devices like the Linksys WRT350n. Signed-off-by: Michael Buesch <mb@bu3sch.de> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/ssb/driver_chipcommon.c')
-rw-r--r--drivers/ssb/driver_chipcommon.c36
1 files changed, 31 insertions, 5 deletions
diff --git a/drivers/ssb/driver_chipcommon.c b/drivers/ssb/driver_chipcommon.c
index 6fbf1c53b6f2..7cc03f2dd5a6 100644
--- a/drivers/ssb/driver_chipcommon.c
+++ b/drivers/ssb/driver_chipcommon.c
@@ -376,6 +376,7 @@ int ssb_chipco_serial_init(struct ssb_chipcommon *cc,
376 unsigned int irq; 376 unsigned int irq;
377 u32 baud_base, div; 377 u32 baud_base, div;
378 u32 i, n; 378 u32 i, n;
379 unsigned int ccrev = cc->dev->id.revision;
379 380
380 plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT); 381 plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT);
381 irq = ssb_mips_irq(cc->dev); 382 irq = ssb_mips_irq(cc->dev);
@@ -387,14 +388,39 @@ int ssb_chipco_serial_init(struct ssb_chipcommon *cc,
387 chipco_read32(cc, SSB_CHIPCO_CLOCK_M2)); 388 chipco_read32(cc, SSB_CHIPCO_CLOCK_M2));
388 div = 1; 389 div = 1;
389 } else { 390 } else {
390 if (cc->dev->id.revision >= 11) { 391 if (ccrev == 20) {
392 /* BCM5354 uses constant 25MHz clock */
393 baud_base = 25000000;
394 div = 48;
395 /* Set the override bit so we don't divide it */
396 chipco_write32(cc, SSB_CHIPCO_CORECTL,
397 chipco_read32(cc, SSB_CHIPCO_CORECTL)
398 | SSB_CHIPCO_CORECTL_UARTCLK0);
399 } else if ((ccrev >= 11) && (ccrev != 15)) {
391 /* Fixed ALP clock */ 400 /* Fixed ALP clock */
392 baud_base = 20000000; 401 baud_base = 20000000;
402 if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
403 /* FIXME: baud_base is different for devices with a PMU */
404 SSB_WARN_ON(1);
405 }
393 div = 1; 406 div = 1;
407 if (ccrev >= 21) {
408 /* Turn off UART clock before switching clocksource. */
409 chipco_write32(cc, SSB_CHIPCO_CORECTL,
410 chipco_read32(cc, SSB_CHIPCO_CORECTL)
411 & ~SSB_CHIPCO_CORECTL_UARTCLKEN);
412 }
394 /* Set the override bit so we don't divide it */ 413 /* Set the override bit so we don't divide it */
395 chipco_write32(cc, SSB_CHIPCO_CORECTL, 414 chipco_write32(cc, SSB_CHIPCO_CORECTL,
396 SSB_CHIPCO_CORECTL_UARTCLK0); 415 chipco_read32(cc, SSB_CHIPCO_CORECTL)
397 } else if (cc->dev->id.revision >= 3) { 416 | SSB_CHIPCO_CORECTL_UARTCLK0);
417 if (ccrev >= 21) {
418 /* Re-enable the UART clock. */
419 chipco_write32(cc, SSB_CHIPCO_CORECTL,
420 chipco_read32(cc, SSB_CHIPCO_CORECTL)
421 | SSB_CHIPCO_CORECTL_UARTCLKEN);
422 }
423 } else if (ccrev >= 3) {
398 /* Internal backplane clock */ 424 /* Internal backplane clock */
399 baud_base = ssb_clockspeed(bus); 425 baud_base = ssb_clockspeed(bus);
400 div = chipco_read32(cc, SSB_CHIPCO_CLKDIV) 426 div = chipco_read32(cc, SSB_CHIPCO_CLKDIV)
@@ -406,7 +432,7 @@ int ssb_chipco_serial_init(struct ssb_chipcommon *cc,
406 } 432 }
407 433
408 /* Clock source depends on strapping if UartClkOverride is unset */ 434 /* Clock source depends on strapping if UartClkOverride is unset */
409 if ((cc->dev->id.revision > 0) && 435 if ((ccrev > 0) &&
410 !(chipco_read32(cc, SSB_CHIPCO_CORECTL) & SSB_CHIPCO_CORECTL_UARTCLK0)) { 436 !(chipco_read32(cc, SSB_CHIPCO_CORECTL) & SSB_CHIPCO_CORECTL_UARTCLK0)) {
411 if ((cc->capabilities & SSB_CHIPCO_CAP_UARTCLK) == 437 if ((cc->capabilities & SSB_CHIPCO_CAP_UARTCLK) ==
412 SSB_CHIPCO_CAP_UARTCLK_INT) { 438 SSB_CHIPCO_CAP_UARTCLK_INT) {
@@ -428,7 +454,7 @@ int ssb_chipco_serial_init(struct ssb_chipcommon *cc,
428 cc_mmio = cc->dev->bus->mmio + (cc->dev->core_index * SSB_CORE_SIZE); 454 cc_mmio = cc->dev->bus->mmio + (cc->dev->core_index * SSB_CORE_SIZE);
429 uart_regs = cc_mmio + SSB_CHIPCO_UART0_DATA; 455 uart_regs = cc_mmio + SSB_CHIPCO_UART0_DATA;
430 /* Offset changed at after rev 0 */ 456 /* Offset changed at after rev 0 */
431 if (cc->dev->id.revision == 0) 457 if (ccrev == 0)
432 uart_regs += (i * 8); 458 uart_regs += (i * 8);
433 else 459 else
434 uart_regs += (i * 256); 460 uart_regs += (i * 256);