spmi: pmic_arb: add support for interrupt handling

The Qualcomm PMIC Arbiter, in addition to being a basic SPMI controller,
also implements interrupt handling for slave devices.  Note, this is
outside the scope of SPMI, as SPMI leaves interrupt handling completely
unspecified.

Extend the driver to provide a irq_chip implementation and chained irq
handling which allows for these interrupts to be used.

Cc: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Josh Cartwright <joshc@codeaurora.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

2 files changed, 376 insertions, 2 deletions

diff --git a/drivers/spmi/Kconfig b/drivers/spmi/Kconfig
index 80b79013fd1e..075bd79e1ac4 100644
--- a/drivers/spmi/Kconfig
+++ b/drivers/spmi/Kconfig
@@ -13,6 +13,7 @@ if SPMI
 config SPMI_MSM_PMIC_ARB
         tristate "Qualcomm MSM SPMI Controller (PMIC Arbiter)"
         depends on ARM
+        depends on IRQ_DOMAIN
         depends on ARCH_MSM || COMPILE_TEST
         default ARCH_MSM
         help
diff --git a/drivers/spmi/spmi-pmic-arb.c b/drivers/spmi/spmi-pmic-arb.c
index 2dd27e8d140d..246e03a18c94 100644
--- a/drivers/spmi/spmi-pmic-arb.c
+++ b/drivers/spmi/spmi-pmic-arb.c
@@ -13,6 +13,9 @@
 #include <linux/err.h>
 #include <linux/interrupt.h>
 #include <linux/io.h>
+#include <linux/irqchip/chained_irq.h>
+#include <linux/irqdomain.h>
+#include <linux/irq.h>
 #include <linux/kernel.h>
 #include <linux/module.h>
 #include <linux/of.h>
@@ -103,6 +106,14 @@ enum pmic_arb_cmd_op_code {
  * @cnfg:               address of the PMIC Arbiter configuration registers.
  * @lock:               lock to synchronize accesses.
  * @channel:            which channel to use for accesses.
+ * @irq:                PMIC ARB interrupt.
+ * @ee:                 the current Execution Environment
+ * @min_apid:           minimum APID (used for bounding IRQ search)
+ * @max_apid:           maximum APID
+ * @mapping_table:      in-memory copy of PPID -> APID mapping table.
+ * @domain:             irq domain object for PMIC IRQ domain
+ * @spmic:              SPMI controller object
+ * @apid_to_ppid:       cached mapping from APID to PPID
  */
 struct spmi_pmic_arb_dev {
         void __iomem            *base;
@@ -110,6 +121,14 @@ struct spmi_pmic_arb_dev {
         void __iomem            *cnfg;
         raw_spinlock_t          lock;
         u8                      channel;
+        int                     irq;
+        u8                      ee;
+        u8                      min_apid;
+        u8                      max_apid;
+        u32                     mapping_table[SPMI_MAPPING_TABLE_LEN];
+        struct irq_domain       *domain;
+        struct spmi_controller  *spmic;
+        u16                     apid_to_ppid[256];
 };
 
 static inline u32 pmic_arb_base_read(struct spmi_pmic_arb_dev *dev, u32 offset)
@@ -306,12 +325,316 @@ static int pmic_arb_write_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid,
         return rc;
 }
 
+enum qpnpint_regs {
+        QPNPINT_REG_RT_STS              = 0x10,
+        QPNPINT_REG_SET_TYPE            = 0x11,
+        QPNPINT_REG_POLARITY_HIGH       = 0x12,
+        QPNPINT_REG_POLARITY_LOW        = 0x13,
+        QPNPINT_REG_LATCHED_CLR         = 0x14,
+        QPNPINT_REG_EN_SET              = 0x15,
+        QPNPINT_REG_EN_CLR              = 0x16,
+        QPNPINT_REG_LATCHED_STS         = 0x18,
+};
+
+struct spmi_pmic_arb_qpnpint_type {
+        u8 type; /* 1 -> edge */
+        u8 polarity_high;
+        u8 polarity_low;
+} __packed;
+
+/* Simplified accessor functions for irqchip callbacks */
+static void qpnpint_spmi_write(struct irq_data *d, u8 reg, void *buf,
+                               size_t len)
+{
+        struct spmi_pmic_arb_dev *pa = irq_data_get_irq_chip_data(d);
+        u8 sid = d->hwirq >> 24;
+        u8 per = d->hwirq >> 16;
+
+        if (pmic_arb_write_cmd(pa->spmic, SPMI_CMD_EXT_WRITEL, sid,
+                               (per << 8) + reg, buf, len))
+                dev_err_ratelimited(&pa->spmic->dev,
+                                "failed irqchip transaction on %x\n",
+                                    d->irq);
+}
+
+static void qpnpint_spmi_read(struct irq_data *d, u8 reg, void *buf, size_t len)
+{
+        struct spmi_pmic_arb_dev *pa = irq_data_get_irq_chip_data(d);
+        u8 sid = d->hwirq >> 24;
+        u8 per = d->hwirq >> 16;
+
+        if (pmic_arb_read_cmd(pa->spmic, SPMI_CMD_EXT_READL, sid,
+                              (per << 8) + reg, buf, len))
+                dev_err_ratelimited(&pa->spmic->dev,
+                                "failed irqchip transaction on %x\n",
+                                    d->irq);
+}
+
+static void periph_interrupt(struct spmi_pmic_arb_dev *pa, u8 apid)
+{
+        unsigned int irq;
+        u32 status;
+        int id;
+
+        status = readl_relaxed(pa->intr + SPMI_PIC_IRQ_STATUS(apid));
+        while (status) {
+                id = ffs(status) - 1;
+                status &= ~(1 << id);
+                irq = irq_find_mapping(pa->domain,
+                                       pa->apid_to_ppid[apid] << 16
+                                     | id << 8
+                                     | apid);
+                generic_handle_irq(irq);
+        }
+}
+
+static void pmic_arb_chained_irq(unsigned int irq, struct irq_desc *desc)
+{
+        struct spmi_pmic_arb_dev *pa = irq_get_handler_data(irq);
+        struct irq_chip *chip = irq_get_chip(irq);
+        void __iomem *intr = pa->intr;
+        int first = pa->min_apid >> 5;
+        int last = pa->max_apid >> 5;
+        u32 status;
+        int i, id;
+
+        chained_irq_enter(chip, desc);
+
+        for (i = first; i <= last; ++i) {
+                status = readl_relaxed(intr +
+                                       SPMI_PIC_OWNER_ACC_STATUS(pa->ee, i));
+                while (status) {
+                        id = ffs(status) - 1;
+                        status &= ~(1 << id);
+                        periph_interrupt(pa, id + i * 32);
+                }
+        }
+
+        chained_irq_exit(chip, desc);
+}
+
+static void qpnpint_irq_ack(struct irq_data *d)
+{
+        struct spmi_pmic_arb_dev *pa = irq_data_get_irq_chip_data(d);
+        u8 irq  = d->hwirq >> 8;
+        u8 apid = d->hwirq;
+        unsigned long flags;
+        u8 data;
+
+        raw_spin_lock_irqsave(&pa->lock, flags);
+        writel_relaxed(1 << irq, pa->intr + SPMI_PIC_IRQ_CLEAR(apid));
+        raw_spin_unlock_irqrestore(&pa->lock, flags);
+
+        data = 1 << irq;
+        qpnpint_spmi_write(d, QPNPINT_REG_LATCHED_CLR, &data, 1);
+}
+
+static void qpnpint_irq_mask(struct irq_data *d)
+{
+        struct spmi_pmic_arb_dev *pa = irq_data_get_irq_chip_data(d);
+        u8 irq  = d->hwirq >> 8;
+        u8 apid = d->hwirq;
+        unsigned long flags;
+        u32 status;
+        u8 data;
+
+        raw_spin_lock_irqsave(&pa->lock, flags);
+        status = readl_relaxed(pa->intr + SPMI_PIC_ACC_ENABLE(apid));
+        if (status & SPMI_PIC_ACC_ENABLE_BIT) {
+                status = status & ~SPMI_PIC_ACC_ENABLE_BIT;
+                writel_relaxed(status, pa->intr + SPMI_PIC_ACC_ENABLE(apid));
+        }
+        raw_spin_unlock_irqrestore(&pa->lock, flags);
+
+        data = 1 << irq;