diff options
author | Shimoda, Yoshihiro <yoshihiro.shimoda.uh@renesas.com> | 2012-03-07 00:45:37 -0500 |
---|---|---|
committer | Grant Likely <grant.likely@secretlab.ca> | 2012-03-07 21:18:45 -0500 |
commit | 0eb8880fac7b0f32ebab33f99e758c6b308e3aa1 (patch) | |
tree | 2d8ca659f3db6d17a1957fd6c9957beace6c171e /drivers/spi | |
parent | d5a8003135da7afe311e4e13ff42000ab7cd2078 (diff) |
spi/spi-sh: add IORESOURCE_MEM_TYPE_MASK decoding for access size
This SPI controller's access size is 32, or 8-bit. The previous driver
supported 32-bit only. So, this patch adds IORESOURCE_MEM_TYPE_MASK
decoding, an then, the driver can handle the SPI controller of 8-bit.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
Diffstat (limited to 'drivers/spi')
-rw-r--r-- | drivers/spi/spi-sh.c | 25 |
1 files changed, 23 insertions, 2 deletions
diff --git a/drivers/spi/spi-sh.c b/drivers/spi/spi-sh.c index 70c8af9f7ccc..79442c31bcd9 100644 --- a/drivers/spi/spi-sh.c +++ b/drivers/spi/spi-sh.c | |||
@@ -92,17 +92,26 @@ struct spi_sh_data { | |||
92 | unsigned long cr1; | 92 | unsigned long cr1; |
93 | wait_queue_head_t wait; | 93 | wait_queue_head_t wait; |
94 | spinlock_t lock; | 94 | spinlock_t lock; |
95 | int width; | ||
95 | }; | 96 | }; |
96 | 97 | ||
97 | static void spi_sh_write(struct spi_sh_data *ss, unsigned long data, | 98 | static void spi_sh_write(struct spi_sh_data *ss, unsigned long data, |
98 | unsigned long offset) | 99 | unsigned long offset) |
99 | { | 100 | { |
100 | writel(data, ss->addr + offset); | 101 | if (ss->width == 8) |
102 | iowrite8(data, ss->addr + (offset >> 2)); | ||
103 | else if (ss->width == 32) | ||
104 | iowrite32(data, ss->addr + offset); | ||
101 | } | 105 | } |
102 | 106 | ||
103 | static unsigned long spi_sh_read(struct spi_sh_data *ss, unsigned long offset) | 107 | static unsigned long spi_sh_read(struct spi_sh_data *ss, unsigned long offset) |
104 | { | 108 | { |
105 | return readl(ss->addr + offset); | 109 | if (ss->width == 8) |
110 | return ioread8(ss->addr + (offset >> 2)); | ||
111 | else if (ss->width == 32) | ||
112 | return ioread32(ss->addr + offset); | ||
113 | else | ||
114 | return 0; | ||
106 | } | 115 | } |
107 | 116 | ||
108 | static void spi_sh_set_bit(struct spi_sh_data *ss, unsigned long val, | 117 | static void spi_sh_set_bit(struct spi_sh_data *ss, unsigned long val, |
@@ -464,6 +473,18 @@ static int __devinit spi_sh_probe(struct platform_device *pdev) | |||
464 | ss = spi_master_get_devdata(master); | 473 | ss = spi_master_get_devdata(master); |
465 | dev_set_drvdata(&pdev->dev, ss); | 474 | dev_set_drvdata(&pdev->dev, ss); |
466 | 475 | ||
476 | switch (res->flags & IORESOURCE_MEM_TYPE_MASK) { | ||
477 | case IORESOURCE_MEM_8BIT: | ||
478 | ss->width = 8; | ||
479 | break; | ||
480 | case IORESOURCE_MEM_32BIT: | ||
481 | ss->width = 32; | ||
482 | break; | ||
483 | default: | ||
484 | dev_err(&pdev->dev, "No support width\n"); | ||
485 | ret = -ENODEV; | ||
486 | goto error1; | ||
487 | } | ||
467 | ss->irq = irq; | 488 | ss->irq = irq; |
468 | ss->master = master; | 489 | ss->master = master; |
469 | ss->addr = ioremap(res->start, resource_size(res)); | 490 | ss->addr = ioremap(res->start, resource_size(res)); |