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authorAndy Shevchenko <andriy.shevchenko@linux.intel.com>2014-10-02 09:31:07 -0400
committerMark Brown <broonie@kernel.org>2014-10-02 12:06:26 -0400
commit15ee3be78b017ee9d697fe59d45cdfbb35d9fdeb (patch)
treee93d0c3c779c72b96496842aedcd3482871cfed4 /drivers/spi
parentc3c6e231d860774037e7001ff3d536e5644fe2da (diff)
spi: dw-mid: change magic numbers to the constants
Instead of using magic numbers in the code we create a bit map definition of the DMACR register and use it. There is no functional change. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'drivers/spi')
-rw-r--r--drivers/spi/spi-dw-mid.c4
-rw-r--r--drivers/spi/spi-dw.h4
2 files changed, 6 insertions, 2 deletions
diff --git a/drivers/spi/spi-dw-mid.c b/drivers/spi/spi-dw-mid.c
index ecae30fe28af..7bdf93747e5f 100644
--- a/drivers/spi/spi-dw-mid.c
+++ b/drivers/spi/spi-dw-mid.c
@@ -124,9 +124,9 @@ static int mid_spi_dma_transfer(struct dw_spi *dws, int cs_change)
124 dw_writew(dws, DW_SPI_DMARDLR, 0xf); 124 dw_writew(dws, DW_SPI_DMARDLR, 0xf);
125 dw_writew(dws, DW_SPI_DMATDLR, 0x10); 125 dw_writew(dws, DW_SPI_DMATDLR, 0x10);
126 if (dws->tx_dma) 126 if (dws->tx_dma)
127 dma_ctrl |= 0x2; 127 dma_ctrl |= SPI_DMA_TDMAE;
128 if (dws->rx_dma) 128 if (dws->rx_dma)
129 dma_ctrl |= 0x1; 129 dma_ctrl |= SPI_DMA_RDMAE;
130 dw_writew(dws, DW_SPI_DMACR, dma_ctrl); 130 dw_writew(dws, DW_SPI_DMACR, dma_ctrl);
131 spi_enable_chip(dws, 1); 131 spi_enable_chip(dws, 1);
132 } 132 }
diff --git a/drivers/spi/spi-dw.h b/drivers/spi/spi-dw.h
index 089fc4ba3ace..83a103a76481 100644
--- a/drivers/spi/spi-dw.h
+++ b/drivers/spi/spi-dw.h
@@ -74,6 +74,10 @@
74#define SPI_INT_RXFI (1 << 4) 74#define SPI_INT_RXFI (1 << 4)
75#define SPI_INT_MSTI (1 << 5) 75#define SPI_INT_MSTI (1 << 5)
76 76
77/* Bit fields in DMACR */
78#define SPI_DMA_RDMAE (1 << 0)
79#define SPI_DMA_TDMAE (1 << 1)
80
77/* TX RX interrupt level threshold, max can be 256 */ 81/* TX RX interrupt level threshold, max can be 256 */
78#define SPI_INT_THRESHOLD 32 82#define SPI_INT_THRESHOLD 32
79 83