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authorBryan Wu <bryan.wu@analog.com>2008-02-06 04:38:18 -0500
committerLinus Torvalds <torvalds@woody.linux-foundation.org>2008-02-06 13:41:11 -0500
commite26aa015dd34d5768b80815836ad60e8495e9553 (patch)
tree18521ecaa37b2d51b97f3b4f256762dca1d445cb /drivers/spi
parentaab0d83ee771b19082c3ee24576cf5508d319294 (diff)
spi_bfin: wait for tx to complete on some cs_chg paths
PBX 2 SPI devices need the nonstandard "cs change per word" mechanism. This patch is one of three updating this driver to make the last data bits get sent before advancing the transfer ... in this case, before the chipselect gets deactivated. Signed-off-by: Bryan Wu <bryan.wu@analog.com> Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Diffstat (limited to 'drivers/spi')
-rw-r--r--drivers/spi/spi_bfin5xx.c40
1 files changed, 12 insertions, 28 deletions
diff --git a/drivers/spi/spi_bfin5xx.c b/drivers/spi/spi_bfin5xx.c
index 52beb5c924b7..ce4692cdb3b2 100644
--- a/drivers/spi/spi_bfin5xx.c
+++ b/drivers/spi/spi_bfin5xx.c
@@ -294,16 +294,14 @@ static void u8_cs_chg_writer(struct driver_data *drv_data)
294{ 294{
295 struct chip_data *chip = drv_data->cur_chip; 295 struct chip_data *chip = drv_data->cur_chip;
296 296
297 /* poll for SPI completion before start */
298 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
299 cpu_relax();
300
301 while (drv_data->tx < drv_data->tx_end) { 297 while (drv_data->tx < drv_data->tx_end) {
302 cs_active(drv_data, chip); 298 cs_active(drv_data, chip);
303 299
304 write_TDBR(drv_data, (*(u8 *) (drv_data->tx))); 300 write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
305 while (read_STAT(drv_data) & BIT_STAT_TXS) 301 while (read_STAT(drv_data) & BIT_STAT_TXS)
306 cpu_relax(); 302 cpu_relax();
303 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
304 cpu_relax();
307 305
308 cs_deactive(drv_data, chip); 306 cs_deactive(drv_data, chip);
309 307
@@ -342,31 +340,20 @@ static void u8_cs_chg_reader(struct driver_data *drv_data)
342{ 340{
343 struct chip_data *chip = drv_data->cur_chip; 341 struct chip_data *chip = drv_data->cur_chip;
344 342
345 /* poll for SPI completion before start */ 343 while (drv_data->rx < drv_data->rx_end) {
346 while (!(read_STAT(drv_data) & BIT_STAT_SPIF)) 344 cs_active(drv_data, chip);
347 cpu_relax(); 345 read_RDBR(drv_data); /* kick off */
348
349 /* clear TDBR buffer before read(else it will be shifted out) */
350 write_TDBR(drv_data, 0xFFFF);
351 346
352 cs_active(drv_data, chip); 347 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
353 dummy_read(drv_data); 348 cpu_relax();
349 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
350 cpu_relax();
354 351
355 while (drv_data->rx < drv_data->rx_end - 1) { 352 *(u8 *) (drv_data->rx) = read_SHAW(drv_data);
356 cs_deactive(drv_data, chip); 353 cs_deactive(drv_data, chip);
357 354
358 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
359 cpu_relax();
360 cs_active(drv_data, chip);
361 *(u8 *) (drv_data->rx) = read_RDBR(drv_data);
362 ++drv_data->rx; 355 ++drv_data->rx;
363 } 356 }
364 cs_deactive(drv_data, chip);
365
366 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
367 cpu_relax();
368 *(u8 *) (drv_data->rx) = read_SHAW(drv_data);
369 ++drv_data->rx;
370} 357}
371 358
372static void u8_duplex(struct driver_data *drv_data) 359static void u8_duplex(struct driver_data *drv_data)
@@ -392,15 +379,12 @@ static void u8_cs_chg_duplex(struct driver_data *drv_data)
392{ 379{
393 struct chip_data *chip = drv_data->cur_chip; 380 struct chip_data *chip = drv_data->cur_chip;
394 381
395 /* poll for SPI completion before start */
396 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
397 cpu_relax();
398
399 while (drv_data->rx < drv_data->rx_end) { 382 while (drv_data->rx < drv_data->rx_end) {
400 cs_active(drv_data, chip); 383 cs_active(drv_data, chip);
401 384
402 write_TDBR(drv_data, (*(u8 *) (drv_data->tx))); 385 write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
403 while (read_STAT(drv_data) & BIT_STAT_TXS) 386
387 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
404 cpu_relax(); 388 cpu_relax();
405 while (!(read_STAT(drv_data) & BIT_STAT_RXS)) 389 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
406 cpu_relax(); 390 cpu_relax();