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authorUwe Kleine-König <u.kleine-koenig@pengutronix.de>2009-10-01 18:44:28 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2009-10-01 19:11:16 -0400
commit6cdeb00218b0d0eaf1329d1e6a0959ee3f0fa14c (patch)
tree7d743beba03f9a67c6c557b6d853ebd9e17b8cd5 /drivers/spi
parent80e50be4220e1244fcf6d5f75b997f8586ae1300 (diff)
spi-imx: rename source file to spi_imx.c
This makes the filename match the Kconfig symbol and the driver name. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Cc: Sascha Hauer <s.hauer@pengutronix.de> Cc: David Brownell <dbrownell@users.sourceforge.net> Cc: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Diffstat (limited to 'drivers/spi')
-rw-r--r--drivers/spi/Makefile2
-rw-r--r--drivers/spi/spi_imx.c (renamed from drivers/spi/mxc_spi.c)336
2 files changed, 169 insertions, 169 deletions
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 6d7a3f82c54b..21a118269cac 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -17,7 +17,7 @@ obj-$(CONFIG_SPI_BITBANG) += spi_bitbang.o
17obj-$(CONFIG_SPI_AU1550) += au1550_spi.o 17obj-$(CONFIG_SPI_AU1550) += au1550_spi.o
18obj-$(CONFIG_SPI_BUTTERFLY) += spi_butterfly.o 18obj-$(CONFIG_SPI_BUTTERFLY) += spi_butterfly.o
19obj-$(CONFIG_SPI_GPIO) += spi_gpio.o 19obj-$(CONFIG_SPI_GPIO) += spi_gpio.o
20obj-$(CONFIG_SPI_IMX) += mxc_spi.o 20obj-$(CONFIG_SPI_IMX) += spi_imx.o
21obj-$(CONFIG_SPI_LM70_LLP) += spi_lm70llp.o 21obj-$(CONFIG_SPI_LM70_LLP) += spi_lm70llp.o
22obj-$(CONFIG_SPI_PXA2XX) += pxa2xx_spi.o 22obj-$(CONFIG_SPI_PXA2XX) += pxa2xx_spi.o
23obj-$(CONFIG_SPI_OMAP_UWIRE) += omap_uwire.o 23obj-$(CONFIG_SPI_OMAP_UWIRE) += omap_uwire.o
diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/spi_imx.c
index b1447236ae81..b1f530fd6bdc 100644
--- a/drivers/spi/mxc_spi.c
+++ b/drivers/spi/spi_imx.c
@@ -48,14 +48,14 @@
48#define MXC_INT_RR (1 << 0) /* Receive data ready interrupt */ 48#define MXC_INT_RR (1 << 0) /* Receive data ready interrupt */
49#define MXC_INT_TE (1 << 1) /* Transmit FIFO empty interrupt */ 49#define MXC_INT_TE (1 << 1) /* Transmit FIFO empty interrupt */
50 50
51struct mxc_spi_config { 51struct spi_imx_config {
52 unsigned int speed_hz; 52 unsigned int speed_hz;
53 unsigned int bpw; 53 unsigned int bpw;
54 unsigned int mode; 54 unsigned int mode;
55 int cs; 55 int cs;
56}; 56};
57 57
58struct mxc_spi_data { 58struct spi_imx_data {
59 struct spi_bitbang bitbang; 59 struct spi_bitbang bitbang;
60 60
61 struct completion xfer_done; 61 struct completion xfer_done;
@@ -66,43 +66,43 @@ struct mxc_spi_data {
66 int *chipselect; 66 int *chipselect;
67 67
68 unsigned int count; 68 unsigned int count;
69 void (*tx)(struct mxc_spi_data *); 69 void (*tx)(struct spi_imx_data *);
70 void (*rx)(struct mxc_spi_data *); 70 void (*rx)(struct spi_imx_data *);
71 void *rx_buf; 71 void *rx_buf;
72 const void *tx_buf; 72 const void *tx_buf;
73 unsigned int txfifo; /* number of words pushed in tx FIFO */ 73 unsigned int txfifo; /* number of words pushed in tx FIFO */
74 74
75 /* SoC specific functions */ 75 /* SoC specific functions */
76 void (*intctrl)(struct mxc_spi_data *, int); 76 void (*intctrl)(struct spi_imx_data *, int);
77 int (*config)(struct mxc_spi_data *, struct mxc_spi_config *); 77 int (*config)(struct spi_imx_data *, struct spi_imx_config *);
78 void (*trigger)(struct mxc_spi_data *); 78 void (*trigger)(struct spi_imx_data *);
79 int (*rx_available)(struct mxc_spi_data *); 79 int (*rx_available)(struct spi_imx_data *);
80}; 80};
81 81
82#define MXC_SPI_BUF_RX(type) \ 82#define MXC_SPI_BUF_RX(type) \
83static void mxc_spi_buf_rx_##type(struct mxc_spi_data *mxc_spi) \ 83static void spi_imx_buf_rx_##type(struct spi_imx_data *spi_imx) \
84{ \ 84{ \
85 unsigned int val = readl(mxc_spi->base + MXC_CSPIRXDATA); \ 85 unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA); \
86 \ 86 \
87 if (mxc_spi->rx_buf) { \ 87 if (spi_imx->rx_buf) { \
88 *(type *)mxc_spi->rx_buf = val; \ 88 *(type *)spi_imx->rx_buf = val; \
89 mxc_spi->rx_buf += sizeof(type); \ 89 spi_imx->rx_buf += sizeof(type); \
90 } \ 90 } \
91} 91}
92 92
93#define MXC_SPI_BUF_TX(type) \ 93#define MXC_SPI_BUF_TX(type) \
94static void mxc_spi_buf_tx_##type(struct mxc_spi_data *mxc_spi) \ 94static void spi_imx_buf_tx_##type(struct spi_imx_data *spi_imx) \
95{ \ 95{ \
96 type val = 0; \ 96 type val = 0; \
97 \ 97 \
98 if (mxc_spi->tx_buf) { \ 98 if (spi_imx->tx_buf) { \
99 val = *(type *)mxc_spi->tx_buf; \ 99 val = *(type *)spi_imx->tx_buf; \
100 mxc_spi->tx_buf += sizeof(type); \ 100 spi_imx->tx_buf += sizeof(type); \
101 } \ 101 } \
102 \ 102 \
103 mxc_spi->count -= sizeof(type); \ 103 spi_imx->count -= sizeof(type); \
104 \ 104 \
105 writel(val, mxc_spi->base + MXC_CSPITXDATA); \ 105 writel(val, spi_imx->base + MXC_CSPITXDATA); \
106} 106}
107 107
108MXC_SPI_BUF_RX(u8) 108MXC_SPI_BUF_RX(u8)
@@ -119,7 +119,7 @@ static int mxc_clkdivs[] = {0, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128, 192,
119 256, 384, 512, 768, 1024}; 119 256, 384, 512, 768, 1024};
120 120
121/* MX21, MX27 */ 121/* MX21, MX27 */
122static unsigned int mxc_spi_clkdiv_1(unsigned int fin, 122static unsigned int spi_imx_clkdiv_1(unsigned int fin,
123 unsigned int fspi) 123 unsigned int fspi)
124{ 124{
125 int i, max; 125 int i, max;
@@ -137,7 +137,7 @@ static unsigned int mxc_spi_clkdiv_1(unsigned int fin,
137} 137}
138 138
139/* MX1, MX31, MX35 */ 139/* MX1, MX31, MX35 */
140static unsigned int mxc_spi_clkdiv_2(unsigned int fin, 140static unsigned int spi_imx_clkdiv_2(unsigned int fin,
141 unsigned int fspi) 141 unsigned int fspi)
142{ 142{
143 int i, div = 4; 143 int i, div = 4;
@@ -174,7 +174,7 @@ static unsigned int mxc_spi_clkdiv_2(unsigned int fin,
174 * the i.MX35 has a slightly different register layout for bits 174 * the i.MX35 has a slightly different register layout for bits
175 * we do not use here. 175 * we do not use here.
176 */ 176 */
177static void mx31_intctrl(struct mxc_spi_data *mxc_spi, int enable) 177static void mx31_intctrl(struct spi_imx_data *spi_imx, int enable)
178{ 178{
179 unsigned int val = 0; 179 unsigned int val = 0;
180 180
@@ -183,24 +183,24 @@ static void mx31_intctrl(struct mxc_spi_data *mxc_spi, int enable)
183 if (enable & MXC_INT_RR) 183 if (enable & MXC_INT_RR)
184 val |= MX31_INTREG_RREN; 184 val |= MX31_INTREG_RREN;
185 185
186 writel(val, mxc_spi->base + MXC_CSPIINT); 186 writel(val, spi_imx->base + MXC_CSPIINT);
187} 187}
188 188
189static void mx31_trigger(struct mxc_spi_data *mxc_spi) 189static void mx31_trigger(struct spi_imx_data *spi_imx)
190{ 190{
191 unsigned int reg; 191 unsigned int reg;
192 192
193 reg = readl(mxc_spi->base + MXC_CSPICTRL); 193 reg = readl(spi_imx->base + MXC_CSPICTRL);
194 reg |= MX31_CSPICTRL_XCH; 194 reg |= MX31_CSPICTRL_XCH;
195 writel(reg, mxc_spi->base + MXC_CSPICTRL); 195 writel(reg, spi_imx->base + MXC_CSPICTRL);
196} 196}
197 197
198static int mx31_config(struct mxc_spi_data *mxc_spi, 198static int mx31_config(struct spi_imx_data *spi_imx,
199 struct mxc_spi_config *config) 199 struct spi_imx_config *config)
200{ 200{
201 unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_MASTER; 201 unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_MASTER;
202 202
203 reg |= mxc_spi_clkdiv_2(mxc_spi->spi_clk, config->speed_hz) << 203 reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz) <<
204 MX31_CSPICTRL_DR_SHIFT; 204 MX31_CSPICTRL_DR_SHIFT;
205 205
206 if (cpu_is_mx31()) 206 if (cpu_is_mx31())
@@ -223,14 +223,14 @@ static int mx31_config(struct mxc_spi_data *mxc_spi,
223 reg |= (config->cs + 32) << MX35_CSPICTRL_CS_SHIFT; 223 reg |= (config->cs + 32) << MX35_CSPICTRL_CS_SHIFT;
224 } 224 }
225 225
226 writel(reg, mxc_spi->base + MXC_CSPICTRL); 226 writel(reg, spi_imx->base + MXC_CSPICTRL);
227 227
228 return 0; 228 return 0;
229} 229}
230 230
231static int mx31_rx_available(struct mxc_spi_data *mxc_spi) 231static int mx31_rx_available(struct spi_imx_data *spi_imx)
232{ 232{
233 return readl(mxc_spi->base + MX31_CSPISTATUS) & MX31_STATUS_RR; 233 return readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR;
234} 234}
235 235
236#define MX27_INTREG_RR (1 << 4) 236#define MX27_INTREG_RR (1 << 4)
@@ -246,7 +246,7 @@ static int mx31_rx_available(struct mxc_spi_data *mxc_spi)
246#define MX27_CSPICTRL_DR_SHIFT 14 246#define MX27_CSPICTRL_DR_SHIFT 14
247#define MX27_CSPICTRL_CS_SHIFT 19 247#define MX27_CSPICTRL_CS_SHIFT 19
248 248
249static void mx27_intctrl(struct mxc_spi_data *mxc_spi, int enable) 249static void mx27_intctrl(struct spi_imx_data *spi_imx, int enable)
250{ 250{
251 unsigned int val = 0; 251 unsigned int val = 0;
252 252
@@ -255,24 +255,24 @@ static void mx27_intctrl(struct mxc_spi_data *mxc_spi, int enable)
255 if (enable & MXC_INT_RR) 255 if (enable & MXC_INT_RR)
256 val |= MX27_INTREG_RREN; 256 val |= MX27_INTREG_RREN;
257 257
258 writel(val, mxc_spi->base + MXC_CSPIINT); 258 writel(val, spi_imx->base + MXC_CSPIINT);
259} 259}
260 260
261static void mx27_trigger(struct mxc_spi_data *mxc_spi) 261static void mx27_trigger(struct spi_imx_data *spi_imx)
262{ 262{
263 unsigned int reg; 263 unsigned int reg;
264 264
265 reg = readl(mxc_spi->base + MXC_CSPICTRL); 265 reg = readl(spi_imx->base + MXC_CSPICTRL);
266 reg |= MX27_CSPICTRL_XCH; 266 reg |= MX27_CSPICTRL_XCH;
267 writel(reg, mxc_spi->base + MXC_CSPICTRL); 267 writel(reg, spi_imx->base + MXC_CSPICTRL);
268} 268}
269 269
270static int mx27_config(struct mxc_spi_data *mxc_spi, 270static int mx27_config(struct spi_imx_data *spi_imx,
271 struct mxc_spi_config *config) 271 struct spi_imx_config *config)
272{ 272{
273 unsigned int reg = MX27_CSPICTRL_ENABLE | MX27_CSPICTRL_MASTER; 273 unsigned int reg = MX27_CSPICTRL_ENABLE | MX27_CSPICTRL_MASTER;
274 274
275 reg |= mxc_spi_clkdiv_1(mxc_spi->spi_clk, config->speed_hz) << 275 reg |= spi_imx_clkdiv_1(spi_imx->spi_clk, config->speed_hz) <<
276 MX27_CSPICTRL_DR_SHIFT; 276 MX27_CSPICTRL_DR_SHIFT;
277 reg |= config->bpw - 1; 277 reg |= config->bpw - 1;
278 278
@@ -285,14 +285,14 @@ static int mx27_config(struct mxc_spi_data *mxc_spi,
285 if (config->cs < 0) 285 if (config->cs < 0)
286 reg |= (config->cs + 32) << MX27_CSPICTRL_CS_SHIFT; 286 reg |= (config->cs + 32) << MX27_CSPICTRL_CS_SHIFT;
287 287
288 writel(reg, mxc_spi->base + MXC_CSPICTRL); 288 writel(reg, spi_imx->base + MXC_CSPICTRL);
289 289
290 return 0; 290 return 0;
291} 291}
292 292
293static int mx27_rx_available(struct mxc_spi_data *mxc_spi) 293static int mx27_rx_available(struct spi_imx_data *spi_imx)
294{ 294{
295 return readl(mxc_spi->base + MXC_CSPIINT) & MX27_INTREG_RR; 295 return readl(spi_imx->base + MXC_CSPIINT) & MX27_INTREG_RR;
296} 296}
297 297
298#define MX1_INTREG_RR (1 << 3) 298#define MX1_INTREG_RR (1 << 3)
@@ -306,7 +306,7 @@ static int mx27_rx_available(struct mxc_spi_data *mxc_spi)
306#define MX1_CSPICTRL_MASTER (1 << 10) 306#define MX1_CSPICTRL_MASTER (1 << 10)
307#define MX1_CSPICTRL_DR_SHIFT 13 307#define MX1_CSPICTRL_DR_SHIFT 13
308 308
309static void mx1_intctrl(struct mxc_spi_data *mxc_spi, int enable) 309static void mx1_intctrl(struct spi_imx_data *spi_imx, int enable)
310{ 310{
311 unsigned int val = 0; 311 unsigned int val = 0;
312 312
@@ -315,24 +315,24 @@ static void mx1_intctrl(struct mxc_spi_data *mxc_spi, int enable)
315 if (enable & MXC_INT_RR) 315 if (enable & MXC_INT_RR)
316 val |= MX1_INTREG_RREN; 316 val |= MX1_INTREG_RREN;
317 317
318 writel(val, mxc_spi->base + MXC_CSPIINT); 318 writel(val, spi_imx->base + MXC_CSPIINT);
319} 319}
320 320
321static void mx1_trigger(struct mxc_spi_data *mxc_spi) 321static void mx1_trigger(struct spi_imx_data *spi_imx)
322{ 322{
323 unsigned int reg; 323 unsigned int reg;
324 324
325 reg = readl(mxc_spi->base + MXC_CSPICTRL); 325 reg = readl(spi_imx->base + MXC_CSPICTRL);
326 reg |= MX1_CSPICTRL_XCH; 326 reg |= MX1_CSPICTRL_XCH;
327 writel(reg, mxc_spi->base + MXC_CSPICTRL); 327 writel(reg, spi_imx->base + MXC_CSPICTRL);
328} 328}
329 329
330static int mx1_config(struct mxc_spi_data *mxc_spi, 330static int mx1_config(struct spi_imx_data *spi_imx,
331 struct mxc_spi_config *config) 331 struct spi_imx_config *config)
332{ 332{
333 unsigned int reg = MX1_CSPICTRL_ENABLE | MX1_CSPICTRL_MASTER; 333 unsigned int reg = MX1_CSPICTRL_ENABLE | MX1_CSPICTRL_MASTER;
334 334
335 reg |= mxc_spi_clkdiv_2(mxc_spi->spi_clk, config->speed_hz) << 335 reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz) <<
336 MX1_CSPICTRL_DR_SHIFT; 336 MX1_CSPICTRL_DR_SHIFT;
337 reg |= config->bpw - 1; 337 reg |= config->bpw - 1;
338 338
@@ -341,22 +341,22 @@ static int mx1_config(struct mxc_spi_data *mxc_spi,
341 if (config->mode & SPI_CPOL) 341 if (config->mode & SPI_CPOL)
342 reg |= MX1_CSPICTRL_POL; 342 reg |= MX1_CSPICTRL_POL;
343 343
344 writel(reg, mxc_spi->base + MXC_CSPICTRL); 344 writel(reg, spi_imx->base + MXC_CSPICTRL);
345 345
346 return 0; 346 return 0;
347} 347}
348 348
349static int mx1_rx_available(struct mxc_spi_data *mxc_spi) 349static int mx1_rx_available(struct spi_imx_data *spi_imx)
350{ 350{
351 return readl(mxc_spi->base + MXC_CSPIINT) & MX1_INTREG_RR; 351 return readl(spi_imx->base + MXC_CSPIINT) & MX1_INTREG_RR;
352} 352}
353 353
354static void mxc_spi_chipselect(struct spi_device *spi, int is_active) 354static void spi_imx_chipselect(struct spi_device *spi, int is_active)
355{ 355{
356 struct mxc_spi_data *mxc_spi = spi_master_get_devdata(spi->master); 356 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
357 unsigned int cs = 0; 357 unsigned int cs = 0;
358 int gpio = mxc_spi->chipselect[spi->chip_select]; 358 int gpio = spi_imx->chipselect[spi->chip_select];
359 struct mxc_spi_config config; 359 struct spi_imx_config config;
360 360
361 if (spi->mode & SPI_CS_HIGH) 361 if (spi->mode & SPI_CS_HIGH)
362 cs = 1; 362 cs = 1;
@@ -370,20 +370,20 @@ static void mxc_spi_chipselect(struct spi_device *spi, int is_active)
370 config.bpw = spi->bits_per_word; 370 config.bpw = spi->bits_per_word;
371 config.speed_hz = spi->max_speed_hz; 371 config.speed_hz = spi->max_speed_hz;
372 config.mode = spi->mode; 372 config.mode = spi->mode;
373 config.cs = mxc_spi->chipselect[spi->chip_select]; 373 config.cs = spi_imx->chipselect[spi->chip_select];
374 374
375 mxc_spi->config(mxc_spi, &config); 375 spi_imx->config(spi_imx, &config);
376 376
377 /* Initialize the functions for transfer */ 377 /* Initialize the functions for transfer */
378 if (config.bpw <= 8) { 378 if (config.bpw <= 8) {
379 mxc_spi->rx = mxc_spi_buf_rx_u8; 379 spi_imx->rx = spi_imx_buf_rx_u8;
380 mxc_spi->tx = mxc_spi_buf_tx_u8; 380 spi_imx->tx = spi_imx_buf_tx_u8;
381 } else if (config.bpw <= 16) { 381 } else if (config.bpw <= 16) {
382 mxc_spi->rx = mxc_spi_buf_rx_u16; 382 spi_imx->rx = spi_imx_buf_rx_u16;
383 mxc_spi->tx = mxc_spi_buf_tx_u16; 383 spi_imx->tx = spi_imx_buf_tx_u16;
384 } else if (config.bpw <= 32) { 384 } else if (config.bpw <= 32) {
385 mxc_spi->rx = mxc_spi_buf_rx_u32; 385 spi_imx->rx = spi_imx_buf_rx_u32;
386 mxc_spi->tx = mxc_spi_buf_tx_u32; 386 spi_imx->tx = spi_imx_buf_tx_u32;
387 } else 387 } else
388 BUG(); 388 BUG();
389 389
@@ -393,83 +393,83 @@ static void mxc_spi_chipselect(struct spi_device *spi, int is_active)
393 return; 393 return;
394} 394}
395 395
396static void mxc_spi_push(struct mxc_spi_data *mxc_spi) 396static void spi_imx_push(struct spi_imx_data *spi_imx)
397{ 397{
398 while (mxc_spi->txfifo < 8) { 398 while (spi_imx->txfifo < 8) {
399 if (!mxc_spi->count) 399 if (!spi_imx->count)
400 break; 400 break;
401 mxc_spi->tx(mxc_spi); 401 spi_imx->tx(spi_imx);
402 mxc_spi->txfifo++; 402 spi_imx->txfifo++;
403 } 403 }
404 404
405 mxc_spi->trigger(mxc_spi); 405 spi_imx->trigger(spi_imx);
406} 406}
407 407
408static irqreturn_t mxc_spi_isr(int irq, void *dev_id) 408static irqreturn_t spi_imx_isr(int irq, void *dev_id)
409{ 409{
410 struct mxc_spi_data *mxc_spi = dev_id; 410 struct spi_imx_data *spi_imx = dev_id;
411 411
412 while (mxc_spi->rx_available(mxc_spi)) { 412 while (spi_imx->rx_available(spi_imx)) {
413 mxc_spi->rx(mxc_spi); 413 spi_imx->rx(spi_imx);
414 mxc_spi->txfifo--; 414 spi_imx->txfifo--;
415 } 415 }
416 416
417 if (mxc_spi->count) { 417 if (spi_imx->count) {
418 mxc_spi_push(mxc_spi); 418 spi_imx_push(spi_imx);
419 return IRQ_HANDLED; 419 return IRQ_HANDLED;
420 } 420 }
421 421
422 if (mxc_spi->txfifo) { 422 if (spi_imx->txfifo) {
423 /* No data left to push, but still waiting for rx data, 423 /* No data left to push, but still waiting for rx data,
424 * enable receive data available interrupt. 424 * enable receive data available interrupt.
425 */ 425 */
426 mxc_spi->intctrl(mxc_spi, MXC_INT_RR); 426 spi_imx->intctrl(spi_imx, MXC_INT_RR);
427 return IRQ_HANDLED; 427 return IRQ_HANDLED;
428 } 428 }
429 429
430 mxc_spi->intctrl(mxc_spi, 0); 430 spi_imx->intctrl(spi_imx, 0);
431 complete(&mxc_spi->xfer_done); 431 complete(&spi_imx->xfer_done);
432 432
433 return IRQ_HANDLED; 433 return IRQ_HANDLED;
434} 434}
435 435
436static int mxc_spi_setupxfer(struct spi_device *spi, 436static int spi_imx_setupxfer(struct spi_device *spi,
437 struct spi_transfer *t) 437 struct spi_transfer *t)
438{ 438{
439 struct mxc_spi_data *mxc_spi = spi_master_get_devdata(spi->master); 439 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
440 struct mxc_spi_config config; 440 struct spi_imx_config config;
441 441
442 config.bpw = t ? t->bits_per_word : spi->bits_per_word; 442 config.bpw = t ? t->bits_per_word : spi->bits_per_word;
443 config.speed_hz = t ? t->speed_hz : spi->max_speed_hz; 443 config.speed_hz = t ? t->speed_hz : spi->max_speed_hz;
444 config.mode = spi->mode; 444 config.mode = spi->mode;
445 445
446 mxc_spi->config(mxc_spi, &config); 446 spi_imx->config(spi_imx, &config);
447 447
448 return 0; 448 return 0;
449} 449}
450 450
451static int mxc_spi_transfer(struct spi_device *spi, 451static int spi_imx_transfer(struct spi_device *spi,
452 struct spi_transfer *transfer) 452 struct spi_transfer *transfer)
453{ 453{
454 struct mxc_spi_data *mxc_spi = spi_master_get_devdata(spi->master); 454 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
455 455
456 mxc_spi->tx_buf = transfer->tx_buf; 456 spi_imx->tx_buf = transfer->tx_buf;
457 mxc_spi->rx_buf = transfer->rx_buf; 457 spi_imx->rx_buf = transfer->rx_buf;
458 mxc_spi->count = transfer->len; 458 spi_imx->count = transfer->len;
459 mxc_spi->txfifo = 0; 459 spi_imx->txfifo = 0;
460 460
461 init_completion(&mxc_spi->xfer_done); 461 init_completion(&spi_imx->xfer_done);
462 462
463 mxc_spi_push(mxc_spi); 463 spi_imx_push(spi_imx);
464 464
465 mxc_spi->intctrl(mxc_spi, MXC_INT_TE); 465 spi_imx->intctrl(spi_imx, MXC_INT_TE);
466 466
467 wait_for_completion(&mxc_spi->xfer_done); 467 wait_for_completion(&spi_imx->xfer_done);
468 468
469 return transfer->len; 469 return transfer->len;
470} 470}
471 471
472static int mxc_spi_setup(struct spi_device *spi) 472static int spi_imx_setup(struct spi_device *spi)
473{ 473{
474 if (!spi->bits_per_word) 474 if (!spi->bits_per_word)
475 spi->bits_per_word = 8; 475 spi->bits_per_word = 8;
@@ -477,20 +477,20 @@ static int mxc_spi_setup(struct spi_device *spi)
477 pr_debug("%s: mode %d, %u bpw, %d hz\n", __func__, 477 pr_debug("%s: mode %d, %u bpw, %d hz\n", __func__,
478 spi->mode, spi->bits_per_word, spi->max_speed_hz); 478 spi->mode, spi->bits_per_word, spi->max_speed_hz);
479 479
480 mxc_spi_chipselect(spi, BITBANG_CS_INACTIVE); 480 spi_imx_chipselect(spi, BITBANG_CS_INACTIVE);
481 481
482 return 0; 482 return 0;
483} 483}
484 484
485static void mxc_spi_cleanup(struct spi_device *spi) 485static void spi_imx_cleanup(struct spi_device *spi)
486{ 486{
487} 487}
488 488
489static int __init mxc_spi_probe(struct platform_device *pdev) 489static int __init spi_imx_probe(struct platform_device *pdev)
490{ 490{
491 struct spi_imx_master *mxc_platform_info; 491 struct spi_imx_master *mxc_platform_info;
492 struct spi_master *master; 492 struct spi_master *master;
493 struct mxc_spi_data *mxc_spi; 493 struct spi_imx_data *spi_imx;
494 struct resource *res; 494 struct resource *res;
495 int i, ret; 495 int i, ret;
496 496
@@ -500,7 +500,7 @@ static int __init mxc_spi_probe(struct platform_device *pdev)
500 return -EINVAL; 500 return -EINVAL;
501 } 501 }
502 502
503 master = spi_alloc_master(&pdev->dev, sizeof(struct mxc_spi_data)); 503 master = spi_alloc_master(&pdev->dev, sizeof(struct spi_imx_data));
504 if (!master) 504 if (!master)
505 return -ENOMEM; 505 return -ENOMEM;
506 506
@@ -509,32 +509,32 @@ static int __init mxc_spi_probe(struct platform_device *pdev)
509 master->bus_num = pdev->id; 509 master->bus_num = pdev->id;
510 master->num_chipselect = mxc_platform_info->num_chipselect; 510 master->num_chipselect = mxc_platform_info->num_chipselect;
511 511
512 mxc_spi = spi_master_get_devdata(master); 512 spi_imx = spi_master_get_devdata(master);
513 mxc_spi->bitbang.master = spi_master_get(master); 513 spi_imx->bitbang.master = spi_master_get(master);
514 mxc_spi->chipselect = mxc_platform_info->chipselect; 514 spi_imx->chipselect = mxc_platform_info->chipselect;
515 515
516 for (i = 0; i < master->num_chipselect; i++) { 516 for (i = 0; i < master->num_chipselect; i++) {
517 if (mxc_spi->chipselect[i] < 0) 517 if (spi_imx->chipselect[i] < 0)
518 continue; 518 continue;
519 ret = gpio_request(mxc_spi->chipselect[i], DRIVER_NAME); 519 ret = gpio_request(spi_imx->chipselect[i], DRIVER_NAME);
520 if (ret) { 520 if (ret) {
521 i--; 521 i--;
522 while (i > 0) 522 while (i > 0)
523 if (mxc_spi->chipselect[i] >= 0) 523 if (spi_imx->chipselect[i] >= 0)
524 gpio_free(mxc_spi->chipselect[i--]); 524 gpio_free(spi_imx->chipselect[i--]);
525 dev_err(&pdev->dev, "can't get cs gpios"); 525 dev_err(&pdev->dev, "can't get cs gpios");
526 goto out_master_put; 526 goto out_master_put;
527 } 527 }
528 gpio_direction_output(mxc_spi->chipselect[i], 1); 528 gpio_direction_output(spi_imx->chipselect[i], 1);
529 } 529 }
530 530
531 mxc_spi->bitbang.chipselect = mxc_spi_chipselect; 531 spi_imx->bitbang.chipselect = spi_imx_chipselect;
532 mxc_spi->bitbang.setup_transfer = mxc_spi_setupxfer; 532 spi_imx->bitbang.setup_transfer = spi_imx_setupxfer;
533 mxc_spi->bitbang.txrx_bufs = mxc_spi_transfer; 533 spi_imx->bitbang.txrx_bufs = spi_imx_transfer;
534 mxc_spi->bitbang.master->setup = mxc_spi_setup; 534 spi_imx->bitbang.master->setup = spi_imx_setup;
535 mxc_spi->bitbang.master->cleanup = mxc_spi_cleanup; 535 spi_imx->bitbang.master->cleanup = spi_imx_cleanup;
536 536
537 init_completion(&mxc_spi->xfer_done); 537 init_completion(&spi_imx->xfer_done);
538 538
539 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 539 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
540 if (!res) { 540 if (!res) {
@@ -549,58 +549,58 @@ static int __init mxc_spi_probe(struct platform_device *pdev)
549 goto out_gpio_free; 549 goto out_gpio_free;
550 } 550 }
551 551
552 mxc_spi->base = ioremap(res->start, resource_size(res)); 552 spi_imx->base = ioremap(res->start, resource_size(res));
553 if (!mxc_spi->base) { 553 if (!spi_imx->base) {
554 ret = -EINVAL; 554 ret = -EINVAL;
555 goto out_release_mem; 555 goto out_release_mem;
556 } 556 }
557 557
558 mxc_spi->irq = platform_get_irq(pdev, 0); 558 spi_imx->irq = platform_get_irq(pdev, 0);
559 if (!mxc_spi->irq) { 559 if (!spi_imx->irq) {
560 ret = -EINVAL; 560 ret = -EINVAL;
561 goto out_iounmap; 561 goto out_iounmap;
562 } 562 }
563 563
564 ret = request_irq(mxc_spi->irq, mxc_spi_isr, 0, DRIVER_NAME, mxc_spi); 564 ret = request_irq(spi_imx->irq, spi_imx_isr, 0, DRIVER_NAME, spi_imx);
565 if (ret) { 565 if (ret) {
566 dev_err(&pdev->dev, "can't get irq%d: %d\n", mxc_spi->irq, ret); 566 dev_err(&pdev->dev, "can't get irq%d: %d\n", spi_imx->irq, ret);
567 goto out_iounmap; 567 goto out_iounmap;
568 } 568 }
569 569
570 if (cpu_is_mx31() || cpu_is_mx35()) { 570 if (cpu_is_mx31() || cpu_is_mx35()) {
571 mxc_spi->intctrl = mx31_intctrl; 571 spi_imx->intctrl = mx31_intctrl;
572 mxc_spi->config = mx31_config; 572 spi_imx->config = mx31_config;
573 mxc_spi->trigger = mx31_trigger; 573 spi_imx->trigger = mx31_trigger;
574 mxc_spi->rx_available = mx31_rx_available; 574 spi_imx->rx_available = mx31_rx_available;
575 } else if (cpu_is_mx27() || cpu_is_mx21()) { 575 } else if (cpu_is_mx27() || cpu_is_mx21()) {
576 mxc_spi->intctrl = mx27_intctrl; 576 spi_imx->intctrl = mx27_intctrl;
577 mxc_spi->config = mx27_config; 577 spi_imx->config = mx27_config;
578 mxc_spi->trigger = mx27_trigger; 578 spi_imx->trigger = mx27_trigger;
579 mxc_spi->rx_available = mx27_rx_available; 579 spi_imx->rx_available = mx27_rx_available;
580 } else if (cpu_is_mx1()) { 580 } else if (cpu_is_mx1()) {
581 mxc_spi->intctrl = mx1_intctrl; 581 spi_imx->intctrl = mx1_intctrl;
582 mxc_spi->config = mx1_config; 582 spi_imx->config = mx1_config;
583 mxc_spi->trigger = mx1_trigger; 583 spi_imx->trigger = mx1_trigger;
584 mxc_spi->rx_available = mx1_rx_available; 584 spi_imx->rx_available = mx1_rx_available;
585 } else 585 } else
586 BUG(); 586 BUG();
587 587
588 mxc_spi->clk = clk_get(&pdev->dev, NULL); 588 spi_imx->clk = clk_get(&pdev->dev, NULL);
589 if (IS_ERR(mxc_spi->clk)) { 589 if (IS_ERR(spi_imx->clk)) {
590 dev_err(&pdev->dev, "unable to get clock\n"); 590 dev_err(&pdev->dev, "unable to get clock\n");
591 ret = PTR_ERR(mxc_spi->clk); 591 ret = PTR_ERR(spi_imx->clk);
592 goto out_free_irq; 592 goto out_free_irq;
593 } 593 }
594 594
595 clk_enable(mxc_spi->clk); 595 clk_enable(spi_imx->clk);
596 mxc_spi->spi_clk = clk_get_rate(mxc_spi->clk); 596 spi_imx->spi_clk = clk_get_rate(spi_imx->clk);
597 597
598 if (!cpu_is_mx31() || !cpu_is_mx35()) 598 if (!cpu_is_mx31() || !cpu_is_mx35())
599 writel(1, mxc_spi->base + MXC_RESET); 599 writel(1, spi_imx->base + MXC_RESET);
600 600
601 mxc_spi->intctrl(mxc_spi, 0); 601 spi_imx->intctrl(spi_imx, 0);
602 602
603 ret = spi_bitbang_start(&mxc_spi->bitbang); 603 ret = spi_bitbang_start(&spi_imx->bitbang);
604 if (ret) { 604 if (ret) {
605 dev_err(&pdev->dev, "bitbang start failed with %d\n", ret); 605 dev_err(&pdev->dev, "bitbang start failed with %d\n", ret);
606 goto out_clk_put; 606 goto out_clk_put;
@@ -611,18 +611,18 @@ static int __init mxc_spi_probe(struct platform_device *pdev)
611 return ret; 611 return ret;
612 612
613out_clk_put: 613out_clk_put:
614 clk_disable(mxc_spi->clk); 614 clk_disable(spi_imx->clk);
615 clk_put(mxc_spi->clk); 615 clk_put(spi_imx->clk);
616out_free_irq: 616out_free_irq:
617 free_irq(mxc_spi->irq, mxc_spi); 617 free_irq(spi_imx->irq, spi_imx);
618out_iounmap: 618out_iounmap:
619 iounmap(mxc_spi->base); 619 iounmap(spi_imx->base);
620out_release_mem: 620out_release_mem:
621 release_mem_region(res->start, resource_size(res)); 621 release_mem_region(res->start, resource_size(res));
622out_gpio_free: 622out_gpio_free:
623 for (i = 0; i < master->num_chipselect; i++) 623 for (i = 0; i < master->num_chipselect; i++)
624 if (mxc_spi->chipselect[i] >= 0) 624 if (spi_imx->chipselect[i] >= 0)
625 gpio_free(mxc_spi->chipselect[i]); 625 gpio_free(spi_imx->chipselect[i]);
626out_master_put: 626out_master_put:
627 spi_master_put(master); 627 spi_master_put(master);
628 kfree(master); 628 kfree(master);
@@ -630,24 +630,24 @@ out_master_put:
630 return ret; 630 return ret;
631} 631}
632 632
633static int __exit mxc_spi_remove(struct platform_device *pdev) 633static int __exit spi_imx_remove(struct platform_device *pdev)
634{ 634{
635 struct spi_master *master = platform_get_drvdata(pdev); 635 struct spi_master *master = platform_get_drvdata(pdev);
636 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 636 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
637 struct mxc_spi_data *mxc_spi = spi_master_get_devdata(master); 637 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
638 int i; 638 int i;
639 639
640 spi_bitbang_stop(&mxc_spi->bitbang); 640 spi_bitbang_stop(&spi_imx->bitbang);
641 641
642 writel(0, mxc_spi->base + MXC_CSPICTRL); 642 writel(0, spi_imx->base + MXC_CSPICTRL);
643 clk_disable(mxc_spi->clk); 643 clk_disable(spi_imx->clk);
644 clk_put(mxc_spi->clk); 644 clk_put(spi_imx->clk);
645 free_irq(mxc_spi->irq, mxc_spi); 645 free_irq(spi_imx->irq, spi_imx);
646 iounmap(mxc_spi->base); 646 iounmap(spi_imx->base);
647 647
648 for (i = 0; i < master->num_chipselect; i++) 648 for (i = 0; i < master->num_chipselect; i++)
649 if (mxc_spi->chipselect[i] >= 0) 649 if (spi_imx->chipselect[i] >= 0)
650 gpio_free(mxc_spi->chipselect[i]); 650 gpio_free(spi_imx->chipselect[i]);
651 651
652 spi_master_put(master); 652 spi_master_put(master);
653 653
@@ -658,27 +658,27 @@ static int __exit mxc_spi_remove(struct platform_device *pdev)
658 return 0; 658 return 0;
659} 659}
660 660
661static struct platform_driver mxc_spi_driver = { 661static struct platform_driver spi_imx_driver = {
662 .driver = { 662 .driver = {
663 .name = DRIVER_NAME, 663 .name = DRIVER_NAME,
664 .owner = THIS_MODULE, 664 .owner = THIS_MODULE,
665 }, 665 },
666 .probe = mxc_spi_probe, 666 .probe = spi_imx_probe,
667 .remove = __exit_p(mxc_spi_remove), 667 .remove = __exit_p(spi_imx_remove),
668}; 668};
669 669
670static int __init mxc_spi_init(void) 670static int __init spi_imx_init(void)
671{ 671{
672 return platform_driver_register(&mxc_spi_driver); 672 return platform_driver_register(&spi_imx_driver);
673} 673}
674 674
675static void __exit mxc_spi_exit(void) 675static void __exit spi_imx_exit(void)
676{ 676{
677 platform_driver_unregister(&mxc_spi_driver); 677 platform_driver_unregister(&spi_imx_driver);
678} 678}
679 679
680module_init(mxc_spi_init); 680module_init(spi_imx_init);
681module_exit(mxc_spi_exit); 681module_exit(spi_imx_exit);
682 682
683MODULE_DESCRIPTION("SPI Master Controller driver"); 683MODULE_DESCRIPTION("SPI Master Controller driver");
684MODULE_AUTHOR("Sascha Hauer, Pengutronix"); 684MODULE_AUTHOR("Sascha Hauer, Pengutronix");