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authorRussell King <rmk+kernel@arm.linux.org.uk>2009-09-24 16:22:33 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2009-09-24 16:22:33 -0400
commitbaea7b946f00a291b166ccae7fcfed6c01530cc6 (patch)
tree4aa275fbdbec9c7b9b4629e8bee2bbecd3c6a6af /drivers/spi
parentae19ffbadc1b2100285a5b5b3d0a4e0a11390904 (diff)
parent94e0fb086fc5663c38bbc0fe86d698be8314f82f (diff)
Merge branch 'origin' into for-linus
Conflicts: MAINTAINERS
Diffstat (limited to 'drivers/spi')
-rw-r--r--drivers/spi/Kconfig23
-rw-r--r--drivers/spi/Makefile4
-rw-r--r--drivers/spi/mxc_spi.c685
-rw-r--r--drivers/spi/omap2_mcspi.c210
-rw-r--r--drivers/spi/omap_uwire.c2
-rw-r--r--drivers/spi/pxa2xx_spi.c2
-rw-r--r--drivers/spi/spi.c85
-rw-r--r--drivers/spi/spi_imx.c1770
-rw-r--r--drivers/spi/spi_ppc4xx.c612
-rw-r--r--drivers/spi/spi_s3c24xx.c159
-rw-r--r--drivers/spi/spi_stmp.c679
-rw-r--r--drivers/spi/spidev.c1
-rw-r--r--drivers/spi/tle62x0.c1
13 files changed, 2340 insertions, 1893 deletions
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 2c733c27db2f..4b6f7cba3b3d 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -117,10 +117,11 @@ config SPI_GPIO
117 speed with a custom version of this driver; see the source code. 117 speed with a custom version of this driver; see the source code.
118 118
119config SPI_IMX 119config SPI_IMX
120 tristate "Freescale iMX SPI controller" 120 tristate "Freescale i.MX SPI controllers"
121 depends on ARCH_MX1 && EXPERIMENTAL 121 depends on ARCH_MXC
122 select SPI_BITBANG
122 help 123 help
123 This enables using the Freescale iMX SPI controller in master 124 This enables using the Freescale i.MX SPI controllers in master
124 mode. 125 mode.
125 126
126config SPI_LM70_LLP 127config SPI_LM70_LLP
@@ -173,11 +174,21 @@ config SPI_PL022
173 tristate "ARM AMBA PL022 SSP controller (EXPERIMENTAL)" 174 tristate "ARM AMBA PL022 SSP controller (EXPERIMENTAL)"
174 depends on ARM_AMBA && EXPERIMENTAL 175 depends on ARM_AMBA && EXPERIMENTAL
175 default y if MACH_U300 176 default y if MACH_U300
177 default y if ARCH_REALVIEW
178 default y if INTEGRATOR_IMPD1
179 default y if ARCH_VERSATILE
176 help 180 help
177 This selects the ARM(R) AMBA(R) PrimeCell PL022 SSP 181 This selects the ARM(R) AMBA(R) PrimeCell PL022 SSP
178 controller. If you have an embedded system with an AMBA(R) 182 controller. If you have an embedded system with an AMBA(R)
179 bus and a PL022 controller, say Y or M here. 183 bus and a PL022 controller, say Y or M here.
180 184
185config SPI_PPC4xx
186 tristate "PPC4xx SPI Controller"
187 depends on PPC32 && 4xx && SPI_MASTER
188 select SPI_BITBANG
189 help
190 This selects a driver for the PPC4xx SPI Controller.
191
181config SPI_PXA2XX 192config SPI_PXA2XX
182 tristate "PXA2xx SSP SPI master" 193 tristate "PXA2xx SSP SPI master"
183 depends on ARCH_PXA && EXPERIMENTAL 194 depends on ARCH_PXA && EXPERIMENTAL
@@ -211,6 +222,12 @@ config SPI_SH_SCI
211 help 222 help
212 SPI driver for SuperH SCI blocks. 223 SPI driver for SuperH SCI blocks.
213 224
225config SPI_STMP3XXX
226 tristate "Freescale STMP37xx/378x SPI/SSP controller"
227 depends on ARCH_STMP3XXX && SPI_MASTER
228 help
229 SPI driver for Freescale STMP37xx/378x SoC SSP interface
230
214config SPI_TXX9 231config SPI_TXX9
215 tristate "Toshiba TXx9 SPI controller" 232 tristate "Toshiba TXx9 SPI controller"
216 depends on GENERIC_GPIO && CPU_TX49XX 233 depends on GENERIC_GPIO && CPU_TX49XX
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 3de408d294ba..6d7a3f82c54b 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -17,7 +17,7 @@ obj-$(CONFIG_SPI_BITBANG) += spi_bitbang.o
17obj-$(CONFIG_SPI_AU1550) += au1550_spi.o 17obj-$(CONFIG_SPI_AU1550) += au1550_spi.o
18obj-$(CONFIG_SPI_BUTTERFLY) += spi_butterfly.o 18obj-$(CONFIG_SPI_BUTTERFLY) += spi_butterfly.o
19obj-$(CONFIG_SPI_GPIO) += spi_gpio.o 19obj-$(CONFIG_SPI_GPIO) += spi_gpio.o
20obj-$(CONFIG_SPI_IMX) += spi_imx.o 20obj-$(CONFIG_SPI_IMX) += mxc_spi.o
21obj-$(CONFIG_SPI_LM70_LLP) += spi_lm70llp.o 21obj-$(CONFIG_SPI_LM70_LLP) += spi_lm70llp.o
22obj-$(CONFIG_SPI_PXA2XX) += pxa2xx_spi.o 22obj-$(CONFIG_SPI_PXA2XX) += pxa2xx_spi.o
23obj-$(CONFIG_SPI_OMAP_UWIRE) += omap_uwire.o 23obj-$(CONFIG_SPI_OMAP_UWIRE) += omap_uwire.o
@@ -26,11 +26,13 @@ obj-$(CONFIG_SPI_ORION) += orion_spi.o
26obj-$(CONFIG_SPI_PL022) += amba-pl022.o 26obj-$(CONFIG_SPI_PL022) += amba-pl022.o
27obj-$(CONFIG_SPI_MPC52xx_PSC) += mpc52xx_psc_spi.o 27obj-$(CONFIG_SPI_MPC52xx_PSC) += mpc52xx_psc_spi.o
28obj-$(CONFIG_SPI_MPC8xxx) += spi_mpc8xxx.o 28obj-$(CONFIG_SPI_MPC8xxx) += spi_mpc8xxx.o
29obj-$(CONFIG_SPI_PPC4xx) += spi_ppc4xx.o
29obj-$(CONFIG_SPI_S3C24XX_GPIO) += spi_s3c24xx_gpio.o 30obj-$(CONFIG_SPI_S3C24XX_GPIO) += spi_s3c24xx_gpio.o
30obj-$(CONFIG_SPI_S3C24XX) += spi_s3c24xx.o 31obj-$(CONFIG_SPI_S3C24XX) += spi_s3c24xx.o
31obj-$(CONFIG_SPI_TXX9) += spi_txx9.o 32obj-$(CONFIG_SPI_TXX9) += spi_txx9.o
32obj-$(CONFIG_SPI_XILINX) += xilinx_spi.o 33obj-$(CONFIG_SPI_XILINX) += xilinx_spi.o
33obj-$(CONFIG_SPI_SH_SCI) += spi_sh_sci.o 34obj-$(CONFIG_SPI_SH_SCI) += spi_sh_sci.o
35obj-$(CONFIG_SPI_STMP3XXX) += spi_stmp.o
34# ... add above this line ... 36# ... add above this line ...
35 37
36# SPI protocol drivers (device/link on bus) 38# SPI protocol drivers (device/link on bus)
diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c
new file mode 100644
index 000000000000..b1447236ae81
--- /dev/null
+++ b/drivers/spi/mxc_spi.c
@@ -0,0 +1,685 @@
1/*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright (C) 2008 Juergen Beisert
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the
16 * Free Software Foundation
17 * 51 Franklin Street, Fifth Floor
18 * Boston, MA 02110-1301, USA.
19 */
20
21#include <linux/clk.h>
22#include <linux/completion.h>
23#include <linux/delay.h>
24#include <linux/err.h>
25#include <linux/gpio.h>
26#include <linux/init.h>
27#include <linux/interrupt.h>
28#include <linux/io.h>
29#include <linux/irq.h>
30#include <linux/kernel.h>
31#include <linux/module.h>
32#include <linux/platform_device.h>
33#include <linux/spi/spi.h>
34#include <linux/spi/spi_bitbang.h>
35#include <linux/types.h>
36
37#include <mach/spi.h>
38
39#define DRIVER_NAME "spi_imx"
40
41#define MXC_CSPIRXDATA 0x00
42#define MXC_CSPITXDATA 0x04
43#define MXC_CSPICTRL 0x08
44#define MXC_CSPIINT 0x0c
45#define MXC_RESET 0x1c
46
47/* generic defines to abstract from the different register layouts */
48#define MXC_INT_RR (1 << 0) /* Receive data ready interrupt */
49#define MXC_INT_TE (1 << 1) /* Transmit FIFO empty interrupt */
50
51struct mxc_spi_config {
52 unsigned int speed_hz;
53 unsigned int bpw;
54 unsigned int mode;
55 int cs;
56};
57
58struct mxc_spi_data {
59 struct spi_bitbang bitbang;
60
61 struct completion xfer_done;
62 void *base;
63 int irq;
64 struct clk *clk;
65 unsigned long spi_clk;
66 int *chipselect;
67
68 unsigned int count;
69 void (*tx)(struct mxc_spi_data *);
70 void (*rx)(struct mxc_spi_data *);
71 void *rx_buf;
72 const void *tx_buf;
73 unsigned int txfifo; /* number of words pushed in tx FIFO */
74
75 /* SoC specific functions */
76 void (*intctrl)(struct mxc_spi_data *, int);
77 int (*config)(struct mxc_spi_data *, struct mxc_spi_config *);
78 void (*trigger)(struct mxc_spi_data *);
79 int (*rx_available)(struct mxc_spi_data *);
80};
81
82#define MXC_SPI_BUF_RX(type) \
83static void mxc_spi_buf_rx_##type(struct mxc_spi_data *mxc_spi) \
84{ \
85 unsigned int val = readl(mxc_spi->base + MXC_CSPIRXDATA); \
86 \
87 if (mxc_spi->rx_buf) { \
88 *(type *)mxc_spi->rx_buf = val; \
89 mxc_spi->rx_buf += sizeof(type); \
90 } \
91}
92
93#define MXC_SPI_BUF_TX(type) \
94static void mxc_spi_buf_tx_##type(struct mxc_spi_data *mxc_spi) \
95{ \
96 type val = 0; \
97 \
98 if (mxc_spi->tx_buf) { \
99 val = *(type *)mxc_spi->tx_buf; \
100 mxc_spi->tx_buf += sizeof(type); \
101 } \
102 \
103 mxc_spi->count -= sizeof(type); \
104 \
105 writel(val, mxc_spi->base + MXC_CSPITXDATA); \
106}
107
108MXC_SPI_BUF_RX(u8)
109MXC_SPI_BUF_TX(u8)
110MXC_SPI_BUF_RX(u16)
111MXC_SPI_BUF_TX(u16)
112MXC_SPI_BUF_RX(u32)
113MXC_SPI_BUF_TX(u32)
114
115/* First entry is reserved, second entry is valid only if SDHC_SPIEN is set
116 * (which is currently not the case in this driver)
117 */
118static int mxc_clkdivs[] = {0, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128, 192,
119 256, 384, 512, 768, 1024};
120
121/* MX21, MX27 */
122static unsigned int mxc_spi_clkdiv_1(unsigned int fin,
123 unsigned int fspi)
124{
125 int i, max;
126
127 if (cpu_is_mx21())
128 max = 18;
129 else
130 max = 16;
131
132 for (i = 2; i < max; i++)
133 if (fspi * mxc_clkdivs[i] >= fin)
134 return i;
135
136 return max;
137}
138
139/* MX1, MX31, MX35 */
140static unsigned int mxc_spi_clkdiv_2(unsigned int fin,
141 unsigned int fspi)
142{
143 int i, div = 4;
144
145 for (i = 0; i < 7; i++) {
146 if (fspi * div >= fin)
147 return i;
148 div <<= 1;
149 }
150
151 return 7;
152}
153
154#define MX31_INTREG_TEEN (1 << 0)
155#define MX31_INTREG_RREN (1 << 3)
156
157#define MX31_CSPICTRL_ENABLE (1 << 0)
158#define MX31_CSPICTRL_MASTER (1 << 1)
159#define MX31_CSPICTRL_XCH (1 << 2)
160#define MX31_CSPICTRL_POL (1 << 4)
161#define MX31_CSPICTRL_PHA (1 << 5)
162#define MX31_CSPICTRL_SSCTL (1 << 6)
163#define MX31_CSPICTRL_SSPOL (1 << 7)
164#define MX31_CSPICTRL_BC_SHIFT 8
165#define MX35_CSPICTRL_BL_SHIFT 20
166#define MX31_CSPICTRL_CS_SHIFT 24
167#define MX35_CSPICTRL_CS_SHIFT 12
168#define MX31_CSPICTRL_DR_SHIFT 16
169
170#define MX31_CSPISTATUS 0x14
171#define MX31_STATUS_RR (1 << 3)
172
173/* These functions also work for the i.MX35, but be aware that
174 * the i.MX35 has a slightly different register layout for bits
175 * we do not use here.
176 */
177static void mx31_intctrl(struct mxc_spi_data *mxc_spi, int enable)
178{
179 unsigned int val = 0;
180
181 if (enable & MXC_INT_TE)
182 val |= MX31_INTREG_TEEN;
183 if (enable & MXC_INT_RR)
184 val |= MX31_INTREG_RREN;
185
186 writel(val, mxc_spi->base + MXC_CSPIINT);
187}
188
189static void mx31_trigger(struct mxc_spi_data *mxc_spi)
190{
191 unsigned int reg;
192
193 reg = readl(mxc_spi->base + MXC_CSPICTRL);
194 reg |= MX31_CSPICTRL_XCH;
195 writel(reg, mxc_spi->base + MXC_CSPICTRL);
196}
197
198static int mx31_config(struct mxc_spi_data *mxc_spi,
199 struct mxc_spi_config *config)
200{
201 unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_MASTER;
202
203 reg |= mxc_spi_clkdiv_2(mxc_spi->spi_clk, config->speed_hz) <<
204 MX31_CSPICTRL_DR_SHIFT;
205
206 if (cpu_is_mx31())
207 reg |= (config->bpw - 1) << MX31_CSPICTRL_BC_SHIFT;
208 else if (cpu_is_mx35()) {
209 reg |= (config->bpw - 1) << MX35_CSPICTRL_BL_SHIFT;
210 reg |= MX31_CSPICTRL_SSCTL;
211 }
212
213 if (config->mode & SPI_CPHA)
214 reg |= MX31_CSPICTRL_PHA;
215 if (config->mode & SPI_CPOL)
216 reg |= MX31_CSPICTRL_POL;
217 if (config->mode & SPI_CS_HIGH)
218 reg |= MX31_CSPICTRL_SSPOL;
219 if (config->cs < 0) {
220 if (cpu_is_mx31())
221 reg |= (config->cs + 32) << MX31_CSPICTRL_CS_SHIFT;
222 else if (cpu_is_mx35())
223 reg |= (config->cs + 32) << MX35_CSPICTRL_CS_SHIFT;
224 }
225
226 writel(reg, mxc_spi->base + MXC_CSPICTRL);
227
228 return 0;
229}
230
231static int mx31_rx_available(struct mxc_spi_data *mxc_spi)
232{
233 return readl(mxc_spi->base + MX31_CSPISTATUS) & MX31_STATUS_RR;
234}
235
236#define MX27_INTREG_RR (1 << 4)
237#define MX27_INTREG_TEEN (1 << 9)
238#define MX27_INTREG_RREN (1 << 13)
239
240#define MX27_CSPICTRL_POL (1 << 5)
241#define MX27_CSPICTRL_PHA (1 << 6)
242#define MX27_CSPICTRL_SSPOL (1 << 8)
243#define MX27_CSPICTRL_XCH (1 << 9)
244#define MX27_CSPICTRL_ENABLE (1 << 10)
245#define MX27_CSPICTRL_MASTER (1 << 11)
246#define MX27_CSPICTRL_DR_SHIFT 14
247#define MX27_CSPICTRL_CS_SHIFT 19
248
249static void mx27_intctrl(struct mxc_spi_data *mxc_spi, int enable)
250{
251 unsigned int val = 0;
252
253 if (enable & MXC_INT_TE)
254 val |= MX27_INTREG_TEEN;
255 if (enable & MXC_INT_RR)
256 val |= MX27_INTREG_RREN;
257
258 writel(val, mxc_spi->base + MXC_CSPIINT);
259}
260
261static void mx27_trigger(struct mxc_spi_data *mxc_spi)
262{
263 unsigned int reg;
264
265 reg = readl(mxc_spi->base + MXC_CSPICTRL);
266 reg |= MX27_CSPICTRL_XCH;
267 writel(reg, mxc_spi->base + MXC_CSPICTRL);
268}
269
270static int mx27_config(struct mxc_spi_data *mxc_spi,
271 struct mxc_spi_config *config)
272{
273 unsigned int reg = MX27_CSPICTRL_ENABLE | MX27_CSPICTRL_MASTER;
274
275 reg |= mxc_spi_clkdiv_1(mxc_spi->spi_clk, config->speed_hz) <<
276 MX27_CSPICTRL_DR_SHIFT;
277 reg |= config->bpw - 1;
278
279 if (config->mode & SPI_CPHA)
280 reg |= MX27_CSPICTRL_PHA;
281 if (config->mode & SPI_CPOL)
282 reg |= MX27_CSPICTRL_POL;
283 if (config->mode & SPI_CS_HIGH)
284 reg |= MX27_CSPICTRL_SSPOL;
285 if (config->cs < 0)
286 reg |= (config->cs + 32) << MX27_CSPICTRL_CS_SHIFT;
287
288 writel(reg, mxc_spi->base + MXC_CSPICTRL);
289
290 return 0;
291}
292
293static int mx27_rx_available(struct mxc_spi_data *mxc_spi)
294{
295 return readl(mxc_spi->base + MXC_CSPIINT) & MX27_INTREG_RR;
296}
297
298#define MX1_INTREG_RR (1 << 3)
299#define MX1_INTREG_TEEN (1 << 8)
300#define MX1_INTREG_RREN (1 << 11)
301
302#define MX1_CSPICTRL_POL (1 << 4)
303#define MX1_CSPICTRL_PHA (1 << 5)
304#define MX1_CSPICTRL_XCH (1 << 8)
305#define MX1_CSPICTRL_ENABLE (1 << 9)
306#define MX1_CSPICTRL_MASTER (1 << 10)
307#define MX1_CSPICTRL_DR_SHIFT 13
308
309static void mx1_intctrl(struct mxc_spi_data *mxc_spi, int enable)
310{
311 unsigned int val = 0;
312
313 if (enable & MXC_INT_TE)
314 val |= MX1_INTREG_TEEN;
315 if (enable & MXC_INT_RR)
316 val |= MX1_INTREG_RREN;
317
318 writel(val, mxc_spi->base + MXC_CSPIINT);
319}
320
321static void mx1_trigger(struct mxc_spi_data *mxc_spi)
322{
323 unsigned int reg;
324
325 reg = readl(mxc_spi->base + MXC_CSPICTRL);
326 reg |= MX1_CSPICTRL_XCH;
327 writel(reg, mxc_spi->base + MXC_CSPICTRL);
328}
329
330static int mx1_config(struct mxc_spi_data *mxc_spi,
331 struct mxc_spi_config *config)
332{
333 unsigned int reg = MX1_CSPICTRL_ENABLE | MX1_CSPICTRL_MASTER;
334
335 reg |= mxc_spi_clkdiv_2(mxc_spi->spi_clk, config->speed_hz) <<
336 MX1_CSPICTRL_DR_SHIFT;
337 reg |= config->bpw - 1;
338
339 if (config->mode & SPI_CPHA)
340 reg |= MX1_CSPICTRL_PHA;
341 if (config->mode & SPI_CPOL)
342 reg |= MX1_CSPICTRL_POL;
343
344 writel(reg, mxc_spi->base + MXC_CSPICTRL);
345
346 return 0;
347}
348
349static int mx1_rx_available(struct mxc_spi_data *mxc_spi)
350{
351 return readl(mxc_spi->base + MXC_CSPIINT) & MX1_INTREG_RR;
352}
353
354static void mxc_spi_chipselect(struct spi_device *spi, int is_active)
355{
356 struct mxc_spi_data *mxc_spi = spi_master_get_devdata(spi->master);
357 unsigned int cs = 0;
358 int gpio = mxc_spi->chipselect[spi->chip_select];
359 struct mxc_spi_config config;
360
361 if (spi->mode & SPI_CS_HIGH)
362 cs = 1;
363
364 if (is_active == BITBANG_CS_INACTIVE) {
365 if (gpio >= 0)
366 gpio_set_value(gpio, !cs);
367 return;
368 }
369
370 config.bpw = spi->bits_per_word;
371 config.speed_hz = spi->max_speed_hz;
372 config.mode = spi->mode;
373 config.cs = mxc_spi->chipselect[spi->chip_select];
374
375 mxc_spi->config(mxc_spi, &config);
376
377 /* Initialize the functions for transfer */
378 if (config.bpw <= 8) {
379 mxc_spi->rx = mxc_spi_buf_rx_u8;
380 mxc_spi->tx = mxc_spi_buf_tx_u8;
381 } else if (config.bpw <= 16) {
382 mxc_spi->rx = mxc_spi_buf_rx_u16;
383 mxc_spi->tx = mxc_spi_buf_tx_u16;
384 } else if (config.bpw <= 32) {
385 mxc_spi->rx = mxc_spi_buf_rx_u32;
386 mxc_spi->tx = mxc_spi_buf_tx_u32;
387 } else
388 BUG();
389
390 if (gpio >= 0)
391 gpio_set_value(gpio, cs);
392
393 return;
394}
395
396static void mxc_spi_push(struct mxc_spi_data *mxc_spi)
397{
398 while (mxc_spi->txfifo < 8) {
399 if (!mxc_spi->count)
400 break;
401 mxc_spi->tx(mxc_spi);
402 mxc_spi->txfifo++;
403 }
404
405 mxc_spi->trigger(mxc_spi);
406}
407
408static irqreturn_t mxc_spi_isr(int irq, void *dev_id)
409{
410 struct mxc_spi_data *mxc_spi = dev_id;
411
412 while (mxc_spi->rx_available(mxc_spi)) {
413 mxc_spi->rx(mxc_spi);
414 mxc_spi->txfifo--;
415 }
416
417 if (mxc_spi->count) {
418 mxc_spi_push(mxc_spi);
419 return IRQ_HANDLED;
420 }
421
422 if (mxc_spi->txfifo) {
423 /* No data left to push, but still waiting for rx data,
424 * enable receive data available interrupt.
425 */
426 mxc_spi->intctrl(mxc_spi, MXC_INT_RR);
427 return IRQ_HANDLED;
428 }
429
430 mxc_spi->intctrl(mxc_spi, 0);
431 complete(&mxc_spi->xfer_done);
432
433 return IRQ_HANDLED;
434}
435
436static int mxc_spi_setupxfer(struct spi_device *spi,
437 struct spi_transfer *t)
438{
439 struct mxc_spi_data *mxc_spi = spi_master_get_devdata(spi->master);
440 struct mxc_spi_config config;
441
442 config.bpw = t ? t->bits_per_word : spi->bits_per_word;
443 config.speed_hz = t ? t->speed_hz : spi->max_speed_hz;
444 config.mode = spi->mode;
445
446 mxc_spi->config(mxc_spi, &config);
447
448 return 0;
449}
450
451static int mxc_spi_transfer(struct spi_device *spi,
452 struct spi_transfer *transfer)
453{
454 struct mxc_spi_data *mxc_spi = spi_master_get_devdata(spi->master);
455
456 mxc_spi->tx_buf = transfer->tx_buf;
457 mxc_spi->rx_buf = transfer->rx_buf;
458 mxc_spi->count = transfer->len;
459 mxc_spi->txfifo = 0;
460
461 init_completion(&mxc_spi->xfer_done);
462
463 mxc_spi_push(mxc_spi);
464
465 mxc_spi->intctrl(mxc_spi, MXC_INT_TE);
466
467 wait_for_completion(&mxc_spi->xfer_done);
468
469 return transfer->len;
470}
471
472static int mxc_spi_setup(struct spi_device *spi)
473{
474 if (!spi->bits_per_word)
475 spi->bits_per_word = 8;
476
477 pr_debug("%s: mode %d, %u bpw, %d hz\n", __func__,
478 spi->mode, spi->bits_per_word, spi->max_speed_hz);
479
480 mxc_spi_chipselect(spi, BITBANG_CS_INACTIVE);
481
482 return 0;
483}
484
485static void mxc_spi_cleanup(struct spi_device *spi)
486{
487}
488
489static int __init mxc_spi_probe(struct platform_device *pdev)
490{
491 struct spi_imx_master *mxc_platform_info;
492 struct spi_master *master;
493 struct mxc_spi_data *mxc_spi;
494 struct resource *res;
495 int i, ret;
496
497 mxc_platform_info = (struct spi_imx_master *)pdev->dev.platform_data;
498 if (!mxc_platform_info) {
499 dev_err(&pdev->dev, "can't get the platform data\n");
500 return -EINVAL;
501 }
502
503 master = spi_alloc_master(&pdev->dev, sizeof(struct mxc_spi_data));
504 if (!master)
505 return -ENOMEM;
506
507 platform_set_drvdata(pdev, master);
508
509 master->bus_num = pdev->id;
510 master->num_chipselect = mxc_platform_info->num_chipselect;
511
512 mxc_spi = spi_master_get_devdata(master);
513 mxc_spi->bitbang.master = spi_master_get(master);
514 mxc_spi->chipselect = mxc_platform_info->chipselect;
515
516 for (i = 0; i < master->num_chipselect; i++) {
517 if (mxc_spi->chipselect[i] < 0)
518 continue;
519 ret = gpio_request(mxc_spi->chipselect[i], DRIVER_NAME);
520 if (ret) {
521 i--;
522 while (i > 0)
523 if (mxc_spi->chipselect[i] >= 0)
524 gpio_free(mxc_spi->chipselect[i--]);
525 dev_err(&pdev->dev, "can't get cs gpios");
526 goto out_master_put;
527 }
528 gpio_direction_output(mxc_spi->chipselect[i], 1);
529 }
530
531 mxc_spi->bitbang.chipselect = mxc_spi_chipselect;
532 mxc_spi->bitbang.setup_transfer = mxc_spi_setupxfer;
533 mxc_spi->bitbang.txrx_bufs = mxc_spi_transfer;
534 mxc_spi->bitbang.master->setup = mxc_spi_setup;
535 mxc_spi->bitbang.master->cleanup = mxc_spi_cleanup;
536
537 init_completion(&mxc_spi->xfer_done);
538
539 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
540 if (!res) {
541 dev_err(&pdev->dev, "can't get platform resource\n");
542 ret = -ENOMEM;
543 goto out_gpio_free;
544 }
545
546 if (!request_mem_region(res->start, resource_size(res), pdev->name)) {
547 dev_err(&pdev->dev, "request_mem_region failed\n");
548 ret = -EBUSY;
549 goto out_gpio_free;
550 }
551
552 mxc_spi->base = ioremap(res->start, resource_size(res));
553 if (!mxc_spi->base) {
554 ret = -EINVAL;
555 goto out_release_mem;
556 }
557
558 mxc_spi->irq = platform_get_irq(pdev, 0);
559 if (!mxc_spi->irq) {
560 ret = -EINVAL;
561 goto out_iounmap;
562 }
563
564 ret = request_irq(mxc_spi->irq, mxc_spi_isr, 0, DRIVER_NAME, mxc_spi);
565 if (ret) {
566 dev_err(&pdev->dev, "can't get irq%d: %d\n", mxc_spi->irq, ret);
567 goto out_iounmap;
568 }
569
570 if (cpu_is_mx31() || cpu_is_mx35()) {
571 mxc_spi->intctrl = mx31_intctrl;
572 mxc_spi->config = mx31_config;
573 mxc_spi->trigger = mx31_trigger;
574 mxc_spi->rx_available = mx31_rx_available;
575 } else if (cpu_is_mx27() || cpu_is_mx21()) {
576 mxc_spi->intctrl = mx27_intctrl;
577 mxc_spi->config = mx27_config;
578 mxc_spi->trigger = mx27_trigger;
579 mxc_spi->rx_available = mx27_rx_available;
580 } else if (cpu_is_mx1()) {
581 mxc_spi->intctrl = mx1_intctrl;
582 mxc_spi->config = mx1_config;
583 mxc_spi->trigger = mx1_trigger;
584 mxc_spi->rx_available = mx1_rx_available;
585 } else
586 BUG();
587
588 mxc_spi->clk = clk_get(&pdev->dev, NULL);
589 if (IS_ERR(mxc_spi->clk)) {
590 dev_err(&pdev->dev, "unable to get clock\n");
591 ret = PTR_ERR(mxc_spi->clk);
592 goto out_free_irq;
593 }
594
595 clk_enable(mxc_spi->clk);
596 mxc_spi->spi_clk = clk_get_rate(mxc_spi->clk);
597
598 if (!cpu_is_mx31() || !cpu_is_mx35())
599 writel(1, mxc_spi->base + MXC_RESET);
600
601 mxc_spi->intctrl(mxc_spi, 0);
602
603 ret = spi_bitbang_start(&mxc_spi->bitbang);
604 if (ret) {
605 dev_err(&pdev->dev, "bitbang start failed with %d\n", ret);
606 goto out_clk_put;
607 }
608
609 dev_info(&pdev->dev, "probed\n");
610
611 return ret;
612
613out_clk_put:
614 clk_disable(mxc_spi->clk);
615 clk_put(mxc_spi->clk);
616out_free_irq:
617 free_irq(mxc_spi->irq, mxc_spi);
618out_iounmap:
619 iounmap(mxc_spi->base);
620out_release_mem:
621 release_mem_region(res->start, resource_size(res));
622out_gpio_free:
623 for (i = 0; i < master->num_chipselect; i++)
624 if (mxc_spi->chipselect[i] >= 0)
625 gpio_free(mxc_spi->chipselect[i]);
626out_master_put:
627 spi_master_put(master);
628 kfree(master);
629 platform_set_drvdata(pdev, NULL);
630 return ret;
631}
632
633static int __exit mxc_spi_remove(struct platform_device *pdev)
634{
635 struct spi_master *master = platform_get_drvdata(pdev);
636 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
637 struct mxc_spi_data *mxc_spi = spi_master_get_devdata(master);
638 int i;
639
640 spi_bitbang_stop(&mxc_spi->bitbang);
641
642 writel(0, mxc_spi->base + MXC_CSPICTRL);
643 clk_disable(mxc_spi->clk);
644 clk_put(mxc_spi->clk);
645 free_irq(mxc_spi->irq, mxc_spi);
646 iounmap(mxc_spi->base);
647
648 for (i = 0; i < master->num_chipselect; i++)
649 if (mxc_spi->chipselect[i] >= 0)
650 gpio_free(mxc_spi->chipselect[i]);
651
652 spi_master_put(master);
653
654 release_mem_region(res->start, resource_size(res));
655
656 platform_set_drvdata(pdev, NULL);
657
658 return 0;
659}
660
661static struct platform_driver mxc_spi_driver = {
662 .driver = {
663 .name = DRIVER_NAME,
664 .owner = THIS_MODULE,
665 },
666 .probe = mxc_spi_probe,
667 .remove = __exit_p(mxc_spi_remove),
668};
669
670static int __init mxc_spi_init(void)
671{
672 return platform_driver_register(&mxc_spi_driver);
673}
674
675static void __exit mxc_spi_exit(void)
676{
677 platform_driver_unregister(&mxc_spi_driver);
678}
679
680module_init(mxc_spi_init);
681module_exit(mxc_spi_exit);
682
683MODULE_DESCRIPTION("SPI Master Controller driver");
684MODULE_AUTHOR("Sascha Hauer, Pengutronix");
685MODULE_LICENSE("GPL");
diff --git a/drivers/spi/omap2_mcspi.c b/drivers/spi/omap2_mcspi.c
index 9b80ad36dbba..ba1a872b221e 100644
--- a/drivers/spi/omap2_mcspi.c
+++ b/drivers/spi/omap2_mcspi.c
@@ -41,6 +41,9 @@
41 41
42#define OMAP2_MCSPI_MAX_FREQ 48000000 42#define OMAP2_MCSPI_MAX_FREQ 48000000
43 43
44/* OMAP2 has 3 SPI controllers, while OMAP3 has 4 */
45#define OMAP2_MCSPI_MAX_CTRL 4
46
44#define OMAP2_MCSPI_REVISION 0x00 47#define OMAP2_MCSPI_REVISION 0x00
45#define OMAP2_MCSPI_SYSCONFIG 0x10 48#define OMAP2_MCSPI_SYSCONFIG 0x10
46#define OMAP2_MCSPI_SYSSTATUS 0x14 49#define OMAP2_MCSPI_SYSSTATUS 0x14
@@ -59,40 +62,40 @@
59 62
60/* per-register bitmasks: */ 63/* per-register bitmasks: */
61 64
62#define OMAP2_MCSPI_SYSCONFIG_SMARTIDLE (2 << 3) 65#define OMAP2_MCSPI_SYSCONFIG_SMARTIDLE BIT(4)
63#define OMAP2_MCSPI_SYSCONFIG_ENAWAKEUP (1 << 2) 66#define OMAP2_MCSPI_SYSCONFIG_ENAWAKEUP BIT(2)
64#define OMAP2_MCSPI_SYSCONFIG_AUTOIDLE (1 << 0) 67#define OMAP2_MCSPI_SYSCONFIG_AUTOIDLE BIT(0)
65#define OMAP2_MCSPI_SYSCONFIG_SOFTRESET (1 << 1) 68#define OMAP2_MCSPI_SYSCONFIG_SOFTRESET BIT(1)
66 69
67#define OMAP2_MCSPI_SYSSTATUS_RESETDONE (1 << 0) 70#define OMAP2_MCSPI_SYSSTATUS_RESETDONE BIT(0)
68 71
69#define OMAP2_MCSPI_MODULCTRL_SINGLE (1 << 0) 72#define OMAP2_MCSPI_MODULCTRL_SINGLE BIT(0)
70#define OMAP2_MCSPI_MODULCTRL_MS (1 << 2) 73#define OMAP2_MCSPI_MODULCTRL_MS BIT(2)
71#define OMAP2_MCSPI_MODULCTRL_STEST (1 << 3) 74#define OMAP2_MCSPI_MODULCTRL_STEST BIT(3)
72 75
73#define OMAP2_MCSPI_CHCONF_PHA (1 << 0) 76#define OMAP2_MCSPI_CHCONF_PHA BIT(0)
74#define OMAP2_MCSPI_CHCONF_POL (1 << 1) 77#define OMAP2_MCSPI_CHCONF_POL BIT(1)
75#define OMAP2_MCSPI_CHCONF_CLKD_MASK (0x0f << 2) 78#define OMAP2_MCSPI_CHCONF_CLKD_MASK (0x0f << 2)
76#define OMAP2_MCSPI_CHCONF_EPOL (1 << 6) 79#define OMAP2_MCSPI_CHCONF_EPOL BIT(6)
77#define OMAP2_MCSPI_CHCONF_WL_MASK (0x1f << 7) 80#define OMAP2_MCSPI_CHCONF_WL_MASK (0x1f << 7)
78#define OMAP2_MCSPI_CHCONF_TRM_RX_ONLY (0x01 << 12) 81#define OMAP2_MCSPI_CHCONF_TRM_RX_ONLY BIT(12)
79#define OMAP2_MCSPI_CHCONF_TRM_TX_ONLY (0x02 << 12) 82#define OMAP2_MCSPI_CHCONF_TRM_TX_ONLY BIT(13)
80#define OMAP2_MCSPI_CHCONF_TRM_MASK (0x03 << 12) 83#define OMAP2_MCSPI_CHCONF_TRM_MASK (0x03 << 12)
81#define OMAP2_MCSPI_CHCONF_DMAW (1 << 14) 84#define OMAP2_MCSPI_CHCONF_DMAW BIT(14)
82#define OMAP2_MCSPI_CHCONF_DMAR (1 << 15) 85#define OMAP2_MCSPI_CHCONF_DMAR BIT(15)
83#define OMAP2_MCSPI_CHCONF_DPE0 (1 << 16) 86#define OMAP2_MCSPI_CHCONF_DPE0 BIT(16)
84#define OMAP2_MCSPI_CHCONF_DPE1 (1 << 17) 87#define OMAP2_MCSPI_CHCONF_DPE1 BIT(17)
85#define OMAP2_MCSPI_CHCONF_IS (1 << 18) 88#define OMAP2_MCSPI_CHCONF_IS BIT(18)
86#define OMAP2_MCSPI_CHCONF_TURBO (1 << 19) 89#define OMAP2_MCSPI_CHCONF_TURBO BIT(19)
87#define OMAP2_MCSPI_CHCONF_FORCE (1 << 20) 90#define OMAP2_MCSPI_CHCONF_FORCE BIT(20)
88 91
89#define OMAP2_MCSPI_CHSTAT_RXS (1 << 0) 92#define OMAP2_MCSPI_CHSTAT_RXS BIT(0)
90#define OMAP2_MCSPI_CHSTAT_TXS (1 << 1) 93#define OMAP2_MCSPI_CHSTAT_TXS BIT(1)
91#define OMAP2_MCSPI_CHSTAT_EOT (1 << 2) 94#define OMAP2_MCSPI_CHSTAT_EOT BIT(2)
92 95
93#define OMAP2_MCSPI_CHCTRL_EN (1 << 0) 96#define OMAP2_MCSPI_CHCTRL_EN BIT(0)
94 97
95#define OMAP2_MCSPI_WAKEUPENABLE_WKEN (1 << 0) 98#define OMAP2_MCSPI_WAKEUPENABLE_WKEN BIT(0)
96 99
97/* We have 2 DMA channels per CS, one for RX and one for TX */ 100/* We have 2 DMA channels per CS, one for RX and one for TX */
98struct omap2_mcspi_dma { 101struct omap2_mcspi_dma {
@@ -131,8 +134,23 @@ struct omap2_mcspi_cs {
131 void __iomem *base; 134 void __iomem *base;
132 unsigned long phys; 135 unsigned long phys;
133 int word_len; 136 int word_len;
137 struct list_head node;
138 /* Context save and restore shadow register */
139 u32 chconf0;
140};
141
142/* used for context save and restore, structure members to be updated whenever
143 * corresponding registers are modified.
144 */
145struct omap2_mcspi_regs {
146 u32 sysconfig;
147 u32 modulctrl;
148 u32 wakeupenable;
149 struct list_head cs;
134}; 150};
135 151
152static struct omap2_mcspi_regs omap2_mcspi_ctx[OMAP2_MCSPI_MAX_CTRL];
153
136static struct workqueue_struct *omap2_mcspi_wq; 154static struct workqueue_struct *omap2_mcspi_wq;
137 155
138#define MOD_REG_BIT(val, mask, set) do { \ 156#define MOD_REG_BIT(val, mask, set) do { \
@@ -172,12 +190,27 @@ static inline u32 mcspi_read_cs_reg(const struct spi_device *spi, int idx)
172 return __raw_readl(cs->base + idx); 190 return __raw_readl(cs->base + idx);
173} 191}
174 192
193static inline u32 mcspi_cached_chconf0(const struct spi_device *spi)
194{
195 struct omap2_mcspi_cs *cs = spi->controller_state;
196
197 return cs->chconf0;
198}
199
200static inline void mcspi_write_chconf0(const struct spi_device *spi, u32 val)
201{
202 struct omap2_mcspi_cs *cs = spi->controller_state;
203
204 cs->chconf0 = val;
205 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, val);
206}
207
175static void omap2_mcspi_set_dma_req(const struct spi_device *spi, 208static void omap2_mcspi_set_dma_req(const struct spi_device *spi,
176 int is_read, int enable) 209 int is_read, int enable)
177{ 210{
178 u32 l, rw; 211 u32 l, rw;
179 212
180 l = mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0); 213 l = mcspi_cached_chconf0(spi);
181 214
182 if (is_read) /* 1 is read, 0 write */ 215 if (is_read) /* 1 is read, 0 write */
183 rw = OMAP2_MCSPI_CHCONF_DMAR; 216 rw = OMAP2_MCSPI_CHCONF_DMAR;
@@ -185,7 +218,7 @@ static void omap2_mcspi_set_dma_req(const struct spi_device *spi,
185 rw = OMAP2_MCSPI_CHCONF_DMAW; 218 rw = OMAP2_MCSPI_CHCONF_DMAW;
186 219
187 MOD_REG_BIT(l, rw, enable); 220 MOD_REG_BIT(l, rw, enable);
188 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, l); 221 mcspi_write_chconf0(spi, l);
189} 222}
190 223
191static void omap2_mcspi_set_enable(const struct spi_device *spi, int enable) 224static void omap2_mcspi_set_enable(const struct spi_device *spi, int enable)
@@ -200,9 +233,9 @@ static void omap2_mcspi_force_cs(struct spi_device *spi, int cs_active)
200{ 233{
201 u32 l; 234 u32 l;
202 235
203 l = mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0); 236 l = mcspi_cached_chconf0(spi);
204 MOD_REG_BIT(l, OMAP2_MCSPI_CHCONF_FORCE, cs_active); 237 MOD_REG_BIT(l, OMAP2_MCSPI_CHCONF_FORCE, cs_active);
205 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, l); 238 mcspi_write_chconf0(spi, l);
206} 239}
207 240
208static void omap2_mcspi_set_master_mode(struct spi_master *master) 241static void omap2_mcspi_set_master_mode(struct spi_master *master)
@@ -217,6 +250,46 @@ static void omap2_mcspi_set_master_mode(struct spi_master *master)
217 MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_MS, 0); 250 MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_MS, 0);
218 MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_SINGLE, 1); 251 MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_SINGLE, 1);
219 mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, l); 252 mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, l);
253
254 omap2_mcspi_ctx[master->bus_num - 1].modulctrl = l;
255}
256
257static void omap2_mcspi_restore_ctx(struct omap2_mcspi *mcspi)
258{
259 struct spi_master *spi_cntrl;
260 struct omap2_mcspi_cs *cs;
261 spi_cntrl = mcspi->master;
262
263 /* McSPI: context restore */
264 mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_MODULCTRL,
265 omap2_mcspi_ctx[spi_cntrl->bus_num - 1].modulctrl);
266
267 mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_SYSCONFIG,
268 omap2_mcspi_ctx[spi_cntrl->bus_num - 1].sysconfig);
269
270 mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_WAKEUPENABLE,
271 omap2_mcspi_ctx[spi_cntrl->bus_num - 1].wakeupenable);
272
273 list_for_each_entry(cs, &omap2_mcspi_ctx[spi_cntrl->bus_num - 1].cs,
274 node)
275 __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
276}
277static void omap2_mcspi_disable_clocks(struct omap2_mcspi *mcspi)
278{
279 clk_disable(mcspi->ick);
280 clk_disable(mcspi->fck);
281}
282
283static int omap2_mcspi_enable_clocks(struct omap2_mcspi *mcspi)
284{
285 if (clk_enable(mcspi->ick))
286 return -ENODEV;
287 if (clk_enable(mcspi->fck))
288 return -ENODEV;
289
290 omap2_mcspi_restore_ctx(mcspi);
291
292 return 0;
220} 293}
221 294
222static unsigned 295static unsigned
@@ -357,7 +430,7 @@ omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
357 c = count; 430 c = count;
358 word_len = cs->word_len; 431 word_len = cs->word_len;
359 432
360 l = mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0); 433 l = mcspi_cached_chconf0(spi);
361 l &= ~OMAP2_MCSPI_CHCONF_TRM_MASK; 434 l &= ~OMAP2_MCSPI_CHCONF_TRM_MASK;
362 435
363 /* We store the pre-calculated register addresses on stack to speed 436 /* We store the pre-calculated register addresses on stack to speed
@@ -397,8 +470,7 @@ omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
397 * more word i/o: switch to rx+tx 470 * more word i/o: switch to rx+tx
398 */ 471 */
399 if (c == 0 && tx == NULL) 472 if (c == 0 && tx == NULL)
400 mcspi_write_cs_reg(spi, 473 mcspi_write_chconf0(spi, l);
401 OMAP2_MCSPI_CHCONF0, l);
402 *rx++ = __raw_readl(rx_reg); 474 *rx++ = __raw_readl(rx_reg);
403#ifdef VERBOSE 475#ifdef VERBOSE
404 dev_dbg(&spi->dev, "read-%d %02x\n", 476 dev_dbg(&spi->dev, "read-%d %02x\n",
@@ -436,8 +508,7 @@ omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
436 * more word i/o: switch to rx+tx 508 * more word i/o: switch to rx+tx
437 */ 509 */
438 if (c == 0 && tx == NULL) 510 if (c == 0 && tx == NULL)
439 mcspi_write_cs_reg(spi, 511 mcspi_write_chconf0(spi, l);
440 OMAP2_MCSPI_CHCONF0, l);
441 *rx++ = __raw_readl(rx_reg); 512 *rx++ = __raw_readl(rx_reg);
442#ifdef VERBOSE 513#ifdef VERBOSE
443 dev_dbg(&spi->dev, "read-%d %04x\n", 514 dev_dbg(&spi->dev, "read-%d %04x\n",
@@ -475,8 +546,7 @@ omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
475 * more word i/o: switch to rx+tx 546 * more word i/o: switch to rx+tx
476 */ 547 */
477 if (c == 0 && tx == NULL) 548 if (c == 0 && tx == NULL)
478 mcspi_write_cs_reg(spi, 549 mcspi_write_chconf0(spi, l);
479 OMAP2_MCSPI_CHCONF0, l);
480 *rx++ = __raw_readl(rx_reg); 550 *rx++ = __raw_readl(rx_reg);
481#ifdef VERBOSE 551#ifdef VERBOSE
482 dev_dbg(&spi->dev, "read-%d %04x\n", 552 dev_dbg(&spi->dev, "read-%d %04x\n",
@@ -505,10 +575,12 @@ static int omap2_mcspi_setup_transfer(struct spi_device *spi,
505{ 575{
506 struct omap2_mcspi_cs *cs = spi->controller_state; 576 struct omap2_mcspi_cs *cs = spi->controller_state;
507 struct omap2_mcspi *mcspi; 577 struct omap2_mcspi *mcspi;
578 struct spi_master *spi_cntrl;
508 u32 l = 0, div = 0; 579 u32 l = 0, div = 0;
509 u8 word_len = spi->bits_per_word; 580 u8 word_len = spi->bits_per_word;
510 581
511 mcspi = spi_master_get_devdata(spi->master); 582 mcspi = spi_master_get_devdata(spi->master);
583 spi_cntrl = mcspi->master;
512 584
513 if (t != NULL && t->bits_per_word) 585 if (t != NULL && t->bits_per_word)
514 word_len = t->bits_per_word; 586 word_len = t->bits_per_word;
@@ -522,7 +594,7 @@ static int omap2_mcspi_setup_transfer(struct spi_device *spi,
522 } else 594 } else
523 div = 15; 595 div = 15;
524 596
525 l = mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0); 597 l = mcspi_cached_chconf0(spi);
526 598
527 /* standard 4-wire master mode: SCK, MOSI/out, MISO/in, nCS 599 /* standard 4-wire master mode: SCK, MOSI/out, MISO/in, nCS
528 * REVISIT: this controller could support SPI_3WIRE mode. 600 * REVISIT: this controller could support SPI_3WIRE mode.
@@ -554,7 +626,7 @@ static int omap2_mcspi_setup_transfer(struct spi_device *spi,
554 else 626 else
555 l &= ~OMAP2_MCSPI_CHCONF_PHA; 627 l &= ~OMAP2_MCSPI_CHCONF_PHA;
556 628
557 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, l); 629 mcspi_write_chconf0(spi, l);
558 630
559 dev_dbg(&spi->dev, "setup: speed %d, sample %s edge, clk %s\n", 631 dev_dbg(&spi->dev, "setup: speed %d, sample %s edge, clk %s\n",
560 OMAP2_MCSPI_MAX_FREQ / (1 << div), 632 OMAP2_MCSPI_MAX_FREQ / (1 << div),
@@ -647,7 +719,11 @@ static int omap2_mcspi_setup(struct spi_device *spi)
647 return -ENOMEM; 719 return -ENOMEM;
648 cs->base = mcspi->base + spi->chip_select * 0x14; 720 cs->base = mcspi->base + spi->chip_select * 0x14;
649 cs->phys = mcspi->phys + spi->chip_select * 0x14; 721 cs->phys = mcspi->phys + spi->chip_select * 0x14;
722 cs->chconf0 = 0;
650 spi->controller_state = cs; 723 spi->controller_state = cs;
724 /* Link this to context save list */
725 list_add_tail(&cs->node,
726 &omap2_mcspi_ctx[mcspi->master->bus_num - 1].cs);
651 } 727 }
652 728
653 if (mcspi_dma->dma_rx_channel == -1 729 if (mcspi_dma->dma_rx_channel == -1
@@ -657,11 +733,11 @@ static int omap2_mcspi_setup(struct spi_device *spi)
657 return ret; 733 return ret;
658 } 734 }
659 735
660 clk_enable(mcspi->ick); 736 if (omap2_mcspi_enable_clocks(mcspi))
661 clk_enable(mcspi->fck); 737 return -ENODEV;
738
662 ret = omap2_mcspi_setup_transfer(spi, NULL); 739 ret = omap2_mcspi_setup_transfer(spi, NULL);
663 clk_disable(mcspi->fck); 740 omap2_mcspi_disable_clocks(mcspi);
664 clk_disable(mcspi->ick);
665 741
666 return ret; 742 return ret;
667} 743}
@@ -670,10 +746,15 @@ static void omap2_mcspi_cleanup(struct spi_device *spi)
670{ 746{
671 struct omap2_mcspi *mcspi; 747 struct omap2_mcspi *mcspi;
672 struct omap2_mcspi_dma *mcspi_dma; 748 struct omap2_mcspi_dma *mcspi_dma;
749 struct omap2_mcspi_cs *cs;
673 750
674 mcspi = spi_master_get_devdata(spi->master); 751 mcspi = spi_master_get_devdata(spi->master);
675 mcspi_dma = &mcspi->dma_channels[spi->chip_select]; 752 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
676 753
754 /* Unlink controller state from context save list */
755 cs = spi->controller_state;
756 list_del(&cs->node);
757
677 kfree(spi->controller_state); 758 kfree(spi->controller_state);
678 759
679 if (mcspi_dma->dma_rx_channel != -1) { 760 if (mcspi_dma->dma_rx_channel != -1) {
@@ -693,8 +774,8 @@ static void omap2_mcspi_work(struct work_struct *work)
693 mcspi = container_of(work, struct omap2_mcspi, work); 774 mcspi = container_of(work, struct omap2_mcspi, work);
694 spin_lock_irq(&mcspi->lock); 775 spin_lock_irq(&mcspi->lock);
695 776
696 clk_enable(mcspi->ick); 777 if (omap2_mcspi_enable_clocks(mcspi))
697 clk_enable(mcspi->fck); 778 goto out;
698 779
699 /* We only enable one channel at a time -- the one whose message is 780 /* We only enable one channel at a time -- the one whose message is
700 * at the head of the queue -- although this controller would gladly 781 * at the head of the queue -- although this controller would gladly
@@ -741,13 +822,13 @@ static void omap2_mcspi_work(struct work_struct *work)
741 cs_active = 1; 822 cs_active = 1;
742 } 823 }
743 824
744 chconf = mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0); 825 chconf = mcspi_cached_chconf0(spi);
745 chconf &= ~OMAP2_MCSPI_CHCONF_TRM_MASK; 826 chconf &= ~OMAP2_MCSPI_CHCONF_TRM_MASK;
746 if (t->tx_buf == NULL) 827 if (t->tx_buf == NULL)
747 chconf |= OMAP2_MCSPI_CHCONF_TRM_RX_ONLY; 828 chconf |= OMAP2_MCSPI_CHCONF_TRM_RX_ONLY;
748 else if (t->rx_buf == NULL) 829 else if (t->rx_buf == NULL)
749 chconf |= OMAP2_MCSPI_CHCONF_TRM_TX_ONLY; 830 chconf |= OMAP2_MCSPI_CHCONF_TRM_TX_ONLY;
750 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, chconf); 831 mcspi_write_chconf0(spi, chconf);
751 832
752 if (t->len) { 833 if (t->len) {
753 unsigned count; 834 unsigned count;
@@ -796,9 +877,9 @@ static void omap2_mcspi_work(struct work_struct *work)
796 spin_lock_irq(&mcspi->lock); 877 spin_lock_irq(&mcspi->lock);
797 } 878 }
798 879
799 clk_disable(mcspi->fck); 880 omap2_mcspi_disable_clocks(mcspi);
800 clk_disable(mcspi->ick);
801 881
882out:
802 spin_unlock_irq(&mcspi->lock); 883 spin_unlock_irq(&mcspi->lock);
803} 884}
804 885
@@ -885,8 +966,8 @@ static int __init omap2_mcspi_reset(struct omap2_mcspi *mcspi)
885 struct spi_master *master = mcspi->master; 966 struct spi_master *master = mcspi->master;
886 u32 tmp; 967 u32 tmp;
887 968
888 clk_enable(mcspi->ick); 969 if (omap2_mcspi_enable_clocks(mcspi))
889 clk_enable(mcspi->fck); 970 return -1;
890 971
891 mcspi_write_reg(master, OMAP2_MCSPI_SYSCONFIG, 972 mcspi_write_reg(master, OMAP2_MCSPI_SYSCONFIG,
892 OMAP2_MCSPI_SYSCONFIG_SOFTRESET); 973 OMAP2_MCSPI_SYSCONFIG_SOFTRESET);
@@ -894,18 +975,18 @@ static int __init omap2_mcspi_reset(struct omap2_mcspi *mcspi)
894 tmp = mcspi_read_reg(master, OMAP2_MCSPI_SYSSTATUS); 975 tmp = mcspi_read_reg(master, OMAP2_MCSPI_SYSSTATUS);
895 } while (!(tmp & OMAP2_MCSPI_SYSSTATUS_RESETDONE)); 976 } while (!(tmp & OMAP2_MCSPI_SYSSTATUS_RESETDONE));
896 977
897 mcspi_write_reg(master, OMAP2_MCSPI_SYSCONFIG, 978 tmp = OMAP2_MCSPI_SYSCONFIG_AUTOIDLE |
898 OMAP2_MCSPI_SYSCONFIG_AUTOIDLE | 979 OMAP2_MCSPI_SYSCONFIG_ENAWAKEUP |
899 OMAP2_MCSPI_SYSCONFIG_ENAWAKEUP | 980 OMAP2_MCSPI_SYSCONFIG_SMARTIDLE;
900 OMAP2_MCSPI_SYSCONFIG_SMARTIDLE); 981 mcspi_write_reg(master, OMAP2_MCSPI_SYSCONFIG, tmp);
982 omap2_mcspi_ctx[master->bus_num - 1].sysconfig = tmp;
901 983
902 mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE, 984 tmp = OMAP2_MCSPI_WAKEUPENABLE_WKEN;
903 OMAP2_MCSPI_WAKEUPENABLE_WKEN); 985 mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE, tmp);
986 omap2_mcspi_ctx[master->bus_num - 1].wakeupenable = tmp;
904 987
905 omap2_mcspi_set_master_mode(master); 988 omap2_mcspi_set_master_mode(master);
906 989 omap2_mcspi_disable_clocks(mcspi);
907 clk_disable(mcspi->fck);
908 clk_disable(mcspi->ick);
909 return 0; 990 return 0;
910} 991}
911 992
@@ -933,7 +1014,8 @@ static u8 __initdata spi2_txdma_id[] = {
933 OMAP24XX_DMA_SPI2_TX1, 1014 OMAP24XX_DMA_SPI2_TX1,
934}; 1015};
935 1016
936#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP34XX) 1017#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP34XX) \
1018 || defined(CONFIG_ARCH_OMAP4)
937static u8 __initdata spi3_rxdma_id[] = { 1019static u8 __initdata spi3_rxdma_id[] = {
938 OMAP24XX_DMA_SPI3_RX0, 1020 OMAP24XX_DMA_SPI3_RX0,
939 OMAP24XX_DMA_SPI3_RX1, 1021 OMAP24XX_DMA_SPI3_RX1,
@@ -945,7 +1027,7 @@ static u8 __initdata spi3_txdma_id[] = {
945}; 1027};
946#endif 1028#endif
947 1029
948#ifdef CONFIG_ARCH_OMAP3 1030#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
949static u8 __initdata spi4_rxdma_id[] = { 1031static u8 __initdata spi4_rxdma_id[] = {
950 OMAP34XX_DMA_SPI4_RX0, 1032 OMAP34XX_DMA_SPI4_RX0,
951}; 1033};
@@ -975,14 +1057,15 @@ static int __init omap2_mcspi_probe(struct platform_device *pdev)
975 txdma_id = spi2_txdma_id; 1057 txdma_id = spi2_txdma_id;
976 num_chipselect = 2; 1058 num_chipselect = 2;
977 break; 1059 break;
978#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) 1060#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) \
1061 || defined(CONFIG_ARCH_OMAP4)
979 case 3: 1062 case 3:
980 rxdma_id = spi3_rxdma_id; 1063 rxdma_id = spi3_rxdma_id;
981 txdma_id = spi3_txdma_id; 1064 txdma_id = spi3_txdma_id;
982 num_chipselect = 2; 1065 num_chipselect = 2;
983 break; 1066 break;
984#endif 1067#endif
985#ifdef CONFIG_ARCH_OMAP3 1068#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
986 case 4: 1069 case 4:
987 rxdma_id = spi4_rxdma_id; 1070 rxdma_id = spi4_rxdma_id;
988 txdma_id = spi4_txdma_id; 1071 txdma_id = spi4_txdma_id;
@@ -1038,6 +1121,7 @@ static int __init omap2_mcspi_probe(struct platform_device *pdev)
1038 1121
1039 spin_lock_init(&mcspi->lock); 1122 spin_lock_init(&mcspi->lock);
1040 INIT_LIST_HEAD(&mcspi->msg_queue); 1123 INIT_LIST_HEAD(&mcspi->msg_queue);
1124 INIT_LIST_HEAD(&omap2_mcspi_ctx[master->bus_num - 1].cs);
1041 1125
1042 mcspi->ick = clk_get(&pdev->dev, "ick"); 1126 mcspi->ick = clk_get(&pdev->dev, "ick");
1043 if (IS_ERR(mcspi->ick)) { 1127 if (IS_ERR(mcspi->ick)) {
diff --git a/drivers/spi/omap_uwire.c b/drivers/spi/omap_uwire.c
index 8980a5640bd9..e75ba9b28898 100644
--- a/drivers/spi/omap_uwire.c
+++ b/drivers/spi/omap_uwire.c
@@ -213,7 +213,7 @@ static int uwire_txrx(struct spi_device *spi, struct spi_transfer *t)
213 unsigned bits = ust->bits_per_word; 213 unsigned bits = ust->bits_per_word;
214 unsigned bytes; 214 unsigned bytes;
215 u16 val, w; 215 u16 val, w;
216 int status = 0;; 216 int status = 0;
217 217
218 if (!t->tx_buf && !t->rx_buf) 218 if (!t->tx_buf && !t->rx_buf)
219 return 0; 219 return 0;
diff --git a/drivers/spi/pxa2xx_spi.c b/drivers/spi/pxa2xx_spi.c
index 8a1fb608e8f1..c8c2b693ffac 100644
--- a/drivers/spi/pxa2xx_spi.c
+++ b/drivers/spi/pxa2xx_spi.c
@@ -1731,7 +1731,7 @@ static int __init pxa2xx_spi_init(void)
1731{ 1731{
1732 return platform_driver_probe(&driver, pxa2xx_spi_probe); 1732 return platform_driver_probe(&driver, pxa2xx_spi_probe);
1733} 1733}
1734module_init(pxa2xx_spi_init); 1734subsys_initcall(pxa2xx_spi_init);
1735 1735
1736static void __exit pxa2xx_spi_exit(void) 1736static void __exit pxa2xx_spi_exit(void)
1737{ 1737{
diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c
index 70845ccd85c3..b76f2468a84a 100644
--- a/drivers/spi/spi.c
+++ b/drivers/spi/spi.c
@@ -23,6 +23,7 @@
23#include <linux/init.h> 23#include <linux/init.h>
24#include <linux/cache.h> 24#include <linux/cache.h>
25#include <linux/mutex.h> 25#include <linux/mutex.h>
26#include <linux/mod_devicetable.h>
26#include <linux/spi/spi.h> 27#include <linux/spi/spi.h>
27 28
28 29
@@ -59,9 +60,32 @@ static struct device_attribute spi_dev_attrs[] = {
59 * and the sysfs version makes coldplug work too. 60 * and the sysfs version makes coldplug work too.
60 */ 61 */
61 62
63static const struct spi_device_id *spi_match_id(const struct spi_device_id *id,
64 const struct spi_device *sdev)
65{
66 while (id->name[0]) {
67 if (!strcmp(sdev->modalias, id->name))
68 return id;
69 id++;
70 }
71 return NULL;
72}
73
74const struct spi_device_id *spi_get_device_id(const struct spi_device *sdev)
75{
76 const struct spi_driver *sdrv = to_spi_driver(sdev->dev.driver);
77
78 return spi_match_id(sdrv->id_table, sdev);
79}
80EXPORT_SYMBOL_GPL(spi_get_device_id);
81
62static int spi_match_device(struct device *dev, struct device_driver *drv) 82static int spi_match_device(struct device *dev, struct device_driver *drv)
63{ 83{
64 const struct spi_device *spi = to_spi_device(dev); 84 const struct spi_device *spi = to_spi_device(dev);
85 const struct spi_driver *sdrv = to_spi_driver(drv);
86
87 if (sdrv->id_table)
88 return !!spi_match_id(sdrv->id_table, spi);
65 89
66 return strcmp(spi->modalias, drv->name) == 0; 90 return strcmp(spi->modalias, drv->name) == 0;
67} 91}
@@ -70,7 +94,7 @@ static int spi_uevent(struct device *dev, struct kobj_uevent_env *env)
70{ 94{
71 const struct spi_device *spi = to_spi_device(dev); 95 const struct spi_device *spi = to_spi_device(dev);
72 96
73 add_uevent_var(env, "MODALIAS=%s", spi->modalias); 97 add_uevent_var(env, "MODALIAS=%s%s", SPI_MODULE_PREFIX, spi->modalias);
74 return 0; 98 return 0;
75} 99}
76 100
@@ -639,6 +663,65 @@ int spi_setup(struct spi_device *spi)
639} 663}
640EXPORT_SYMBOL_GPL(spi_setup); 664EXPORT_SYMBOL_GPL(spi_setup);
641 665
666/**
667 * spi_async - asynchronous SPI transfer
668 * @spi: device with which data will be exchanged
669 * @message: describes the data transfers, including completion callback
670 * Context: any (irqs may be blocked, etc)
671 *
672 * This call may be used in_irq and other contexts which can't sleep,
673 * as well as from task contexts which can sleep.
674 *
675 * The completion callback is invoked in a context which can't sleep.
676 * Before that invocation, the value of message->status is undefined.
677 * When the callback is issued, message->status holds either zero (to
678 * indicate complete success) or a negative error code. After that
679 * callback returns, the driver which issued the transfer request may
680 * deallocate the associated memory; it's no longer in use by any SPI
681 * core or controller driver code.
682 *
683 * Note that although all messages to a spi_device are handled in
684 * FIFO order, messages may go to different devices in other orders.
685 * Some device might be higher priority, or have various "hard" access
686 * time requirements, for example.
687 *
688 * On detection of any fault during the transfer, processing of
689 * the entire message is aborted, and the device is deselected.
690 * Until returning from the associated message completion callback,
691 * no other spi_message queued to that device will be processed.
692 * (This rule applies equally to all the synchronous transfer calls,
693 * which are wrappers around this core asynchronous primitive.)
694 */
695int spi_async(struct spi_device *spi, struct spi_message *message)
696{
697 struct spi_master *master = spi->master;
698
699 /* Half-duplex links include original MicroWire, and ones with
700 * only one data pin like SPI_3WIRE (switches direction) or where
701 * either MOSI or MISO is missing. They can also be caused by
702 * software limitations.
703 */
704 if ((master->flags & SPI_MASTER_HALF_DUPLEX)
705 || (spi->mode & SPI_3WIRE)) {
706 struct spi_transfer *xfer;
707 unsigned flags = master->flags;
708
709 list_for_each_entry(xfer, &message->transfers, transfer_list) {
710 if (xfer->rx_buf && xfer->tx_buf)
711 return -EINVAL;
712 if ((flags & SPI_MASTER_NO_TX) && xfer->tx_buf)
713 return -EINVAL;
714 if ((flags & SPI_MASTER_NO_RX) && xfer->rx_buf)
715 return -EINVAL;
716 }
717 }
718
719 message->spi = spi;
720 message->status = -EINPROGRESS;
721 return master->transfer(spi, message);
722}
723EXPORT_SYMBOL_GPL(spi_async);
724
642 725
643/*-------------------------------------------------------------------------*/ 726/*-------------------------------------------------------------------------*/
644 727
diff --git a/drivers/spi/spi_imx.c b/drivers/spi/spi_imx.c
deleted file mode 100644
index c195e45f7f35..000000000000
--- a/drivers/spi/spi_imx.c
+++ /dev/null
@@ -1,1770 +0,0 @@
1/*
2 * drivers/spi/spi_imx.c
3 *
4 * Copyright (C) 2006 SWAPP
5 * Andrea Paterniani <a.paterniani@swapp-eng.it>
6 *
7 * Initial version inspired by:
8 * linux-2.6.17-rc3-mm1/drivers/spi/pxa2xx_spi.c
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 */
20
21#include <linux/init.h>
22#include <linux/module.h>
23#include <linux/device.h>
24#include <linux/ioport.h>
25#include <linux/errno.h>
26#include <linux/interrupt.h>
27#include <linux/platform_device.h>
28#include <linux/dma-mapping.h>
29#include <linux/spi/spi.h>
30#include <linux/workqueue.h>
31#include <linux/delay.h>
32#include <linux/clk.h>
33
34#include <asm/io.h>
35#include <asm/irq.h>
36#include <asm/delay.h>
37
38#include <mach/hardware.h>
39#include <mach/imx-dma.h>
40#include <mach/spi_imx.h>
41
42/*-------------------------------------------------------------------------*/
43/* SPI Registers offsets from peripheral base address */
44#define SPI_RXDATA (0x00)
45#define SPI_TXDATA (0x04)
46#define SPI_CONTROL (0x08)
47#define SPI_INT_STATUS (0x0C)
48#define SPI_TEST (0x10)
49#define SPI_PERIOD (0x14)
50#define SPI_DMA (0x18)
51#define SPI_RESET (0x1C)
52
53/* SPI Control Register Bit Fields & Masks */
54#define SPI_CONTROL_BITCOUNT_MASK (0xF) /* Bit Count Mask */
55#define SPI_CONTROL_BITCOUNT(n) (((n) - 1) & SPI_CONTROL_BITCOUNT_MASK)
56#define SPI_CONTROL_POL (0x1 << 4) /* Clock Polarity Mask */
57#define SPI_CONTROL_POL_ACT_HIGH (0x0 << 4) /* Active high pol. (0=idle) */
58#define SPI_CONTROL_POL_ACT_LOW (0x1 << 4) /* Active low pol. (1=idle) */
59#define SPI_CONTROL_PHA (0x1 << 5) /* Clock Phase Mask */
60#define SPI_CONTROL_PHA_0 (0x0 << 5) /* Clock Phase 0 */
61#define SPI_CONTROL_PHA_1 (0x1 << 5) /* Clock Phase 1 */
62#define SPI_CONTROL_SSCTL (0x1 << 6) /* /SS Waveform Select Mask */
63#define SPI_CONTROL_SSCTL_0 (0x0 << 6) /* Master: /SS stays low between SPI burst
64 Slave: RXFIFO advanced by BIT_COUNT */
65#define SPI_CONTROL_SSCTL_1 (0x1 << 6) /* Master: /SS insert pulse between SPI burst
66 Slave: RXFIFO advanced by /SS rising edge */
67#define SPI_CONTROL_SSPOL (0x1 << 7) /* /SS Polarity Select Mask */
68#define SPI_CONTROL_SSPOL_ACT_LOW (0x0 << 7) /* /SS Active low */
69#define SPI_CONTROL_SSPOL_ACT_HIGH (0x1 << 7) /* /SS Active high */
70#define SPI_CONTROL_XCH (0x1 << 8) /* Exchange */
71#define SPI_CONTROL_SPIEN (0x1 << 9) /* SPI Module Enable */
72#define SPI_CONTROL_MODE (0x1 << 10) /* SPI Mode Select Mask */
73#define SPI_CONTROL_MODE_SLAVE (0x0 << 10) /* SPI Mode Slave */
74#define SPI_CONTROL_MODE_MASTER (0x1 << 10) /* SPI Mode Master */
75#define SPI_CONTROL_DRCTL (0x3 << 11) /* /SPI_RDY Control Mask */
76#define SPI_CONTROL_DRCTL_0 (0x0 << 11) /* Ignore /SPI_RDY */
77#define SPI_CONTROL_DRCTL_1 (0x1 << 11) /* /SPI_RDY falling edge triggers input */
78#define SPI_CONTROL_DRCTL_2 (0x2 << 11) /* /SPI_RDY active low level triggers input */
79#define SPI_CONTROL_DATARATE (0x7 << 13) /* Data Rate Mask */
80#define SPI_PERCLK2_DIV_MIN (0) /* PERCLK2:4 */
81#define SPI_PERCLK2_DIV_MAX (7) /* PERCLK2:512 */
82#define SPI_CONTROL_DATARATE_MIN (SPI_PERCLK2_DIV_MAX << 13)
83#define SPI_CONTROL_DATARATE_MAX (SPI_PERCLK2_DIV_MIN << 13)
84#define SPI_CONTROL_DATARATE_BAD (SPI_CONTROL_DATARATE_MIN + 1)
85
86/* SPI Interrupt/Status Register Bit Fields & Masks */
87#define SPI_STATUS_TE (0x1 << 0) /* TXFIFO Empty Status */
88#define SPI_STATUS_TH (0x1 << 1) /* TXFIFO Half Status */
89#define SPI_STATUS_TF (0x1 << 2) /* TXFIFO Full Status */
90#define SPI_STATUS_RR (0x1 << 3) /* RXFIFO Data Ready Status */
91#define SPI_STATUS_RH (0x1 << 4) /* RXFIFO Half Status */
92#define SPI_STATUS_RF (0x1 << 5) /* RXFIFO Full Status */
93#define SPI_STATUS_RO (0x1 << 6) /* RXFIFO Overflow */
94#define SPI_STATUS_BO (0x1 << 7) /* Bit Count Overflow */
95#define SPI_STATUS (0xFF) /* SPI Status Mask */
96#define SPI_INTEN_TE (0x1 << 8) /* TXFIFO Empty Interrupt Enable */
97#define SPI_INTEN_TH (0x1 << 9) /* TXFIFO Half Interrupt Enable */
98#define SPI_INTEN_TF (0x1 << 10) /* TXFIFO Full Interrupt Enable */
99#define SPI_INTEN_RE (0x1 << 11) /* RXFIFO Data Ready Interrupt Enable */
100#define SPI_INTEN_RH (0x1 << 12) /* RXFIFO Half Interrupt Enable */
101#define SPI_INTEN_RF (0x1 << 13) /* RXFIFO Full Interrupt Enable */
102#define SPI_INTEN_RO (0x1 << 14) /* RXFIFO Overflow Interrupt Enable */
103#define SPI_INTEN_BO (0x1 << 15) /* Bit Count Overflow Interrupt Enable */
104#define SPI_INTEN (0xFF << 8) /* SPI Interrupt Enable Mask */
105
106/* SPI Test Register Bit Fields & Masks */
107#define SPI_TEST_TXCNT (0xF << 0) /* TXFIFO Counter */
108#define SPI_TEST_RXCNT_LSB (4) /* RXFIFO Counter LSB */
109#define SPI_TEST_RXCNT (0xF << 4) /* RXFIFO Counter */
110#define SPI_TEST_SSTATUS (0xF << 8) /* State Machine Status */
111#define SPI_TEST_LBC (0x1 << 14) /* Loop Back Control */
112
113/* SPI Period Register Bit Fields & Masks */
114#define SPI_PERIOD_WAIT (0x7FFF << 0) /* Wait Between Transactions */
115#define SPI_PERIOD_MAX_WAIT (0x7FFF) /* Max Wait Between
116 Transactions */
117#define SPI_PERIOD_CSRC (0x1 << 15) /* Period Clock Source Mask */
118#define SPI_PERIOD_CSRC_BCLK (0x0 << 15) /* Period Clock Source is
119 Bit Clock */
120#define SPI_PERIOD_CSRC_32768 (0x1 << 15) /* Period Clock Source is
121 32.768 KHz Clock */
122
123/* SPI DMA Register Bit Fields & Masks */
124#define SPI_DMA_RHDMA (0x1 << 4) /* RXFIFO Half Status */
125#define SPI_DMA_RFDMA (0x1 << 5) /* RXFIFO Full Status */
126#define SPI_DMA_TEDMA (0x1 << 6) /* TXFIFO Empty Status */
127#define SPI_DMA_THDMA (0x1 << 7) /* TXFIFO Half Status */
128#define SPI_DMA_RHDEN (0x1 << 12) /* RXFIFO Half DMA Request Enable */
129#define SPI_DMA_RFDEN (0x1 << 13) /* RXFIFO Full DMA Request Enable */
130#define SPI_DMA_TEDEN (0x1 << 14) /* TXFIFO Empty DMA Request Enable */
131#define SPI_DMA_THDEN (0x1 << 15) /* TXFIFO Half DMA Request Enable */
132
133/* SPI Soft Reset Register Bit Fields & Masks */
134#define SPI_RESET_START (0x1) /* Start */
135
136/* Default SPI configuration values */
137#define SPI_DEFAULT_CONTROL \
138( \
139 SPI_CONTROL_BITCOUNT(16) | \
140 SPI_CONTROL_POL_ACT_HIGH | \
141 SPI_CONTROL_PHA_0 | \
142 SPI_CONTROL_SPIEN | \
143 SPI_CONTROL_SSCTL_1 | \
144 SPI_CONTROL_MODE_MASTER | \
145 SPI_CONTROL_DRCTL_0 | \
146 SPI_CONTROL_DATARATE_MIN \
147)
148#define SPI_DEFAULT_ENABLE_LOOPBACK (0)
149#define SPI_DEFAULT_ENABLE_DMA (0)
150#define SPI_DEFAULT_PERIOD_WAIT (8)
151/*-------------------------------------------------------------------------*/
152
153
154/*-------------------------------------------------------------------------*/
155/* TX/RX SPI FIFO size */
156#define SPI_FIFO_DEPTH (8)
157#define SPI_FIFO_BYTE_WIDTH (2)
158#define SPI_FIFO_OVERFLOW_MARGIN (2)
159
160/* DMA burst length for half full/empty request trigger */
161#define SPI_DMA_BLR (SPI_FIFO_DEPTH * SPI_FIFO_BYTE_WIDTH / 2)
162
163/* Dummy char output to achieve reads.
164 Choosing something different from all zeroes may help pattern recogition
165 for oscilloscope analysis, but may break some drivers. */
166#define SPI_DUMMY_u8 0
167#define SPI_DUMMY_u16 ((SPI_DUMMY_u8 << 8) | SPI_DUMMY_u8)
168#define SPI_DUMMY_u32 ((SPI_DUMMY_u16 << 16) | SPI_DUMMY_u16)
169
170/**
171 * Macro to change a u32 field:
172 * @r : register to edit
173 * @m : bit mask
174 * @v : new value for the field correctly bit-alligned
175*/
176#define u32_EDIT(r, m, v) r = (r & ~(m)) | (v)
177
178/* Message state */
179#define START_STATE ((void*)0)
180#define RUNNING_STATE ((void*)1)
181#define DONE_STATE ((void*)2)
182#define ERROR_STATE ((void*)-1)
183
184/* Queue state */
185#define QUEUE_RUNNING (0)
186#define QUEUE_STOPPED (1)
187
188#define IS_DMA_ALIGNED(x) (((u32)(x) & 0x03) == 0)
189#define DMA_ALIGNMENT 4
190/*-------------------------------------------------------------------------*/
191
192
193/*-------------------------------------------------------------------------*/
194/* Driver data structs */
195
196/* Context */
197struct driver_data {
198 /* Driver model hookup */
199 struct platform_device *pdev;
200
201 /* SPI framework hookup */
202 struct spi_master *master;
203
204 /* IMX hookup */
205 struct spi_imx_master *master_info;
206
207 /* Memory resources and SPI regs virtual address */
208 struct resource *ioarea;
209 void __iomem *regs;
210
211 /* SPI RX_DATA physical address */
212 dma_addr_t rd_data_phys;
213
214 /* Driver message queue */
215 struct workqueue_struct *workqueue;
216 struct work_struct work;
217 spinlock_t lock;
218 struct list_head queue;
219 int busy;
220 int run;
221
222 /* Message Transfer pump */
223 struct tasklet_struct pump_transfers;
224
225 /* Current message, transfer and state */
226 struct spi_message *cur_msg;
227 struct spi_transfer *cur_transfer;
228 struct chip_data *cur_chip;
229
230 /* Rd / Wr buffers pointers */
231 size_t len;
232 void *tx;
233 void *tx_end;
234 void *rx;
235 void *rx_end;
236
237 u8 rd_only;
238 u8 n_bytes;
239 int cs_change;
240
241 /* Function pointers */
242 irqreturn_t (*transfer_handler)(struct driver_data *drv_data);
243 void (*cs_control)(u32 command);
244
245 /* DMA setup */
246 int rx_channel;
247 int tx_channel;
248 dma_addr_t rx_dma;
249 dma_addr_t tx_dma;
250 int rx_dma_needs_unmap;
251 int tx_dma_needs_unmap;
252 size_t tx_map_len;
253 u32 dummy_dma_buf ____cacheline_aligned;
254
255 struct clk *clk;
256};
257
258/* Runtime state */
259struct chip_data {
260 u32 control;
261 u32 period;
262 u32 test;
263
264 u8 enable_dma:1;
265 u8 bits_per_word;
266 u8 n_bytes;
267 u32 max_speed_hz;
268
269 void (*cs_control)(u32 command);
270};
271/*-------------------------------------------------------------------------*/
272
273
274static void pump_messages(struct work_struct *work);
275
276static void flush(struct driver_data *drv_data)
277{
278 void __iomem *regs = drv_data->regs;
279 u32 control;
280
281 dev_dbg(&drv_data->pdev->dev, "flush\n");
282
283 /* Wait for end of transaction */
284 do {
285 control = readl(regs + SPI_CONTROL);
286 } while (control & SPI_CONTROL_XCH);
287
288 /* Release chip select if requested, transfer delays are
289 handled in pump_transfers */
290 if (drv_data->cs_change)
291 drv_data->cs_control(SPI_CS_DEASSERT);
292
293 /* Disable SPI to flush FIFOs */
294 writel(control & ~SPI_CONTROL_SPIEN, regs + SPI_CONTROL);
295 writel(control, regs + SPI_CONTROL);
296}
297
298static void restore_state(struct driver_data *drv_data)
299{
300 void __iomem *regs = drv_data->regs;
301 struct chip_data *chip = drv_data->cur_chip;
302
303 /* Load chip registers */
304 dev_dbg(&drv_data->pdev->dev,
305 "restore_state\n"
306 " test = 0x%08X\n"
307 " control = 0x%08X\n",
308 chip->test,
309 chip->control);
310 writel(chip->test, regs + SPI_TEST);
311 writel(chip->period, regs + SPI_PERIOD);
312 writel(0, regs + SPI_INT_STATUS);
313 writel(chip->control, regs + SPI_CONTROL);
314}
315
316static void null_cs_control(u32 command)
317{
318}
319
320static inline u32 data_to_write(struct driver_data *drv_data)
321{
322 return ((u32)(drv_data->tx_end - drv_data->tx)) / drv_data->n_bytes;
323}
324
325static inline u32 data_to_read(struct driver_data *drv_data)
326{
327 return ((u32)(drv_data->rx_end - drv_data->rx)) / drv_data->n_bytes;
328}
329
330static int write(struct driver_data *drv_data)
331{
332 void __iomem *regs = drv_data->regs;
333 void *tx = drv_data->tx;
334 void *tx_end = drv_data->tx_end;
335 u8 n_bytes = drv_data->n_bytes;
336 u32 remaining_writes;
337 u32 fifo_avail_space;
338 u32 n;
339 u16 d;
340
341 /* Compute how many fifo writes to do */
342 remaining_writes = (u32)(tx_end - tx) / n_bytes;
343 fifo_avail_space = SPI_FIFO_DEPTH -
344 (readl(regs + SPI_TEST) & SPI_TEST_TXCNT);
345 if (drv_data->rx && (fifo_avail_space > SPI_FIFO_OVERFLOW_MARGIN))
346 /* Fix misunderstood receive overflow */
347 fifo_avail_space -= SPI_FIFO_OVERFLOW_MARGIN;
348 n = min(remaining_writes, fifo_avail_space);
349
350 dev_dbg(&drv_data->pdev->dev,
351 "write type %s\n"
352 " remaining writes = %d\n"
353 " fifo avail space = %d\n"
354 " fifo writes = %d\n",
355 (n_bytes == 1) ? "u8" : "u16",
356 remaining_writes,
357 fifo_avail_space,
358 n);
359
360 if (n > 0) {
361 /* Fill SPI TXFIFO */
362 if (drv_data->rd_only) {
363 tx += n * n_bytes;
364 while (n--)
365 writel(SPI_DUMMY_u16, regs + SPI_TXDATA);
366 } else {
367 if (n_bytes == 1) {
368 while (n--) {
369 d = *(u8*)tx;
370 writel(d, regs + SPI_TXDATA);
371 tx += 1;
372 }
373 } else {
374 while (n--) {
375 d = *(u16*)tx;
376 writel(d, regs + SPI_TXDATA);
377 tx += 2;
378 }
379 }
380 }
381
382 /* Trigger transfer */
383 writel(readl(regs + SPI_CONTROL) | SPI_CONTROL_XCH,
384 regs + SPI_CONTROL);
385
386 /* Update tx pointer */
387 drv_data->tx = tx;
388 }
389
390 return (tx >= tx_end);
391}
392
393static int read(struct driver_data *drv_data)
394{
395 void __iomem *regs = drv_data->regs;
396 void *rx = drv_data->rx;
397 void *rx_end = drv_data->rx_end;
398 u8 n_bytes = drv_data->n_bytes;
399 u32 remaining_reads;
400 u32 fifo_rxcnt;
401 u32 n;
402 u16 d;
403
404 /* Compute how many fifo reads to do */
405 remaining_reads = (u32)(rx_end - rx) / n_bytes;
406 fifo_rxcnt = (readl(regs + SPI_TEST) & SPI_TEST_RXCNT) >>
407 SPI_TEST_RXCNT_LSB;
408 n = min(remaining_reads, fifo_rxcnt);
409
410 dev_dbg(&drv_data->pdev->dev,
411 "read type %s\n"
412 " remaining reads = %d\n"
413 " fifo rx count = %d\n"
414 " fifo reads = %d\n",
415 (n_bytes == 1) ? "u8" : "u16",
416 remaining_reads,
417 fifo_rxcnt,
418 n);
419
420 if (n > 0) {
421 /* Read SPI RXFIFO */
422 if (n_bytes == 1) {
423 while (n--) {
424 d = readl(regs + SPI_RXDATA);
425 *((u8*)rx) = d;
426 rx += 1;
427 }
428 } else {
429 while (n--) {
430 d = readl(regs + SPI_RXDATA);
431 *((u16*)rx) = d;
432 rx += 2;
433 }
434 }
435
436 /* Update rx pointer */
437 drv_data->rx = rx;
438 }
439
440 return (rx >= rx_end);
441}
442
443static void *next_transfer(struct driver_data *drv_data)
444{
445 struct spi_message *msg = drv_data->cur_msg;
446 struct spi_transfer *trans = drv_data->cur_transfer;
447
448 /* Move to next transfer */
449 if (trans->transfer_list.next != &msg->transfers) {
450 drv_data->cur_transfer =
451 list_entry(trans->transfer_list.next,
452 struct spi_transfer,
453 transfer_list);
454 return RUNNING_STATE;
455 }
456
457 return DONE_STATE;
458}
459
460static int map_dma_buffers(struct driver_data *drv_data)
461{
462 struct spi_message *msg;
463 struct device *dev;
464 void *buf;
465
466 drv_data->rx_dma_needs_unmap = 0;
467 drv_data->tx_dma_needs_unmap = 0;
468
469 if (!drv_data->master_info->enable_dma ||
470 !drv_data->cur_chip->enable_dma)
471 return -1;
472
473 msg = drv_data->cur_msg;
474 dev = &msg->spi->dev;
475 if (msg->is_dma_mapped) {
476 if (drv_data->tx_dma)
477 /* The caller provided at least dma and cpu virtual
478 address for write; pump_transfers() will consider the
479 transfer as write only if cpu rx virtual address is
480 NULL */
481 return 0;
482
483 if (drv_data->rx_dma) {
484 /* The caller provided dma and cpu virtual address to
485 performe read only transfer -->
486 use drv_data->dummy_dma_buf for dummy writes to
487 achive reads */
488 buf = &drv_data->dummy_dma_buf;
489 drv_data->tx_map_len = sizeof(drv_data->dummy_dma_buf);
490 drv_data->tx_dma = dma_map_single(dev,
491 buf,
492 drv_data->tx_map_len,
493 DMA_TO_DEVICE);
494 if (dma_mapping_error(dev, drv_data->tx_dma))
495 return -1;
496
497 drv_data->tx_dma_needs_unmap = 1;
498
499 /* Flags transfer as rd_only for pump_transfers() DMA
500 regs programming (should be redundant) */
501 drv_data->tx = NULL;
502
503 return 0;
504 }
505 }
506
507 if (!IS_DMA_ALIGNED(drv_data->rx) || !IS_DMA_ALIGNED(drv_data->tx))
508 return -1;
509
510 if (drv_data->tx == NULL) {
511 /* Read only message --> use drv_data->dummy_dma_buf for dummy
512 writes to achive reads */
513 buf = &drv_data->dummy_dma_buf;
514 drv_data->tx_map_len = sizeof(drv_data->dummy_dma_buf);
515 } else {
516 buf = drv_data->tx;
517 drv_data->tx_map_len = drv_data->len;
518 }
519 drv_data->tx_dma = dma_map_single(dev,
520 buf,
521 drv_data->tx_map_len,
522 DMA_TO_DEVICE);
523 if (dma_mapping_error(dev, drv_data->tx_dma))
524 return -1;
525 drv_data->tx_dma_needs_unmap = 1;
526
527 /* NULL rx means write-only transfer and no map needed
528 * since rx DMA will not be used */
529 if (drv_data->rx) {
530 buf = drv_data->rx;
531 drv_data->rx_dma = dma_map_single(dev,
532 buf,
533 drv_data->len,
534 DMA_FROM_DEVICE);
535 if (dma_mapping_error(dev, drv_data->rx_dma)) {
536 if (drv_data->tx_dma) {
537 dma_unmap_single(dev,
538 drv_data->tx_dma,
539 drv_data->tx_map_len,
540 DMA_TO_DEVICE);
541 drv_data->tx_dma_needs_unmap = 0;
542 }
543 return -1;
544 }
545 drv_data->rx_dma_needs_unmap = 1;
546 }
547
548 return 0;
549}
550
551static void unmap_dma_buffers(struct driver_data *drv_data)
552{
553 struct spi_message *msg = drv_data->cur_msg;
554 struct device *dev = &msg->spi->dev;
555
556 if (drv_data->rx_dma_needs_unmap) {
557 dma_unmap_single(dev,
558 drv_data->rx_dma,
559 drv_data->len,
560 DMA_FROM_DEVICE);
561 drv_data->rx_dma_needs_unmap = 0;
562 }
563 if (drv_data->tx_dma_needs_unmap) {
564 dma_unmap_single(dev,
565 drv_data->tx_dma,
566 drv_data->tx_map_len,
567 DMA_TO_DEVICE);
568 drv_data->tx_dma_needs_unmap = 0;
569 }
570}
571
572/* Caller already set message->status (dma is already blocked) */
573static void giveback(struct spi_message *message, struct driver_data *drv_data)
574{
575 void __iomem *regs = drv_data->regs;
576
577 /* Bring SPI to sleep; restore_state() and pump_transfer()
578 will do new setup */
579 writel(0, regs + SPI_INT_STATUS);
580 writel(0, regs + SPI_DMA);
581
582 /* Unconditioned deselct */
583 drv_data->cs_control(SPI_CS_DEASSERT);
584
585 message->state = NULL;
586 if (message->complete)
587 message->complete(message->context);
588
589 drv_data->cur_msg = NULL;
590 drv_data->cur_transfer = NULL;
591 drv_data->cur_chip = NULL;
592 queue_work(drv_data->workqueue, &drv_data->work);
593}
594
595static void dma_err_handler(int channel, void *data, int errcode)
596{
597 struct driver_data *drv_data = data;
598 struct spi_message *msg = drv_data->cur_msg;
599
600 dev_dbg(&drv_data->pdev->dev, "dma_err_handler\n");
601
602 /* Disable both rx and tx dma channels */
603 imx_dma_disable(drv_data->rx_channel);
604 imx_dma_disable(drv_data->tx_channel);
605 unmap_dma_buffers(drv_data);
606
607 flush(drv_data);
608
609 msg->state = ERROR_STATE;
610 tasklet_schedule(&drv_data->pump_transfers);
611}
612
613static void dma_tx_handler(int channel, void *data)
614{
615 struct driver_data *drv_data = data;
616
617 dev_dbg(&drv_data->pdev->dev, "dma_tx_handler\n");
618
619 imx_dma_disable(channel);
620
621 /* Now waits for TX FIFO empty */
622 writel(SPI_INTEN_TE, drv_data->regs + SPI_INT_STATUS);
623}
624
625static irqreturn_t dma_transfer(struct driver_data *drv_data)
626{
627 u32 status;
628 struct spi_message *msg = drv_data->cur_msg;
629 void __iomem *regs = drv_data->regs;
630
631 status = readl(regs + SPI_INT_STATUS);
632
633 if ((status & (SPI_INTEN_RO | SPI_STATUS_RO))
634 == (SPI_INTEN_RO | SPI_STATUS_RO)) {
635 writel(status & ~SPI_INTEN, regs + SPI_INT_STATUS);
636
637 imx_dma_disable(drv_data->tx_channel);
638 imx_dma_disable(drv_data->rx_channel);
639 unmap_dma_buffers(drv_data);
640
641 flush(drv_data);
642
643 dev_warn(&drv_data->pdev->dev,
644 "dma_transfer - fifo overun\n");
645
646 msg->state = ERROR_STATE;
647 tasklet_schedule(&drv_data->pump_transfers);
648
649 return IRQ_HANDLED;
650 }
651
652 if (status & SPI_STATUS_TE) {
653 writel(status & ~SPI_INTEN_TE, regs + SPI_INT_STATUS);
654
655 if (drv_data->rx) {
656 /* Wait end of transfer before read trailing data */
657 while (readl(regs + SPI_CONTROL) & SPI_CONTROL_XCH)
658 cpu_relax();
659
660 imx_dma_disable(drv_data->rx_channel);
661 unmap_dma_buffers(drv_data);
662
663 /* Release chip select if requested, transfer delays are
664 handled in pump_transfers() */
665 if (drv_data->cs_change)
666 drv_data->cs_control(SPI_CS_DEASSERT);
667
668 /* Calculate number of trailing data and read them */
669 dev_dbg(&drv_data->pdev->dev,
670 "dma_transfer - test = 0x%08X\n",
671 readl(regs + SPI_TEST));
672 drv_data->rx = drv_data->rx_end -
673 ((readl(regs + SPI_TEST) &
674 SPI_TEST_RXCNT) >>
675 SPI_TEST_RXCNT_LSB)*drv_data->n_bytes;
676 read(drv_data);
677 } else {
678 /* Write only transfer */
679 unmap_dma_buffers(drv_data);
680
681 flush(drv_data);
682 }
683
684 /* End of transfer, update total byte transfered */
685 msg->actual_length += drv_data->len;
686
687 /* Move to next transfer */
688 msg->state = next_transfer(drv_data);
689
690 /* Schedule transfer tasklet */
691 tasklet_schedule(&drv_data->pump_transfers);
692
693 return IRQ_HANDLED;
694 }
695
696 /* Opps problem detected */
697 return IRQ_NONE;
698}
699
700static irqreturn_t interrupt_wronly_transfer(struct driver_data *drv_data)
701{
702 struct spi_message *msg = drv_data->cur_msg;
703 void __iomem *regs = drv_data->regs;
704 u32 status;
705 irqreturn_t handled = IRQ_NONE;
706
707 status = readl(regs + SPI_INT_STATUS);
708
709 if (status & SPI_INTEN_TE) {
710 /* TXFIFO Empty Interrupt on the last transfered word */
711 writel(status & ~SPI_INTEN, regs + SPI_INT_STATUS);
712 dev_dbg(&drv_data->pdev->dev,
713 "interrupt_wronly_transfer - end of tx\n");
714
715 flush(drv_data);
716
717 /* Update total byte transfered */
718 msg->actual_length += drv_data->len;
719
720 /* Move to next transfer */
721 msg->state = next_transfer(drv_data);
722
723 /* Schedule transfer tasklet */
724 tasklet_schedule(&drv_data->pump_transfers);
725
726 return IRQ_HANDLED;
727 } else {
728 while (status & SPI_STATUS_TH) {
729 dev_dbg(&drv_data->pdev->dev,
730 "interrupt_wronly_transfer - status = 0x%08X\n",
731 status);
732
733 /* Pump data */
734 if (write(drv_data)) {
735 /* End of TXFIFO writes,
736 now wait until TXFIFO is empty */
737 writel(SPI_INTEN_TE, regs + SPI_INT_STATUS);
738 return IRQ_HANDLED;
739 }
740
741 status = readl(regs + SPI_INT_STATUS);
742
743 /* We did something */
744 handled = IRQ_HANDLED;
745 }
746 }
747
748 return handled;
749}
750
751static irqreturn_t interrupt_transfer(struct driver_data *drv_data)
752{
753 struct spi_message *msg = drv_data->cur_msg;
754 void __iomem *regs = drv_data->regs;
755 u32 status, control;
756 irqreturn_t handled = IRQ_NONE;
757 unsigned long limit;
758
759 status = readl(regs + SPI_INT_STATUS);
760
761 if (status & SPI_INTEN_TE) {
762 /* TXFIFO Empty Interrupt on the last transfered word */
763 writel(status & ~SPI_INTEN, regs + SPI_INT_STATUS);
764 dev_dbg(&drv_data->pdev->dev,
765 "interrupt_transfer - end of tx\n");
766
767 if (msg->state == ERROR_STATE) {
768 /* RXFIFO overrun was detected and message aborted */
769 flush(drv_data);
770 } else {
771 /* Wait for end of transaction */
772 do {
773 control = readl(regs + SPI_CONTROL);
774 } while (control & SPI_CONTROL_XCH);
775
776 /* Release chip select if requested, transfer delays are
777 handled in pump_transfers */
778 if (drv_data->cs_change)
779 drv_data->cs_control(SPI_CS_DEASSERT);
780
781 /* Read trailing bytes */
782 limit = loops_per_jiffy << 1;
783 while ((read(drv_data) == 0) && --limit)
784 cpu_relax();
785
786 if (limit == 0)
787 dev_err(&drv_data->pdev->dev,
788 "interrupt_transfer - "
789 "trailing byte read failed\n");
790 else
791 dev_dbg(&drv_data->pdev->dev,
792 "interrupt_transfer - end of rx\n");
793
794 /* Update total byte transfered */
795 msg->actual_length += drv_data->len;
796
797 /* Move to next transfer */
798 msg->state = next_transfer(drv_data);
799 }
800
801 /* Schedule transfer tasklet */
802 tasklet_schedule(&drv_data->pump_transfers);
803
804 return IRQ_HANDLED;
805 } else {
806 while (status & (SPI_STATUS_TH | SPI_STATUS_RO)) {
807 dev_dbg(&drv_data->pdev->dev,
808 "interrupt_transfer - status = 0x%08X\n",
809 status);
810
811 if (status & SPI_STATUS_RO) {
812 /* RXFIFO overrun, abort message end wait
813 until TXFIFO is empty */
814 writel(SPI_INTEN_TE, regs + SPI_INT_STATUS);
815
816 dev_warn(&drv_data->pdev->dev,
817 "interrupt_transfer - fifo overun\n"
818 " data not yet written = %d\n"
819 " data not yet read = %d\n",
820 data_to_write(drv_data),
821 data_to_read(drv_data));
822
823 msg->state = ERROR_STATE;
824
825 return IRQ_HANDLED;
826 }
827
828 /* Pump data */
829 read(drv_data);
830 if (write(drv_data)) {
831 /* End of TXFIFO writes,
832 now wait until TXFIFO is empty */
833 writel(SPI_INTEN_TE, regs + SPI_INT_STATUS);
834 return IRQ_HANDLED;
835 }
836
837 status = readl(regs + SPI_INT_STATUS);
838
839 /* We did something */
840 handled = IRQ_HANDLED;
841 }
842 }
843
844 return handled;
845}
846
847static irqreturn_t spi_int(int irq, void *dev_id)
848{
849 struct driver_data *drv_data = (struct driver_data *)dev_id;
850
851 if (!drv_data->cur_msg) {
852 dev_err(&drv_data->pdev->dev,
853 "spi_int - bad message state\n");
854 /* Never fail */
855 return IRQ_HANDLED;
856 }
857
858 return drv_data->transfer_handler(drv_data);
859}
860
861static inline u32 spi_speed_hz(struct driver_data *drv_data, u32 data_rate)
862{
863 return clk_get_rate(drv_data->clk) / (4 << ((data_rate) >> 13));
864}
865
866static u32 spi_data_rate(struct driver_data *drv_data, u32 speed_hz)
867{
868 u32 div;
869 u32 quantized_hz = clk_get_rate(drv_data->clk) >> 2;
870
871 for (div = SPI_PERCLK2_DIV_MIN;
872 div <= SPI_PERCLK2_DIV_MAX;
873 div++, quantized_hz >>= 1) {
874 if (quantized_hz <= speed_hz)
875 /* Max available speed LEQ required speed */
876 return div << 13;
877 }
878 return SPI_CONTROL_DATARATE_BAD;
879}
880
881static void pump_transfers(unsigned long data)
882{
883 struct driver_data *drv_data = (struct driver_data *)data;
884 struct spi_message *message;
885 struct spi_transfer *transfer, *previous;
886 struct chip_data *chip;
887 void __iomem *regs;
888 u32 tmp, control;
889
890 dev_dbg(&drv_data->pdev->dev, "pump_transfer\n");
891
892 message = drv_data->cur_msg;
893
894 /* Handle for abort */
895 if (message->state == ERROR_STATE) {
896 message->status = -EIO;
897 giveback(message, drv_data);
898 return;
899 }
900
901 /* Handle end of message */
902 if (message->state == DONE_STATE) {
903 message->status = 0;
904 giveback(message, drv_data);
905 return;
906 }
907
908 chip = drv_data->cur_chip;
909
910 /* Delay if requested at end of transfer*/
911 transfer = drv_data->cur_transfer;
912 if (message->state == RUNNING_STATE) {
913 previous = list_entry(transfer->transfer_list.prev,
914 struct spi_transfer,
915 transfer_list);
916 if (previous->delay_usecs)
917 udelay(previous->delay_usecs);
918 } else {
919 /* START_STATE */
920 message->state = RUNNING_STATE;
921 drv_data->cs_control = chip->cs_control;
922 }
923
924 transfer = drv_data->cur_transfer;
925 drv_data->tx = (void *)transfer->tx_buf;
926 drv_data->tx_end = drv_data->tx + transfer->len;
927 drv_data->rx = transfer->rx_buf;
928 drv_data->rx_end = drv_data->rx + transfer->len;
929 drv_data->rx_dma = transfer->rx_dma;
930 drv_data->tx_dma = transfer->tx_dma;
931 drv_data->len = transfer->len;
932 drv_data->cs_change = transfer->cs_change;
933 drv_data->rd_only = (drv_data->tx == NULL);
934
935 regs = drv_data->regs;
936 control = readl(regs + SPI_CONTROL);
937
938 /* Bits per word setup */
939 tmp = transfer->bits_per_word;
940 if (tmp == 0) {
941 /* Use device setup */
942 tmp = chip->bits_per_word;
943 drv_data->n_bytes = chip->n_bytes;
944 } else
945 /* Use per-transfer setup */
946 drv_data->n_bytes = (tmp <= 8) ? 1 : 2;
947 u32_EDIT(control, SPI_CONTROL_BITCOUNT_MASK, tmp - 1);
948
949 /* Speed setup (surely valid because already checked) */
950 tmp = transfer->speed_hz;
951 if (tmp == 0)
952 tmp = chip->max_speed_hz;
953 tmp = spi_data_rate(drv_data, tmp);
954 u32_EDIT(control, SPI_CONTROL_DATARATE, tmp);
955
956 writel(control, regs + SPI_CONTROL);
957
958 /* Assert device chip-select */
959 drv_data->cs_control(SPI_CS_ASSERT);
960
961 /* DMA cannot read/write SPI FIFOs other than 16 bits at a time; hence
962 if bits_per_word is less or equal 8 PIO transfers are performed.
963 Moreover DMA is convinient for transfer length bigger than FIFOs
964 byte size. */
965 if ((drv_data->n_bytes == 2) &&
966 (drv_data->len > SPI_FIFO_DEPTH*SPI_FIFO_BYTE_WIDTH) &&
967 (map_dma_buffers(drv_data) == 0)) {
968 dev_dbg(&drv_data->pdev->dev,
969 "pump dma transfer\n"
970 " tx = %p\n"
971 " tx_dma = %08X\n"
972 " rx = %p\n"
973 " rx_dma = %08X\n"
974 " len = %d\n",
975 drv_data->tx,
976 (unsigned int)drv_data->tx_dma,
977 drv_data->rx,
978 (unsigned int)drv_data->rx_dma,
979 drv_data->len);
980
981 /* Ensure we have the correct interrupt handler */
982 drv_data->transfer_handler = dma_transfer;
983
984 /* Trigger transfer */
985 writel(readl(regs + SPI_CONTROL) | SPI_CONTROL_XCH,
986 regs + SPI_CONTROL);
987
988 /* Setup tx DMA */
989 if (drv_data->tx)
990 /* Linear source address */
991 CCR(drv_data->tx_channel) =
992 CCR_DMOD_FIFO |
993 CCR_SMOD_LINEAR |
994 CCR_SSIZ_32 | CCR_DSIZ_16 |
995 CCR_REN;
996 else
997 /* Read only transfer -> fixed source address for
998 dummy write to achive read */
999 CCR(drv_data->tx_channel) =
1000 CCR_DMOD_FIFO |
1001 CCR_SMOD_FIFO |
1002 CCR_SSIZ_32 | CCR_DSIZ_16 |
1003 CCR_REN;
1004
1005 imx_dma_setup_single(
1006 drv_data->tx_channel,
1007 drv_data->tx_dma,
1008 drv_data->len,
1009 drv_data->rd_data_phys + 4,
1010 DMA_MODE_WRITE);
1011
1012 if (drv_data->rx) {
1013 /* Setup rx DMA for linear destination address */
1014 CCR(drv_data->rx_channel) =
1015 CCR_DMOD_LINEAR |
1016 CCR_SMOD_FIFO |
1017 CCR_DSIZ_32 | CCR_SSIZ_16 |
1018 CCR_REN;
1019 imx_dma_setup_single(
1020 drv_data->rx_channel,
1021 drv_data->rx_dma,
1022 drv_data->len,
1023 drv_data->rd_data_phys,
1024 DMA_MODE_READ);
1025 imx_dma_enable(drv_data->rx_channel);
1026
1027 /* Enable SPI interrupt */
1028 writel(SPI_INTEN_RO, regs + SPI_INT_STATUS);
1029
1030 /* Set SPI to request DMA service on both
1031 Rx and Tx half fifo watermark */
1032 writel(SPI_DMA_RHDEN | SPI_DMA_THDEN, regs + SPI_DMA);
1033 } else
1034 /* Write only access -> set SPI to request DMA
1035 service on Tx half fifo watermark */
1036 writel(SPI_DMA_THDEN, regs + SPI_DMA);
1037
1038 imx_dma_enable(drv_data->tx_channel);
1039 } else {
1040 dev_dbg(&drv_data->pdev->dev,
1041 "pump pio transfer\n"
1042 " tx = %p\n"
1043 " rx = %p\n"
1044 " len = %d\n",
1045 drv_data->tx,
1046 drv_data->rx,
1047 drv_data->len);
1048
1049 /* Ensure we have the correct interrupt handler */
1050 if (drv_data->rx)
1051 drv_data->transfer_handler = interrupt_transfer;
1052 else
1053 drv_data->transfer_handler = interrupt_wronly_transfer;
1054
1055 /* Enable SPI interrupt */
1056 if (drv_data->rx)
1057 writel(SPI_INTEN_TH | SPI_INTEN_RO,
1058 regs + SPI_INT_STATUS);
1059 else
1060 writel(SPI_INTEN_TH, regs + SPI_INT_STATUS);
1061 }
1062}
1063
1064static void pump_messages(struct work_struct *work)
1065{
1066 struct driver_data *drv_data =
1067 container_of(work, struct driver_data, work);
1068 unsigned long flags;
1069
1070 /* Lock queue and check for queue work */
1071 spin_lock_irqsave(&drv_data->lock, flags);
1072 if (list_empty(&drv_data->queue) || drv_data->run == QUEUE_STOPPED) {
1073 drv_data->busy = 0;
1074 spin_unlock_irqrestore(&drv_data->lock, flags);
1075 return;
1076 }
1077
1078 /* Make sure we are not already running a message */
1079 if (drv_data->cur_msg) {
1080 spin_unlock_irqrestore(&drv_data->lock, flags);
1081 return;
1082 }
1083
1084 /* Extract head of queue */
1085 drv_data->cur_msg = list_entry(drv_data->queue.next,
1086 struct spi_message, queue);
1087 list_del_init(&drv_data->cur_msg->queue);
1088 drv_data->busy = 1;
1089 spin_unlock_irqrestore(&drv_data->lock, flags);
1090
1091 /* Initial message state */
1092 drv_data->cur_msg->state = START_STATE;
1093 drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next,
1094 struct spi_transfer,
1095 transfer_list);
1096
1097 /* Setup the SPI using the per chip configuration */
1098 drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi);
1099 restore_state(drv_data);
1100
1101 /* Mark as busy and launch transfers */
1102 tasklet_schedule(&drv_data->pump_transfers);
1103}
1104
1105static int transfer(struct spi_device *spi, struct spi_message *msg)
1106{
1107 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
1108 u32 min_speed_hz, max_speed_hz, tmp;
1109 struct spi_transfer *trans;
1110 unsigned long flags;
1111
1112 msg->actual_length = 0;
1113
1114 /* Per transfer setup check */
1115 min_speed_hz = spi_speed_hz(drv_data, SPI_CONTROL_DATARATE_MIN);
1116 max_speed_hz = spi->max_speed_hz;
1117 list_for_each_entry(trans, &msg->transfers, transfer_list) {
1118 tmp = trans->bits_per_word;
1119 if (tmp > 16) {
1120 dev_err(&drv_data->pdev->dev,
1121 "message rejected : "
1122 "invalid transfer bits_per_word (%d bits)\n",
1123 tmp);
1124 goto msg_rejected;
1125 }
1126 tmp = trans->speed_hz;
1127 if (tmp) {
1128 if (tmp < min_speed_hz) {
1129 dev_err(&drv_data->pdev->dev,
1130 "message rejected : "
1131 "device min speed (%d Hz) exceeds "
1132 "required transfer speed (%d Hz)\n",
1133 min_speed_hz,
1134 tmp);
1135 goto msg_rejected;
1136 } else if (tmp > max_speed_hz) {
1137 dev_err(&drv_data->pdev->dev,
1138 "message rejected : "
1139 "transfer speed (%d Hz) exceeds "
1140 "device max speed (%d Hz)\n",
1141 tmp,
1142 max_speed_hz);
1143 goto msg_rejected;
1144 }
1145 }
1146 }
1147
1148 /* Message accepted */
1149 msg->status = -EINPROGRESS;
1150 msg->state = START_STATE;
1151
1152 spin_lock_irqsave(&drv_data->lock, flags);
1153 if (drv_data->run == QUEUE_STOPPED) {
1154 spin_unlock_irqrestore(&drv_data->lock, flags);
1155 return -ESHUTDOWN;
1156 }
1157
1158 list_add_tail(&msg->queue, &drv_data->queue);
1159 if (drv_data->run == QUEUE_RUNNING && !drv_data->busy)
1160 queue_work(drv_data->workqueue, &drv_data->work);
1161
1162 spin_unlock_irqrestore(&drv_data->lock, flags);
1163 return 0;
1164
1165msg_rejected:
1166 /* Message rejected and not queued */
1167 msg->status = -EINVAL;
1168 msg->state = ERROR_STATE;
1169 if (msg->complete)
1170 msg->complete(msg->context);
1171 return -EINVAL;
1172}
1173
1174/* On first setup bad values must free chip_data memory since will cause
1175 spi_new_device to fail. Bad value setup from protocol driver are simply not
1176 applied and notified to the calling driver. */
1177static int setup(struct spi_device *spi)
1178{
1179 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
1180 struct spi_imx_chip *chip_info;
1181 struct chip_data *chip;
1182 int first_setup = 0;
1183 u32 tmp;
1184 int status = 0;
1185
1186 /* Get controller data */
1187 chip_info = spi->controller_data;
1188
1189 /* Get controller_state */
1190 chip = spi_get_ctldata(spi);
1191 if (chip == NULL) {
1192 first_setup = 1;
1193
1194 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
1195 if (!chip) {
1196 dev_err(&spi->dev,
1197 "setup - cannot allocate controller state\n");
1198 return -ENOMEM;
1199 }
1200 chip->control = SPI_DEFAULT_CONTROL;
1201
1202 if (chip_info == NULL) {
1203 /* spi_board_info.controller_data not is supplied */
1204 chip_info = kzalloc(sizeof(struct spi_imx_chip),
1205 GFP_KERNEL);
1206 if (!chip_info) {
1207 dev_err(&spi->dev,
1208 "setup - "
1209 "cannot allocate controller data\n");
1210 status = -ENOMEM;
1211 goto err_first_setup;
1212 }
1213 /* Set controller data default value */
1214 chip_info->enable_loopback =
1215 SPI_DEFAULT_ENABLE_LOOPBACK;
1216 chip_info->enable_dma = SPI_DEFAULT_ENABLE_DMA;
1217 chip_info->ins_ss_pulse = 1;
1218 chip_info->bclk_wait = SPI_DEFAULT_PERIOD_WAIT;
1219 chip_info->cs_control = null_cs_control;
1220 }
1221 }
1222
1223 /* Now set controller state based on controller data */
1224
1225 if (first_setup) {
1226 /* SPI loopback */
1227 if (chip_info->enable_loopback)
1228 chip->test = SPI_TEST_LBC;
1229 else
1230 chip->test = 0;
1231
1232 /* SPI dma driven */
1233 chip->enable_dma = chip_info->enable_dma;
1234
1235 /* SPI /SS pulse between spi burst */
1236 if (chip_info->ins_ss_pulse)
1237 u32_EDIT(chip->control,
1238 SPI_CONTROL_SSCTL, SPI_CONTROL_SSCTL_1);
1239 else
1240 u32_EDIT(chip->control,
1241 SPI_CONTROL_SSCTL, SPI_CONTROL_SSCTL_0);
1242
1243 /* SPI bclk waits between each bits_per_word spi burst */
1244 if (chip_info->bclk_wait > SPI_PERIOD_MAX_WAIT) {
1245 dev_err(&spi->dev,
1246 "setup - "
1247 "bclk_wait exceeds max allowed (%d)\n",
1248 SPI_PERIOD_MAX_WAIT);
1249 goto err_first_setup;
1250 }
1251 chip->period = SPI_PERIOD_CSRC_BCLK |
1252 (chip_info->bclk_wait & SPI_PERIOD_WAIT);
1253 }
1254
1255 /* SPI mode */
1256 tmp = spi->mode;
1257 if (tmp & SPI_CS_HIGH) {
1258 u32_EDIT(chip->control,
1259 SPI_CONTROL_SSPOL, SPI_CONTROL_SSPOL_ACT_HIGH);
1260 }
1261 switch (tmp & SPI_MODE_3) {
1262 case SPI_MODE_0:
1263 tmp = 0;
1264 break;
1265 case SPI_MODE_1:
1266 tmp = SPI_CONTROL_PHA_1;
1267 break;
1268 case SPI_MODE_2:
1269 tmp = SPI_CONTROL_POL_ACT_LOW;
1270 break;
1271 default:
1272 /* SPI_MODE_3 */
1273 tmp = SPI_CONTROL_PHA_1 | SPI_CONTROL_POL_ACT_LOW;
1274 break;
1275 }
1276 u32_EDIT(chip->control, SPI_CONTROL_POL | SPI_CONTROL_PHA, tmp);
1277
1278 /* SPI word width */
1279 tmp = spi->bits_per_word;
1280 if (tmp > 16) {
1281 status = -EINVAL;
1282 dev_err(&spi->dev,
1283 "setup - "
1284 "invalid bits_per_word (%d)\n",
1285 tmp);
1286 if (first_setup)
1287 goto err_first_setup;
1288 else {
1289 /* Undo setup using chip as backup copy */
1290 tmp = chip->bits_per_word;
1291 spi->bits_per_word = tmp;
1292 }
1293 }
1294 chip->bits_per_word = tmp;
1295 u32_EDIT(chip->control, SPI_CONTROL_BITCOUNT_MASK, tmp - 1);
1296 chip->n_bytes = (tmp <= 8) ? 1 : 2;
1297
1298 /* SPI datarate */
1299 tmp = spi_data_rate(drv_data, spi->max_speed_hz);
1300 if (tmp == SPI_CONTROL_DATARATE_BAD) {
1301 status = -EINVAL;
1302 dev_err(&spi->dev,
1303 "setup - "
1304 "HW min speed (%d Hz) exceeds required "
1305 "max speed (%d Hz)\n",
1306 spi_speed_hz(drv_data, SPI_CONTROL_DATARATE_MIN),
1307 spi->max_speed_hz);
1308 if (first_setup)
1309 goto err_first_setup;
1310 else
1311 /* Undo setup using chip as backup copy */
1312 spi->max_speed_hz = chip->max_speed_hz;
1313 } else {
1314 u32_EDIT(chip->control, SPI_CONTROL_DATARATE, tmp);
1315 /* Actual rounded max_speed_hz */
1316 tmp = spi_speed_hz(drv_data, tmp);
1317 spi->max_speed_hz = tmp;
1318 chip->max_speed_hz = tmp;
1319 }
1320
1321 /* SPI chip-select management */
1322 if (chip_info->cs_control)
1323 chip->cs_control = chip_info->cs_control;
1324 else
1325 chip->cs_control = null_cs_control;
1326
1327 /* Save controller_state */
1328 spi_set_ctldata(spi, chip);
1329
1330 /* Summary */
1331 dev_dbg(&spi->dev,
1332 "setup succeded\n"
1333 " loopback enable = %s\n"
1334 " dma enable = %s\n"
1335 " insert /ss pulse = %s\n"
1336 " period wait = %d\n"
1337 " mode = %d\n"
1338 " bits per word = %d\n"
1339 " min speed = %d Hz\n"
1340 " rounded max speed = %d Hz\n",
1341 chip->test & SPI_TEST_LBC ? "Yes" : "No",
1342 chip->enable_dma ? "Yes" : "No",
1343 chip->control & SPI_CONTROL_SSCTL ? "Yes" : "No",
1344 chip->period & SPI_PERIOD_WAIT,
1345 spi->mode,
1346 spi->bits_per_word,
1347 spi_speed_hz(drv_data, SPI_CONTROL_DATARATE_MIN),
1348 spi->max_speed_hz);
1349 return status;
1350
1351err_first_setup:
1352 kfree(chip);
1353 return status;
1354}
1355
1356static void cleanup(struct spi_device *spi)
1357{
1358 kfree(spi_get_ctldata(spi));
1359}
1360
1361static int __init init_queue(struct driver_data *drv_data)
1362{
1363 INIT_LIST_HEAD(&drv_data->queue);
1364 spin_lock_init(&drv_data->lock);
1365
1366 drv_data->run = QUEUE_STOPPED;
1367 drv_data->busy = 0;
1368
1369 tasklet_init(&drv_data->pump_transfers,
1370 pump_transfers, (unsigned long)drv_data);
1371
1372 INIT_WORK(&drv_data->work, pump_messages);
1373 drv_data->workqueue = create_singlethread_workqueue(
1374 dev_name(drv_data->master->dev.parent));
1375 if (drv_data->workqueue == NULL)
1376 return -EBUSY;
1377
1378 return 0;
1379}
1380
1381static int start_queue(struct driver_data *drv_data)
1382{
1383 unsigned long flags;
1384
1385 spin_lock_irqsave(&drv_data->lock, flags);
1386
1387 if (drv_data->run == QUEUE_RUNNING || drv_data->busy) {
1388 spin_unlock_irqrestore(&drv_data->lock, flags);
1389 return -EBUSY;
1390 }
1391
1392 drv_data->run = QUEUE_RUNNING;
1393 drv_data->cur_msg = NULL;
1394 drv_data->cur_transfer = NULL;
1395 drv_data->cur_chip = NULL;
1396 spin_unlock_irqrestore(&drv_data->lock, flags);
1397
1398 queue_work(drv_data->workqueue, &drv_data->work);
1399
1400 return 0;
1401}
1402
1403static int stop_queue(struct driver_data *drv_data)
1404{
1405 unsigned long flags;
1406 unsigned limit = 500;
1407 int status = 0;
1408
1409 spin_lock_irqsave(&drv_data->lock, flags);
1410
1411 /* This is a bit lame, but is optimized for the common execution path.
1412 * A wait_queue on the drv_data->busy could be used, but then the common
1413 * execution path (pump_messages) would be required to call wake_up or
1414 * friends on every SPI message. Do this instead */
1415 drv_data->run = QUEUE_STOPPED;
1416 while (!list_empty(&drv_data->queue) && drv_data->busy && limit--) {
1417 spin_unlock_irqrestore(&drv_data->lock, flags);
1418 msleep(10);
1419 spin_lock_irqsave(&drv_data->lock, flags);
1420 }
1421
1422 if (!list_empty(&drv_data->queue) || drv_data->busy)
1423 status = -EBUSY;
1424
1425 spin_unlock_irqrestore(&drv_data->lock, flags);
1426
1427 return status;
1428}
1429
1430static int destroy_queue(struct driver_data *drv_data)
1431{
1432 int status;
1433
1434 status = stop_queue(drv_data);
1435 if (status != 0)
1436 return status;
1437
1438 if (drv_data->workqueue)
1439 destroy_workqueue(drv_data->workqueue);
1440
1441 return 0;
1442}
1443
1444static int __init spi_imx_probe(struct platform_device *pdev)
1445{
1446 struct device *dev = &pdev->dev;
1447 struct spi_imx_master *platform_info;
1448 struct spi_master *master;
1449 struct driver_data *drv_data;
1450 struct resource *res;
1451 int irq, status = 0;
1452
1453 platform_info = dev->platform_data;
1454 if (platform_info == NULL) {
1455 dev_err(&pdev->dev, "probe - no platform data supplied\n");
1456 status = -ENODEV;
1457 goto err_no_pdata;
1458 }
1459
1460 /* Allocate master with space for drv_data */
1461 master = spi_alloc_master(dev, sizeof(struct driver_data));
1462 if (!master) {
1463 dev_err(&pdev->dev, "probe - cannot alloc spi_master\n");
1464 status = -ENOMEM;
1465 goto err_no_mem;
1466 }
1467 drv_data = spi_master_get_devdata(master);
1468 drv_data->master = master;
1469 drv_data->master_info = platform_info;
1470 drv_data->pdev = pdev;
1471
1472 /* the spi->mode bits understood by this driver: */
1473 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1474
1475 master->bus_num = pdev->id;
1476 master->num_chipselect = platform_info->num_chipselect;
1477 master->dma_alignment = DMA_ALIGNMENT;
1478 master->cleanup = cleanup;
1479 master->setup = setup;
1480 master->transfer = transfer;
1481
1482 drv_data->dummy_dma_buf = SPI_DUMMY_u32;
1483
1484 drv_data->clk = clk_get(&pdev->dev, "perclk2");
1485 if (IS_ERR(drv_data->clk)) {
1486 dev_err(&pdev->dev, "probe - cannot get clock\n");
1487 status = PTR_ERR(drv_data->clk);
1488 goto err_no_clk;
1489 }
1490 clk_enable(drv_data->clk);
1491
1492 /* Find and map resources */
1493 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1494 if (!res) {
1495 dev_err(&pdev->dev, "probe - MEM resources not defined\n");
1496 status = -ENODEV;
1497 goto err_no_iores;
1498 }
1499 drv_data->ioarea = request_mem_region(res->start,
1500 res->end - res->start + 1,
1501 pdev->name);
1502 if (drv_data->ioarea == NULL) {
1503 dev_err(&pdev->dev, "probe - cannot reserve region\n");
1504 status = -ENXIO;
1505 goto err_no_iores;
1506 }
1507 drv_data->regs = ioremap(res->start, res->end - res->start + 1);
1508 if (drv_data->regs == NULL) {
1509 dev_err(&pdev->dev, "probe - cannot map IO\n");
1510 status = -ENXIO;
1511 goto err_no_iomap;
1512 }
1513 drv_data->rd_data_phys = (dma_addr_t)res->start;
1514
1515 /* Attach to IRQ */
1516 irq = platform_get_irq(pdev, 0);
1517 if (irq < 0) {
1518 dev_err(&pdev->dev, "probe - IRQ resource not defined\n");
1519 status = -ENODEV;
1520 goto err_no_irqres;
1521 }
1522 status = request_irq(irq, spi_int, IRQF_DISABLED,
1523 dev_name(dev), drv_data);
1524 if (status < 0) {
1525 dev_err(&pdev->dev, "probe - cannot get IRQ (%d)\n", status);
1526 goto err_no_irqres;
1527 }
1528
1529 /* Setup DMA if requested */
1530 drv_data->tx_channel = -1;
1531 drv_data->rx_channel = -1;
1532 if (platform_info->enable_dma) {
1533 /* Get rx DMA channel */
1534 drv_data->rx_channel = imx_dma_request_by_prio("spi_imx_rx",
1535 DMA_PRIO_HIGH);
1536 if (drv_data->rx_channel < 0) {
1537 dev_err(dev,
1538 "probe - problem (%d) requesting rx channel\n",
1539 drv_data->rx_channel);
1540 goto err_no_rxdma;
1541 } else
1542 imx_dma_setup_handlers(drv_data->rx_channel, NULL,
1543 dma_err_handler, drv_data);
1544
1545 /* Get tx DMA channel */
1546 drv_data->tx_channel = imx_dma_request_by_prio("spi_imx_tx",
1547 DMA_PRIO_MEDIUM);
1548 if (drv_data->tx_channel < 0) {
1549 dev_err(dev,
1550 "probe - problem (%d) requesting tx channel\n",
1551 drv_data->tx_channel);
1552 imx_dma_free(drv_data->rx_channel);
1553 goto err_no_txdma;
1554 } else
1555 imx_dma_setup_handlers(drv_data->tx_channel,
1556 dma_tx_handler, dma_err_handler,
1557 drv_data);
1558
1559 /* Set request source and burst length for allocated channels */
1560 switch (drv_data->pdev->id) {
1561 case 1:
1562 /* Using SPI1 */
1563 RSSR(drv_data->rx_channel) = DMA_REQ_SPI1_R;
1564 RSSR(drv_data->tx_channel) = DMA_REQ_SPI1_T;
1565 break;
1566 case 2:
1567 /* Using SPI2 */
1568 RSSR(drv_data->rx_channel) = DMA_REQ_SPI2_R;
1569 RSSR(drv_data->tx_channel) = DMA_REQ_SPI2_T;
1570 break;
1571 default:
1572 dev_err(dev, "probe - bad SPI Id\n");
1573 imx_dma_free(drv_data->rx_channel);
1574 imx_dma_free(drv_data->tx_channel);
1575 status = -ENODEV;
1576 goto err_no_devid;
1577 }
1578 BLR(drv_data->rx_channel) = SPI_DMA_BLR;
1579 BLR(drv_data->tx_channel) = SPI_DMA_BLR;
1580 }
1581
1582 /* Load default SPI configuration */
1583 writel(SPI_RESET_START, drv_data->regs + SPI_RESET);
1584 writel(0, drv_data->regs + SPI_RESET);
1585 writel(SPI_DEFAULT_CONTROL, drv_data->regs + SPI_CONTROL);
1586
1587 /* Initial and start queue */
1588 status = init_queue(drv_data);
1589 if (status != 0) {
1590 dev_err(&pdev->dev, "probe - problem initializing queue\n");
1591 goto err_init_queue;
1592 }
1593 status = start_queue(drv_data);
1594 if (status != 0) {
1595 dev_err(&pdev->dev, "probe - problem starting queue\n");
1596 goto err_start_queue;
1597 }
1598
1599 /* Register with the SPI framework */
1600 platform_set_drvdata(pdev, drv_data);
1601 status = spi_register_master(master);
1602 if (status != 0) {
1603 dev_err(&pdev->dev, "probe - problem registering spi master\n");
1604 goto err_spi_register;
1605 }
1606
1607 dev_dbg(dev, "probe succeded\n");
1608 return 0;
1609
1610err_init_queue:
1611err_start_queue:
1612err_spi_register:
1613 destroy_queue(drv_data);
1614
1615err_no_rxdma:
1616err_no_txdma:
1617err_no_devid:
1618 free_irq(irq, drv_data);
1619
1620err_no_irqres:
1621 iounmap(drv_data->regs);
1622
1623err_no_iomap:
1624 release_resource(drv_data->ioarea);
1625 kfree(drv_data->ioarea);
1626
1627err_no_iores:
1628 clk_disable(drv_data->clk);
1629 clk_put(drv_data->clk);
1630
1631err_no_clk:
1632 spi_master_put(master);
1633
1634err_no_pdata:
1635err_no_mem:
1636 return status;
1637}
1638
1639static int __exit spi_imx_remove(struct platform_device *pdev)
1640{
1641 struct driver_data *drv_data = platform_get_drvdata(pdev);
1642 int irq;
1643 int status = 0;
1644
1645 if (!drv_data)
1646 return 0;
1647
1648 tasklet_kill(&drv_data->pump_transfers);
1649
1650 /* Remove the queue */
1651 status = destroy_queue(drv_data);
1652 if (status != 0) {
1653 dev_err(&pdev->dev, "queue remove failed (%d)\n", status);
1654 return status;
1655 }
1656
1657 /* Reset SPI */
1658 writel(SPI_RESET_START, drv_data->regs + SPI_RESET);
1659 writel(0, drv_data->regs + SPI_RESET);
1660
1661 /* Release DMA */
1662 if (drv_data->master_info->enable_dma) {
1663 RSSR(drv_data->rx_channel) = 0;
1664 RSSR(drv_data->tx_channel) = 0;
1665 imx_dma_free(drv_data->tx_channel);
1666 imx_dma_free(drv_data->rx_channel);
1667 }
1668
1669 /* Release IRQ */
1670 irq = platform_get_irq(pdev, 0);
1671 if (irq >= 0)
1672 free_irq(irq, drv_data);
1673
1674 clk_disable(drv_data->clk);
1675 clk_put(drv_data->clk);
1676
1677 /* Release map resources */
1678 iounmap(drv_data->regs);
1679 release_resource(drv_data->ioarea);
1680 kfree(drv_data->ioarea);
1681
1682 /* Disconnect from the SPI framework */
1683 spi_unregister_master(drv_data->master);
1684 spi_master_put(drv_data->master);
1685
1686 /* Prevent double remove */
1687 platform_set_drvdata(pdev, NULL);
1688
1689 dev_dbg(&pdev->dev, "remove succeded\n");
1690
1691 return 0;
1692}
1693
1694static void spi_imx_shutdown(struct platform_device *pdev)
1695{
1696 struct driver_data *drv_data = platform_get_drvdata(pdev);
1697
1698 /* Reset SPI */
1699 writel(SPI_RESET_START, drv_data->regs + SPI_RESET);
1700 writel(0, drv_data->regs + SPI_RESET);
1701
1702 dev_dbg(&pdev->dev, "shutdown succeded\n");
1703}
1704
1705#ifdef CONFIG_PM
1706
1707static int spi_imx_suspend(struct platform_device *pdev, pm_message_t state)
1708{
1709 struct driver_data *drv_data = platform_get_drvdata(pdev);
1710 int status = 0;
1711
1712 status = stop_queue(drv_data);
1713 if (status != 0) {
1714 dev_warn(&pdev->dev, "suspend cannot stop queue\n");
1715 return status;
1716 }
1717
1718 dev_dbg(&pdev->dev, "suspended\n");
1719
1720 return 0;
1721}
1722
1723static int spi_imx_resume(struct platform_device *pdev)
1724{
1725 struct driver_data *drv_data = platform_get_drvdata(pdev);
1726 int status = 0;
1727
1728 /* Start the queue running */
1729 status = start_queue(drv_data);
1730 if (status != 0)
1731 dev_err(&pdev->dev, "problem starting queue (%d)\n", status);
1732 else
1733 dev_dbg(&pdev->dev, "resumed\n");
1734
1735 return status;
1736}
1737#else
1738#define spi_imx_suspend NULL
1739#define spi_imx_resume NULL
1740#endif /* CONFIG_PM */
1741
1742/* work with hotplug and coldplug */
1743MODULE_ALIAS("platform:spi_imx");
1744
1745static struct platform_driver driver = {
1746 .driver = {
1747 .name = "spi_imx",
1748 .owner = THIS_MODULE,
1749 },
1750 .remove = __exit_p(spi_imx_remove),
1751 .shutdown = spi_imx_shutdown,
1752 .suspend = spi_imx_suspend,
1753 .resume = spi_imx_resume,
1754};
1755
1756static int __init spi_imx_init(void)
1757{
1758 return platform_driver_probe(&driver, spi_imx_probe);
1759}
1760module_init(spi_imx_init);
1761
1762static void __exit spi_imx_exit(void)
1763{
1764 platform_driver_unregister(&driver);
1765}
1766module_exit(spi_imx_exit);
1767
1768MODULE_AUTHOR("Andrea Paterniani, <a.paterniani@swapp-eng.it>");
1769MODULE_DESCRIPTION("iMX SPI Controller Driver");
1770MODULE_LICENSE("GPL");
diff --git a/drivers/spi/spi_ppc4xx.c b/drivers/spi/spi_ppc4xx.c
new file mode 100644
index 000000000000..140a18d6cf3e
--- /dev/null
+++ b/drivers/spi/spi_ppc4xx.c
@@ -0,0 +1,612 @@
1/*
2 * SPI_PPC4XX SPI controller driver.
3 *
4 * Copyright (C) 2007 Gary Jennejohn <garyj@denx.de>
5 * Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
6 * Copyright 2009 Harris Corporation, Steven A. Falco <sfalco@harris.com>
7 *
8 * Based in part on drivers/spi/spi_s3c24xx.c
9 *
10 * Copyright (c) 2006 Ben Dooks
11 * Copyright (c) 2006 Simtec Electronics
12 * Ben Dooks <ben@simtec.co.uk>
13 *
14 * This program is free software; you can redistribute it and/or modify it
15 * under the terms of the GNU General Public License version 2 as published
16 * by the Free Software Foundation.
17 */
18
19/*
20 * The PPC4xx SPI controller has no FIFO so each sent/received byte will
21 * generate an interrupt to the CPU. This can cause high CPU utilization.
22 * This driver allows platforms to reduce the interrupt load on the CPU
23 * during SPI transfers by setting max_speed_hz via the device tree.
24 */
25
26#include <linux/module.h>
27#include <linux/init.h>
28#include <linux/sched.h>
29#include <linux/errno.h>
30#include <linux/wait.h>
31#include <linux/of_platform.h>
32#include <linux/of_spi.h>
33#include <linux/of_gpio.h>
34#include <linux/interrupt.h>
35#include <linux/delay.h>
36
37#include <linux/gpio.h>
38#include <linux/spi/spi.h>
39#include <linux/spi/spi_bitbang.h>
40
41#include <asm/io.h>
42#include <asm/dcr.h>
43#include <asm/dcr-regs.h>
44
45/* bits in mode register - bit 0 is MSb */
46
47/*
48 * SPI_PPC4XX_MODE_SCP = 0 means "data latched on trailing edge of clock"
49 * SPI_PPC4XX_MODE_SCP = 1 means "data latched on leading edge of clock"
50 * Note: This is the inverse of CPHA.
51 */
52#define SPI_PPC4XX_MODE_SCP (0x80 >> 3)
53
54/* SPI_PPC4XX_MODE_SPE = 1 means "port enabled" */
55#define SPI_PPC4XX_MODE_SPE (0x80 >> 4)
56
57/*
58 * SPI_PPC4XX_MODE_RD = 0 means "MSB first" - this is the normal mode
59 * SPI_PPC4XX_MODE_RD = 1 means "LSB first" - this is bit-reversed mode
60 * Note: This is identical to SPI_LSB_FIRST.
61 */
62#define SPI_PPC4XX_MODE_RD (0x80 >> 5)
63
64/*
65 * SPI_PPC4XX_MODE_CI = 0 means "clock idles low"
66 * SPI_PPC4XX_MODE_CI = 1 means "clock idles high"
67 * Note: This is identical to CPOL.
68 */
69#define SPI_PPC4XX_MODE_CI (0x80 >> 6)
70
71/*
72 * SPI_PPC4XX_MODE_IL = 0 means "loopback disable"
73 * SPI_PPC4XX_MODE_IL = 1 means "loopback enable"
74 */
75#define SPI_PPC4XX_MODE_IL (0x80 >> 7)
76
77/* bits in control register */
78/* starts a transfer when set */
79#define SPI_PPC4XX_CR_STR (0x80 >> 7)
80
81/* bits in status register */
82/* port is busy with a transfer */
83#define SPI_PPC4XX_SR_BSY (0x80 >> 6)
84/* RxD ready */
85#define SPI_PPC4XX_SR_RBR (0x80 >> 7)
86
87/* clock settings (SCP and CI) for various SPI modes */
88#define SPI_CLK_MODE0 (SPI_PPC4XX_MODE_SCP | 0)
89#define SPI_CLK_MODE1 (0 | 0)
90#define SPI_CLK_MODE2 (SPI_PPC4XX_MODE_SCP | SPI_PPC4XX_MODE_CI)
91#define SPI_CLK_MODE3 (0 | SPI_PPC4XX_MODE_CI)
92
93#define DRIVER_NAME "spi_ppc4xx_of"
94
95struct spi_ppc4xx_regs {
96 u8 mode;
97 u8 rxd;
98 u8 txd;
99 u8 cr;
100 u8 sr;
101 u8 dummy;
102 /*
103 * Clock divisor modulus register
104 * This uses the follwing formula:
105 * SCPClkOut = OPBCLK/(4(CDM + 1))
106 * or
107 * CDM = (OPBCLK/4*SCPClkOut) - 1
108 * bit 0 is the MSb!
109 */
110 u8 cdm;
111};
112
113/* SPI Controller driver's private data. */
114struct ppc4xx_spi {
115 /* bitbang has to be first */
116 struct spi_bitbang bitbang;
117 struct completion done;
118
119 u64 mapbase;
120 u64 mapsize;
121 int irqnum;
122 /* need this to set the SPI clock */
123 unsigned int opb_freq;
124
125 /* for transfers */
126 int len;
127 int count;
128 /* data buffers */
129 const unsigned char *tx;
130 unsigned char *rx;
131
132 int *gpios;
133
134 struct spi_ppc4xx_regs __iomem *regs; /* pointer to the registers */
135 struct spi_master *master;
136 struct device *dev;
137};
138
139/* need this so we can set the clock in the chipselect routine */
140struct spi_ppc4xx_cs {
141 u8 mode;
142};
143
144static int spi_ppc4xx_txrx(struct spi_device *spi, struct spi_transfer *t)
145{
146 struct ppc4xx_spi *hw;
147 u8 data;
148
149 dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n",
150 t->tx_buf, t->rx_buf, t->len);
151
152 hw = spi_master_get_devdata(spi->master);
153
154 hw->tx = t->tx_buf;
155 hw->rx = t->rx_buf;
156 hw->len = t->len;
157 hw->count = 0;
158
159 /* send the first byte */
160 data = hw->tx ? hw->tx[0] : 0;
161 out_8(&hw->regs->txd, data);
162 out_8(&hw->regs->cr, SPI_PPC4XX_CR_STR);
163 wait_for_completion(&hw->done);
164
165 return hw->count;
166}
167
168static int spi_ppc4xx_setupxfer(struct spi_device *spi, struct spi_transfer *t)
169{
170 struct ppc4xx_spi *hw = spi_master_get_devdata(spi->master);
171 struct spi_ppc4xx_cs *cs = spi->controller_state;
172 int scr;
173 u8 cdm = 0;
174 u32 speed;
175 u8 bits_per_word;
176
177 /* Start with the generic configuration for this device. */
178 bits_per_word = spi->bits_per_word;
179 speed = spi->max_speed_hz;
180
181 /*
182 * Modify the configuration if the transfer overrides it. Do not allow
183 * the transfer to overwrite the generic configuration with zeros.
184 */
185 if (t) {
186 if (t->bits_per_word)
187 bits_per_word = t->bits_per_word;
188
189 if (t->speed_hz)
190 speed = min(t->speed_hz, spi->max_speed_hz);
191 }
192
193 if (bits_per_word != 8) {
194 dev_err(&spi->dev, "invalid bits-per-word (%d)\n",
195 bits_per_word);
196 return -EINVAL;
197 }
198
199 if (!speed || (speed > spi->max_speed_hz)) {
200 dev_err(&spi->dev, "invalid speed_hz (%d)\n", speed);
201 return -EINVAL;
202 }
203
204 /* Write new configration */
205 out_8(&hw->regs->mode, cs->mode);
206
207 /* Set the clock */
208 /* opb_freq was already divided by 4 */
209 scr = (hw->opb_freq / speed) - 1;
210 if (scr > 0)
211 cdm = min(scr, 0xff);
212
213 dev_dbg(&spi->dev, "setting pre-scaler to %d (hz %d)\n", cdm, speed);
214
215 if (in_8(&hw->regs->cdm) != cdm)
216 out_8(&hw->regs->cdm, cdm);
217
218 spin_lock(&hw->bitbang.lock);
219 if (!hw->bitbang.busy) {
220 hw->bitbang.chipselect(spi, BITBANG_CS_INACTIVE);
221 /* Need to ndelay here? */
222 }
223 spin_unlock(&hw->bitbang.lock);
224
225 return 0;
226}
227
228static int spi_ppc4xx_setup(struct spi_device *spi)
229{
230 struct spi_ppc4xx_cs *cs = spi->controller_state;
231
232 if (spi->bits_per_word != 8) {
233 dev_err(&spi->dev, "invalid bits-per-word (%d)\n",
234 spi->bits_per_word);
235 return -EINVAL;
236 }
237
238 if (!spi->max_speed_hz) {
239 dev_err(&spi->dev, "invalid max_speed_hz (must be non-zero)\n");
240 return -EINVAL;
241 }
242
243 if (cs == NULL) {
244 cs = kzalloc(sizeof *cs, GFP_KERNEL);
245 if (!cs)
246 return -ENOMEM;
247 spi->controller_state = cs;
248 }
249
250 /*
251 * We set all bits of the SPI0_MODE register, so,
252 * no need to read-modify-write
253 */
254 cs->mode = SPI_PPC4XX_MODE_SPE;
255
256 switch (spi->mode & (SPI_CPHA | SPI_CPOL)) {
257 case SPI_MODE_0:
258 cs->mode |= SPI_CLK_MODE0;
259 break;
260 case SPI_MODE_1:
261 cs->mode |= SPI_CLK_MODE1;
262 break;
263 case SPI_MODE_2:
264 cs->mode |= SPI_CLK_MODE2;
265 break;
266 case SPI_MODE_3:
267 cs->mode |= SPI_CLK_MODE3;
268 break;
269 }
270
271 if (spi->mode & SPI_LSB_FIRST)
272 cs->mode |= SPI_PPC4XX_MODE_RD;
273
274 return 0;
275}
276
277static void spi_ppc4xx_chipsel(struct spi_device *spi, int value)
278{
279 struct ppc4xx_spi *hw = spi_master_get_devdata(spi->master);
280 unsigned int cs = spi->chip_select;
281 unsigned int cspol;
282
283 /*
284 * If there are no chip selects at all, or if this is the special
285 * case of a non-existent (dummy) chip select, do nothing.
286 */
287
288 if (!hw->master->num_chipselect || hw->gpios[cs] == -EEXIST)
289 return;
290
291 cspol = spi->mode & SPI_CS_HIGH ? 1 : 0;
292 if (value == BITBANG_CS_INACTIVE)
293 cspol = !cspol;
294
295 gpio_set_value(hw->gpios[cs], cspol);
296}
297
298static irqreturn_t spi_ppc4xx_int(int irq, void *dev_id)
299{
300 struct ppc4xx_spi *hw;
301 u8 status;
302 u8 data;
303 unsigned int count;
304
305 hw = (struct ppc4xx_spi *)dev_id;
306
307 status = in_8(&hw->regs->sr);
308 if (!status)
309 return IRQ_NONE;
310
311 /*
312 * BSY de-asserts one cycle after the transfer is complete. The
313 * interrupt is asserted after the transfer is complete. The exact
314 * relationship is not documented, hence this code.
315 */
316
317 if (unlikely(status & SPI_PPC4XX_SR_BSY)) {
318 u8 lstatus;
319 int cnt = 0;
320
321 dev_dbg(hw->dev, "got interrupt but spi still busy?\n");
322 do {
323 ndelay(10);
324 lstatus = in_8(&hw->regs->sr);
325 } while (++cnt < 100 && lstatus & SPI_PPC4XX_SR_BSY);
326
327 if (cnt >= 100) {
328 dev_err(hw->dev, "busywait: too many loops!\n");
329 complete(&hw->done);
330 return IRQ_HANDLED;
331 } else {
332 /* status is always 1 (RBR) here */
333 status = in_8(&hw->regs->sr);
334 dev_dbg(hw->dev, "loops %d status %x\n", cnt, status);
335 }
336 }
337
338 count = hw->count;
339 hw->count++;
340
341 /* RBR triggered this interrupt. Therefore, data must be ready. */
342 data = in_8(&hw->regs->rxd);
343 if (hw->rx)
344 hw->rx[count] = data;
345
346 count++;
347
348 if (count < hw->len) {
349 data = hw->tx ? hw->tx[count] : 0;
350 out_8(&hw->regs->txd, data);
351 out_8(&hw->regs->cr, SPI_PPC4XX_CR_STR);
352 } else {
353 complete(&hw->done);
354 }
355
356 return IRQ_HANDLED;
357}
358
359static void spi_ppc4xx_cleanup(struct spi_device *spi)
360{
361 kfree(spi->controller_state);
362}
363
364static void spi_ppc4xx_enable(struct ppc4xx_spi *hw)
365{
366 /*
367 * On all 4xx PPC's the SPI bus is shared/multiplexed with
368 * the 2nd I2C bus. We need to enable the the SPI bus before
369 * using it.
370 */
371
372 /* need to clear bit 14 to enable SPC */
373 dcri_clrset(SDR0, SDR0_PFC1, 0x80000000 >> 14, 0);
374}
375
376static void free_gpios(struct ppc4xx_spi *hw)
377{
378 if (hw->master->num_chipselect) {
379 int i;
380 for (i = 0; i < hw->master->num_chipselect; i++)
381 if (gpio_is_valid(hw->gpios[i]))
382 gpio_free(hw->gpios[i]);
383
384 kfree(hw->gpios);
385 hw->gpios = NULL;
386 }
387}
388
389/*
390 * of_device layer stuff...
391 */
392static int __init spi_ppc4xx_of_probe(struct of_device *op,
393 const struct of_device_id *match)
394{
395 struct ppc4xx_spi *hw;
396 struct spi_master *master;
397 struct spi_bitbang *bbp;
398 struct resource resource;
399 struct device_node *np = op->node;
400 struct device *dev = &op->dev;
401 struct device_node *opbnp;
402 int ret;
403 int num_gpios;
404 const unsigned int *clk;
405
406 master = spi_alloc_master(dev, sizeof *hw);
407 if (master == NULL)
408 return -ENOMEM;
409 dev_set_drvdata(dev, master);
410 hw = spi_master_get_devdata(master);
411 hw->master = spi_master_get(master);
412 hw->dev = dev;
413
414 init_completion(&hw->done);
415
416 /*
417 * A count of zero implies a single SPI device without any chip-select.
418 * Note that of_gpio_count counts all gpios assigned to this spi master.
419 * This includes both "null" gpio's and real ones.
420 */
421 num_gpios = of_gpio_count(np);
422 if (num_gpios) {
423 int i;
424
425 hw->gpios = kzalloc(sizeof(int) * num_gpios, GFP_KERNEL);
426 if (!hw->gpios) {
427 ret = -ENOMEM;
428 goto free_master;
429 }
430
431 for (i = 0; i < num_gpios; i++) {
432 int gpio;
433 enum of_gpio_flags flags;
434
435 gpio = of_get_gpio_flags(np, i, &flags);
436 hw->gpios[i] = gpio;
437
438 if (gpio_is_valid(gpio)) {
439 /* Real CS - set the initial state. */
440 ret = gpio_request(gpio, np->name);
441 if (ret < 0) {
442 dev_err(dev, "can't request gpio "
443 "#%d: %d\n", i, ret);
444 goto free_gpios;
445 }
446
447 gpio_direction_output(gpio,
448 !!(flags & OF_GPIO_ACTIVE_LOW));
449 } else if (gpio == -EEXIST) {
450 ; /* No CS, but that's OK. */
451 } else {
452 dev_err(dev, "invalid gpio #%d: %d\n", i, gpio);
453 ret = -EINVAL;
454 goto free_gpios;
455 }
456 }
457 }
458
459 /* Setup the state for the bitbang driver */
460 bbp = &hw->bitbang;
461 bbp->master = hw->master;
462 bbp->setup_transfer = spi_ppc4xx_setupxfer;
463 bbp->chipselect = spi_ppc4xx_chipsel;
464 bbp->txrx_bufs = spi_ppc4xx_txrx;
465 bbp->use_dma = 0;
466 bbp->master->setup = spi_ppc4xx_setup;
467 bbp->master->cleanup = spi_ppc4xx_cleanup;
468
469 /* Allocate bus num dynamically. */
470 bbp->master->bus_num = -1;
471
472 /* the spi->mode bits understood by this driver: */
473 bbp->master->mode_bits =
474 SPI_CPHA | SPI_CPOL | SPI_CS_HIGH | SPI_LSB_FIRST;
475
476 /* this many pins in all GPIO controllers */
477 bbp->master->num_chipselect = num_gpios;
478
479 /* Get the clock for the OPB */
480 opbnp = of_find_compatible_node(NULL, NULL, "ibm,opb");
481 if (opbnp == NULL) {
482 dev_err(dev, "OPB: cannot find node\n");
483 ret = -ENODEV;
484 goto free_gpios;
485 }
486 /* Get the clock (Hz) for the OPB */
487 clk = of_get_property(opbnp, "clock-frequency", NULL);
488 if (clk == NULL) {
489 dev_err(dev, "OPB: no clock-frequency property set\n");
490 of_node_put(opbnp);
491 ret = -ENODEV;
492 goto free_gpios;
493 }
494 hw->opb_freq = *clk;
495 hw->opb_freq >>= 2;
496 of_node_put(opbnp);
497
498 ret = of_address_to_resource(np, 0, &resource);
499 if (ret) {
500 dev_err(dev, "error while parsing device node resource\n");
501 goto free_gpios;
502 }
503 hw->mapbase = resource.start;
504 hw->mapsize = resource.end - resource.start + 1;
505
506 /* Sanity check */
507 if (hw->mapsize < sizeof(struct spi_ppc4xx_regs)) {
508 dev_err(dev, "too small to map registers\n");
509 ret = -EINVAL;
510 goto free_gpios;
511 }
512
513 /* Request IRQ */
514 hw->irqnum = irq_of_parse_and_map(np, 0);
515 ret = request_irq(hw->irqnum, spi_ppc4xx_int,
516 IRQF_DISABLED, "spi_ppc4xx_of", (void *)hw);
517 if (ret) {
518 dev_err(dev, "unable to allocate interrupt\n");
519 goto free_gpios;
520 }
521
522 if (!request_mem_region(hw->mapbase, hw->mapsize, DRIVER_NAME)) {
523 dev_err(dev, "resource unavailable\n");
524 ret = -EBUSY;
525 goto request_mem_error;
526 }
527
528 hw->regs = ioremap(hw->mapbase, sizeof(struct spi_ppc4xx_regs));
529
530 if (!hw->regs) {
531 dev_err(dev, "unable to memory map registers\n");
532 ret = -ENXIO;
533 goto map_io_error;
534 }
535
536 spi_ppc4xx_enable(hw);
537
538 /* Finally register our spi controller */
539 dev->dma_mask = 0;
540 ret = spi_bitbang_start(bbp);
541 if (ret) {
542 dev_err(dev, "failed to register SPI master\n");
543 goto unmap_regs;
544 }
545
546 dev_info(dev, "driver initialized\n");
547 of_register_spi_devices(master, np);
548
549 return 0;
550
551unmap_regs:
552 iounmap(hw->regs);
553map_io_error:
554 release_mem_region(hw->mapbase, hw->mapsize);
555request_mem_error:
556 free_irq(hw->irqnum, hw);
557free_gpios:
558 free_gpios(hw);
559free_master:
560 dev_set_drvdata(dev, NULL);
561 spi_master_put(master);
562
563 dev_err(dev, "initialization failed\n");
564 return ret;
565}
566
567static int __exit spi_ppc4xx_of_remove(struct of_device *op)
568{
569 struct spi_master *master = dev_get_drvdata(&op->dev);
570 struct ppc4xx_spi *hw = spi_master_get_devdata(master);
571
572 spi_bitbang_stop(&hw->bitbang);
573 dev_set_drvdata(&op->dev, NULL);
574 release_mem_region(hw->mapbase, hw->mapsize);
575 free_irq(hw->irqnum, hw);
576 iounmap(hw->regs);
577 free_gpios(hw);
578 return 0;
579}
580
581static struct of_device_id spi_ppc4xx_of_match[] = {
582 { .compatible = "ibm,ppc4xx-spi", },
583 {},
584};
585
586MODULE_DEVICE_TABLE(of, spi_ppc4xx_of_match);
587
588static struct of_platform_driver spi_ppc4xx_of_driver = {
589 .match_table = spi_ppc4xx_of_match,
590 .probe = spi_ppc4xx_of_probe,
591 .remove = __exit_p(spi_ppc4xx_of_remove),
592 .driver = {
593 .name = DRIVER_NAME,
594 .owner = THIS_MODULE,
595 },
596};
597
598static int __init spi_ppc4xx_init(void)
599{
600 return of_register_platform_driver(&spi_ppc4xx_of_driver);
601}
602module_init(spi_ppc4xx_init);
603
604static void __exit spi_ppc4xx_exit(void)
605{
606 of_unregister_platform_driver(&spi_ppc4xx_of_driver);
607}
608module_exit(spi_ppc4xx_exit);
609
610MODULE_AUTHOR("Gary Jennejohn & Stefan Roese");
611MODULE_DESCRIPTION("Simple PPC4xx SPI Driver");
612MODULE_LICENSE("GPL");
diff --git a/drivers/spi/spi_s3c24xx.c b/drivers/spi/spi_s3c24xx.c
index 3f3119d760db..33d94f76b9ef 100644
--- a/drivers/spi/spi_s3c24xx.c
+++ b/drivers/spi/spi_s3c24xx.c
@@ -20,17 +20,28 @@
20#include <linux/clk.h> 20#include <linux/clk.h>
21#include <linux/platform_device.h> 21#include <linux/platform_device.h>
22#include <linux/gpio.h> 22#include <linux/gpio.h>
23#include <linux/io.h>
23 24
24#include <linux/spi/spi.h> 25#include <linux/spi/spi.h>
25#include <linux/spi/spi_bitbang.h> 26#include <linux/spi/spi_bitbang.h>
26 27
27#include <asm/io.h>
28#include <asm/dma.h>
29#include <mach/hardware.h>
30
31#include <plat/regs-spi.h> 28#include <plat/regs-spi.h>
32#include <mach/spi.h> 29#include <mach/spi.h>
33 30
31/**
32 * s3c24xx_spi_devstate - per device data
33 * @hz: Last frequency calculated for @sppre field.
34 * @mode: Last mode setting for the @spcon field.
35 * @spcon: Value to write to the SPCON register.
36 * @sppre: Value to write to the SPPRE register.
37 */
38struct s3c24xx_spi_devstate {
39 unsigned int hz;
40 unsigned int mode;
41 u8 spcon;
42 u8 sppre;
43};
44
34struct s3c24xx_spi { 45struct s3c24xx_spi {
35 /* bitbang has to be first */ 46 /* bitbang has to be first */
36 struct spi_bitbang bitbang; 47 struct spi_bitbang bitbang;
@@ -71,43 +82,31 @@ static void s3c24xx_spi_gpiocs(struct s3c2410_spi_info *spi, int cs, int pol)
71 82
72static void s3c24xx_spi_chipsel(struct spi_device *spi, int value) 83static void s3c24xx_spi_chipsel(struct spi_device *spi, int value)
73{ 84{
85 struct s3c24xx_spi_devstate *cs = spi->controller_state;
74 struct s3c24xx_spi *hw = to_hw(spi); 86 struct s3c24xx_spi *hw = to_hw(spi);
75 unsigned int cspol = spi->mode & SPI_CS_HIGH ? 1 : 0; 87 unsigned int cspol = spi->mode & SPI_CS_HIGH ? 1 : 0;
76 unsigned int spcon; 88
89 /* change the chipselect state and the state of the spi engine clock */
77 90
78 switch (value) { 91 switch (value) {
79 case BITBANG_CS_INACTIVE: 92 case BITBANG_CS_INACTIVE:
80 hw->set_cs(hw->pdata, spi->chip_select, cspol^1); 93 hw->set_cs(hw->pdata, spi->chip_select, cspol^1);
94 writeb(cs->spcon, hw->regs + S3C2410_SPCON);
81 break; 95 break;
82 96
83 case BITBANG_CS_ACTIVE: 97 case BITBANG_CS_ACTIVE:
84 spcon = readb(hw->regs + S3C2410_SPCON); 98 writeb(cs->spcon | S3C2410_SPCON_ENSCK,
85 99 hw->regs + S3C2410_SPCON);
86 if (spi->mode & SPI_CPHA)
87 spcon |= S3C2410_SPCON_CPHA_FMTB;
88 else
89 spcon &= ~S3C2410_SPCON_CPHA_FMTB;
90
91 if (spi->mode & SPI_CPOL)
92 spcon |= S3C2410_SPCON_CPOL_HIGH;
93 else
94 spcon &= ~S3C2410_SPCON_CPOL_HIGH;
95
96 spcon |= S3C2410_SPCON_ENSCK;
97
98 /* write new configration */
99
100 writeb(spcon, hw->regs + S3C2410_SPCON);
101 hw->set_cs(hw->pdata, spi->chip_select, cspol); 100 hw->set_cs(hw->pdata, spi->chip_select, cspol);
102
103 break; 101 break;
104 } 102 }
105} 103}
106 104
107static int s3c24xx_spi_setupxfer(struct spi_device *spi, 105static int s3c24xx_spi_update_state(struct spi_device *spi,
108 struct spi_transfer *t) 106 struct spi_transfer *t)
109{ 107{
110 struct s3c24xx_spi *hw = to_hw(spi); 108 struct s3c24xx_spi *hw = to_hw(spi);
109 struct s3c24xx_spi_devstate *cs = spi->controller_state;
111 unsigned int bpw; 110 unsigned int bpw;
112 unsigned int hz; 111 unsigned int hz;
113 unsigned int div; 112 unsigned int div;
@@ -127,41 +126,89 @@ static int s3c24xx_spi_setupxfer(struct spi_device *spi,
127 return -EINVAL; 126 return -EINVAL;
128 } 127 }
129 128
130 clk = clk_get_rate(hw->clk); 129 if (spi->mode != cs->mode) {
131 div = DIV_ROUND_UP(clk, hz * 2) - 1; 130 u8 spcon = SPCON_DEFAULT;
132 131
133 if (div > 255) 132 if (spi->mode & SPI_CPHA)
134 div = 255; 133 spcon |= S3C2410_SPCON_CPHA_FMTB;
135 134
136 dev_dbg(&spi->dev, "setting pre-scaler to %d (wanted %d, got %ld)\n", 135 if (spi->mode & SPI_CPOL)
137 div, hz, clk / (2 * (div + 1))); 136 spcon |= S3C2410_SPCON_CPOL_HIGH;
138 137
138 cs->mode = spi->mode;
139 cs->spcon = spcon;
140 }
139 141
140 writeb(div, hw->regs + S3C2410_SPPRE); 142 if (cs->hz != hz) {
143 clk = clk_get_rate(hw->clk);
144 div = DIV_ROUND_UP(clk, hz * 2) - 1;
141 145
142 spin_lock(&hw->bitbang.lock); 146 if (div > 255)
143 if (!hw->bitbang.busy) { 147 div = 255;
144 hw->bitbang.chipselect(spi, BITBANG_CS_INACTIVE); 148
145 /* need to ndelay for 0.5 clocktick ? */ 149 dev_dbg(&spi->dev, "pre-scaler=%d (wanted %d, got %ld)\n",
150 div, hz, clk / (2 * (div + 1)));
151
152 cs->hz = hz;
153 cs->sppre = div;
146 } 154 }
147 spin_unlock(&hw->bitbang.lock);
148 155
149 return 0; 156 return 0;
150} 157}
151 158
159static int s3c24xx_spi_setupxfer(struct spi_device *spi,
160 struct spi_transfer *t)
161{
162 struct s3c24xx_spi_devstate *cs = spi->controller_state;
163 struct s3c24xx_spi *hw = to_hw(spi);
164 int ret;
165
166 ret = s3c24xx_spi_update_state(spi, t);
167 if (!ret)
168 writeb(cs->sppre, hw->regs + S3C2410_SPPRE);
169
170 return ret;
171}
172
152static int s3c24xx_spi_setup(struct spi_device *spi) 173static int s3c24xx_spi_setup(struct spi_device *spi)
153{ 174{
175 struct s3c24xx_spi_devstate *cs = spi->controller_state;
176 struct s3c24xx_spi *hw = to_hw(spi);
154 int ret; 177 int ret;
155 178
156 ret = s3c24xx_spi_setupxfer(spi, NULL); 179 /* allocate settings on the first call */
157 if (ret < 0) { 180 if (!cs) {
158 dev_err(&spi->dev, "setupxfer returned %d\n", ret); 181 cs = kzalloc(sizeof(struct s3c24xx_spi_devstate), GFP_KERNEL);
182 if (!cs) {
183 dev_err(&spi->dev, "no memory for controller state\n");
184 return -ENOMEM;
185 }
186
187 cs->spcon = SPCON_DEFAULT;
188 cs->hz = -1;
189 spi->controller_state = cs;
190 }
191
192 /* initialise the state from the device */
193 ret = s3c24xx_spi_update_state(spi, NULL);
194 if (ret)
159 return ret; 195 return ret;
196
197 spin_lock(&hw->bitbang.lock);
198 if (!hw->bitbang.busy) {
199 hw->bitbang.chipselect(spi, BITBANG_CS_INACTIVE);
200 /* need to ndelay for 0.5 clocktick ? */
160 } 201 }
202 spin_unlock(&hw->bitbang.lock);
161 203
162 return 0; 204 return 0;
163} 205}
164 206
207static void s3c24xx_spi_cleanup(struct spi_device *spi)
208{
209 kfree(spi->controller_state);
210}
211
165static inline unsigned int hw_txbyte(struct s3c24xx_spi *hw, int count) 212static inline unsigned int hw_txbyte(struct s3c24xx_spi *hw, int count)
166{ 213{
167 return hw->tx ? hw->tx[count] : 0; 214 return hw->tx ? hw->tx[count] : 0;
@@ -289,7 +336,9 @@ static int __init s3c24xx_spi_probe(struct platform_device *pdev)
289 hw->bitbang.setup_transfer = s3c24xx_spi_setupxfer; 336 hw->bitbang.setup_transfer = s3c24xx_spi_setupxfer;
290 hw->bitbang.chipselect = s3c24xx_spi_chipsel; 337 hw->bitbang.chipselect = s3c24xx_spi_chipsel;
291 hw->bitbang.txrx_bufs = s3c24xx_spi_txrx; 338 hw->bitbang.txrx_bufs = s3c24xx_spi_txrx;
292 hw->bitbang.master->setup = s3c24xx_spi_setup; 339
340 hw->master->setup = s3c24xx_spi_setup;
341 hw->master->cleanup = s3c24xx_spi_cleanup;
293 342
294 dev_dbg(hw->dev, "bitbang at %p\n", &hw->bitbang); 343 dev_dbg(hw->dev, "bitbang at %p\n", &hw->bitbang);
295 344
@@ -302,7 +351,7 @@ static int __init s3c24xx_spi_probe(struct platform_device *pdev)
302 goto err_no_iores; 351 goto err_no_iores;
303 } 352 }
304 353
305 hw->ioarea = request_mem_region(res->start, (res->end - res->start)+1, 354 hw->ioarea = request_mem_region(res->start, resource_size(res),
306 pdev->name); 355 pdev->name);
307 356
308 if (hw->ioarea == NULL) { 357 if (hw->ioarea == NULL) {
@@ -311,7 +360,7 @@ static int __init s3c24xx_spi_probe(struct platform_device *pdev)
311 goto err_no_iores; 360 goto err_no_iores;
312 } 361 }
313 362
314 hw->regs = ioremap(res->start, (res->end - res->start)+1); 363 hw->regs = ioremap(res->start, resource_size(res));
315 if (hw->regs == NULL) { 364 if (hw->regs == NULL) {
316 dev_err(&pdev->dev, "Cannot map IO\n"); 365 dev_err(&pdev->dev, "Cannot map IO\n");
317 err = -ENXIO; 366 err = -ENXIO;
@@ -388,7 +437,7 @@ static int __init s3c24xx_spi_probe(struct platform_device *pdev)
388 437
389 err_no_iores: 438 err_no_iores:
390 err_no_pdata: 439 err_no_pdata:
391 spi_master_put(hw->master);; 440 spi_master_put(hw->master);
392 441
393 err_nomem: 442 err_nomem:
394 return err; 443 return err;
@@ -421,9 +470,9 @@ static int __exit s3c24xx_spi_remove(struct platform_device *dev)
421 470
422#ifdef CONFIG_PM 471#ifdef CONFIG_PM
423 472
424static int s3c24xx_spi_suspend(struct platform_device *pdev, pm_message_t msg) 473static int s3c24xx_spi_suspend(struct device *dev)
425{ 474{
426 struct s3c24xx_spi *hw = platform_get_drvdata(pdev); 475 struct s3c24xx_spi *hw = platform_get_drvdata(to_platform_device(dev));
427 476
428 if (hw->pdata && hw->pdata->gpio_setup) 477 if (hw->pdata && hw->pdata->gpio_setup)
429 hw->pdata->gpio_setup(hw->pdata, 0); 478 hw->pdata->gpio_setup(hw->pdata, 0);
@@ -432,27 +481,31 @@ static int s3c24xx_spi_suspend(struct platform_device *pdev, pm_message_t msg)
432 return 0; 481 return 0;
433} 482}
434 483
435static int s3c24xx_spi_resume(struct platform_device *pdev) 484static int s3c24xx_spi_resume(struct device *dev)
436{ 485{
437 struct s3c24xx_spi *hw = platform_get_drvdata(pdev); 486 struct s3c24xx_spi *hw = platform_get_drvdata(to_platform_device(dev));
438 487
439 s3c24xx_spi_initialsetup(hw); 488 s3c24xx_spi_initialsetup(hw);
440 return 0; 489 return 0;
441} 490}
442 491
492static struct dev_pm_ops s3c24xx_spi_pmops = {
493 .suspend = s3c24xx_spi_suspend,
494 .resume = s3c24xx_spi_resume,
495};
496
497#define S3C24XX_SPI_PMOPS &s3c24xx_spi_pmops
443#else 498#else
444#define s3c24xx_spi_suspend NULL 499#define S3C24XX_SPI_PMOPS NULL
445#define s3c24xx_spi_resume NULL 500#endif /* CONFIG_PM */
446#endif
447 501
448MODULE_ALIAS("platform:s3c2410-spi"); 502MODULE_ALIAS("platform:s3c2410-spi");
449static struct platform_driver s3c24xx_spi_driver = { 503static struct platform_driver s3c24xx_spi_driver = {
450 .remove = __exit_p(s3c24xx_spi_remove), 504 .remove = __exit_p(s3c24xx_spi_remove),
451 .suspend = s3c24xx_spi_suspend,
452 .resume = s3c24xx_spi_resume,
453 .driver = { 505 .driver = {
454 .name = "s3c2410-spi", 506 .name = "s3c2410-spi",
455 .owner = THIS_MODULE, 507 .owner = THIS_MODULE,
508 .pm = S3C24XX_SPI_PMOPS,
456 }, 509 },
457}; 510};
458 511
diff --git a/drivers/spi/spi_stmp.c b/drivers/spi/spi_stmp.c
new file mode 100644
index 000000000000..d871dc23909c
--- /dev/null
+++ b/drivers/spi/spi_stmp.c
@@ -0,0 +1,679 @@
1/*
2 * Freescale STMP378X SPI master driver
3 *
4 * Author: dmitry pervushin <dimka@embeddedalley.com>
5 *
6 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 */
9
10/*
11 * The code contained herein is licensed under the GNU General Public
12 * License. You may obtain a copy of the GNU General Public License
13 * Version 2 or later at the following locations:
14 *
15 * http://www.opensource.org/licenses/gpl-license.html
16 * http://www.gnu.org/copyleft/gpl.html
17 */
18#include <linux/module.h>
19#include <linux/init.h>
20#include <linux/interrupt.h>
21#include <linux/platform_device.h>
22#include <linux/spi/spi.h>
23#include <linux/err.h>
24#include <linux/clk.h>
25#include <linux/io.h>
26#include <linux/dma-mapping.h>
27#include <linux/delay.h>
28
29#include <mach/platform.h>
30#include <mach/stmp3xxx.h>
31#include <mach/dma.h>
32#include <mach/regs-ssp.h>
33#include <mach/regs-apbh.h>
34
35
36/* 0 means DMA mode(recommended, default), !0 - PIO mode */
37static int pio;
38static int clock;
39
40/* default timeout for busy waits is 2 seconds */
41#define STMP_SPI_TIMEOUT (2 * HZ)
42
43struct stmp_spi {
44 int id;
45
46 void * __iomem regs; /* vaddr of the control registers */
47
48 int irq, err_irq;
49 u32 dma;
50 struct stmp3xxx_dma_descriptor d;
51
52 u32 speed_khz;
53 u32 saved_timings;
54 u32 divider;
55
56 struct clk *clk;
57 struct device *master_dev;
58
59 struct work_struct work;
60 struct workqueue_struct *workqueue;
61
62 /* lock protects queue access */
63 spinlock_t lock;
64 struct list_head queue;
65
66 struct completion done;
67};
68
69#define busy_wait(cond) \
70 ({ \
71 unsigned long end_jiffies = jiffies + STMP_SPI_TIMEOUT; \
72 bool succeeded = false; \
73 do { \
74 if (cond) { \
75 succeeded = true; \
76 break; \
77 } \
78 cpu_relax(); \
79 } while (time_before(end_jiffies, jiffies)); \
80 succeeded; \
81 })
82
83/**
84 * stmp_spi_init_hw
85 * Initialize the SSP port
86 */
87static int stmp_spi_init_hw(struct stmp_spi *ss)
88{
89 int err = 0;
90 void *pins = ss->master_dev->platform_data;
91
92 err = stmp3xxx_request_pin_group(pins, dev_name(ss->master_dev));
93 if (err)
94 goto out;
95
96 ss->clk = clk_get(NULL, "ssp");
97 if (IS_ERR(ss->clk)) {
98 err = PTR_ERR(ss->clk);
99 goto out_free_pins;
100 }
101 clk_enable(ss->clk);
102
103 stmp3xxx_reset_block(ss->regs, false);
104 stmp3xxx_dma_reset_channel(ss->dma);
105
106 return 0;
107
108out_free_pins:
109 stmp3xxx_release_pin_group(pins, dev_name(ss->master_dev));
110out:
111 return err;
112}
113
114static void stmp_spi_release_hw(struct stmp_spi *ss)
115{
116 void *pins = ss->master_dev->platform_data;
117
118 if (ss->clk && !IS_ERR(ss->clk)) {
119 clk_disable(ss->clk);
120 clk_put(ss->clk);
121 }
122 stmp3xxx_release_pin_group(pins, dev_name(ss->master_dev));
123}
124
125static int stmp_spi_setup_transfer(struct spi_device *spi,
126 struct spi_transfer *t)
127{
128 u8 bits_per_word;
129 u32 hz;
130 struct stmp_spi *ss = spi_master_get_devdata(spi->master);
131 u16 rate;
132
133 bits_per_word = spi->bits_per_word;
134 if (t && t->bits_per_word)
135 bits_per_word = t->bits_per_word;
136
137 /*
138 * Calculate speed:
139 * - by default, use maximum speed from ssp clk
140 * - if device overrides it, use it
141 * - if transfer specifies other speed, use transfer's one
142 */
143 hz = 1000 * ss->speed_khz / ss->divider;
144 if (spi->max_speed_hz)
145 hz = min(hz, spi->max_speed_hz);
146 if (t && t->speed_hz)
147 hz = min(hz, t->speed_hz);
148
149 if (hz == 0) {
150 dev_err(&spi->dev, "Cannot continue with zero clock\n");
151 return -EINVAL;
152 }
153
154 if (bits_per_word != 8) {
155 dev_err(&spi->dev, "%s, unsupported bits_per_word=%d\n",
156 __func__, bits_per_word);
157 return -EINVAL;
158 }
159
160 dev_dbg(&spi->dev, "Requested clk rate = %uHz, max = %uHz/%d = %uHz\n",
161 hz, ss->speed_khz, ss->divider,
162 ss->speed_khz * 1000 / ss->divider);
163
164 if (ss->speed_khz * 1000 / ss->divider < hz) {
165 dev_err(&spi->dev, "%s, unsupported clock rate %uHz\n",
166 __func__, hz);
167 return -EINVAL;
168 }
169
170 rate = 1000 * ss->speed_khz/ss->divider/hz;
171
172 writel(BF(ss->divider, SSP_TIMING_CLOCK_DIVIDE) |
173 BF(rate - 1, SSP_TIMING_CLOCK_RATE),
174 HW_SSP_TIMING + ss->regs);
175
176 writel(BF(1 /* mode SPI */, SSP_CTRL1_SSP_MODE) |
177 BF(4 /* 8 bits */, SSP_CTRL1_WORD_LENGTH) |
178 ((spi->mode & SPI_CPOL) ? BM_SSP_CTRL1_POLARITY : 0) |
179 ((spi->mode & SPI_CPHA) ? BM_SSP_CTRL1_PHASE : 0) |
180 (pio ? 0 : BM_SSP_CTRL1_DMA_ENABLE),
181 ss->regs + HW_SSP_CTRL1);
182
183 return 0;
184}
185
186static int stmp_spi_setup(struct spi_device *spi)
187{
188 /* spi_setup() does basic checks,
189 * stmp_spi_setup_transfer() does more later
190 */
191 if (spi->bits_per_word != 8) {
192 dev_err(&spi->dev, "%s, unsupported bits_per_word=%d\n",
193 __func__, spi->bits_per_word);
194 return -EINVAL;
195 }
196 return 0;
197}
198
199static inline u32 stmp_spi_cs(unsigned cs)
200{
201 return ((cs & 1) ? BM_SSP_CTRL0_WAIT_FOR_CMD : 0) |
202 ((cs & 2) ? BM_SSP_CTRL0_WAIT_FOR_IRQ : 0);
203}
204
205static int stmp_spi_txrx_dma(struct stmp_spi *ss, int cs,
206 unsigned char *buf, dma_addr_t dma_buf, int len,
207 int first, int last, bool write)
208{
209 u32 c0 = 0;
210 dma_addr_t spi_buf_dma = dma_buf;
211 int status = 0;
212 enum dma_data_direction dir = write ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
213
214 c0 |= (first ? BM_SSP_CTRL0_LOCK_CS : 0);
215 c0 |= (last ? BM_SSP_CTRL0_IGNORE_CRC : 0);
216 c0 |= (write ? 0 : BM_SSP_CTRL0_READ);
217 c0 |= BM_SSP_CTRL0_DATA_XFER;
218
219 c0 |= stmp_spi_cs(cs);
220
221 c0 |= BF(len, SSP_CTRL0_XFER_COUNT);
222
223 if (!dma_buf)
224 spi_buf_dma = dma_map_single(ss->master_dev, buf, len, dir);
225
226 ss->d.command->cmd =
227 BF(len, APBH_CHn_CMD_XFER_COUNT) |
228 BF(1, APBH_CHn_CMD_CMDWORDS) |
229 BM_APBH_CHn_CMD_WAIT4ENDCMD |
230 BM_APBH_CHn_CMD_IRQONCMPLT |
231 BF(write ? BV_APBH_CHn_CMD_COMMAND__DMA_READ :
232 BV_APBH_CHn_CMD_COMMAND__DMA_WRITE,
233 APBH_CHn_CMD_COMMAND);
234 ss->d.command->pio_words[0] = c0;
235 ss->d.command->buf_ptr = spi_buf_dma;
236
237 stmp3xxx_dma_reset_channel(ss->dma);
238 stmp3xxx_dma_clear_interrupt(ss->dma);
239 stmp3xxx_dma_enable_interrupt(ss->dma);
240 init_completion(&ss->done);
241 stmp3xxx_dma_go(ss->dma, &ss->d, 1);
242 wait_for_completion(&ss->done);
243
244 if (!busy_wait(readl(ss->regs + HW_SSP_CTRL0) & BM_SSP_CTRL0_RUN))
245 status = ETIMEDOUT;
246
247 if (!dma_buf)
248 dma_unmap_single(ss->master_dev, spi_buf_dma, len, dir);
249
250 return status;
251}
252
253static inline void stmp_spi_enable(struct stmp_spi *ss)
254{
255 stmp3xxx_setl(BM_SSP_CTRL0_LOCK_CS, ss->regs + HW_SSP_CTRL0);
256 stmp3xxx_clearl(BM_SSP_CTRL0_IGNORE_CRC, ss->regs + HW_SSP_CTRL0);
257}
258
259static inline void stmp_spi_disable(struct stmp_spi *ss)
260{
261 stmp3xxx_clearl(BM_SSP_CTRL0_LOCK_CS, ss->regs + HW_SSP_CTRL0);
262 stmp3xxx_setl(BM_SSP_CTRL0_IGNORE_CRC, ss->regs + HW_SSP_CTRL0);
263}
264
265static int stmp_spi_txrx_pio(struct stmp_spi *ss, int cs,
266 unsigned char *buf, int len,
267 bool first, bool last, bool write)
268{
269 if (first)
270 stmp_spi_enable(ss);
271
272 stmp3xxx_setl(stmp_spi_cs(cs), ss->regs + HW_SSP_CTRL0);
273
274 while (len--) {
275 if (last && len <= 0)
276 stmp_spi_disable(ss);
277
278 stmp3xxx_clearl(BM_SSP_CTRL0_XFER_COUNT,
279 ss->regs + HW_SSP_CTRL0);
280 stmp3xxx_setl(1, ss->regs + HW_SSP_CTRL0);
281
282 if (write)
283 stmp3xxx_clearl(BM_SSP_CTRL0_READ,
284 ss->regs + HW_SSP_CTRL0);
285 else
286 stmp3xxx_setl(BM_SSP_CTRL0_READ,
287 ss->regs + HW_SSP_CTRL0);
288
289 /* Run! */
290 stmp3xxx_setl(BM_SSP_CTRL0_RUN, ss->regs + HW_SSP_CTRL0);
291
292 if (!busy_wait(readl(ss->regs + HW_SSP_CTRL0) &
293 BM_SSP_CTRL0_RUN))
294 break;
295
296 if (write)
297 writel(*buf, ss->regs + HW_SSP_DATA);
298
299 /* Set TRANSFER */
300 stmp3xxx_setl(BM_SSP_CTRL0_DATA_XFER, ss->regs + HW_SSP_CTRL0);
301
302 if (!write) {
303 if (busy_wait((readl(ss->regs + HW_SSP_STATUS) &
304 BM_SSP_STATUS_FIFO_EMPTY)))
305 break;
306 *buf = readl(ss->regs + HW_SSP_DATA) & 0xFF;
307 }
308
309 if (!busy_wait(readl(ss->regs + HW_SSP_CTRL0) &
310 BM_SSP_CTRL0_RUN))
311 break;
312
313 /* advance to the next byte */
314 buf++;
315 }
316
317 return len < 0 ? 0 : -ETIMEDOUT;
318}
319
320static int stmp_spi_handle_message(struct stmp_spi *ss, struct spi_message *m)
321{
322 bool first, last;
323 struct spi_transfer *t, *tmp_t;
324 int status = 0;
325 int cs;
326
327 cs = m->spi->chip_select;
328
329 list_for_each_entry_safe(t, tmp_t, &m->transfers, transfer_list) {
330
331 first = (&t->transfer_list == m->transfers.next);
332 last = (&t->transfer_list == m->transfers.prev);
333
334 if (first || t->speed_hz || t->bits_per_word)
335 stmp_spi_setup_transfer(m->spi, t);
336
337 /* reject "not last" transfers which request to change cs */
338 if (t->cs_change && !last) {
339 dev_err(&m->spi->dev,
340 "Message with t->cs_change has been skipped\n");
341 continue;
342 }
343
344 if (t->tx_buf) {
345 status = pio ?
346 stmp_spi_txrx_pio(ss, cs, (void *)t->tx_buf,
347 t->len, first, last, true) :
348 stmp_spi_txrx_dma(ss, cs, (void *)t->tx_buf,
349 t->tx_dma, t->len, first, last, true);
350#ifdef DEBUG
351 if (t->len < 0x10)
352 print_hex_dump_bytes("Tx ",
353 DUMP_PREFIX_OFFSET,
354 t->tx_buf, t->len);
355 else
356 pr_debug("Tx: %d bytes\n", t->len);
357#endif
358 }
359 if (t->rx_buf) {
360 status = pio ?
361 stmp_spi_txrx_pio(ss, cs, t->rx_buf,
362 t->len, first, last, false) :
363 stmp_spi_txrx_dma(ss, cs, t->rx_buf,
364 t->rx_dma, t->len, first, last, false);
365#ifdef DEBUG
366 if (t->len < 0x10)
367 print_hex_dump_bytes("Rx ",
368 DUMP_PREFIX_OFFSET,
369 t->rx_buf, t->len);
370 else
371 pr_debug("Rx: %d bytes\n", t->len);
372#endif
373 }
374
375 if (t->delay_usecs)
376 udelay(t->delay_usecs);
377
378 if (status)
379 break;
380
381 }
382 return status;
383}
384
385/**
386 * stmp_spi_handle - handle messages from the queue
387 */
388static void stmp_spi_handle(struct work_struct *w)
389{
390 struct stmp_spi *ss = container_of(w, struct stmp_spi, work);
391 unsigned long flags;
392 struct spi_message *m;
393
394 spin_lock_irqsave(&ss->lock, flags);
395 while (!list_empty(&ss->queue)) {
396 m = list_entry(ss->queue.next, struct spi_message, queue);
397 list_del_init(&m->queue);
398 spin_unlock_irqrestore(&ss->lock, flags);
399
400 m->status = stmp_spi_handle_message(ss, m);
401 m->complete(m->context);
402
403 spin_lock_irqsave(&ss->lock, flags);
404 }
405 spin_unlock_irqrestore(&ss->lock, flags);
406
407 return;
408}
409
410/**
411 * stmp_spi_transfer - perform message transfer.
412 * Called indirectly from spi_async, queues all the messages to
413 * spi_handle_message.
414 * @spi: spi device
415 * @m: message to be queued
416 */
417static int stmp_spi_transfer(struct spi_device *spi, struct spi_message *m)
418{
419 struct stmp_spi *ss = spi_master_get_devdata(spi->master);
420 unsigned long flags;
421
422 m->status = -EINPROGRESS;
423 spin_lock_irqsave(&ss->lock, flags);
424 list_add_tail(&m->queue, &ss->queue);
425 queue_work(ss->workqueue, &ss->work);
426 spin_unlock_irqrestore(&ss->lock, flags);
427 return 0;
428}
429
430static irqreturn_t stmp_spi_irq(int irq, void *dev_id)
431{
432 struct stmp_spi *ss = dev_id;
433
434 stmp3xxx_dma_clear_interrupt(ss->dma);
435 complete(&ss->done);
436 return IRQ_HANDLED;
437}
438
439static irqreturn_t stmp_spi_irq_err(int irq, void *dev_id)
440{
441 struct stmp_spi *ss = dev_id;
442 u32 c1, st;
443
444 c1 = readl(ss->regs + HW_SSP_CTRL1);
445 st = readl(ss->regs + HW_SSP_STATUS);
446 dev_err(ss->master_dev, "%s: status = 0x%08X, c1 = 0x%08X\n",
447 __func__, st, c1);
448 stmp3xxx_clearl(c1 & 0xCCCC0000, ss->regs + HW_SSP_CTRL1);
449
450 return IRQ_HANDLED;
451}
452
453static int __devinit stmp_spi_probe(struct platform_device *dev)
454{
455 int err = 0;
456 struct spi_master *master;
457 struct stmp_spi *ss;
458 struct resource *r;
459
460 master = spi_alloc_master(&dev->dev, sizeof(struct stmp_spi));
461 if (master == NULL) {
462 err = -ENOMEM;
463 goto out0;
464 }
465 master->flags = SPI_MASTER_HALF_DUPLEX;
466
467 ss = spi_master_get_devdata(master);
468 platform_set_drvdata(dev, master);
469
470 /* Get resources(memory, IRQ) associated with the device */
471 r = platform_get_resource(dev, IORESOURCE_MEM, 0);
472 if (r == NULL) {
473 err = -ENODEV;
474 goto out_put_master;
475 }
476 ss->regs = ioremap(r->start, resource_size(r));
477 if (!ss->regs) {
478 err = -EINVAL;
479 goto out_put_master;
480 }
481
482 ss->master_dev = &dev->dev;
483 ss->id = dev->id;
484
485 INIT_WORK(&ss->work, stmp_spi_handle);
486 INIT_LIST_HEAD(&ss->queue);
487 spin_lock_init(&ss->lock);
488
489 ss->workqueue = create_singlethread_workqueue(dev_name(&dev->dev));
490 if (!ss->workqueue) {
491 err = -ENXIO;
492 goto out_put_master;
493 }
494 master->transfer = stmp_spi_transfer;
495 master->setup = stmp_spi_setup;
496
497 /* the spi->mode bits understood by this driver: */
498 master->mode_bits = SPI_CPOL | SPI_CPHA;
499
500 ss->irq = platform_get_irq(dev, 0);
501 if (ss->irq < 0) {
502 err = ss->irq;
503 goto out_put_master;
504 }
505 ss->err_irq = platform_get_irq(dev, 1);
506 if (ss->err_irq < 0) {
507 err = ss->err_irq;
508 goto out_put_master;
509 }
510
511 r = platform_get_resource(dev, IORESOURCE_DMA, 0);
512 if (r == NULL) {
513 err = -ENODEV;
514 goto out_put_master;
515 }
516
517 ss->dma = r->start;
518 err = stmp3xxx_dma_request(ss->dma, &dev->dev, dev_name(&dev->dev));
519 if (err)
520 goto out_put_master;
521
522 err = stmp3xxx_dma_allocate_command(ss->dma, &ss->d);
523 if (err)
524 goto out_free_dma;
525
526 master->bus_num = dev->id;
527 master->num_chipselect = 1;
528
529 /* SPI controller initializations */
530 err = stmp_spi_init_hw(ss);
531 if (err) {
532 dev_dbg(&dev->dev, "cannot initialize hardware\n");
533 goto out_free_dma_desc;
534 }
535
536 if (clock) {
537 dev_info(&dev->dev, "clock rate forced to %d\n", clock);
538 clk_set_rate(ss->clk, clock);
539 }
540 ss->speed_khz = clk_get_rate(ss->clk);
541 ss->divider = 2;
542 dev_info(&dev->dev, "max possible speed %d = %ld/%d kHz\n",
543 ss->speed_khz, clk_get_rate(ss->clk), ss->divider);
544
545 /* Register for SPI interrupt */
546 err = request_irq(ss->irq, stmp_spi_irq, 0,
547 dev_name(&dev->dev), ss);
548 if (err) {
549 dev_dbg(&dev->dev, "request_irq failed, %d\n", err);
550 goto out_release_hw;
551 }
552
553 /* ..and shared interrupt for all SSP controllers */
554 err = request_irq(ss->err_irq, stmp_spi_irq_err, IRQF_SHARED,
555 dev_name(&dev->dev), ss);
556 if (err) {
557 dev_dbg(&dev->dev, "request_irq(error) failed, %d\n", err);
558 goto out_free_irq;
559 }
560
561 err = spi_register_master(master);
562 if (err) {
563 dev_dbg(&dev->dev, "cannot register spi master, %d\n", err);
564 goto out_free_irq_2;
565 }
566 dev_info(&dev->dev, "at (mapped) 0x%08X, irq=%d, bus %d, %s mode\n",
567 (u32)ss->regs, ss->irq, master->bus_num,
568 pio ? "PIO" : "DMA");
569 return 0;
570
571out_free_irq_2:
572 free_irq(ss->err_irq, ss);
573out_free_irq:
574 free_irq(ss->irq, ss);
575out_free_dma_desc:
576 stmp3xxx_dma_free_command(ss->dma, &ss->d);
577out_free_dma:
578 stmp3xxx_dma_release(ss->dma);
579out_release_hw:
580 stmp_spi_release_hw(ss);
581out_put_master:
582 if (ss->workqueue)
583 destroy_workqueue(ss->workqueue);
584 if (ss->regs)
585 iounmap(ss->regs);
586 platform_set_drvdata(dev, NULL);
587 spi_master_put(master);
588out0:
589 return err;
590}
591
592static int __devexit stmp_spi_remove(struct platform_device *dev)
593{
594 struct stmp_spi *ss;
595 struct spi_master *master;
596
597 master = platform_get_drvdata(dev);
598 if (master == NULL)
599 goto out0;
600 ss = spi_master_get_devdata(master);
601
602 spi_unregister_master(master);
603
604 free_irq(ss->err_irq, ss);
605 free_irq(ss->irq, ss);
606 stmp3xxx_dma_free_command(ss->dma, &ss->d);
607 stmp3xxx_dma_release(ss->dma);
608 stmp_spi_release_hw(ss);
609 destroy_workqueue(ss->workqueue);
610 iounmap(ss->regs);
611 spi_master_put(master);
612 platform_set_drvdata(dev, NULL);
613out0:
614 return 0;
615}
616
617#ifdef CONFIG_PM
618static int stmp_spi_suspend(struct platform_device *pdev, pm_message_t pmsg)
619{
620 struct stmp_spi *ss;
621 struct spi_master *master;
622
623 master = platform_get_drvdata(pdev);
624 ss = spi_master_get_devdata(master);
625
626 ss->saved_timings = readl(HW_SSP_TIMING + ss->regs);
627 clk_disable(ss->clk);
628
629 return 0;
630}
631
632static int stmp_spi_resume(struct platform_device *pdev)
633{
634 struct stmp_spi *ss;
635 struct spi_master *master;
636
637 master = platform_get_drvdata(pdev);
638 ss = spi_master_get_devdata(master);
639
640 clk_enable(ss->clk);
641 stmp3xxx_reset_block(ss->regs, false);
642 writel(ss->saved_timings, ss->regs + HW_SSP_TIMING);
643
644 return 0;
645}
646
647#else
648#define stmp_spi_suspend NULL
649#define stmp_spi_resume NULL
650#endif
651
652static struct platform_driver stmp_spi_driver = {
653 .probe = stmp_spi_probe,
654 .remove = __devexit_p(stmp_spi_remove),
655 .driver = {
656 .name = "stmp3xxx_ssp",
657 .owner = THIS_MODULE,
658 },
659 .suspend = stmp_spi_suspend,
660 .resume = stmp_spi_resume,
661};
662
663static int __init stmp_spi_init(void)
664{
665 return platform_driver_register(&stmp_spi_driver);
666}
667
668static void __exit stmp_spi_exit(void)
669{
670 platform_driver_unregister(&stmp_spi_driver);
671}
672
673module_init(stmp_spi_init);
674module_exit(stmp_spi_exit);
675module_param(pio, int, S_IRUGO);
676module_param(clock, int, S_IRUGO);
677MODULE_AUTHOR("dmitry pervushin <dpervushin@embeddedalley.com>");
678MODULE_DESCRIPTION("STMP3xxx SPI/SSP driver");
679MODULE_LICENSE("GPL");
diff --git a/drivers/spi/spidev.c b/drivers/spi/spidev.c
index 606e7a40a8da..f921bd1109e1 100644
--- a/drivers/spi/spidev.c
+++ b/drivers/spi/spidev.c
@@ -688,3 +688,4 @@ module_exit(spidev_exit);
688MODULE_AUTHOR("Andrea Paterniani, <a.paterniani@swapp-eng.it>"); 688MODULE_AUTHOR("Andrea Paterniani, <a.paterniani@swapp-eng.it>");
689MODULE_DESCRIPTION("User mode SPI device interface"); 689MODULE_DESCRIPTION("User mode SPI device interface");
690MODULE_LICENSE("GPL"); 690MODULE_LICENSE("GPL");
691MODULE_ALIAS("spi:spidev");
diff --git a/drivers/spi/tle62x0.c b/drivers/spi/tle62x0.c
index 455991fbe28f..bf9540f5fb98 100644
--- a/drivers/spi/tle62x0.c
+++ b/drivers/spi/tle62x0.c
@@ -329,3 +329,4 @@ module_exit(tle62x0_exit);
329MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>"); 329MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
330MODULE_DESCRIPTION("TLE62x0 SPI driver"); 330MODULE_DESCRIPTION("TLE62x0 SPI driver");
331MODULE_LICENSE("GPL v2"); 331MODULE_LICENSE("GPL v2");
332MODULE_ALIAS("spi:tle62x0");
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-21 23:41:58 -0500