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authorTomoya MORINAGA <tomoya-linux@dsn.okisemi.com>2011-06-07 01:50:11 -0400
committerGrant Likely <grant.likely@secretlab.ca>2011-06-08 18:53:50 -0400
commitc37f3c2749b53225d36faa5c583203c5f12ae15b (patch)
treeab67e00c7e51d696172f35647dfb327824ddbd3c /drivers/spi
parentf016aeb655350ef935ddf336e22cb00452a1c41e (diff)
spi/topcliff_pch: DMA support
This patch enables this SPI driver works with DMA mode. Signed-off-by: Tomoya MORINAGA <tomoya-linux@dsn.okisemi.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
Diffstat (limited to 'drivers/spi')
-rw-r--r--drivers/spi/spi-topcliff-pch.c594
1 files changed, 488 insertions, 106 deletions
diff --git a/drivers/spi/spi-topcliff-pch.c b/drivers/spi/spi-topcliff-pch.c
index be84e3a36406..1b8030bc24b7 100644
--- a/drivers/spi/spi-topcliff-pch.c
+++ b/drivers/spi/spi-topcliff-pch.c
@@ -28,6 +28,9 @@
28#include <linux/device.h> 28#include <linux/device.h>
29#include <linux/platform_device.h> 29#include <linux/platform_device.h>
30 30
31#include <linux/dmaengine.h>
32#include <linux/pch_dma.h>
33
31/* Register offsets */ 34/* Register offsets */
32#define PCH_SPCR 0x00 /* SPI control register */ 35#define PCH_SPCR 0x00 /* SPI control register */
33#define PCH_SPBRR 0x04 /* SPI baud rate register */ 36#define PCH_SPBRR 0x04 /* SPI baud rate register */
@@ -36,7 +39,7 @@
36#define PCH_SPDRR 0x10 /* SPI read data register */ 39#define PCH_SPDRR 0x10 /* SPI read data register */
37#define PCH_SSNXCR 0x18 /* SSN Expand Control Register */ 40#define PCH_SSNXCR 0x18 /* SSN Expand Control Register */
38#define PCH_SRST 0x1C /* SPI reset register */ 41#define PCH_SRST 0x1C /* SPI reset register */
39#define PCH_SPI_ADDRESS_SIZE 0x20 42#define PCH_ADDRESS_SIZE 0x20
40 43
41#define PCH_SPSR_TFD 0x000007C0 44#define PCH_SPSR_TFD 0x000007C0
42#define PCH_SPSR_RFD 0x0000F800 45#define PCH_SPSR_RFD 0x0000F800
@@ -54,8 +57,6 @@
54#define STATUS_EXITING 2 57#define STATUS_EXITING 2
55#define PCH_SLEEP_TIME 10 58#define PCH_SLEEP_TIME 10
56 59
57#define PCH_ADDRESS_SIZE 0x20
58
59#define SSN_LOW 0x02U 60#define SSN_LOW 0x02U
60#define SSN_NO_CONTROL 0x00U 61#define SSN_NO_CONTROL 0x00U
61#define PCH_MAX_CS 0xFF 62#define PCH_MAX_CS 0xFF
@@ -75,6 +76,7 @@
75#define SPSR_TFI_BIT (1 << 0) 76#define SPSR_TFI_BIT (1 << 0)
76#define SPSR_RFI_BIT (1 << 1) 77#define SPSR_RFI_BIT (1 << 1)
77#define SPSR_FI_BIT (1 << 2) 78#define SPSR_FI_BIT (1 << 2)
79#define SPSR_ORF_BIT (1 << 3)
78#define SPBRR_SIZE_BIT (1 << 10) 80#define SPBRR_SIZE_BIT (1 << 10)
79 81
80#define PCH_ALL (SPCR_TFIE_BIT|SPCR_RFIE_BIT|SPCR_FIE_BIT|\ 82#define PCH_ALL (SPCR_TFIE_BIT|SPCR_RFIE_BIT|SPCR_FIE_BIT|\
@@ -83,10 +85,9 @@
83#define SPCR_RFIC_FIELD 20 85#define SPCR_RFIC_FIELD 20
84#define SPCR_TFIC_FIELD 16 86#define SPCR_TFIC_FIELD 16
85 87
86#define SPSR_INT_BITS 0x1F 88#define MASK_SPBRR_SPBR_BITS ((1 << 10) - 1)
87#define MASK_SPBRR_SPBR_BITS (~((1 << 10) - 1)) 89#define MASK_RFIC_SPCR_BITS (0xf << SPCR_RFIC_FIELD)
88#define MASK_RFIC_SPCR_BITS (~(0xf << 20)) 90#define MASK_TFIC_SPCR_BITS (0xf << SPCR_TFIC_FIELD)
89#define MASK_TFIC_SPCR_BITS (~(0xf000f << 12))
90 91
91#define PCH_CLOCK_HZ 50000000 92#define PCH_CLOCK_HZ 50000000
92#define PCH_MAX_SPBR 1023 93#define PCH_MAX_SPBR 1023
@@ -102,6 +103,28 @@
102*/ 103*/
103#define PCH_SPI_MAX_DEV 2 104#define PCH_SPI_MAX_DEV 2
104 105
106#define PCH_BUF_SIZE 4096
107#define PCH_DMA_TRANS_SIZE 12
108
109static int use_dma = 1;
110
111struct pch_spi_dma_ctrl {
112 struct dma_async_tx_descriptor *desc_tx;
113 struct dma_async_tx_descriptor *desc_rx;
114 struct pch_dma_slave param_tx;
115 struct pch_dma_slave param_rx;
116 struct dma_chan *chan_tx;
117 struct dma_chan *chan_rx;
118 struct scatterlist *sg_tx_p;
119 struct scatterlist *sg_rx_p;
120 struct scatterlist sg_tx;
121 struct scatterlist sg_rx;
122 int nent;
123 void *tx_buf_virt;
124 void *rx_buf_virt;
125 dma_addr_t tx_buf_dma;
126 dma_addr_t rx_buf_dma;
127};
105/** 128/**
106 * struct pch_spi_data - Holds the SPI channel specific details 129 * struct pch_spi_data - Holds the SPI channel specific details
107 * @io_remap_addr: The remapped PCI base address 130 * @io_remap_addr: The remapped PCI base address
@@ -140,6 +163,7 @@
140 */ 163 */
141struct pch_spi_data { 164struct pch_spi_data {
142 void __iomem *io_remap_addr; 165 void __iomem *io_remap_addr;
166 unsigned long io_base_addr;
143 struct spi_master *master; 167 struct spi_master *master;
144 struct work_struct work; 168 struct work_struct work;
145 struct workqueue_struct *wk; 169 struct workqueue_struct *wk;
@@ -162,6 +186,8 @@ struct pch_spi_data {
162 struct pch_spi_board_data *board_dat; 186 struct pch_spi_board_data *board_dat;
163 struct platform_device *plat_dev; 187 struct platform_device *plat_dev;
164 int ch; 188 int ch;
189 struct pch_spi_dma_ctrl dma;
190 int use_dma;
165 u8 irq_reg_sts; 191 u8 irq_reg_sts;
166}; 192};
167 193
@@ -273,10 +299,10 @@ static void pch_spi_handler_sub(struct pch_spi_data *data, u32 reg_spsr_val,
273 reg_spcr_val &= ~SPCR_RFIE_BIT; /* disable RFI */ 299 reg_spcr_val &= ~SPCR_RFIE_BIT; /* disable RFI */
274 300
275 /* reset rx threshold */ 301 /* reset rx threshold */
276 reg_spcr_val &= MASK_RFIC_SPCR_BITS; 302 reg_spcr_val &= ~MASK_RFIC_SPCR_BITS;
277 reg_spcr_val |= (PCH_RX_THOLD_MAX << SPCR_RFIC_FIELD); 303 reg_spcr_val |= (PCH_RX_THOLD_MAX << SPCR_RFIC_FIELD);
278 iowrite32(((reg_spcr_val) &= (~(SPCR_RFIE_BIT))), 304
279 (io_remap_addr + PCH_SPCR)); 305 iowrite32(reg_spcr_val, (io_remap_addr + PCH_SPCR));
280 } 306 }
281 307
282 /* update counts */ 308 /* update counts */
@@ -287,12 +313,15 @@ static void pch_spi_handler_sub(struct pch_spi_data *data, u32 reg_spsr_val,
287 313
288 /* if transfer complete interrupt */ 314 /* if transfer complete interrupt */
289 if (reg_spsr_val & SPSR_FI_BIT) { 315 if (reg_spsr_val & SPSR_FI_BIT) {
290 /* disable FI & RFI interrupts */ 316 if (tx_index < bpw_len)
291 pch_spi_setclr_reg(data->master, PCH_SPCR, 0, 317 dev_err(&data->master->dev,
292 SPCR_FIE_BIT | SPCR_RFIE_BIT); 318 "%s : Transfer is not completed", __func__);
319 /* disable interrupts */
320 pch_spi_setclr_reg(data->master, PCH_SPCR, 0, PCH_ALL);
293 321
294 /* transfer is completed;inform pch_spi_process_messages */ 322 /* transfer is completed;inform pch_spi_process_messages */
295 data->transfer_complete = true; 323 data->transfer_complete = true;
324 data->transfer_active = false;
296 wake_up(&data->wait); 325 wake_up(&data->wait);
297 } 326 }
298} 327}
@@ -316,12 +345,17 @@ static irqreturn_t pch_spi_handler(int irq, void *dev_id)
316 "%s returning due to suspend\n", __func__); 345 "%s returning due to suspend\n", __func__);
317 return IRQ_NONE; 346 return IRQ_NONE;
318 } 347 }
348 if (data->use_dma)
349 return IRQ_NONE;
319 350
320 io_remap_addr = data->io_remap_addr; 351 io_remap_addr = data->io_remap_addr;
321 spsr = io_remap_addr + PCH_SPSR; 352 spsr = io_remap_addr + PCH_SPSR;
322 353
323 reg_spsr_val = ioread32(spsr); 354 reg_spsr_val = ioread32(spsr);
324 355
356 if (reg_spsr_val & SPSR_ORF_BIT)
357 dev_err(&board_dat->pdev->dev, "%s Over run error", __func__);
358
325 /* Check if the interrupt is for SPI device */ 359 /* Check if the interrupt is for SPI device */
326 if (reg_spsr_val & (SPSR_FI_BIT | SPSR_RFI_BIT)) { 360 if (reg_spsr_val & (SPSR_FI_BIT | SPSR_RFI_BIT)) {
327 pch_spi_handler_sub(data, reg_spsr_val, io_remap_addr); 361 pch_spi_handler_sub(data, reg_spsr_val, io_remap_addr);
@@ -347,7 +381,7 @@ static void pch_spi_set_baud_rate(struct spi_master *master, u32 speed_hz)
347 if (n_spbr > PCH_MAX_SPBR) 381 if (n_spbr > PCH_MAX_SPBR)
348 n_spbr = PCH_MAX_SPBR; 382 n_spbr = PCH_MAX_SPBR;
349 383
350 pch_spi_setclr_reg(master, PCH_SPBRR, n_spbr, ~MASK_SPBRR_SPBR_BITS); 384 pch_spi_setclr_reg(master, PCH_SPBRR, n_spbr, MASK_SPBRR_SPBR_BITS);
351} 385}
352 386
353/** 387/**
@@ -456,26 +490,27 @@ static int pch_spi_transfer(struct spi_device *pspi, struct spi_message *pmsg)
456 dev_dbg(&pspi->dev, "%s Transfer List not empty. " 490 dev_dbg(&pspi->dev, "%s Transfer List not empty. "
457 "Transfer Speed is set.\n", __func__); 491 "Transfer Speed is set.\n", __func__);
458 492
493 spin_lock_irqsave(&data->lock, flags);
459 /* validate Tx/Rx buffers and Transfer length */ 494 /* validate Tx/Rx buffers and Transfer length */
460 list_for_each_entry(transfer, &pmsg->transfers, transfer_list) { 495 list_for_each_entry(transfer, &pmsg->transfers, transfer_list) {
461 if (!transfer->tx_buf && !transfer->rx_buf) { 496 if (!transfer->tx_buf && !transfer->rx_buf) {
462 dev_err(&pspi->dev, 497 dev_err(&pspi->dev,
463 "%s Tx and Rx buffer NULL\n", __func__); 498 "%s Tx and Rx buffer NULL\n", __func__);
464 retval = -EINVAL; 499 retval = -EINVAL;
465 goto err_out; 500 goto err_return_spinlock;
466 } 501 }
467 502
468 if (!transfer->len) { 503 if (!transfer->len) {
469 dev_err(&pspi->dev, "%s Transfer length invalid\n", 504 dev_err(&pspi->dev, "%s Transfer length invalid\n",
470 __func__); 505 __func__);
471 retval = -EINVAL; 506 retval = -EINVAL;
472 goto err_out; 507 goto err_return_spinlock;
473 } 508 }
474 509
475 dev_dbg(&pspi->dev, "%s Tx/Rx buffer valid. Transfer length" 510 dev_dbg(&pspi->dev, "%s Tx/Rx buffer valid. Transfer length"
476 " valid\n", __func__); 511 " valid\n", __func__);
477 512
478 /* if baud rate hs been specified validate the same */ 513 /* if baud rate has been specified validate the same */
479 if (transfer->speed_hz > PCH_MAX_BAUDRATE) 514 if (transfer->speed_hz > PCH_MAX_BAUDRATE)
480 transfer->speed_hz = PCH_MAX_BAUDRATE; 515 transfer->speed_hz = PCH_MAX_BAUDRATE;
481 516
@@ -486,25 +521,24 @@ static int pch_spi_transfer(struct spi_device *pspi, struct spi_message *pmsg)
486 retval = -EINVAL; 521 retval = -EINVAL;
487 dev_err(&pspi->dev, 522 dev_err(&pspi->dev,
488 "%s Invalid bits per word\n", __func__); 523 "%s Invalid bits per word\n", __func__);
489 goto err_out; 524 goto err_return_spinlock;
490 } 525 }
491 } 526 }
492 } 527 }
493 528 spin_unlock_irqrestore(&data->lock, flags);
494 spin_lock_irqsave(&data->lock, flags);
495 529
496 /* We won't process any messages if we have been asked to terminate */ 530 /* We won't process any messages if we have been asked to terminate */
497 if (data->status == STATUS_EXITING) { 531 if (data->status == STATUS_EXITING) {
498 dev_err(&pspi->dev, "%s status = STATUS_EXITING.\n", __func__); 532 dev_err(&pspi->dev, "%s status = STATUS_EXITING.\n", __func__);
499 retval = -ESHUTDOWN; 533 retval = -ESHUTDOWN;
500 goto err_return_spinlock; 534 goto err_out;
501 } 535 }
502 536
503 /* If suspended ,return -EINVAL */ 537 /* If suspended ,return -EINVAL */
504 if (data->board_dat->suspend_sts) { 538 if (data->board_dat->suspend_sts) {
505 dev_err(&pspi->dev, "%s suspend; returning EINVAL\n", __func__); 539 dev_err(&pspi->dev, "%s suspend; returning EINVAL\n", __func__);
506 retval = -EINVAL; 540 retval = -EINVAL;
507 goto err_return_spinlock; 541 goto err_out;
508 } 542 }
509 543
510 /* set status of message */ 544 /* set status of message */
@@ -512,9 +546,11 @@ static int pch_spi_transfer(struct spi_device *pspi, struct spi_message *pmsg)
512 dev_dbg(&pspi->dev, "%s - pmsg->status =%d\n", __func__, pmsg->status); 546 dev_dbg(&pspi->dev, "%s - pmsg->status =%d\n", __func__, pmsg->status);
513 547
514 pmsg->status = -EINPROGRESS; 548 pmsg->status = -EINPROGRESS;
515 549 spin_lock_irqsave(&data->lock, flags);
516 /* add message to queue */ 550 /* add message to queue */
517 list_add_tail(&pmsg->queue, &data->queue); 551 list_add_tail(&pmsg->queue, &data->queue);
552 spin_unlock_irqrestore(&data->lock, flags);
553
518 dev_dbg(&pspi->dev, "%s - Invoked list_add_tail\n", __func__); 554 dev_dbg(&pspi->dev, "%s - Invoked list_add_tail\n", __func__);
519 555
520 /* schedule work queue to run */ 556 /* schedule work queue to run */
@@ -523,11 +559,13 @@ static int pch_spi_transfer(struct spi_device *pspi, struct spi_message *pmsg)
523 559
524 retval = 0; 560 retval = 0;
525 561
526err_return_spinlock:
527 spin_unlock_irqrestore(&data->lock, flags);
528err_out: 562err_out:
529 dev_dbg(&pspi->dev, "%s RETURN=%d\n", __func__, retval); 563 dev_dbg(&pspi->dev, "%s RETURN=%d\n", __func__, retval);
530 return retval; 564 return retval;
565err_return_spinlock:
566 dev_dbg(&pspi->dev, "%s RETURN=%d\n", __func__, retval);
567 spin_unlock_irqrestore(&data->lock, flags);
568 return retval;
531} 569}
532 570
533static inline void pch_spi_select_chip(struct pch_spi_data *data, 571static inline void pch_spi_select_chip(struct pch_spi_data *data,
@@ -548,8 +586,7 @@ static inline void pch_spi_select_chip(struct pch_spi_data *data,
548 pch_spi_setup_transfer(pspi); 586 pch_spi_setup_transfer(pspi);
549} 587}
550 588
551static void pch_spi_set_tx(struct pch_spi_data *data, int *bpw, 589static void pch_spi_set_tx(struct pch_spi_data *data, int *bpw)
552 struct spi_message **ppmsg)
553{ 590{
554 int size; 591 int size;
555 u32 n_writes; 592 u32 n_writes;
@@ -558,8 +595,6 @@ static void pch_spi_set_tx(struct pch_spi_data *data, int *bpw,
558 const u8 *tx_buf; 595 const u8 *tx_buf;
559 const u16 *tx_sbuf; 596 const u16 *tx_sbuf;
560 597
561 pmsg = *ppmsg;
562
563 /* set baud rate if needed */ 598 /* set baud rate if needed */
564 if (data->cur_trans->speed_hz) { 599 if (data->cur_trans->speed_hz) {
565 dev_dbg(&data->master->dev, "%s:setting baud rate\n", __func__); 600 dev_dbg(&data->master->dev, "%s:setting baud rate\n", __func__);
@@ -642,10 +677,9 @@ static void pch_spi_set_tx(struct pch_spi_data *data, int *bpw,
642 data->transfer_active = true; 677 data->transfer_active = true;
643} 678}
644 679
645 680static void pch_spi_nomore_transfer(struct pch_spi_data *data)
646static void pch_spi_nomore_transfer(struct pch_spi_data *data,
647 struct spi_message *pmsg)
648{ 681{
682 struct spi_message *pmsg;
649 dev_dbg(&data->master->dev, "%s called\n", __func__); 683 dev_dbg(&data->master->dev, "%s called\n", __func__);
650 /* Invoke complete callback 684 /* Invoke complete callback
651 * [To the spi core..indicating end of transfer] */ 685 * [To the spi core..indicating end of transfer] */
@@ -696,29 +730,21 @@ static void pch_spi_nomore_transfer(struct pch_spi_data *data,
696 730
697static void pch_spi_set_ir(struct pch_spi_data *data) 731static void pch_spi_set_ir(struct pch_spi_data *data)
698{ 732{
699 /* enable interrupts */ 733 /* enable interrupts, set threshold, enable SPI */
700 if ((data->bpw_len) > PCH_MAX_FIFO_DEPTH) { 734 if ((data->bpw_len) > PCH_MAX_FIFO_DEPTH)
701 /* set receive threshold to PCH_RX_THOLD */ 735 /* set receive threshold to PCH_RX_THOLD */
702 pch_spi_setclr_reg(data->master, PCH_SPCR, 736 pch_spi_setclr_reg(data->master, PCH_SPCR,
703 PCH_RX_THOLD << SPCR_RFIC_FIELD, 737 PCH_RX_THOLD << SPCR_RFIC_FIELD |
704 ~MASK_RFIC_SPCR_BITS); 738 SPCR_FIE_BIT | SPCR_RFIE_BIT |
705 /* enable FI and RFI interrupts */ 739 SPCR_ORIE_BIT | SPCR_SPE_BIT,
706 pch_spi_setclr_reg(data->master, PCH_SPCR, 740 MASK_RFIC_SPCR_BITS | PCH_ALL);
707 SPCR_RFIE_BIT | SPCR_FIE_BIT, 0); 741 else
708 } else {
709 /* set receive threshold to maximum */ 742 /* set receive threshold to maximum */
710 pch_spi_setclr_reg(data->master, PCH_SPCR, 743 pch_spi_setclr_reg(data->master, PCH_SPCR,
711 PCH_RX_THOLD_MAX << SPCR_TFIC_FIELD, 744 PCH_RX_THOLD_MAX << SPCR_RFIC_FIELD |
712 ~MASK_TFIC_SPCR_BITS); 745 SPCR_FIE_BIT | SPCR_ORIE_BIT |
713 /* enable FI interrupt */ 746 SPCR_SPE_BIT,
714 pch_spi_setclr_reg(data->master, PCH_SPCR, SPCR_FIE_BIT, 0); 747 MASK_RFIC_SPCR_BITS | PCH_ALL);
715 }
716
717 dev_dbg(&data->master->dev,
718 "%s:invoking pch_spi_set_enable to enable SPI\n", __func__);
719
720 /* SPI set enable */
721 pch_spi_setclr_reg(data->current_chip->master, PCH_SPCR, SPCR_SPE_BIT, 0);
722 748
723 /* Wait until the transfer completes; go to sleep after 749 /* Wait until the transfer completes; go to sleep after
724 initiating the transfer. */ 750 initiating the transfer. */
@@ -731,15 +757,13 @@ static void pch_spi_set_ir(struct pch_spi_data *data)
731 dev_dbg(&data->master->dev, 757 dev_dbg(&data->master->dev,
732 "%s:no more control over SSN-writing 0 to SSNXCR.", __func__); 758 "%s:no more control over SSN-writing 0 to SSNXCR.", __func__);
733 759
734 data->transfer_active = false;
735 dev_dbg(&data->master->dev,
736 "%s set data->transfer_active = false\n", __func__);
737
738 /* clear all interrupts */ 760 /* clear all interrupts */
739 pch_spi_writereg(data->master, PCH_SPSR, 761 pch_spi_writereg(data->master, PCH_SPSR,
740 pch_spi_readreg(data->master, PCH_SPSR)); 762 pch_spi_readreg(data->master, PCH_SPSR));
741 /* disable interrupts */ 763 /* Disable interrupts and SPI transfer */
742 pch_spi_setclr_reg(data->master, PCH_SPCR, 0, PCH_ALL); 764 pch_spi_setclr_reg(data->master, PCH_SPCR, 0, PCH_ALL | SPCR_SPE_BIT);
765 /* clear FIFO */
766 pch_spi_clear_fifo(data->master);
743} 767}
744 768
745static void pch_spi_copy_rx_data(struct pch_spi_data *data, int bpw) 769static void pch_spi_copy_rx_data(struct pch_spi_data *data, int bpw)
@@ -763,6 +787,327 @@ static void pch_spi_copy_rx_data(struct pch_spi_data *data, int bpw)
763 } 787 }
764} 788}
765 789
790static void pch_spi_copy_rx_data_for_dma(struct pch_spi_data *data, int bpw)
791{
792 int j;
793 u8 *rx_buf;
794 u16 *rx_sbuf;
795 const u8 *rx_dma_buf;
796 const u16 *rx_dma_sbuf;
797
798 /* copy Rx Data */
799 if (!data->cur_trans->rx_buf)
800 return;
801
802 if (bpw == 8) {
803 rx_buf = data->cur_trans->rx_buf;
804 rx_dma_buf = data->dma.rx_buf_virt;
805 for (j = 0; j < data->bpw_len; j++)
806 *rx_buf++ = *rx_dma_buf++ & 0xFF;
807 } else {
808 rx_sbuf = data->cur_trans->rx_buf;
809 rx_dma_sbuf = data->dma.rx_buf_virt;
810 for (j = 0; j < data->bpw_len; j++)
811 *rx_sbuf++ = *rx_dma_sbuf++;
812 }
813}
814
815static void pch_spi_start_transfer(struct pch_spi_data *data)
816{
817 struct pch_spi_dma_ctrl *dma;
818 unsigned long flags;
819
820 dma = &data->dma;
821
822 spin_lock_irqsave(&data->lock, flags);
823
824 /* disable interrupts, SPI set enable */
825 pch_spi_setclr_reg(data->master, PCH_SPCR, SPCR_SPE_BIT, PCH_ALL);
826
827 spin_unlock_irqrestore(&data->lock, flags);
828
829 /* Wait until the transfer completes; go to sleep after
830 initiating the transfer. */
831 dev_dbg(&data->master->dev,
832 "%s:waiting for transfer to get over\n", __func__);
833 wait_event_interruptible(data->wait, data->transfer_complete);
834
835 dma_sync_sg_for_cpu(&data->master->dev, dma->sg_rx_p, dma->nent,
836 DMA_FROM_DEVICE);
837 async_tx_ack(dma->desc_rx);
838 async_tx_ack(dma->desc_tx);
839 kfree(dma->sg_tx_p);
840 kfree(dma->sg_rx_p);
841
842 spin_lock_irqsave(&data->lock, flags);
843 pch_spi_writereg(data->master, PCH_SSNXCR, SSN_NO_CONTROL);
844 dev_dbg(&data->master->dev,
845 "%s:no more control over SSN-writing 0 to SSNXCR.", __func__);
846
847 /* clear fifo threshold, disable interrupts, disable SPI transfer */
848 pch_spi_setclr_reg(data->master, PCH_SPCR, 0,
849 MASK_RFIC_SPCR_BITS | MASK_TFIC_SPCR_BITS | PCH_ALL |
850 SPCR_SPE_BIT);
851 /* clear all interrupts */
852 pch_spi_writereg(data->master, PCH_SPSR,
853 pch_spi_readreg(data->master, PCH_SPSR));
854 /* clear FIFO */
855 pch_spi_clear_fifo(data->master);
856
857 spin_unlock_irqrestore(&data->lock, flags);
858}
859
860static void pch_dma_rx_complete(void *arg)
861{
862 struct pch_spi_data *data = arg;
863
864 /* transfer is completed;inform pch_spi_process_messages_dma */
865 data->transfer_complete = true;
866 wake_up_interruptible(&data->wait);
867}
868
869static bool pch_spi_filter(struct dma_chan *chan, void *slave)
870{
871 struct pch_dma_slave *param = slave;
872
873 if ((chan->chan_id == param->chan_id) &&
874 (param->dma_dev == chan->device->dev)) {
875 chan->private = param;
876 return true;
877 } else {
878 return false;
879 }
880}
881
882static void pch_spi_request_dma(struct pch_spi_data *data, int bpw)
883{
884 dma_cap_mask_t mask;
885 struct dma_chan *chan;
886 struct pci_dev *dma_dev;
887 struct pch_dma_slave *param;
888 struct pch_spi_dma_ctrl *dma;
889 unsigned int width;
890
891 if (bpw == 8)
892 width = PCH_DMA_WIDTH_1_BYTE;
893 else
894 width = PCH_DMA_WIDTH_2_BYTES;
895
896 dma = &data->dma;
897 dma_cap_zero(mask);
898 dma_cap_set(DMA_SLAVE, mask);
899
900 /* Get DMA's dev information */
901 dma_dev = pci_get_bus_and_slot(2, PCI_DEVFN(12, 0));
902
903 /* Set Tx DMA */
904 param = &dma->param_tx;
905 param->dma_dev = &dma_dev->dev;
906 param->chan_id = data->master->bus_num * 2; /* Tx = 0, 2 */
907 param->tx_reg = data->io_base_addr + PCH_SPDWR;
908 param->width = width;
909 chan = dma_request_channel(mask, pch_spi_filter, param);
910 if (!chan) {
911 dev_err(&data->master->dev,
912 "ERROR: dma_request_channel FAILS(Tx)\n");
913 data->use_dma = 0;
914 return;
915 }
916 dma->chan_tx = chan;
917
918 /* Set Rx DMA */
919 param = &dma->param_rx;
920 param->dma_dev = &dma_dev->dev;
921 param->chan_id = data->master->bus_num * 2 + 1; /* Rx = Tx + 1 */
922 param->rx_reg = data->io_base_addr + PCH_SPDRR;
923 param->width = width;
924 chan = dma_request_channel(mask, pch_spi_filter, param);
925 if (!chan) {
926 dev_err(&data->master->dev,
927 "ERROR: dma_request_channel FAILS(Rx)\n");
928 dma_release_channel(dma->chan_tx);
929 dma->chan_tx = NULL;
930 data->use_dma = 0;
931 return;
932 }
933 dma->chan_rx = chan;
934}
935
936static void pch_spi_release_dma(struct pch_spi_data *data)
937{
938 struct pch_spi_dma_ctrl *dma;
939
940 dma = &data->dma;
941 if (dma->chan_tx) {
942 dma_release_channel(dma->chan_tx);
943 dma->chan_tx = NULL;
944 }
945 if (dma->chan_rx) {
946 dma_release_channel(dma->chan_rx);
947 dma->chan_rx = NULL;
948 }
949 return;
950}
951
952static void pch_spi_handle_dma(struct pch_spi_data *data, int *bpw)
953{
954 const u8 *tx_buf;
955 const u16 *tx_sbuf;
956 u8 *tx_dma_buf;
957 u16 *tx_dma_sbuf;
958 struct scatterlist *sg;
959 struct dma_async_tx_descriptor *desc_tx;
960 struct dma_async_tx_descriptor *desc_rx;
961 int num;
962 int i;
963 int size;
964 int rem;
965 unsigned long flags;
966 struct pch_spi_dma_ctrl *dma;
967
968 dma = &data->dma;
969
970 /* set baud rate if needed */
971 if (data->cur_trans->speed_hz) {
972 dev_dbg(&data->master->dev, "%s:setting baud rate\n", __func__);
973 spin_lock_irqsave(&data->lock, flags);
974 pch_spi_set_baud_rate(data->master, data->cur_trans->speed_hz);
975 spin_unlock_irqrestore(&data->lock, flags);
976 }
977
978 /* set bits per word if needed */
979 if (data->cur_trans->bits_per_word &&
980 (data->current_msg->spi->bits_per_word !=
981 data->cur_trans->bits_per_word)) {
982 dev_dbg(&data->master->dev, "%s:set bits per word\n", __func__);
983 spin_lock_irqsave(&data->lock, flags);
984 pch_spi_set_bits_per_word(data->master,
985 data->cur_trans->bits_per_word);
986 spin_unlock_irqrestore(&data->lock, flags);
987 *bpw = data->cur_trans->bits_per_word;
988 } else {
989 *bpw = data->current_msg->spi->bits_per_word;
990 }
991 data->bpw_len = data->cur_trans->len / (*bpw / 8);
992
993 /* copy Tx Data */
994 if (data->cur_trans->tx_buf != NULL) {
995 if (*bpw == 8) {
996 tx_buf = data->cur_trans->tx_buf;
997 tx_dma_buf = dma->tx_buf_virt;
998 for (i = 0; i < data->bpw_len; i++)
999 *tx_dma_buf++ = *tx_buf++;
1000 } else {
1001 tx_sbuf = data->cur_trans->tx_buf;
1002 tx_dma_sbuf = dma->tx_buf_virt;
1003 for (i = 0; i < data->bpw_len; i++)
1004 *tx_dma_sbuf++ = *tx_sbuf++;
1005 }
1006 }
1007 if (data->bpw_len > PCH_DMA_TRANS_SIZE) {
1008 num = data->bpw_len / PCH_DMA_TRANS_SIZE + 1;
1009 size = PCH_DMA_TRANS_SIZE;
1010 rem = data->bpw_len % PCH_DMA_TRANS_SIZE;
1011 } else {
1012 num = 1;
1013 size = data->bpw_len;
1014 rem = data->bpw_len;
1015 }
1016 dev_dbg(&data->master->dev, "%s num=%d size=%d rem=%d\n",
1017 __func__, num, size, rem);
1018 spin_lock_irqsave(&data->lock, flags);
1019
1020 /* set receive fifo threshold and transmit fifo threshold */
1021 pch_spi_setclr_reg(data->master, PCH_SPCR,
1022 ((size - 1) << SPCR_RFIC_FIELD) |
1023 ((PCH_MAX_FIFO_DEPTH - PCH_DMA_TRANS_SIZE) <<
1024 SPCR_TFIC_FIELD),
1025 MASK_RFIC_SPCR_BITS | MASK_TFIC_SPCR_BITS);
1026
1027 spin_unlock_irqrestore(&data->lock, flags);
1028
1029 /* RX */
1030 dma->sg_rx_p = kzalloc(sizeof(struct scatterlist)*num, GFP_ATOMIC);
1031 sg_init_table(dma->sg_rx_p, num); /* Initialize SG table */
1032 /* offset, length setting */
1033 sg = dma->sg_rx_p;
1034 for (i = 0; i < num; i++, sg++) {
1035 if (i == 0) {
1036 sg->offset = 0;
1037 sg_set_page(sg, virt_to_page(dma->rx_buf_virt), rem,
1038 sg->offset);
1039 sg_dma_len(sg) = rem;
1040 } else {
1041 sg->offset = rem + size * (i - 1);
1042 sg->offset = sg->offset * (*bpw / 8);
1043 sg_set_page(sg, virt_to_page(dma->rx_buf_virt), size,
1044 sg->offset);
1045 sg_dma_len(sg) = size;
1046 }
1047 sg_dma_address(sg) = dma->rx_buf_dma + sg->offset;
1048 }
1049 sg = dma->sg_rx_p;
1050 desc_rx = dma->chan_rx->device->device_prep_slave_sg(dma->chan_rx, sg,
1051 num, DMA_FROM_DEVICE,
1052 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1053 if (!desc_rx) {
1054 dev_err(&data->master->dev, "%s:device_prep_slave_sg Failed\n",
1055 __func__);
1056 return;
1057 }
1058 dma_sync_sg_for_device(&data->master->dev, sg, num, DMA_FROM_DEVICE);
1059 desc_rx->callback = pch_dma_rx_complete;
1060 desc_rx->callback_param = data;
1061 dma->nent = num;
1062 dma->desc_rx = desc_rx;
1063
1064 /* TX */
1065 dma->sg_tx_p = kzalloc(sizeof(struct scatterlist)*num, GFP_ATOMIC);
1066 sg_init_table(dma->sg_tx_p, num); /* Initialize SG table */
1067 /* offset, length setting */
1068 sg = dma->sg_tx_p;
1069 for (i = 0; i < num; i++, sg++) {
1070 if (i == 0) {
1071 sg->offset = 0;
1072 sg_set_page(sg, virt_to_page(dma->tx_buf_virt), rem,
1073 sg->offset);
1074 sg_dma_len(sg) = rem;
1075 } else {
1076 sg->offset = rem + size * (i - 1);
1077 sg->offset = sg->offset * (*bpw / 8);
1078 sg_set_page(sg, virt_to_page(dma->tx_buf_virt), size,
1079 sg->offset);
1080 sg_dma_len(sg) = size;
1081 }
1082 sg_dma_address(sg) = dma->tx_buf_dma + sg->offset;
1083 }
1084 sg = dma->sg_tx_p;
1085 desc_tx = dma->chan_tx->device->device_prep_slave_sg(dma->chan_tx,
1086 sg, num, DMA_TO_DEVICE,
1087 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1088 if (!desc_tx) {
1089 dev_err(&data->master->dev, "%s:device_prep_slave_sg Failed\n",
1090 __func__);
1091 return;
1092 }
1093 dma_sync_sg_for_device(&data->master->dev, sg, num, DMA_TO_DEVICE);
1094 desc_tx->callback = NULL;
1095 desc_tx->callback_param = data;
1096 dma->nent = num;
1097 dma->desc_tx = desc_tx;
1098
1099 dev_dbg(&data->master->dev, "\n%s:Pulling down SSN low - writing "
1100 "0x2 to SSNXCR\n", __func__);
1101
1102 spin_lock_irqsave(&data->lock, flags);
1103 pch_spi_writereg(data->master, PCH_SSNXCR, SSN_LOW);
1104 desc_rx->tx_submit(desc_rx);
1105 desc_tx->tx_submit(desc_tx);
1106 spin_unlock_irqrestore(&data->lock, flags);
1107
1108 /* reset transfer complete flag */
1109 data->transfer_complete = false;
1110}
766 1111
767static void pch_spi_process_messages(struct work_struct *pwork) 1112static void pch_spi_process_messages(struct work_struct *pwork)
768{ 1113{
@@ -774,13 +1119,10 @@ static void pch_spi_process_messages(struct work_struct *pwork)
774 dev_dbg(&data->master->dev, "%s data initialized\n", __func__); 1119 dev_dbg(&data->master->dev, "%s data initialized\n", __func__);
775 1120
776 spin_lock(&data->lock); 1121 spin_lock(&data->lock);
777
778 /* check if suspend has been initiated;if yes flush queue */ 1122 /* check if suspend has been initiated;if yes flush queue */
779 if (data->board_dat->suspend_sts || (data->status == STATUS_EXITING)) { 1123 if (data->board_dat->suspend_sts || (data->status == STATUS_EXITING)) {
780 dev_dbg(&data->master->dev, 1124 dev_dbg(&data->master->dev, "%s suspend/remove initiated,"
781 "%s suspend/remove initiated,flushing queue\n", 1125 "flushing queue\n", __func__);
782 __func__);
783
784 list_for_each_entry(pmsg, data->queue.next, queue) { 1126 list_for_each_entry(pmsg, data->queue.next, queue) {
785 pmsg->status = -EIO; 1127 pmsg->status = -EIO;
786 1128
@@ -814,53 +1156,42 @@ static void pch_spi_process_messages(struct work_struct *pwork)
814 1156
815 spin_unlock(&data->lock); 1157 spin_unlock(&data->lock);
816 1158
1159 if (data->use_dma)
1160 pch_spi_request_dma(data,
1161 data->current_msg->spi->bits_per_word);
817 do { 1162 do {
818 /* If we are already processing a message get the next 1163 /* If we are already processing a message get the next
819 transfer structure from the message otherwise retrieve 1164 transfer structure from the message otherwise retrieve
820 the 1st transfer request from the message. */ 1165 the 1st transfer request from the message. */
821 spin_lock(&data->lock); 1166 spin_lock(&data->lock);
822
823 if (data->cur_trans == NULL) { 1167 if (data->cur_trans == NULL) {
824 data->cur_trans = 1168 data->cur_trans =
825 list_entry(data->current_msg->transfers. 1169 list_entry(data->current_msg->transfers.next,
826 next, struct spi_transfer, 1170 struct spi_transfer, transfer_list);
827 transfer_list); 1171 dev_dbg(&data->master->dev, "%s "
828 dev_dbg(&data->master->dev, 1172 ":Getting 1st transfer message\n", __func__);
829 "%s :Getting 1st transfer message\n", __func__);
830 } else { 1173 } else {
831 data->cur_trans = 1174 data->cur_trans =
832 list_entry(data->cur_trans->transfer_list.next, 1175 list_entry(data->cur_trans->transfer_list.next,
833 struct spi_transfer, 1176 struct spi_transfer, transfer_list);
834 transfer_list); 1177 dev_dbg(&data->master->dev, "%s "
835 dev_dbg(&data->master->dev, 1178 ":Getting next transfer message\n", __func__);
836 "%s :Getting next transfer message\n",
837 __func__);
838 } 1179 }
839
840 spin_unlock(&data->lock); 1180 spin_unlock(&data->lock);
841 1181
842 pch_spi_set_tx(data, &bpw, &pmsg); 1182 if (data->use_dma) {
843 1183 pch_spi_handle_dma(data, &bpw);
844 /* Control interrupt*/ 1184 pch_spi_start_transfer(data);
845 pch_spi_set_ir(data); 1185 pch_spi_copy_rx_data_for_dma(data, bpw);
846 1186 } else {
847 /* Disable SPI transfer */ 1187 pch_spi_set_tx(data, &bpw);
848 pch_spi_setclr_reg(data->current_chip->master, PCH_SPCR, 0, 1188 pch_spi_set_ir(data);
849 SPCR_SPE_BIT); 1189 pch_spi_copy_rx_data(data, bpw);
850 1190 kfree(data->pkt_rx_buff);
851 /* clear FIFO */ 1191 data->pkt_rx_buff = NULL;
852 pch_spi_clear_fifo(data->master); 1192 kfree(data->pkt_tx_buff);
853 1193 data->pkt_tx_buff = NULL;
854 /* copy Rx Data */ 1194 }
855 pch_spi_copy_rx_data(data, bpw);
856
857 /* free memory */
858 kfree(data->pkt_rx_buff);
859 data->pkt_rx_buff = NULL;
860
861 kfree(data->pkt_tx_buff);
862 data->pkt_tx_buff = NULL;
863
864 /* increment message count */ 1195 /* increment message count */
865 data->current_msg->actual_length += data->cur_trans->len; 1196 data->current_msg->actual_length += data->cur_trans->len;
866 1197
@@ -881,12 +1212,15 @@ static void pch_spi_process_messages(struct work_struct *pwork)
881 /* No more transfer in this message. */ 1212 /* No more transfer in this message. */
882 if ((data->cur_trans->transfer_list.next) == 1213 if ((data->cur_trans->transfer_list.next) ==
883 &(data->current_msg->transfers)) { 1214 &(data->current_msg->transfers)) {
884 pch_spi_nomore_transfer(data, pmsg); 1215 pch_spi_nomore_transfer(data);
885 } 1216 }
886 1217
887 spin_unlock(&data->lock); 1218 spin_unlock(&data->lock);
888 1219
889 } while (data->cur_trans != NULL); 1220 } while (data->cur_trans != NULL);
1221
1222 if (data->use_dma)
1223 pch_spi_release_dma(data);
890} 1224}
891 1225
892static void pch_spi_free_resources(struct pch_spi_board_data *board_dat, 1226static void pch_spi_free_resources(struct pch_spi_board_data *board_dat,
@@ -939,6 +1273,35 @@ err_return:
939 return retval; 1273 return retval;
940} 1274}
941 1275
1276static void pch_free_dma_buf(struct pch_spi_board_data *board_dat,
1277 struct pch_spi_data *data)
1278{
1279 struct pch_spi_dma_ctrl *dma;
1280
1281 dma = &data->dma;
1282 if (dma->tx_buf_dma)
1283 dma_free_coherent(&board_dat->pdev->dev, PCH_BUF_SIZE,
1284 dma->tx_buf_virt, dma->tx_buf_dma);
1285 if (dma->rx_buf_dma)
1286 dma_free_coherent(&board_dat->pdev->dev, PCH_BUF_SIZE,
1287 dma->rx_buf_virt, dma->rx_buf_dma);
1288 return;
1289}
1290
1291static void pch_alloc_dma_buf(struct pch_spi_board_data *board_dat,
1292 struct pch_spi_data *data)
1293{
1294 struct pch_spi_dma_ctrl *dma;
1295
1296 dma = &data->dma;
1297 /* Get Consistent memory for Tx DMA */
1298 dma->tx_buf_virt = dma_alloc_coherent(&board_dat->pdev->dev,
1299 PCH_BUF_SIZE, &dma->tx_buf_dma, GFP_KERNEL);
1300 /* Get Consistent memory for Rx DMA */
1301 dma->rx_buf_virt = dma_alloc_coherent(&board_dat->pdev->dev,
1302 PCH_BUF_SIZE, &dma->rx_buf_dma, GFP_KERNEL);
1303}
1304
942static int __devinit pch_spi_pd_probe(struct platform_device *plat_dev) 1305static int __devinit pch_spi_pd_probe(struct platform_device *plat_dev)
943{ 1306{
944 int ret; 1307 int ret;
@@ -946,6 +1309,8 @@ static int __devinit pch_spi_pd_probe(struct platform_device *plat_dev)
946 struct pch_spi_board_data *board_dat = dev_get_platdata(&plat_dev->dev); 1309 struct pch_spi_board_data *board_dat = dev_get_platdata(&plat_dev->dev);
947 struct pch_spi_data *data; 1310 struct pch_spi_data *data;
948 1311
1312 dev_dbg(&plat_dev->dev, "%s:debug\n", __func__);
1313
949 master = spi_alloc_master(&board_dat->pdev->dev, 1314 master = spi_alloc_master(&board_dat->pdev->dev,
950 sizeof(struct pch_spi_data)); 1315 sizeof(struct pch_spi_data));
951 if (!master) { 1316 if (!master) {
@@ -959,9 +1324,11 @@ static int __devinit pch_spi_pd_probe(struct platform_device *plat_dev)
959 1324
960 platform_set_drvdata(plat_dev, data); 1325 platform_set_drvdata(plat_dev, data);
961 1326
962 /* baseaddress + 0x20(offset) */ 1327 /* baseaddress + address offset) */
1328 data->io_base_addr = pci_resource_start(board_dat->pdev, 1) +
1329 PCH_ADDRESS_SIZE * plat_dev->id;
963 data->io_remap_addr = pci_iomap(board_dat->pdev, 1, 0) + 1330 data->io_remap_addr = pci_iomap(board_dat->pdev, 1, 0) +
964 0x20 * plat_dev->id; 1331 PCH_ADDRESS_SIZE * plat_dev->id;
965 if (!data->io_remap_addr) { 1332 if (!data->io_remap_addr) {
966 dev_err(&plat_dev->dev, "%s pci_iomap failed\n", __func__); 1333 dev_err(&plat_dev->dev, "%s pci_iomap failed\n", __func__);
967 ret = -ENOMEM; 1334 ret = -ENOMEM;
@@ -982,6 +1349,7 @@ static int __devinit pch_spi_pd_probe(struct platform_device *plat_dev)
982 data->n_curnt_chip = 255; 1349 data->n_curnt_chip = 255;
983 data->status = STATUS_RUNNING; 1350 data->status = STATUS_RUNNING;
984 data->ch = plat_dev->id; 1351 data->ch = plat_dev->id;
1352 data->use_dma = use_dma;
985 1353
986 INIT_LIST_HEAD(&data->queue); 1354 INIT_LIST_HEAD(&data->queue);
987 spin_lock_init(&data->lock); 1355 spin_lock_init(&data->lock);
@@ -1012,6 +1380,11 @@ static int __devinit pch_spi_pd_probe(struct platform_device *plat_dev)
1012 goto err_spi_register_master; 1380 goto err_spi_register_master;
1013 } 1381 }
1014 1382
1383 if (use_dma) {
1384 dev_info(&plat_dev->dev, "Use DMA for data transfers\n");
1385 pch_alloc_dma_buf(board_dat, data);
1386 }
1387
1015 return 0; 1388 return 0;
1016 1389
1017err_spi_register_master: 1390err_spi_register_master:
@@ -1031,22 +1404,27 @@ static int __devexit pch_spi_pd_remove(struct platform_device *plat_dev)
1031 struct pch_spi_board_data *board_dat = dev_get_platdata(&plat_dev->dev); 1404 struct pch_spi_board_data *board_dat = dev_get_platdata(&plat_dev->dev);
1032 struct pch_spi_data *data = platform_get_drvdata(plat_dev); 1405 struct pch_spi_data *data = platform_get_drvdata(plat_dev);
1033 int count; 1406 int count;
1407 unsigned long flags;
1034 1408
1035 dev_dbg(&plat_dev->dev, "%s:[ch%d] irq=%d\n", 1409 dev_dbg(&plat_dev->dev, "%s:[ch%d] irq=%d\n",
1036 __func__, plat_dev->id, board_dat->pdev->irq); 1410 __func__, plat_dev->id, board_dat->pdev->irq);
1411
1412 if (use_dma)
1413 pch_free_dma_buf(board_dat, data);
1414
1037 /* check for any pending messages; no action is taken if the queue 1415 /* check for any pending messages; no action is taken if the queue
1038 * is still full; but at least we tried. Unload anyway */ 1416 * is still full; but at least we tried. Unload anyway */
1039 count = 500; 1417 count = 500;
1040 spin_lock(&data->lock); 1418 spin_lock_irqsave(&data->lock, flags);
1041 data->status = STATUS_EXITING; 1419 data->status = STATUS_EXITING;
1042 while ((list_empty(&data->queue) == 0) && --count) { 1420 while ((list_empty(&data->queue) == 0) && --count) {
1043 dev_dbg(&board_dat->pdev->dev, "%s :queue not empty\n", 1421 dev_dbg(&board_dat->pdev->dev, "%s :queue not empty\n",
1044 __func__); 1422 __func__);
1045 spin_unlock(&data->lock); 1423 spin_unlock_irqrestore(&data->lock, flags);
1046 msleep(PCH_SLEEP_TIME); 1424 msleep(PCH_SLEEP_TIME);
1047 spin_lock(&data->lock); 1425 spin_lock_irqsave(&data->lock, flags);
1048 } 1426 }
1049 spin_unlock(&data->lock); 1427 spin_unlock_irqrestore(&data->lock, flags);
1050 1428
1051 pch_spi_free_resources(board_dat, data); 1429 pch_spi_free_resources(board_dat, data);
1052 /* disable interrupts & free IRQ */ 1430 /* disable interrupts & free IRQ */
@@ -1083,8 +1461,8 @@ static int pch_spi_pd_suspend(struct platform_device *pd_dev,
1083 /* check if the current message is processed: 1461 /* check if the current message is processed:
1084 Only after thats done the transfer will be suspended */ 1462 Only after thats done the transfer will be suspended */
1085 count = 255; 1463 count = 255;
1086 while ((--count) > 0) 1464 while ((--count) > 0) {
1087 if (!(data->bcurrent_msg_processing)) { 1465 if (!(data->bcurrent_msg_processing))
1088 break; 1466 break;
1089 msleep(PCH_SLEEP_TIME); 1467 msleep(PCH_SLEEP_TIME);
1090 } 1468 }
@@ -1328,5 +1706,9 @@ static void __exit pch_spi_exit(void)
1328} 1706}
1329module_exit(pch_spi_exit); 1707module_exit(pch_spi_exit);
1330 1708
1709module_param(use_dma, int, 0644);
1710MODULE_PARM_DESC(use_dma,
1711 "to use DMA for data transfers pass 1 else 0; default 1");
1712
1331MODULE_LICENSE("GPL"); 1713MODULE_LICENSE("GPL");
1332MODULE_DESCRIPTION("Intel EG20T PCH/OKI SEMICONDUCTOR ML7213 IOH SPI Driver"); 1714MODULE_DESCRIPTION("Intel EG20T PCH/OKI SEMICONDUCTOR ML7213 IOH SPI Driver");