spi/rockchip: Add device tree property to configure Rx Sample Delay

We have found that we can sometimes see read failures on boards with
high-capacitance SPI lines. It seems that the controller samples the Rx
data line too early, and its register interface has an "Rx Sample Delay"
setting to fine-tune against this issue.

This patch adds a new optional device tree entry that can configure this
delay in terms of nanoseconds. The kernel will calculate the
best-fitting amount of parent clock ticks to program the controller with
based on that.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Signed-off-by: Mark Brown <broonie@kernel.org>

1 files changed, 21 insertions, 0 deletions

diff --git a/drivers/spi/spi-rockchip.c b/drivers/spi/spi-rockchip.c
index 25003c408c92..f65384b3417f 100644
--- a/drivers/spi/spi-rockchip.c
+++ b/drivers/spi/spi-rockchip.c
@@ -179,6 +179,7 @@ struct rockchip_spi {
         u8 tmode;
         u8 bpw;
         u8 n_bytes;
+        u8 rsd_nsecs;
         unsigned len;
         u32 speed;
 
@@ -499,6 +500,7 @@ static void rockchip_spi_config(struct rockchip_spi *rs)
 {
         u32 div = 0;
         u32 dmacr = 0;
+        int rsd = 0;
 
         u32 cr0 = (CR0_BHT_8BIT << CR0_BHT_OFFSET)
                 | (CR0_SSD_ONE << CR0_SSD_OFFSET);
@@ -528,6 +530,20 @@ static void rockchip_spi_config(struct rockchip_spi *rs)
         div = max_t(u32, rs->max_freq / rs->speed, 1);
         div = (div + 1) & 0xfffe;
 
+        /* Rx sample delay is expressed in parent clock cycles (max 3) */
+        rsd = DIV_ROUND_CLOSEST(rs->rsd_nsecs * (rs->max_freq >> 8),
+                                1000000000 >> 8);
+        if (!rsd && rs->rsd_nsecs) {
+                pr_warn_once("rockchip-spi: %u Hz are too slow to express %u ns delay\n",
+                             rs->max_freq, rs->rsd_nsecs);
+        } else if (rsd > 3) {
+                rsd = 3;
+                pr_warn_once("rockchip-spi: %u Hz are too fast to express %u ns delay, clamping at %u ns\n",
+                             rs->max_freq, rs->rsd_nsecs,
+                             rsd * 1000000000U / rs->max_freq);
+        }
+        cr0 |= rsd << CR0_RSD_OFFSET;
+
         writel_relaxed(cr0, rs->regs + ROCKCHIP_SPI_CTRLR0);
 
         writel_relaxed(rs->len - 1, rs->regs + ROCKCHIP_SPI_CTRLR1);
@@ -620,6 +636,7 @@ static int rockchip_spi_probe(struct platform_device *pdev)
         struct rockchip_spi *rs;
         struct spi_master *master;
         struct resource *mem;
+        u32 rsd_nsecs;
 
         master = spi_alloc_master(&pdev->dev, sizeof(struct rockchip_spi));
         if (!master)
@@ -671,6 +688,10 @@ static int rockchip_spi_probe(struct platform_device *pdev)
         rs->dev = &pdev->dev;
         rs->max_freq = clk_get_rate(rs->spiclk);
 
+        if (!of_property_read_u32(pdev->dev.of_node, "rx-sample-delay-ns",
+                                  &rsd_nsecs))
+                rs->rsd_nsecs = rsd_nsecs;
+
         rs->fifo_len = get_fifo_len(rs);
         if (!rs->fifo_len) {
                 dev_err(&pdev->dev, "Failed to get fifo length\n");