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authorJonas Gorski <jogo@openwrt.org>2013-03-11 19:13:46 -0400
committerMark Brown <broonie@opensource.wolfsonmicro.com>2013-03-12 15:14:48 -0400
commit68792e2a1989bf34a9498356c3e3cc70b9231df2 (patch)
treeebb3edd0319b3399fee12563bb51cc941eb4aef5 /drivers/spi
parentc94df49542a9cf2c095468e62be6a16ba86dd811 (diff)
spi/bcm63xx: inline hz usage in bcm63xx_spi_setup_transfer
bcm63xx_spi_setup_transfer is called from only one place, and that has t always set, to hz will always be t->speed_hz - just use it directly in the two places instead of moving it in a local variable. Signed-off-by: Jonas Gorski <jogo@openwrt.org> Acked-by: Florian Fainelli <florian@openwrt.org> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Diffstat (limited to 'drivers/spi')
-rw-r--r--drivers/spi/spi-bcm63xx.c7
1 files changed, 2 insertions, 5 deletions
diff --git a/drivers/spi/spi-bcm63xx.c b/drivers/spi/spi-bcm63xx.c
index d777f6311100..2d64db4ac6a2 100644
--- a/drivers/spi/spi-bcm63xx.c
+++ b/drivers/spi/spi-bcm63xx.c
@@ -97,15 +97,12 @@ static void bcm63xx_spi_setup_transfer(struct spi_device *spi,
97 struct spi_transfer *t) 97 struct spi_transfer *t)
98{ 98{
99 struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master); 99 struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
100 u32 hz;
101 u8 clk_cfg, reg; 100 u8 clk_cfg, reg;
102 int i; 101 int i;
103 102
104 hz = (t) ? t->speed_hz : spi->max_speed_hz;
105
106 /* Find the closest clock configuration */ 103 /* Find the closest clock configuration */
107 for (i = 0; i < SPI_CLK_MASK; i++) { 104 for (i = 0; i < SPI_CLK_MASK; i++) {
108 if (hz >= bcm63xx_spi_freq_table[i][0]) { 105 if (t->speed_hz >= bcm63xx_spi_freq_table[i][0]) {
109 clk_cfg = bcm63xx_spi_freq_table[i][1]; 106 clk_cfg = bcm63xx_spi_freq_table[i][1];
110 break; 107 break;
111 } 108 }
@@ -122,7 +119,7 @@ static void bcm63xx_spi_setup_transfer(struct spi_device *spi,
122 119
123 bcm_spi_writeb(bs, reg, SPI_CLK_CFG); 120 bcm_spi_writeb(bs, reg, SPI_CLK_CFG);
124 dev_dbg(&spi->dev, "Setting clock register to %02x (hz %d)\n", 121 dev_dbg(&spi->dev, "Setting clock register to %02x (hz %d)\n",
125 clk_cfg, hz); 122 clk_cfg, t->speed_hz);
126} 123}
127 124
128/* the spi->mode bits understood by this driver: */ 125/* the spi->mode bits understood by this driver: */