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authorChris Blair <chris.blair@stericsson.com>2011-06-04 02:57:47 -0400
committerLinus Walleij <linus.walleij@linaro.org>2011-12-01 11:16:07 -0500
commit172289df4004cccf798316b19cc3e6284dbe901f (patch)
treeee82043bd2a819a81416730ba7ac2c882bbb311c /drivers/spi
parentcaca6a03d365883564885f2c1da3e88dcf65d139 (diff)
spi/pl022: only enable RX interrupts when TX is complete
For interrupt mode transfers, start with only TX interrupts enabled to reduce the overall number of interrupts received. Once TX is complete, enable RX interrupts to complete the transfer. Reviewed-by: Viresh Kumar <viresh.kumar@st.com> Signed-off-by: Chris Blair <chris.blair@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/spi')
-rw-r--r--drivers/spi/spi-pl022.c15
1 files changed, 10 insertions, 5 deletions
diff --git a/drivers/spi/spi-pl022.c b/drivers/spi/spi-pl022.c
index 5559b2299198..5b7209f9f100 100644
--- a/drivers/spi/spi-pl022.c
+++ b/drivers/spi/spi-pl022.c
@@ -1244,9 +1244,9 @@ static irqreturn_t pl022_interrupt_handler(int irq, void *dev_id)
1244 1244
1245 if ((pl022->tx == pl022->tx_end) && (flag == 0)) { 1245 if ((pl022->tx == pl022->tx_end) && (flag == 0)) {
1246 flag = 1; 1246 flag = 1;
1247 /* Disable Transmit interrupt */ 1247 /* Disable Transmit interrupt, enable receive interrupt */
1248 writew(readw(SSP_IMSC(pl022->virtbase)) & 1248 writew((readw(SSP_IMSC(pl022->virtbase)) &
1249 (~SSP_IMSC_MASK_TXIM), 1249 ~SSP_IMSC_MASK_TXIM) | SSP_IMSC_MASK_RXIM,
1250 SSP_IMSC(pl022->virtbase)); 1250 SSP_IMSC(pl022->virtbase));
1251 } 1251 }
1252 1252
@@ -1379,12 +1379,17 @@ static void pump_transfers(unsigned long data)
1379 } 1379 }
1380 1380
1381err_config_dma: 1381err_config_dma:
1382 writew(ENABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase)); 1382 /* enable all interrupts except RX */
1383 writew(ENABLE_ALL_INTERRUPTS & ~SSP_IMSC_MASK_RXIM, SSP_IMSC(pl022->virtbase));
1383} 1384}
1384 1385
1385static void do_interrupt_dma_transfer(struct pl022 *pl022) 1386static void do_interrupt_dma_transfer(struct pl022 *pl022)
1386{ 1387{
1387 u32 irqflags = ENABLE_ALL_INTERRUPTS; 1388 /*
1389 * Default is to enable all interrupts except RX -
1390 * this will be enabled once TX is complete
1391 */
1392 u32 irqflags = ENABLE_ALL_INTERRUPTS & ~SSP_IMSC_MASK_RXIM;
1388 1393
1389 /* Enable target chip */ 1394 /* Enable target chip */
1390 pl022->cur_chip->cs_control(SSP_CHIP_SELECT); 1395 pl022->cur_chip->cs_control(SSP_CHIP_SELECT);