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authorGovindraj.R <govindraj.raja@ti.com>2011-02-02 07:22:15 -0500
committerTony Lindgren <tony@atomide.com>2011-02-17 12:54:13 -0500
commit1f1a4384b6500273020e48130f73601e4ba7d84b (patch)
tree433633041e1e726e882453c4aa8dcfc3c2dbded0 /drivers/spi
parent1a5d81905aec1536783fb6ab875f31910f449941 (diff)
OMAP: runtime: McSPI driver runtime conversion
McSPI runtime conversion. Changes involves: 1) remove clock framework apis to use runtime framework apis. 2) context restore from runtime resume which is a callback for get_sync. 3) Remove SYSCONFIG(sysc) register handling (a) Remove context save and restore of sysc reg and remove soft reset done from sysc reg as this will be done with hwmod framework. (b) Also cleanup sysc reg bit macros. 4) Rename the omap2_mcspi_reset function to omap2_mcspi_master_setup function as with hwmod changes soft reset will be done in hwmod framework itself and use the return value from clock enable function to return for failure scenarios. Signed-off-by: Charulatha V <charu@ti.com> Signed-off-by: Govindraj.R <govindraj.raja@ti.com> Acked-by: Grant Likely <grant.likely@secretlab.ca> Reviewed-by: Partha Basak <p-basak2@ti.com> Reviewed-by: Kevin Hilman <khilman@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'drivers/spi')
-rw-r--r--drivers/spi/omap2_mcspi.c116
1 files changed, 42 insertions, 74 deletions
diff --git a/drivers/spi/omap2_mcspi.c b/drivers/spi/omap2_mcspi.c
index f7851325c61e..36501adc125d 100644
--- a/drivers/spi/omap2_mcspi.c
+++ b/drivers/spi/omap2_mcspi.c
@@ -33,6 +33,7 @@
33#include <linux/clk.h> 33#include <linux/clk.h>
34#include <linux/io.h> 34#include <linux/io.h>
35#include <linux/slab.h> 35#include <linux/slab.h>
36#include <linux/pm_runtime.h>
36 37
37#include <linux/spi/spi.h> 38#include <linux/spi/spi.h>
38 39
@@ -46,7 +47,6 @@
46#define OMAP2_MCSPI_MAX_CTRL 4 47#define OMAP2_MCSPI_MAX_CTRL 4
47 48
48#define OMAP2_MCSPI_REVISION 0x00 49#define OMAP2_MCSPI_REVISION 0x00
49#define OMAP2_MCSPI_SYSCONFIG 0x10
50#define OMAP2_MCSPI_SYSSTATUS 0x14 50#define OMAP2_MCSPI_SYSSTATUS 0x14
51#define OMAP2_MCSPI_IRQSTATUS 0x18 51#define OMAP2_MCSPI_IRQSTATUS 0x18
52#define OMAP2_MCSPI_IRQENABLE 0x1c 52#define OMAP2_MCSPI_IRQENABLE 0x1c
@@ -63,13 +63,6 @@
63 63
64/* per-register bitmasks: */ 64/* per-register bitmasks: */
65 65
66#define OMAP2_MCSPI_SYSCONFIG_SMARTIDLE BIT(4)
67#define OMAP2_MCSPI_SYSCONFIG_ENAWAKEUP BIT(2)
68#define OMAP2_MCSPI_SYSCONFIG_AUTOIDLE BIT(0)
69#define OMAP2_MCSPI_SYSCONFIG_SOFTRESET BIT(1)
70
71#define OMAP2_MCSPI_SYSSTATUS_RESETDONE BIT(0)
72
73#define OMAP2_MCSPI_MODULCTRL_SINGLE BIT(0) 66#define OMAP2_MCSPI_MODULCTRL_SINGLE BIT(0)
74#define OMAP2_MCSPI_MODULCTRL_MS BIT(2) 67#define OMAP2_MCSPI_MODULCTRL_MS BIT(2)
75#define OMAP2_MCSPI_MODULCTRL_STEST BIT(3) 68#define OMAP2_MCSPI_MODULCTRL_STEST BIT(3)
@@ -122,13 +115,12 @@ struct omap2_mcspi {
122 spinlock_t lock; 115 spinlock_t lock;
123 struct list_head msg_queue; 116 struct list_head msg_queue;
124 struct spi_master *master; 117 struct spi_master *master;
125 struct clk *ick;
126 struct clk *fck;
127 /* Virtual base address of the controller */ 118 /* Virtual base address of the controller */
128 void __iomem *base; 119 void __iomem *base;
129 unsigned long phys; 120 unsigned long phys;
130 /* SPI1 has 4 channels, while SPI2 has 2 */ 121 /* SPI1 has 4 channels, while SPI2 has 2 */
131 struct omap2_mcspi_dma *dma_channels; 122 struct omap2_mcspi_dma *dma_channels;
123 struct device *dev;
132}; 124};
133 125
134struct omap2_mcspi_cs { 126struct omap2_mcspi_cs {
@@ -144,7 +136,6 @@ struct omap2_mcspi_cs {
144 * corresponding registers are modified. 136 * corresponding registers are modified.
145 */ 137 */
146struct omap2_mcspi_regs { 138struct omap2_mcspi_regs {
147 u32 sysconfig;
148 u32 modulctrl; 139 u32 modulctrl;
149 u32 wakeupenable; 140 u32 wakeupenable;
150 struct list_head cs; 141 struct list_head cs;
@@ -268,9 +259,6 @@ static void omap2_mcspi_restore_ctx(struct omap2_mcspi *mcspi)
268 mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_MODULCTRL, 259 mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_MODULCTRL,
269 omap2_mcspi_ctx[spi_cntrl->bus_num - 1].modulctrl); 260 omap2_mcspi_ctx[spi_cntrl->bus_num - 1].modulctrl);
270 261
271 mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_SYSCONFIG,
272 omap2_mcspi_ctx[spi_cntrl->bus_num - 1].sysconfig);
273
274 mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_WAKEUPENABLE, 262 mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_WAKEUPENABLE,
275 omap2_mcspi_ctx[spi_cntrl->bus_num - 1].wakeupenable); 263 omap2_mcspi_ctx[spi_cntrl->bus_num - 1].wakeupenable);
276 264
@@ -280,20 +268,12 @@ static void omap2_mcspi_restore_ctx(struct omap2_mcspi *mcspi)
280} 268}
281static void omap2_mcspi_disable_clocks(struct omap2_mcspi *mcspi) 269static void omap2_mcspi_disable_clocks(struct omap2_mcspi *mcspi)
282{ 270{
283 clk_disable(mcspi->ick); 271 pm_runtime_put_sync(mcspi->dev);
284 clk_disable(mcspi->fck);
285} 272}
286 273
287static int omap2_mcspi_enable_clocks(struct omap2_mcspi *mcspi) 274static int omap2_mcspi_enable_clocks(struct omap2_mcspi *mcspi)
288{ 275{
289 if (clk_enable(mcspi->ick)) 276 return pm_runtime_get_sync(mcspi->dev);
290 return -ENODEV;
291 if (clk_enable(mcspi->fck))
292 return -ENODEV;
293
294 omap2_mcspi_restore_ctx(mcspi);
295
296 return 0;
297} 277}
298 278
299static int mcspi_wait_for_reg_bit(void __iomem *reg, unsigned long bit) 279static int mcspi_wait_for_reg_bit(void __iomem *reg, unsigned long bit)
@@ -819,8 +799,9 @@ static int omap2_mcspi_setup(struct spi_device *spi)
819 return ret; 799 return ret;
820 } 800 }
821 801
822 if (omap2_mcspi_enable_clocks(mcspi)) 802 ret = omap2_mcspi_enable_clocks(mcspi);
823 return -ENODEV; 803 if (ret < 0)
804 return ret;
824 805
825 ret = omap2_mcspi_setup_transfer(spi, NULL); 806 ret = omap2_mcspi_setup_transfer(spi, NULL);
826 omap2_mcspi_disable_clocks(mcspi); 807 omap2_mcspi_disable_clocks(mcspi);
@@ -863,10 +844,11 @@ static void omap2_mcspi_work(struct work_struct *work)
863 struct omap2_mcspi *mcspi; 844 struct omap2_mcspi *mcspi;
864 845
865 mcspi = container_of(work, struct omap2_mcspi, work); 846 mcspi = container_of(work, struct omap2_mcspi, work);
866 spin_lock_irq(&mcspi->lock);
867 847
868 if (omap2_mcspi_enable_clocks(mcspi)) 848 if (omap2_mcspi_enable_clocks(mcspi) < 0)
869 goto out; 849 return;
850
851 spin_lock_irq(&mcspi->lock);
870 852
871 /* We only enable one channel at a time -- the one whose message is 853 /* We only enable one channel at a time -- the one whose message is
872 * at the head of the queue -- although this controller would gladly 854 * at the head of the queue -- although this controller would gladly
@@ -979,10 +961,9 @@ static void omap2_mcspi_work(struct work_struct *work)
979 spin_lock_irq(&mcspi->lock); 961 spin_lock_irq(&mcspi->lock);
980 } 962 }
981 963
982 omap2_mcspi_disable_clocks(mcspi);
983
984out:
985 spin_unlock_irq(&mcspi->lock); 964 spin_unlock_irq(&mcspi->lock);
965
966 omap2_mcspi_disable_clocks(mcspi);
986} 967}
987 968
988static int omap2_mcspi_transfer(struct spi_device *spi, struct spi_message *m) 969static int omap2_mcspi_transfer(struct spi_device *spi, struct spi_message *m)
@@ -1058,25 +1039,15 @@ static int omap2_mcspi_transfer(struct spi_device *spi, struct spi_message *m)
1058 return 0; 1039 return 0;
1059} 1040}
1060 1041
1061static int __init omap2_mcspi_reset(struct omap2_mcspi *mcspi) 1042static int __init omap2_mcspi_master_setup(struct omap2_mcspi *mcspi)
1062{ 1043{
1063 struct spi_master *master = mcspi->master; 1044 struct spi_master *master = mcspi->master;
1064 u32 tmp; 1045 u32 tmp;
1046 int ret = 0;
1065 1047
1066 if (omap2_mcspi_enable_clocks(mcspi)) 1048 ret = omap2_mcspi_enable_clocks(mcspi);
1067 return -1; 1049 if (ret < 0)
1068 1050 return ret;
1069 mcspi_write_reg(master, OMAP2_MCSPI_SYSCONFIG,
1070 OMAP2_MCSPI_SYSCONFIG_SOFTRESET);
1071 do {
1072 tmp = mcspi_read_reg(master, OMAP2_MCSPI_SYSSTATUS);
1073 } while (!(tmp & OMAP2_MCSPI_SYSSTATUS_RESETDONE));
1074
1075 tmp = OMAP2_MCSPI_SYSCONFIG_AUTOIDLE |
1076 OMAP2_MCSPI_SYSCONFIG_ENAWAKEUP |
1077 OMAP2_MCSPI_SYSCONFIG_SMARTIDLE;
1078 mcspi_write_reg(master, OMAP2_MCSPI_SYSCONFIG, tmp);
1079 omap2_mcspi_ctx[master->bus_num - 1].sysconfig = tmp;
1080 1051
1081 tmp = OMAP2_MCSPI_WAKEUPENABLE_WKEN; 1052 tmp = OMAP2_MCSPI_WAKEUPENABLE_WKEN;
1082 mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE, tmp); 1053 mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE, tmp);
@@ -1087,6 +1058,18 @@ static int __init omap2_mcspi_reset(struct omap2_mcspi *mcspi)
1087 return 0; 1058 return 0;
1088} 1059}
1089 1060
1061static int omap_mcspi_runtime_resume(struct device *dev)
1062{
1063 struct omap2_mcspi *mcspi;
1064 struct spi_master *master;
1065
1066 master = dev_get_drvdata(dev);
1067 mcspi = spi_master_get_devdata(master);
1068 omap2_mcspi_restore_ctx(mcspi);
1069
1070 return 0;
1071}
1072
1090 1073
1091static int __init omap2_mcspi_probe(struct platform_device *pdev) 1074static int __init omap2_mcspi_probe(struct platform_device *pdev)
1092{ 1075{
@@ -1136,34 +1119,22 @@ static int __init omap2_mcspi_probe(struct platform_device *pdev)
1136 if (!mcspi->base) { 1119 if (!mcspi->base) {
1137 dev_dbg(&pdev->dev, "can't ioremap MCSPI\n"); 1120 dev_dbg(&pdev->dev, "can't ioremap MCSPI\n");
1138 status = -ENOMEM; 1121 status = -ENOMEM;
1139 goto err1aa; 1122 goto err2;
1140 } 1123 }
1141 1124
1125 mcspi->dev = &pdev->dev;
1142 INIT_WORK(&mcspi->work, omap2_mcspi_work); 1126 INIT_WORK(&mcspi->work, omap2_mcspi_work);
1143 1127
1144 spin_lock_init(&mcspi->lock); 1128 spin_lock_init(&mcspi->lock);
1145 INIT_LIST_HEAD(&mcspi->msg_queue); 1129 INIT_LIST_HEAD(&mcspi->msg_queue);
1146 INIT_LIST_HEAD(&omap2_mcspi_ctx[master->bus_num - 1].cs); 1130 INIT_LIST_HEAD(&omap2_mcspi_ctx[master->bus_num - 1].cs);
1147 1131
1148 mcspi->ick = clk_get(&pdev->dev, "ick");
1149 if (IS_ERR(mcspi->ick)) {
1150 dev_dbg(&pdev->dev, "can't get mcspi_ick\n");
1151 status = PTR_ERR(mcspi->ick);
1152 goto err1a;
1153 }
1154 mcspi->fck = clk_get(&pdev->dev, "fck");
1155 if (IS_ERR(mcspi->fck)) {
1156 dev_dbg(&pdev->dev, "can't get mcspi_fck\n");
1157 status = PTR_ERR(mcspi->fck);
1158 goto err2;
1159 }
1160
1161 mcspi->dma_channels = kcalloc(master->num_chipselect, 1132 mcspi->dma_channels = kcalloc(master->num_chipselect,
1162 sizeof(struct omap2_mcspi_dma), 1133 sizeof(struct omap2_mcspi_dma),
1163 GFP_KERNEL); 1134 GFP_KERNEL);
1164 1135
1165 if (mcspi->dma_channels == NULL) 1136 if (mcspi->dma_channels == NULL)
1166 goto err3; 1137 goto err2;
1167 1138
1168 for (i = 0; i < master->num_chipselect; i++) { 1139 for (i = 0; i < master->num_chipselect; i++) {
1169 char dma_ch_name[14]; 1140 char dma_ch_name[14];
@@ -1193,8 +1164,10 @@ static int __init omap2_mcspi_probe(struct platform_device *pdev)
1193 mcspi->dma_channels[i].dma_tx_sync_dev = dma_res->start; 1164 mcspi->dma_channels[i].dma_tx_sync_dev = dma_res->start;
1194 } 1165 }
1195 1166
1196 if (omap2_mcspi_reset(mcspi) < 0) 1167 pm_runtime_enable(&pdev->dev);
1197 goto err4; 1168
1169 if (status || omap2_mcspi_master_setup(mcspi) < 0)
1170 goto err3;
1198 1171
1199 status = spi_register_master(master); 1172 status = spi_register_master(master);
1200 if (status < 0) 1173 if (status < 0)
@@ -1203,17 +1176,13 @@ static int __init omap2_mcspi_probe(struct platform_device *pdev)
1203 return status; 1176 return status;
1204 1177
1205err4: 1178err4:
1206 kfree(mcspi->dma_channels); 1179 spi_master_put(master);
1207err3: 1180err3:
1208 clk_put(mcspi->fck); 1181 kfree(mcspi->dma_channels);
1209err2: 1182err2:
1210 clk_put(mcspi->ick);
1211err1a:
1212 iounmap(mcspi->base);
1213err1aa:
1214 release_mem_region(r->start, (r->end - r->start) + 1); 1183 release_mem_region(r->start, (r->end - r->start) + 1);
1184 iounmap(mcspi->base);
1215err1: 1185err1:
1216 spi_master_put(master);
1217 return status; 1186 return status;
1218} 1187}
1219 1188
@@ -1229,9 +1198,7 @@ static int __exit omap2_mcspi_remove(struct platform_device *pdev)
1229 mcspi = spi_master_get_devdata(master); 1198 mcspi = spi_master_get_devdata(master);
1230 dma_channels = mcspi->dma_channels; 1199 dma_channels = mcspi->dma_channels;
1231 1200
1232 clk_put(mcspi->fck); 1201 omap2_mcspi_disable_clocks(mcspi);
1233 clk_put(mcspi->ick);
1234
1235 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1202 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1236 release_mem_region(r->start, (r->end - r->start) + 1); 1203 release_mem_region(r->start, (r->end - r->start) + 1);
1237 1204
@@ -1282,6 +1249,7 @@ static int omap2_mcspi_resume(struct device *dev)
1282 1249
1283static const struct dev_pm_ops omap2_mcspi_pm_ops = { 1250static const struct dev_pm_ops omap2_mcspi_pm_ops = {
1284 .resume = omap2_mcspi_resume, 1251 .resume = omap2_mcspi_resume,
1252 .runtime_resume = omap_mcspi_runtime_resume,
1285}; 1253};
1286 1254
1287static struct platform_driver omap2_mcspi_driver = { 1255static struct platform_driver omap2_mcspi_driver = {